CN109616470B

CN109616470B - Integrated circuit, semiconductor device based on integrated circuit and standard cell library

Info

Publication number: CN109616470B
Application number: CN201910079668.2A
Authority: CN
Inventors: 白尚训; 吴祥奎; 都桢湖; 朴善暎; 李昇映; 元孝植
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2014-07-22
Filing date: 2015-07-22
Publication date: 2023-07-04
Anticipated expiration: 2035-07-22
Also published as: KR101958421B1; CN109616470A; TW201611185A; TWI628741B; KR20160011562A

Abstract

An Integrated Circuit (IC), a semiconductor device, and a standard cell library are provided. An Integrated Circuit (IC) may include at least one unit including: a plurality of wires extending in a first direction and parallel to each other in a second direction perpendicular to the first direction; first contacts respectively arranged at two sides of at least one wire of the plurality of wires; and a second contact disposed on the at least one wire and the first contact and forming a single node by being electrically connected to the at least one wire and the first contact.

Description

Integrated circuit, semiconductor device based on integrated circuit and standard cell library

The present application is a divisional application of patent application having application date 2015, month 07, 22, application number 2015143904. X, entitled "integrated circuit, semiconductor device based on integrated circuit, and standard cell library".

Technical Field

Example embodiments of the inventive concepts relate to an Integrated Circuit (IC) including at least one cell, a semiconductor device based on the IC, and/or a standard cell library storing information related to the at least one cell.

Background

As the size of transistors decreases and semiconductor fabrication techniques further develop, more transistors may be integrated in a semiconductor device. For example, a system-on-chip (SOC), which refers to an Integrated Circuit (IC) that integrates all components of a computer or other electronic system into a single chip, is used in various applications. The increase in performance requirements for applications may require semiconductor devices that include more components.

Disclosure of Invention

According to at least one example embodiment of the inventive concepts, an Integrated Circuit (IC) may include at least one unit including: a plurality of wires extending in a first direction and disposed parallel to each other in a second direction perpendicular to the first direction; first contacts respectively arranged at two sides of at least one wire of the plurality of wires; and a second contact disposed on the at least one wire and the first contact and forming a single node by being electrically connected to the at least one wire and the first contact.

According to other example embodiments of the inventive concepts, a semiconductor device may include: a substrate including a first active region and a second active region having different conductive types; a plurality of wires extending in a first direction and disposed parallel to each other in a second direction perpendicular to the first direction; first contacts respectively arranged at two sides of at least one wire of the plurality of wires; and a second contact disposed on the at least one wire and the first contact in at least one of the first active region and the second active region, and forming a single node by being electrically connected to the at least one wire and the first contact.

According to other example embodiments of the inventive concepts, a standard cell library stored in a non-transitory computer-readable storage medium may include information about a plurality of standard cells. At least one of the plurality of standard cells comprises: the first active region and the second active region have different conductivity types; a plurality of fins disposed parallel to each other in the first active region and the second active region; a plurality of wires extending in a first direction and disposed parallel to each other in a second direction perpendicular to the first direction, over the plurality of fins; first contacts respectively arranged at two sides of at least one wire of the plurality of wires; and a second contact forming a single node by being electrically connected to the at least one wire and the first contact in at least one of the first active region and the second active region.

According to other example embodiments, a semiconductor device may include: a substrate having a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type; a plurality of gate electrodes extending in a first direction such that the plurality of gate electrodes are parallel to each other in a second direction, the second direction being perpendicular to the first direction; a first contact at a corresponding one of both sides of a skipped gate electrode of the plurality of gate electrodes, the skipped gate electrode being a gate electrode of the plurality of gate electrodes connected to the first contact; and a second contact electrically connected to the skipped gate electrode and the first contact in the first active region, such that the second contact, the at least one wire, and the first contact form a single node in the first active region.

The semiconductor device may include at least one asymmetric gate Integrated Circuit (IC) that includes a greater number of transistors in the second active region than in the first active region.

The transistor may be a fin transistor.

The semiconductor device may further include a plurality of fins extending in the second direction under the plurality of gate electrodes extending in the first direction, such that the plurality of fins and the plurality of gate electrodes correspond to fin transistors.

Drawings

Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a layout showing a portion of an Integrated Circuit (IC) according to an example embodiment;

FIG. 2 is a layout showing a portion of an IC according to another example embodiment;

fig. 3 is a cross-sectional view showing an example of the semiconductor device having the layout of fig. 1, which is cut along the line III-III' of fig. 1;

FIG. 4 is a layout showing a portion of an IC that is substantially identical to the example embodiment of FIG. 1;

FIG. 5 is a layout showing a portion of an IC according to another example embodiment;

fig. 6 is a cross-sectional view showing an example of a semiconductor device having the layout of fig. 5;

FIG. 7 is a layout showing a portion of an IC according to another example embodiment;

Fig. 8 is a cross-sectional view showing an example of the semiconductor device having the layout of fig. 5, which is cut along the line VIII-VIII' of fig. 7;

FIG. 9 is a layout showing a portion of an IC that is substantially identical to the example embodiment of FIG. 5;

FIG. 10 is a diagram showing a layout of an IC according to another example embodiment;

FIG. 11 is a layout showing substantially the same IC as the example embodiment of FIG. 10;

fig. 12 is a perspective view showing an example of a semiconductor device having the layout of fig. 10;

fig. 13 is a cross-sectional view showing the semiconductor device cut along line XII-XII' of fig. 12;

fig. 14 is a perspective view showing another example of the semiconductor device having the layout of fig. 10;

fig. 15 is a cross-sectional view showing the semiconductor device cut along line XIV-XIV' of fig. 14;

fig. 16 is a cross-sectional view showing the semiconductor device having the layout of fig. 10, taken along line XVI-XVI' of fig. 10;

FIG. 17 is a diagram showing a layout of an IC according to another example embodiment;

FIG. 18 is a layout showing a portion of an IC that is substantially identical to the example embodiment of FIG. 17;

fig. 19 is a circuit diagram illustrating the IC of fig. 17;

fig. 20 is a circuit diagram illustrating the third node area of fig. 19 in detail;

FIG. 21 is a diagram showing a layout of an IC according to another example embodiment;

FIG. 22 is a layout showing a portion of an IC that is substantially identical to the example embodiment of FIG. 21;

FIG. 23 is a block diagram illustrating a storage medium according to an example embodiment;

fig. 24 is a block diagram illustrating a memory card including an IC according to an example embodiment; and

fig. 25 is a block diagram illustrating a computing system including an IC according to an example embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, some examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Since the inventive concept is susceptible of various modifications and alternative examples, specific example embodiments will be shown in the drawings and will be described in detail in the written description. However, it is not intended to limit the inventive concept to the particular mode of practice, and it will be understood that all changes, equivalents, and alternatives that do not depart from the spirit and technical scope are included in the inventive concept. The dimensions of the components in the figures may be exaggerated for convenience of explanation. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a expression such as "at least one of … …" follows a series of elements (elements), the entire series of elements (elements) is modified without modifying individual elements (elements) of the column.

The terminology used in the description presented herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the inventive concepts. The use of the singular includes the plural unless the context clearly dictates otherwise. In this specification, it will be understood that terms such as "comprises," "comprising," "includes," and "including" are intended to indicate the presence of the features, amounts, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to exclude the possibility that one or more other features, amounts, steps, actions, components, parts, or combinations thereof may be present or added.

Although various components may be described using such terms as "first," "second," etc., these components are not necessarily limited to the above terms. The above terms are used only to distinguish one component from another. For example, within the scope of the inventive concept, a first component may be referred to as a second component and vice versa.

Unless defined otherwise, all terms (including technical and scientific terms) used in the description have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a layout showing a portion of an Integrated Circuit (IC) 100A according to an example embodiment.

Referring to fig. 1, an ic 100a may include at least one cell defined by a cell boundary indicated with a bold line. The unit may include first to third wires 140a to 140c,

first contacts

150a and 150b, and a second contact 160a. Although not shown, a plurality of conductive lines such as metal lines may be additionally provided at an upper portion of the unit.

According to some example embodiments, the cells may be standard cells. According to a method of designing a standard cell layout, a reusable device such as an OR gate OR an AND gate may be designed in advance as a standard cell AND stored in a computer system, the standard cell being set at a necessary position AND connected with a wire during a layout design process. Thus, the layout can be designed in a relatively short time.

The first to third conductive lines 140a to 140c may extend in a first direction (e.g., Y direction). In addition, the first to third conductive lines 140a to 140c may be disposed parallel to each other along a second direction (e.g., X direction) substantially perpendicular to the first direction. The first to third conductive lines 140a to 140c may be formed of a material having conductivity such as polysilicon, metal, and metal alloy.

According to example embodiments, the first to third conductive lines 140a to 140c may correspond to gate electrodes. However, the example embodiments are not limited thereto, and for example, the first to third conductive lines 140a to 140c may be conductive traces. In addition, although fig. 1 shows that the unit includes the first to third conductive lines 140a to 140c, example embodiments are not limited thereto. For example, the cell may include four or more wires extending in a first direction and parallel to each other in a second direction.

The

first contacts

150a and 150b may extend in a first direction. In addition, the

first contacts

150a and 150b may be disposed parallel to each other along a second direction substantially perpendicular to the first direction. The

first contacts

150a and 150b may be formed of a material having conductivity such as polysilicon, metal, and metal alloy. Accordingly, the

first contacts

150a and 150b may supply a power voltage or a ground voltage to a lower region between the first to third conductive lines 140a to 140 c.

According to some example embodiments, the

first contacts

150a and 150b may be disposed at both sides of the second wire 140b, respectively. In particular, the

first contacts

150a and 150b may include a first left contact 150a disposed at a left side of the second wire 140b and a first right contact 150b disposed at a right side of the second wire 140 b. In other words, the first left contact 150a may be disposed between the first and

second wires

140a and 140b, and the first right contact 150b may be disposed between the second and

third wires

140b and 140 c.

According to some example embodiments, a length (i.e., a width W1 a) of the first left contact 150a in the second direction may be smaller than a spacing S1 between the first wire 140a and the second wire 140 b. Also, the length (i.e., the width W1 b) of the first right contact 150b in the second direction may be smaller than the interval S1 between the second wire 140b and the third wire 140 c. According to example embodiments, the width W1a of the first left contact 150a and the width W1b of the first right contact 150b may be substantially the same. However, the example embodiments are not limited thereto. For example, according to another example embodiment, the width W1a of the first left contact 150a may be different from the width W1b of the first right contact 150b.

The second contact 160a may be disposed on the second wire 140b and the

first contacts

150a and 150b, and may form a single node by being electrically connected to the second wire 140b and the

first contacts

150a and 150b. In addition, the second contact 160a may extend in the second direction, and thus, the second contact 160a may extend in a direction horizontally crossing the second wire 140b and the

first contacts

150a and 150b. The second contact 160a may be formed of a material having conductivity such as polysilicon, metal, and metal alloy. Accordingly, the second contact 160a may provide, for example, the same power voltage or the same ground voltage to the second wire 140b and the

first contacts

150a and 150b.

According to some example embodiments, a length (i.e., W1 c) of the second contact 160a in the second direction may be greater than a distance D1a between the first left contact 150a and the first right contact 150b and less than a distance D1b between the first wire 140a and the third wire 140c. Accordingly, the second contact 160a may be electrically connected to the second wire 140b, the first left contact 150a, and the first right contact 150b, without being connected to the first wire 140a and the third wire 140c.

According to some example embodiments, the length of the first left contact 150a in the first direction (i.e., the height H1 a) may be the same as the length of the first right contact 150b in the first direction (i.e., the height H1 b). Accordingly, the first left contact 150a, the first right contact 150b, and the second contact 160a may form an H-shaped jumper (jumper). A jumper is a wire having a relatively short length for connecting two points or two terminals in the IC 100A.

As described above, according to some example embodiments, a single node may be formed by electrically connecting the second wire 140b, the

first contacts

150a and 150b, and the second contact 160 a. Accordingly, in the IC 100A manufactured based on the layout shown in fig. 1, the second conductive line 140b may be skipped or shielded. Thus, an H-jumper according to some example embodiments may be referred to as a jumper.

According to some example embodiments, a cell in which the second wire 140b is skipped may be designed by electrically connecting the second wire 140b, the

first contacts

150a and 150b, and the second contact 160 a. Accordingly, the

first contacts

150a and 150b and the second contact 160a may be separated from the second wire 140b to reduce (or, alternatively, eliminate) the possibility of an electrical short occurring when the jumper wire is formed.

Information about the above-described layout of standard cells may be stored in a standard cell library. In particular, the standard cell library may include information related to a plurality of standard cells and be stored in a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium). Standard cells corresponding to information included in the standard cell library refer to cells of ICs having a size satisfying the standard. For example, the height of the layout of the standard cells (e.g., the length in the Y direction of fig. 1) may be fixed, while the width of the standard cells (e.g., the length in the X direction of fig. 1) may vary according to the standard cells. The standard cell may include an input fin (input fin) for processing an input signal and an output fin (output fin) for outputting an output signal.

The IC may be a plurality of standard cells. The IC design tool may design an IC, i.e., complete the layout of the IC by using a standard cell library that includes information about a plurality of standard cells. The IC design tool may provide vias on pins (i.e., input pins and output pins) included in the standard cells so that the pins are connected with patterns on layers formed after the pins of the standard cells are formed in the semiconductor manufacturing process. That is, by providing a via in a pin of the standard cell, an input signal and an output signal of the standard cell can be transmitted.

Fig. 2 is a layout showing a part of the IC 100B according to other example embodiments.

Referring to fig. 2, the ic 100b may include first to third conductive lines 140a to 140c, a first left contact 150a, a first right contact 150b', and a second contact 160a. IC 100B is a modified example embodiment of IC 100A shown in fig. 1. Accordingly, at least some of the description of fig. 1 is also applicable to IC 100B, and thus features and elements already described with reference to fig. 1 will not be repeated.

According to some example embodiments, a length of the first left contact 150a in the first direction (i.e., the height H1 a) may be different from a length of the first right contact 150b '(i.e., the height H1 b'). Accordingly, the first left contact 150a, the first right contact 150b', and the second contact 160a may form an L-shaped jumper.

According to some example embodiments, the height H1b 'of the first right contact 150b' may be greater than the height H1a of the first left contact 150 a. According to other example embodiments, the height H1a of the first left contact 150a may be greater than the height H1b 'of the first right contact 150 b'. The height H1a of the first left contact 150a and the height H1b 'of the first right contact 150b' may vary in various example embodiments.

Fig. 3 is a cross-sectional view showing an example of the semiconductor device 100a having the layout of fig. 1, which is cut along the line III-III' of fig. 1.

Referring to fig. 3, the semiconductor device 100a may include a substrate 110, a second conductive line 140b,

first contacts

150a and 150b, and a second contact 160a. Although not shown, a voltage terminal providing, for example, a power supply voltage or a ground voltage may be additionally provided on the second contact 160a.

The substrate 110 may be a semiconductor substrate including any one selected from, for example, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon germanium, gallium arsenide. For example, the substrate 110 may be a P-type substrate. In addition, although not shown, the substrate 110 may have an active region doped with impurities.

The second conductive line 140b may be disposed on the substrate 110. According to some example embodiments, the second conductive line 140b may serve as a gate electrode. In this case, a gate insulating layer may be additionally disposed between the first conductive line 140b and the active region of the substrate 110.

The

first contacts

150a and 150b may be disposed on the substrate 110. Accordingly, the

first contacts

150a and 150b may provide, for example, a power voltage or a ground voltage in the active region of the substrate 110. According to some example embodiments, the

first contacts

150a and 150b may be disposed at both sides of the second wire 140b, respectively. According to some example embodiments, the upper portions of the

first contacts

150a and 150b may be on the same level as the upper portion of the second wire 140 b.

The second contact 160a may be disposed on the second wire 140b and the

first contacts

150a and 150b, and form a single node by being electrically connected to the second wire 140b and the

first contacts

150a and 150b.

Fig. 4 is a layout showing a portion of an IC 100A' substantially identical to the example embodiment of fig. 1.

Referring to fig. 4, the ic 100a' may include first and third

conductive lines

140a and 140c and

first contacts

150a and 150b. The

first contacts

150a and 150b may be connected to a single metal line disposed at an upper portion. According to other example embodiments, the IC 100A' may include only one of the first contacts 150A and 150b.

The

first contacts

150a and 150b and the second contact 160a in the layout shown in fig. 1 form an H-shaped jumper. Thus, when the IC 100A is actually manufactured, the IC 100A may be substantially the same as the IC 100A' corresponding to the layout shown in fig. 4. In other words, the second conductive line 140b may be skipped due to the H-shaped jumper line in the layout shown in fig. 1.

Also, the

first contacts

150a and 150b' and the second contact 160a in the layout shown in fig. 2 may form an L-shaped jumper line. Thus, when IC 100B is actually manufactured, IC 100B may be substantially identical to IC 100A' corresponding to the layout shown in fig. 4. In other words, the second conductive line 140b may be skipped due to the L-shaped jumper line in the layout shown in fig. 2.

Fig. 5 is a layout showing a part of the IC 100C according to other example embodiments.

Referring to fig. 5, the ic 100c may include at least one cell defined by a cell boundary indicated by a bold line. The unit may include first to fourth wires 140e to 140h,

first contacts

150c and 150d, and a second contact 160b.

The first to fourth wires 140e to 140h may extend in a first direction (e.g., Y direction). In addition, the first to fourth conductive lines 140e to 140h may be disposed parallel to each other along a second direction (e.g., X direction) substantially perpendicular to the first direction. The first to fourth conductive lines 140e to 140h may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy.

According to some example embodiments, the first to fourth conductive lines 140e to 140h may correspond to gate electrodes. However, the example embodiments are not limited thereto. For example, the first to fourth conductive lines 140e to 140h may be conductive traces. In addition, although fig. 5 shows that the IC 100C includes the first to fourth conductive lines 140e to 140h, example embodiments are not limited thereto, and for example, the IC 100C may include five or more conductive lines extending in the first direction and parallel to each other in the second direction.

The

first contacts

150c and 150d may extend in a first direction. In addition, the

first contacts

150c and 150d may be disposed parallel to each other along a second direction substantially perpendicular to the first direction. The

first contacts

150c and 150d may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy. Accordingly, the

first contacts

150c and 150d may supply a power voltage or a ground voltage to a lower region between the first to fourth wires 140e to 140 h.

According to some example embodiments, the

first contacts

150c and 150d may include a first left contact 150c disposed at a left side of the second wire 140f and a first right contact 150d disposed at a right side of the third wire 140 g. In other words, the first left contact 150c may be disposed between the first and

second wires

140e and 140f, and the first right contact 150d may be disposed between the third and

fourth wires

140g and 140 h.

According to some example embodiments, a length (i.e., a width W2 a) of the first left contact 150c in the second direction may be smaller than a spacing S2 between the first wire 140e and the second wire 140 f. Also, the length (i.e., the width W2 b) of the first right contact 150d in the second direction may be smaller than the interval S2 between the third wire 140g and the fourth wire 140 h. According to some example embodiments, the width W2a of the first left contact 150c may be substantially the same as the width W2b of the first right contact 150d. However, the example embodiments are not limited thereto. For example, according to other example embodiments, the width W2a of the first left contact 150c may be different from the width W2b of the first right contact 150d.

The second contact 160b may be disposed on the second and

third wires

140f and 140g and the

first contacts

150c and 150d, and form a single node by being electrically connected to the second and

third wires

140f and 140g and the

first contacts

150c and 150d. In addition, the second contact 160b may extend in the second direction, and thus, the second contact 160b may be disposed in a direction horizontally crossing the second and

third wires

140f and 140g and the

first contacts

150c and 150d. The second contact 160b may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy. Accordingly, the second contact 160b may supply, for example, the same power supply voltage or the same ground voltage to the second and

third wires

140f and 140g and the

first contacts

150c and 150d.

According to some example embodiments, a length (i.e., a width W2 c) of the second contact 160b in the second direction may be greater than a distance D2a between the first left contact 150c and the first right contact 150D and less than a distance D2b between the first wire 140e and the fourth wire 140h. Accordingly, the second contact 160b may be electrically connected to the second and

third wires

140f and 140g, the first left contact 150c, and the first right contact 150d, without being connected to the first and

fourth wires

140e and 140h.

According to some example embodiments, a length of the first left contact 150c in the first direction (i.e., the height H2 a) may be substantially the same as a length of the first right contact 150c in the first direction (i.e., the height H2 b). Accordingly, the first left contact 150c, the first right contact 150d, and the second contact 160b may form an H-shaped jumper line. A jumper is a wire having a relatively short length for connecting two points or two terminals in the IC 100C.

Although not shown, according to other example embodiments, the length of the first left contact 150c in the first direction (i.e., the height H2 a) may be different from the length of the first right contact 150d in the first direction (i.e., the height H2 b). Accordingly, the first left contact 150c, the first right contact 150d, and the second contact 160b may form an L-shaped jumper line.

As described above, according to some example embodiments, a single node may be formed by electrically shorting the second and

third wires

140f and 140g, the

first contacts

150c and 150d, and the second contact 160 b. Therefore, in the IC 100C manufactured based on the layout shown in fig. 5, the second wire 140f and the third wire 140g can be skipped. Thus, an H-shaped jumper according to some example embodiments may be referred to as a skip device.

Fig. 6 is a cross-sectional view showing an example of the semiconductor device 100c having the layout of fig. 5.

Referring to fig. 6, the semiconductor device 100c may include a substrate 110, second and third

conductive lines

140f and 140g,

first contacts

150c and 150d, and a second contact 160b. Although not shown, a voltage terminal providing, for example, a power supply voltage or a ground voltage may be additionally provided on the second contact 160b.

The substrate 110 may be a semiconductor substrate including any one selected from, for example, silicon, SOI, silicon on sapphire, germanium, silicon germanium, and gallium arsenide. For example, the substrate 110 may be a P-type substrate. In addition, although not shown, the substrate 110 may have an active region doped with impurities.

The second and

third wires

140f and 140g may be disposed on the substrate 110. According to some example embodiments, the second and third

conductive lines

140f and 140g may function as gate electrodes. In this case, a gate insulating layer may be additionally disposed between the second and third

conductive lines

140f and 140g and the active region of the substrate 110.

The

first contacts

150c and 150d may be disposed on the substrate 110. Accordingly, the

first contacts

150c and 150d may provide, for example, a power voltage or a ground voltage in the active region of the substrate 110. According to some example embodiments, the

first contacts

150c and 150d may be disposed at the left side of the second wire 140f and the right side of the third wire 140g, respectively. According to some example embodiments, the upper portions of the

first contacts

150c and 150d may be on the same level as the upper portions of the second and

third wires

140f and 140 g.

The second contact 160b may be disposed on the second and

third wires

140f and 140g and the

first contacts

150c and 150d, and electrically connected to the second and

third wires

140f and 140g and the

first contacts

150c and 150d. Accordingly, the second and

third wires

140f and 140g, the

first contacts

150c and 150d, and the second contact 160b may form a single node.

Fig. 7 is a layout showing a part of the IC 100D according to other example embodiments.

Referring to fig. 7, the ic 100d may include at least one cell defined by a cell boundary indicated by a bold line. The unit may include first to fourth wires 140e to 140h, a first left contact 150c, a first right contact 150d, a first center contact 150e, and a second contact 160c. IC 100D is a modified example embodiment of IC 100C shown in fig. 5, and thus, at least some of the description of fig. 5 is also applicable to IC 100D. Thus, features and elements already described with reference to fig. 5 will not be repeated.

Unlike the IC 100C of fig. 5, the IC 100D according to some example embodiments may also include a first center contact 150e. The first center contact 150e may be disposed between the second wire 140f and the third wire 140 g. According to some example embodiments, the second contact 160c may be electrically connected to the second and

third wires

140f and 140g and the first left, right and

center contacts

150c, 150d and 150e, thus forming a single node.

Fig. 8 is a cross-sectional view showing an example of the semiconductor device 100d having the layout of fig. 5, which is cut along the line VIII-VIII' of fig. 7.

Referring to fig. 8, the semiconductor device 100d may include a substrate 110, second and third

conductive lines

140f and 140g, first left and

right contacts

150c and 150d, first and center contacts 150e, and a second contact 160c. The semiconductor device 100d is a modified embodiment of the semiconductor device 100c of fig. 6, and thus the description of fig. 6 is also applicable to the semiconductor device 100d. Thus, features and elements already described with reference to fig. 6 will not be repeated.

The first left contact 150c, the first right contact 150d, and the first center contact 150e may be disposed on the substrate 110, respectively. Accordingly, the first left contact 150c, the first right contact 150d, and the first center contact 150e may provide, for example, a power voltage or a ground voltage to the active region of the substrate 110. According to some example embodiments, the first center contact 150e may be disposed between the second wire 140f and the third wire 140 g. According to some example embodiments, upper portions of the first left contact 150c, the first right contact 150d, and the first center contact 150e may be on substantially the same horizontal plane as upper portions of the second and

third wires

140f and 140g, respectively.

The second contacts 160c may be disposed on the second and

third wires

140f and 140g and the first left, right and

center contacts

150c, 150d and 150e and electrically connected to the second and

third wires

140f and 140g and the first left, right and

center contacts

150c, 150d and 150e. Accordingly, the second and

third wires

140f and 140g, the first left contact 150c, the first right contact 150d and the first center contact 150e, and the second contact 160b may form a single node.

Fig. 9 is a layout showing a portion of an IC 100C' substantially identical to the example embodiment of fig. 5.

Referring to fig. 9, the ic 100c' may include first and fourth

conductive lines

140e and 140h and

first contacts

150c and 150d. The

first contacts

150c and 150d may be connected to the same metal line disposed over the

first contacts

150c and 150d. According to other example embodiments, the IC 100C' may include only one of the first contacts 150C and 150d.

The

first contacts

150c and 150d and the second contact 160b included in the layout shown in fig. 5 may form an H-shaped jumper. Thus, when the IC 100C is actually manufactured, the IC 100C may be substantially the same as the IC 100C' corresponding to the layout shown in fig. 9. In other words, the second wire 140f and the third wire 140g may be skipped due to the H-shaped jumper in the layout shown in fig. 5.

Also, the first left contact 150c, the first right contact 150d, and the first center contact 150e, and the second contact 160c in the layout shown in fig. 7 may form a jumper line. Thus, when IC 100D is actually manufactured, IC 100D may be substantially the same as IC 100C' corresponding to the layout shown in fig. 9. In other words, the second wire 140f and the third wire 140g may be skipped due to the jumper in the layout shown in fig. 7.

Fig. 10 is a diagram illustrating a layout of an IC 200 according to other example embodiments.

Referring to fig. 10, the ic 200 may include at least one cell defined by a cell boundary drawn with a bold line. Specifically, fig. 10 shows an example of a standard cell in the IC 200. Standard cells include, but are not limited to, first and second

active regions

220a and 220b, a plurality of fins, a plurality of wires, first contacts 250 a-250 d, second contacts 260, and a cutting region 270.

According to some example embodiments, the plurality of fins may include first through sixth fins 230a through 230f, and the plurality of wires may include first through third wires 240a through 240c. However, the example embodiments are not limited thereto. For example, according to other example embodiments, the plurality of fins and the plurality of wires may each include a variety of numbers of fins and wires.

The first active region 220a may be a location where the first to third fins 230a to 230c are disposed, for example, an N-type metal oxide semiconductor (NMOS) defining layer. For example, the first active region 220a may be any region in the P-type substrate. The second active region 220b may be a location where the fourth to sixth fins 230d to 230f are disposed, for example, a P-type MOS (PMOS) defining layer. For example, the second active region 220b may be an N-well region. Although not shown, a device separation region may be disposed between the first active region 220a and the second active region 220 b.

The first to sixth fins 230a to 230f may be disposed parallel to each other along a first direction (e.g., Y direction) and extend along a second direction (e.g., X direction) substantially perpendicular to the first direction. According to some example embodiments, first through sixth fins 230a through 230f may be active fins. The channel width of a fin transistor formed from such fins may increase in proportion to the number of active fins, and thus, the amount of current flowing in the fin transistor may increase. Although not shown, the IC 200 may additionally include dummy fins disposed on the device separation region.

According to some example embodiments, in the layout of IC 200, first through sixth fins 230 a-230 f may have the same respective lengths (i.e., respective widths) along the first direction. The respective widths of the first to sixth fins 230a to 230f are widths two-dimensionally shown on the layout of fig. 10. Since fig. 10 is a 2D layout, the respective heights of first through sixth fins 230a through 230f are not shown.

The first to third conductive lines 240a to 240c may extend in a first direction (e.g., Y direction). In addition, the first to third conductive lines 24a to 240c may be disposed parallel to each other in a second direction (e.g., X direction) substantially perpendicular to the first direction. The first to third conductive lines 240a to 240c may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy. According to some example embodiments, the first to third conductive lines 240a to 240c may correspond to gate electrodes.

The first contacts 250a to 250d may extend in a first direction (e.g., Y direction). In addition, the first contacts 250a to 250d may be disposed parallel to each other along a second direction (e.g., X direction) substantially perpendicular to the first direction. The first contacts 250a to 250d may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy.

According to some example embodiments, the first contacts 250a to 250d may include first

lower contacts

250a and 250b on the first active region 220a and first

upper contacts

250c and 250d on the second active region 220b. The first

lower contacts

250a and 250b may be contacts connected to the first active region 220a, for example, source and drain contacts. Accordingly, the first

lower contacts

250a and 250b may provide, for example, a power voltage or a ground voltage to the first active region 220a. The first

upper contacts

250c and 250d may be contacts connected to the second active region 220b, for example, source and drain contacts. Accordingly, the first

upper contacts

250c and 250d may provide, for example, a power voltage or a ground voltage to the second active region 220b.

According to some example embodiments, the first

lower contacts

250a and 250b may be disposed at both sides of the second wire 240b, respectively. In particular, the first

lower contacts

250a and 250b may include a first lower left contact 250a disposed at the left side of the second wire 240b and a first lower right contact 250b disposed at the right side of the second wire 240 b. In other words, the first lower left contact 250a may be disposed between the first wire 240a and the second wire 240b, and the first lower right contact 250b may be disposed between the second wire 240b and the third wire 240 c.

The second contact 260 may be disposed on the second wire 240b and the first

lower contacts

250a and 250b, and form a single node by being electrically connected to the second wire 240b and the first

lower contacts

250a and 250b. In addition, the second contact 260 may extend in the second direction, and thus, the second contact 260 may be disposed in a direction horizontally crossing the second wire 240b and the first

lower contacts

250a and 250b. The second contact 260 may be formed of a material having conductivity such as polysilicon, metal, and/or metal alloy. Accordingly, the second contact 260 may provide, for example, the same power voltage or the same ground voltage to the second wire 240b and the first

lower contacts

250a and 250b.

According to some example embodiments, the first to third conductive lines 240A to 240c, the first lower contacts 250A and 250b, and the second contact 260 disposed on the first active region 220A may be substantially the same as the IC 100A shown in fig. 1. Thus, the description of FIG. 1 is also applicable to IC 200, and features and elements already described with reference to FIG. 1 will not be repeated.

As described above, according to some example embodiments, a single node is formed by electrically shorting the second conductive line 240b, the first

lower contacts

250a and 250b, and the second contact 260 on the first active region 220 a. Accordingly, in the IC 200 manufactured based on the layout shown in fig. 10, the second conductive line 240b may be skipped in the first active region 220a but not skipped in the second active region 220 b. Thus, IC 200 may include asymmetric gates of two transistors (e.g., two NMOS fin transistors) in first active region 220a and three transistors (e.g., three PMOS fin transistors) in second active region 220 b.

Although fig. 10 illustrates an example embodiment in which the second contact 260 is disposed on the first active region 220a, the example embodiment is not limited thereto. For example, according to other example embodiments, the second contact 260 may be disposed on both the first active region 220a and the second active region 220 b. In this case, the same number of transistors may be disposed on the first active region 220a and the second active region 220 b. According to other example embodiments, the second contact 260 may be disposed only on the second active region 220 b. In this case, more transistors may be disposed on the first active region 220a than on the second active region 220 b.

Fig. 11 is a diagram illustrating a layout of an IC 200' substantially identical to the exemplary embodiment of fig. 10.

Referring to fig. 11, the ic 200' may include first to third conductive lines 240a to 240c and first contacts 250a to 250d. The first

lower contacts

250a and 250b disposed on the first active region 220a may be connected to the same metal line over the first

lower contacts

250a and 250 b. According to other example embodiments, the IC 200' may include only one of the first

lower contacts

250a and 250 b.

The first

lower contacts

250a and 250b and the second contact 260 included in the layout shown in fig. 10 may form an H-shaped jumper. Thus, when IC 200 is actually manufactured, IC 200 may be substantially identical to IC 200' corresponding to the layout shown in fig. 11. In other words, the second conductive line 240b in the first active region 220a may be skipped due to the H-shaped jumper line in the layout shown in fig. 10. Thus, as shown in fig. 11, the second conductive line 240b may be skipped in the first active region 220a, and thus, the ICs 200 and 200' may include two NMOS fin transistors in the first active region 220a and three PMOS fin transistors in the second active region 220 b.

Fig. 12 is a perspective view showing an example of the semiconductor device 200A having the layout of fig. 10. Fig. 13 is a cross-sectional view showing the semiconductor device 200A cut along the line XII-XII' of fig. 12.

Referring to fig. 12 and 13, the semiconductor device 200A may be a bulk (type) fin transistor. The semiconductor device 200A may include a substrate 210, a first insulating layer 233, a second insulating layer 236, first to third fins 230A to 230c, and a first conductive line (hereinafter referred to as a "gate electrode") 240A.

The substrate 210 may be a semiconductor substrate including any one selected from, for example, silicon, SOI, silicon on sapphire, germanium, silicon germanium, gallium arsenide. The substrate 210 may be a P-type substrate and may serve as the first active region 220a.

The first to third fins 230a to 230c may be disposed such that they are connected to the substrate 210. According to some example embodiments, the first to third fins 230a to 230c may be active regions formed by doping a portion protruding vertically from the substrate 210 with an n+ or p+ impurity.

The first insulating layer 233 and the second insulating layer 236 may include an insulating material selected from, for example, oxide, nitride, and/or oxynitride. The first insulating layer 233 may be disposed on the first to third fins 230a to 230 c. The first insulating layer 233 may serve as a gate insulating layer by being disposed between the first to third fins 230a to 230c and the gate electrode 240a. The second insulating layer 236 may be formed to a certain height at a space between the first to third fins 230a to 230 c. The second insulating layer 236 may serve as a device separation layer by being disposed between the first to third fins 230a to 230 c.

The gate electrode 240a may be disposed on the first insulating layer 233 and the second insulating layer 236. Accordingly, the gate electrode 240a may surround the first to third fins 230a to 230c, the first insulating layer 233, and the second insulating layer 236. In other words, the first to third fins 230a to 230c may be located inside the gate electrode 240 a. The gate electrode 240a may include a metal material such as tungsten (W) or tantalum (Ta), a nitride of the metal material, a silicide of the metal material, and/or doped polysilicon and may be formed using a deposition process.

Fig. 14 is a perspective view showing another example of the semiconductor device 200B having the layout of fig. 10.

Fig. 15 is a cross-sectional view showing the semiconductor device 200B cut along the line XIV-XIV' of fig. 14.

Referring to fig. 14 and 15, the semiconductor device 200B may be an SOI-type fin transistor. The semiconductor device 200B may include a substrate 210', a first insulating layer 215, a second insulating layer 233', first to third fins 230a ' to 230c ', and a first conductive line (hereinafter referred to as a "gate electrode") 240a '. The semiconductor device 200B is a modified example embodiment of the semiconductor device 200A shown in fig. 12 and 13. Accordingly, features and elements of the semiconductor device 200B that are different from those of the semiconductor device 200A will be mainly described, and features and elements that have been described with reference to fig. 12 and 13 will not be repeated.

The first insulating layer 215 may be disposed on the substrate 210'. The second insulating layer 233 'may serve as a gate insulating layer by being disposed between the first to third fins 230a' to 230c 'and the gate electrode 240 a'. The first to third fins 230a 'to 230c' may include a semiconductor material, such as silicon and/or doped silicon.

The gate electrode 240a 'may be disposed on the second insulating layer 233'. Accordingly, the gate electrode 240a 'may surround the first to third fins 230a' to 230c 'and the second insulating layer 233'. In other words, the first to third fins 230a ' to 230c ' may be located inside the gate electrode 240a '.

Fig. 16 is a cross-sectional view showing the semiconductor device 200a having the layout of fig. 10, which is cut along the line XVI-XVI' of fig. 10.

Referring to fig. 16, the semiconductor device 200A may include a second fin 230b, a second conductive line 240b, first lower contacts 250A and 250b, and a second contact 260. Although not shown, a voltage terminal providing, for example, a power supply voltage or a ground voltage may be additionally provided on the second contact 260.

Second wire 240b may be disposed on second fin 230 b. According to some example embodiments, the second wire 240b may serve as a gate electrode, and a gate insulating layer may be additionally disposed between the second wire 240b and the second fin 230 b.

First

lower contacts

250a and 250b may be disposed on second fin 230b. Accordingly, the first

lower contacts

250a and 250b may provide, for example, a power supply voltage or a ground voltage to the second fin 230b. According to some example embodiments, the first

lower contacts

250a and 250b may be disposed at both sides of the second wire 240b, respectively. According to some example embodiments, the upper portions of the first

lower contacts

250a and 250b may be on the same level as the upper portion of the second wire 240 b.

The second contact 260 may be disposed on the second wire 240b and the first

lower contacts

250a and 250b and electrically connected to the second wire 240b and the first

lower contacts

250a and 250b. Accordingly, the second wire 240b, the first

lower contacts

250a and 250b, and the second contact 260 may form a single node.

Fig. 17 is a diagram illustrating a layout of an IC 300 according to other example embodiments.

Referring to fig. 17, the ic 300 may include at least one cell defined by a cell boundary drawn with a bold line. Specifically, fig. 17 shows an example of a standard cell in the IC 300. The standard cell may include first and second

active regions

220a and 220b, first through sixth fins 230a through 230f, first through third conductive lines 240a through 240c, first contacts 250a through 250d, second contact 260, cutting region 270, and third contacts 380a through 380c. IC 300 is a modified example embodiment of IC 200 shown in fig. 10. Accordingly, the description of fig. 10 is also applicable to IC 300, and thus features and elements already described with reference to fig. 10 will not be repeated.

In contrast to the IC 200 of fig. 10, the IC 300 according to some example embodiments may additionally include third contacts 380 a-380 c. The first contact 380a of the third contacts may be disposed on the first wire 240a and electrically connected to the first wire 240a. The third contact 380c of the third contacts may be disposed on the third wire 240c and electrically connected to the third wire 240c.

The second contact 380b of the third contacts 380c may be disposed on the second wire 240b and electrically connected to the second wire 240b. Since the cutting region 270 is in the middle of the second conductive line 240b, the third contact 380b is electrically connected only to the second conductive line 240b on the second active region 220b, and is not connected to the second conductive line 240b of the first active region 220 a.

According to some example embodiments, a single node may be formed by electrically shorting the second conductive line 240b, the first

lower contacts

250a and 250b, and the second contact 260 on the first active region 220 a. Accordingly, in the IC 300 manufactured based on the layout shown in fig. 17, the second conductive line 240b may be skipped in the first active region 220a and not skipped in the second active region 220b, so that the IC 300 has an asymmetric transistor. Thus, IC 300 may include two transistors (e.g., two NMOS fin transistors) in first active region 220a and three transistors (e.g., three PMOS fin transistors) in second active region 220 b.

Although fig. 17 illustrates an example embodiment in which the second contact 260 is disposed on the first active region 220a, the example embodiment is not limited thereto. For example, according to other example embodiments, the second contact 260 may be disposed on both the first active region 220a and the second active region 220 b. In this case, the same number of transistors may be disposed on the first active region 220a and the second active region 220 b. According to other example embodiments, the second contact 260 may be disposed only on the second active region 220 b. In this case, more transistors may be disposed on the first active region 220a than on the second active region 220 b.

Fig. 18 is a layout showing a part of an IC 300 substantially identical to the example embodiment of fig. 17.

Referring to fig. 18, the ic 300' may include first to third conductive lines 240a to 240c, first to 250d contacts, and third contacts 380a to 380c. The first

lower contacts

250a and 250b on the first active region 220a may be connected to the same metal line over the first

lower contacts

250a and 250 b. According to other example embodiments, the IC 300' may include only one of the first

lower contacts

250a and 250 b.

The first

lower contacts

250a and 250b and the second contact 260 included in the layout shown in fig. 17 may form an H-shaped jumper. Thus, when IC 300 is actually manufactured, IC 300 may be substantially identical to IC 300' corresponding to the layout shown in fig. 18. In other words, as shown in fig. 18, the second conductive line 240b in the first active region 220a may be skipped due to the H-shaped jumper line in the layout shown in fig. 17. Thus, the ICs 300 and 300' may include two NMOS fin transistors in the first active region 220a and three PMOS fin transistors in the second active region 220 b.

Fig. 19 is a circuit diagram illustrating the IC 300 of fig. 17.

Referring to fig. 17 and 19, the ic 300 may include first to third PMOS fin transistors PM1 to PM3 and first and second NMOS fin transistors NM1 and NM2. The first to third PMOS fin transistors PM1 to PM3 may be formed on the second active region 220b, and the first and second NMOS fin transistors NM1 and NM2 may be formed on the first active region 220 a.

The respective gates of the first PMOS fin transistor PM1 and the first NMOS fin transistor NM1 are each connected to a node a that may correspond to a first contact 380a of the third contacts 380 a. In addition, the gate of the second PMOS fin transistor PM2 may be connected to a node B that may correspond to the second contact 380B of the third contacts 380B. In addition, respective gates of the third PMOS fin transistor PM3 and the second NMOS fin transistor NM2 may each be connected to a node C that may correspond to a third contact 380C of the third contacts 380 b.

Specifically, in some example embodiments, the gate of the first PMOS fin transistor PM1 may be connected to the first contact 380a of the third contacts 380a, the drain of the first PMOS fin transistor PM1 may be connected to the first node area NA1, and the first node area NA1 may correspond to the first upper left contact 250 c. The gate of the second PMOS fin transistor PM2 may be connected to the second contact 380a of the third contacts 380a, the drain of the second PMOS fin transistor PM2 may be connected to the second node area NA2, and the second node area NA2 may correspond to the first upper right contact 250 d. The gate of the third PMOS fin transistor PM3 may be connected to a third contact 380c of the third contacts 380c.

The gate of the first NMOS fin transistor NM1 may be connected to a first contact 380a of the third contacts 380a, and the gate of the second NMOS fin transistor NM2 may be connected to a third contact 380c of the third contacts 380c. The first and second NMOS fin transistors NM1 and NM2 may be connected to a third node area NA3, which may correspond to a jumper line formed by the first

lower contacts

250a and 250b and the second contact 260 of fig. 17.

Fig. 20 is a circuit diagram illustrating the third node area NA3 of fig. 19 in detail.

Referring to fig. 17, 19 and 20, a single node area (i.e., a third node area NA 3) may be formed by a first node ND1 connected between the second fin 230b and the first lower left contact 250a, a second node ND2 between the second fin 230b and the first lower right contact 250b, and a third node ND3 between the second contact 260 and the second wire 240 b.

Fig. 21 is a diagram illustrating a layout of an IC 400 according to other example embodiments.

Referring to fig. 21, an ic 400 may include at least one cell defined by a cell boundary drawn with a bold line. Specifically, fig. 21 shows an example of a standard cell in the IC 400. The standard cell may include first to tenth fins 430a to 430j, a plurality of

gate electrodes

440b, 440c and 440d, a plurality of

dummy gate electrodes

440a and 440e, a plurality of source and

drain contacts

450a and 450b, a second contact 460, a cutting region 470, two input terminals 480, two input contacts 485, and an output terminal 490.

According to example embodiments, the first, fifth, sixth, and

tenth fins

430a, 430e, 430f, and 430j may be dummy fins, and the second, fourth, and seventh, and

ninth fins

430b, 430d, and 430g, and 430i may be active fins. In particular, the second to fourth fins 430b to 430d may be disposed in the first active region 420a, and the seventh to ninth fins 430g to 430i may be disposed in the second active region 420 b. The first fin 430a may be disposed in the first device separation region 425a, the fifth fin 430e and the sixth fin 430f may be disposed in the second device separation region 425b, and the tenth fin 430j may be disposed in the third device separation region 425 c.

First, the first to tenth fins 430a to 430j may be preformed on a semiconductor substrate (not shown) by performing a single manufacturing process. Second, a plurality of source and

drain contacts

450a and 450b may be formed, and a gate electrode including a plurality of

gate electrodes

440b, 440c and 440d and a plurality of

dummy gate electrodes

440a and 440 e. Third, a second contact 460 may be formed on the gate electrode 440c and the plurality of source and

drain contacts

450a and 450 b. Fourth, two input terminals 480 and output terminals 490 may be formed.

The first region R1 is similar to the layout shown in fig. 1, and thus the example embodiments described above with reference to fig. 1 to 9 may be applied to the first region R1. The second region R2 is similar to the layout shown in fig. 10, and thus the example embodiments described above with reference to fig. 10 to 20 may be applied to the second region R2. According to some example embodiments, the second to fourth fins 430b to 430d may form NMOS transistors, and the seventh to ninth fins 430g to 430i may form PMOS transistors.

Although fig. 21 illustrates an example embodiment in which the second contact 460 is disposed on the first active region 420a, the example embodiment is not limited thereto. For example, according to other example embodiments, the second contact 460 may be disposed on both the first active region 420a and the second active region 420 b. In this case, the same number of transistors may be disposed on the first active region 420a and the second active region 420 b. According to other example embodiments, the second contact 460 may be disposed only on the second active region 420 b. In this case, more transistors may be disposed on the first active region 220a than on the second active region 220 b.

Fig. 22 is a layout showing a part of an IC substantially the same as the example embodiment of fig. 21.

Referring to fig. 22, an ic 400' may include first to tenth fins 430a to 430j, a plurality of

gate electrodes

440b, 440c and 440d, a plurality of

dummy gate electrodes

440a and 440e, a plurality of source and

drain contacts

450a and 450b, a second contact 460, two input terminals 480, two input contacts 485, and an output terminal 490. The plurality of source and

drain contacts

450a and 450b on the first active region 420a may be connected to the same metal line over the plurality of source and

drain contacts

450a and 450 b. According to other example embodiments, the IC 400' may include only one of the plurality of source contacts 450a and drain contacts 450b on the first active region 420 a.

The plurality of source and

drain contacts

450a and 450b and the second contact 460 included in the layout shown in fig. 21 may form an H-shaped jumper. Thus, when IC400 is actually manufactured, IC400 may be substantially identical to IC 400' corresponding to the layout shown in fig. 22. In other words, as shown in fig. 22, the gate electrode 440c in the first active region 420a of fig. 22 may be skipped due to the H-shaped jumper line in the layout shown in fig. 21. Thus, each of the ICs 400 and 400' may include two NMOS fin transistors in the first active region 420a and three PMOS fin transistors in the second active region 420 b.

Fig. 23 is a block diagram illustrating a computer-readable storage medium 500 according to some example embodiments.

Referring to fig. 23, a computer-readable storage medium 500 may include a storage medium readable by a computer, for example, to provide instructions and/or data to the computer. The computer-readable storage medium 500 may be non-transitory. For example, non-transitory computer readable storage media 500 may include magnetic storage media (e.g., magnetic disks or tapes) and optical recording media (CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, and DVD-RW), volatile or non-volatile memory (e.g., RAM, ROM, or flash memory), non-volatile memory accessible through a USB interface, and microelectromechanical systems (MEMS). The computer-readable recording medium may be inserted into a computer, integrated into a computer, or combined with a computer through a communication medium such as a network and/or a wireless link.

As shown in fig. 23, the computer-readable storage medium 500 may have stored therein a location and routing program 510, a library 520, an analysis program 530, and a data structure 540. The location and routing program 510 may store a plurality of instructions for performing a method of using a standard cell library or a method of designing an IC according to an example embodiment of the inventive concept. For example, the computer-readable storage medium 500 may store the location and routing program 510 including any instructions for performing all or a portion of the methods described above with reference to the figures. Library 520 may include information about standard cells that are cells included in an IC.

The analysis program 530 may include a plurality of instructions for performing a method of analyzing an IC based on data defining the IC. The data structure 540 may include a memory space for managing data generated during a process of using standard cell libraries in the library 520, extracting tag information from general standard cell libraries in the library 520, or analyzing timing characteristics of ICs performed by the analysis program 530.

Fig. 24 is a block diagram illustrating a memory card 1000 including an IC according to some example embodiments.

Referring to fig. 24, in the memory card 1000, the controller 1100 and the memory 1200 may be configured to exchange electric signals, for example, through a bus. For example, the memory 1200 may transmit data when instructed by the controller 1100.

The controller 1100 and the memory 1200 may include ICs according to example embodiments of the inventive concepts. In particular, in at least one semiconductor device among the plurality of semiconductor devices in the controller 1100 and the memory 1200, at least one wire may be skipped by forming a single node. A single node may be formed by electrically connecting at least two first contacts extending in a first direction (e.g., Y-direction), a second contact extending in a second direction (e.g., X-direction) perpendicular to the first direction, and at least one wire extending in the first direction.

The memory card 1000 may be one selected from various types of memory cards such as a memory stick card, a Smart Media (SM) card, a Secure Digital (SD) card, a mini SD card, and a multimedia card (NMC).

Fig. 25 is a block diagram illustrating a computing system 2000 that includes an IC, according to some example embodiments.

Referring to fig. 25, a computing system 2000 may include a processor 2100, a memory device 2200, a storage device 2300, a power source 2400, and an input/output (I/O) device 2500. Although not shown in fig. 25, the computing system 2000 may additionally include ports for communicating with video cards, sound cards, memory cards, USB devices, or other electronic devices.

The processor 2100, the memory device 2200, the storage device 2300, the power source 2400, and the I/O device 2500 included in the computing system 2000 may include ICs according to example embodiments of the inventive concepts. In particular, in at least one semiconductor device among a plurality of semiconductor devices among the processor 2100, the memory device 2200, the memory device 2300, the power source 2400, and the I/O device 2500, at least one wire may be skipped by forming a single node. A single node may be formed by electrically connecting at least two first contacts extending in a first direction (e.g., Y-direction), a second contact extending in a second direction (e.g., X-direction) perpendicular to the first direction, and at least one wire extending in the first direction.

The processor 2100 may perform desired (or, alternatively, predetermined) computations or tasks. According to an example embodiment, the processor 2100 may be a microprocessor or a Central Processing Unit (CPU). The processor 2100 may communicate with the memory device 2200, the memory device 2300, and the I/O device 2500 through a bus 2600, such as an address bus, a control bus, and a data bus. According to some example embodiments, the processor 2100 may be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The storage 2200 may store data necessary for the operation of the computing system 2000. For example, the memory device 2200 may be a Dynamic Random Access Memory (DRAM), a mobile DRAM, a Static RAM (SRAM), a phase change RAM (PRAM), a Ferroelectric RAM (FRAM), a Resistive RAM (RRAM), and/or a Magnetoresistive RAM (MRAM). The storage device 2300 may include a Solid State Drive (SSD), a Hard Disk Drive (HDD), and a CD-ROM.

The I/O device 2500 may include input devices such as a keyboard, a keypad, and a mouse, and output devices such as a printer and a display. Power supply 2400 may provide an operating voltage required for operation of computing system 2000.

ICs according to example embodiments may be assembled into various types of packages. For example, at least some components of the IC may be mounted using packages such as package on package (PoP), ball Grid Array (BGA), chip Scale Package (CSP), plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), chip in wafer package (Die in Waffle Pack), die on chip (Die in Wafer Form), chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Package (MQFP), thin Quad Flat Package (TQFP), small Outline Integrated Circuit (SOIC), shrink Small Outline Package (SSOP), thin Small Outline Package (TSOP), system In Package (SIP), multi-chip package (MCP), wafer level preparation package (WFP), and wafer level stacking process package (WSP).

While example embodiments of the inventive concepts have been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit comprising at least one cell, the integrated circuit comprising, for each of the at least one cell:

a plurality of wires extending in a first direction and parallel to each other in a second direction, the second direction being perpendicular to the first direction;

a first contact at a respective one of both sides of at least one wire of the plurality of wires and including a first left contact between the first wire of the plurality of wires and the at least one wire; and

and a second contact on the at least one wire and the first contact, the second contact being electrically connected to the at least one wire and the first contact and being physically separated from the first wire and not electrically connected to the first wire, such that the second contact, the at least one wire and the first contact form a single node.

2. The integrated circuit of claim 1, wherein the first contact extends in a first direction and the second contact extends in a second direction.

3. The integrated circuit of claim 1, wherein the second contact extends in a direction perpendicular to the first contact.

4. The integrated circuit of claim 1, wherein,

the at least one cell further includes a first active region and a second active region having different conductivity types, wherein,

the second contact is on at least a selected one of the first active region and the second active region.

5. The integrated circuit of claim 4, wherein,

the plurality of wires respectively correspond to the plurality of gate electrodes,

the number of first transistors in the first active region is less than the number of second transistors in the second active region.

6. The integrated circuit of claim 4, wherein,

the number of first transistors in the first active region is equal to or greater than the number of second transistors in the second active region.

7. The integrated circuit of claim 4, wherein,

the at least one cell further includes a plurality of fins extending in the second direction in the first active region and the second active region, the plurality of fins being parallel to each other in the first direction.

8. The integrated circuit of claim 7, wherein,

the plurality of fins respectively correspond to a plurality of fin transistors,

the first number of the plurality of fin transistors in the first active region is less than the second number of the plurality of fin transistors in the second active region.

9. The integrated circuit of claim 7, wherein,

the first number of the plurality of fin transistors in the first active region is equal to or greater than the second number of the plurality of fin transistors in the second active region.

10. The integrated circuit of claim 4, the integrated circuit further comprising:

a cut region between the first active region and the second active region, the cut region configured to insulate the at least one wire from a single node in the second active region.

11. The integrated circuit of claim 1, wherein,

the at least one wire includes a second wire and a third wire, the third wire being at a first side of the second wire, the first contact further including a first right contact, the first left contact being at a second side of the second wire, the first right contact being at a first side of the third wire.

12. The integrated circuit of claim 11, wherein the second contact is on and electrically connected to the first left contact, the first right contact, the second wire, and the third wire.

13. The integrated circuit of claim 11, wherein the first contact further comprises:

a first center contact between the second wire and the third wire.

14. The integrated circuit of claim 13, wherein the second contact is on and electrically connected to the first left contact, the first right contact, the first center contact, the second wire, and the third wire.

15. The integrated circuit of claim 1, wherein,

the plurality of wires further includes a second wire and a third wire, the first wire to the third wire being adjacent to each other,

the first contact further includes a first right contact, the first left contact being between the first wire and the second wire, the first right contact being between the second wire and the third wire,

the length of the second contact in the second direction is greater than the distance between the first left contact and the first right contact and less than the distance between the first wire and the third wire.

16. The integrated circuit of claim 1, wherein the respective lengths of the first contacts in the second direction are less than a space between two adjacent wires of the plurality of wires.

17. The integrated circuit of claim 1, wherein,

the first contacts have the same length in the first direction,

the first contact and the second contact form an H-shaped jumper.

18. The integrated circuit of claim 1, wherein,

the first contacts have different lengths in a first direction,

the first contact and the second contact form an L-shaped jumper.

19. A semiconductor device, the semiconductor device comprising:

a substrate including a first active region and a second active region, the first active region and the second active region having different conductivity types;

and a second contact on the at least one wire and on the first contact in at least one of the first active region and the second active region, the second contact being electrically connected to the at least one wire and the first contact and being physically separated from the first wire and not electrically connected to the first wire, such that the second contact, the at least one wire, and the first contact form a single node.

20. The semiconductor device of claim 19, wherein,

the first number of transistors in the first active region is less than the second number of transistors in the second active region.

21. The semiconductor device of claim 19, wherein,

the first number of transistors in the first active region is equal to or greater than the second number of transistors in the second active region.

22. A standard cell library stored in a non-transitory computer readable storage medium, the standard cell library comprising information related to at least one standard cell, the at least one standard cell comprising:

a first active region and a second active region, the first active region and the second active region having different conductivity types,

a plurality of fins parallel to each other in the first active region and the second active region;

a plurality of wires extending in a first direction and parallel to each other in a second direction, the second direction being perpendicular to the first direction, over the plurality of fins;

And a second contact electrically connected to the at least one wire and the first contact located in at least one of the first active region and the second active region and physically separated from the first wire and not electrically connected to the first wire, such that the second contact, the at least one wire, and the first contact form a single node in at least one of the first active region and the second active region.

23. The standard cell library of claim 22, wherein the plurality of fins extend in a second direction.

24. A semiconductor device, the semiconductor device comprising:

a substrate;

a plurality of gate electrodes disposed on the substrate and including a first gate electrode, a second gate electrode, and a third gate electrode, the second gate electrode being disposed between the first gate electrode and the third gate electrode;

a first contact disposed between the first gate electrode and the second gate electrode;

a second contact disposed between the second gate electrode and the third gate electrode;

a third contact disposed on the first contact, the second gate electrode, and the second contact and configured to be electrically connected to the first contact, the second gate electrode, and the second contact,

wherein the third contact contacts the first contact, the second gate electrode and the second contact, an

The third contact is configured to be physically separated from and not electrically connected to the first gate electrode and the third gate electrode.

25. The semiconductor device of claim 24, wherein a width of the first contact is the same as a width of the second contact.

26. The semiconductor device of claim 24, wherein a width of the first contact is different than a width of the second contact.

27. The semiconductor device of claim 24, wherein a length of the first contact is the same as a length of the second contact.

28. The semiconductor device of claim 24, wherein a length of the first contact is different from a length of the second contact.

29. The semiconductor device of claim 24, wherein the plurality of gate electrodes further comprises a fourth gate electrode disposed between the first contact and the second gate electrode,

the third contact is electrically connected to the fourth gate electrode.

30. The semiconductor device according to claim 29, further comprising a fourth contact disposed between the fourth gate electrode and the second gate electrode, the fourth contact being electrically connected to the third contact.

31. A semiconductor device, the semiconductor device comprising:

A substrate;

a plurality of gate electrodes disposed on the substrate and including a first gate electrode, a second gate electrode disposed between the first gate electrode and the third gate electrode, a third gate electrode disposed between the second gate electrode and the fourth gate electrode;

a second contact disposed between the third gate electrode and the fourth gate electrode;

a third contact disposed on the first contact, the second gate electrode, the third gate electrode, and the second contact and configured to be electrically connected to the first contact, the second gate electrode, the third gate electrode, and the second contact,

wherein the third contact contacts the first contact, the second gate electrode, the third gate electrode and the second contact,

the third contact is configured to be physically separated from and not electrically connected to the first gate electrode and the fourth gate electrode.

32. The semiconductor device of claim 31, wherein a width of the first contact is the same as a width of the second contact.

33. The semiconductor device of claim 31, wherein a width of the first contact is different than a width of the second contact.

34. The semiconductor device of claim 31, wherein a length of the first contact is the same as a length of the second contact.

35. The semiconductor device of claim 31, wherein a length of the first contact is different from a length of the second contact.

36. A semiconductor device, the semiconductor device comprising:

a substrate including a first active region and a second active region;

a plurality of first fins disposed in the first active region;

a plurality of second fins disposed in the second active region;

a first contact provided between the first gate electrode and the second gate electrode, and provided on the first active region, and connecting a transistor having the first gate electrode as a gate electrode and the first active region as an active region and a transistor having the second gate electrode as a gate electrode and the first active region as an active region;

a second contact disposed between the third gate electrode and the fourth gate electrode and on the first active region, and connecting a transistor having the third gate electrode as a gate electrode and the first active region as an active region and a transistor having the fourth gate electrode as a gate electrode and the first active region as an active region;

A third contact disposed between the first gate electrode and the second gate electrode and on the second active region, and connecting a transistor having the first gate electrode as the gate electrode and the second active region as the active region and a transistor having the second gate electrode as the gate electrode and the second active region as the active region;

a fourth contact disposed between the third gate electrode and the fourth gate electrode and on the second active region, and connecting a transistor having the third gate electrode as a gate electrode and the second active region as an active region and a transistor having the fourth gate electrode as a gate electrode and the second active region as an active region;

a fifth contact disposed on the first contact, the second gate electrode, the third gate electrode, and the second contact, and configured to be electrically connected to the first contact, the second gate electrode, the third gate electrode, and the second contact; and

a cutting region disposed between the first active region and the second active region, configured to electrically insulate the second gate electrode on the second active region from the second gate electrode on the first active region, and configured to electrically insulate the third gate electrode on the second active region from the third gate electrode on the first active region,

Wherein the fifth contact is configured to be physically separated from and not electrically connected to the first gate electrode and the fourth gate electrode,

the fifth contact contacts the first contact, the second gate electrode, the third gate electrode, and the second contact.

37. The semiconductor device according to claim 36, further comprising a sixth contact disposed between the second gate electrode and the third gate electrode, the sixth contact being electrically connected to the fifth contact.

38. An integrated circuit, the integrated circuit comprising:

at least one unit comprising:

a first contact at a respective one of both sides of at least one wire of the plurality of wires; and

a second contact on the at least one wire and the first contact, the second contact electrically connected to the at least one wire and the first contact such that the second contact, the at least one wire and the first contact form a single node,

wherein the first contact has one of the following: (i) The same length in the first direction such that the first contact and the second contact form an H-shaped jumper and (ii) different lengths in the first direction such that the first contact and the second contact form an L-shaped jumper.