TWI627419B - Display panel testing system and display panel testing method - Google Patents

Abstract

A display panel test system includes a test terminal display substrate, a test terminal display substrate, a driving chip, and a test terminal interface circuit. The test-end display substrate includes a display area and a non-display area. The display substrate under test also includes a display area and a non-display area. The driving chip is disposed in a non-display area of the display substrate of the test terminal, and is used for generating a first test signal according to a test instruction. The test terminal interface circuit is disposed in a non-display area of the display substrate of the test terminal, and is used for receiving the first test signal and for outputting the first test signal to the display substrate of the test terminal, so that the display area of the display substrate of the test terminal displays the first A test pattern.

Description

Display panel test system and display panel test method

The present disclosure relates to a test system and a related test method, and more particularly to a display panel test system and a display panel test method.

The current practice of the lighting test of the display panel in the industry is to set the test chip on a special circuit board tailored for the test chip, and then cooperate with flexible printed circuit (FPC) and flexible printed circuit adapter board. (FPC adapter) and probe fixtures output test signals generated by the test chip to the display panel to be tested.

However, the manufacturing of the aforementioned dedicated circuit board requires the use of an additional process mask, thereby reducing the application flexibility of the conventional panel test system. In addition, the aforementioned flexible printed circuit and flexible printed circuit adapter board for outputting test signals will increase the overall circuit complexity, thereby increasing the probability of failure of the conventional panel test system during the test.

In view of this, how to provide a simplified architecture and high application flexibility The display panel test system and display panel test method are really problems to be solved in the industry.

A display panel test system includes a test end display substrate, a test end display substrate, a driving chip, and a test end interface circuit. The test-end display substrate includes a display area and a non-display area. The display substrate under test includes a display area and a non-display area. The driving chip is disposed in a non-display area of the display substrate of the test terminal, and is used for generating at least one test signal according to a test instruction. The test terminal interface circuit is disposed in a non-display area of the display substrate of the test terminal, for receiving the at least one test signal, and for outputting the at least one test signal to the display substrate of the test terminal, so that the display area of the display substrate of the test terminal The first test pattern is displayed.

A display panel test method includes the following steps. Provide test terminal display substrate and test terminal display substrate. The driving chip is arranged on a non-display area of the display substrate on the test end. Enter a test command to the driver chip. The driving chip is used to generate at least one test signal according to the test instruction. The test terminal interface circuit is used to receive at least one test signal. The test terminal interface circuit is disposed in a non-display area of the test terminal display substrate. The test terminal interface circuit is used to output at least one test signal to the display substrate under test. The first test pattern is displayed on the display area of the display substrate of the terminal under test.

100‧‧‧display panel test system

101‧‧‧Control circuit

110‧‧‧test terminal display substrate

112‧‧‧Display area

114‧‧‧ Non-display area

116‧‧‧Gate driving circuit

120‧‧‧ Display board under test

122‧‧‧display area

124‧‧‧non-display area

126‧‧‧Gate driving circuit

130‧‧‧Driver

140‧‧‧test terminal interface circuit

142‧‧‧Select Unit

144‧‧‧connection unit

150‧‧‧Interface circuit under test

152‧‧‧Select Unit

154‧‧‧connection unit

210‧‧‧Test terminal switch

220‧‧‧Test end connection pad

230‧‧‧ switch under test

240‧‧‧ test pad

300‧‧‧Display Panel Test System

310‧‧‧Test terminal display substrate

320‧‧‧laser cutting area

CT1‧‧‧first control signal

CT2‧‧‧Second control signal

CTL‧‧‧Scan control signal combination

DATA‧‧‧Data Signal Combination

TCM‧‧‧Test Instructions

TEST‧‧‧test signal

In order to make the above and other objects, features, advantages, and embodiments of the disclosure document more comprehensible, the description of the drawings is as follows: FIG. 1 is a simplified functional block diagram of a display panel test system according to an embodiment of the present disclosure.

FIG. 2 is a partially enlarged schematic diagram of the display panel test system of FIG. 1.

FIG. 3 is a simplified functional block diagram of a display panel test system according to another embodiment of the present disclosure.

FIG. 4 is a simplified flowchart of a display panel test method according to an embodiment of the disclosure.

Hereinafter, embodiments of the present invention will be described with reference to related drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a display panel test system 100 according to an embodiment of the present disclosure. The display panel test system 100 includes a test-end display substrate 110, a test-end display substrate 120, a driving chip 130, a test-end interface circuit 140, and a test-end interface circuit 150. The display panel test system 100 can operate according to a test command TCM generated by a control circuit 101 to test whether the display function of the display substrate 120 on the terminal under test is normal. In order to make the drawing simple and easy to explain, other components and connection relationships in the display panel test system 100 are not shown in the first figure.

In the embodiment of FIG. 1, the test-end display substrate 110 includes a display area 112, a non-display area 114, and a gate driving circuit 116. The gate driving circuit 116 can be used to drive pixels in the display area 112 (not shown in the figure). The driving chip 130 and the test terminal interface circuit 140 may be disposed in the non-display area 114, and the test terminal interface circuit 140 includes A selection unit 142 and a connection unit 144. The driving chip 130 is configured to generate a plurality of test signals TEST, a first control signal CT1, and a second control signal CT2 according to a test command TCM transmitted from the control circuit 101.

The display substrate 120 under test includes a display area 122, a non-display area 124 and a gate driving circuit 126. The gate driving circuit 126 can be used to drive pixels in the display area 122 (not shown in the figure). The test terminal interface circuit 150 may be disposed in the non-display area 124.

In practice, the driving chip 130 may be a source driver in the display device for providing a data signal, and a timing controller for providing a system voltage or a clock signal required by the display device. In addition, the driving chip 130 may be provided on the test-end display substrate 110 by a chip-on-film, chip-on-glass, or wire bond method.

Also. The plurality of test signals TEST may include positive and negative polarity data signals for lighting the display areas 112 and / or 122, scanning control signals for driving the gate driving circuits 116 and / or 126, and driving touch panels (not shown). (Illustrated in the figure) a sensing signal of the sensing line and a multiplexing control signal of a multiplexer (not shown in the figure) connected to the source signal line for controlling the display area 112 and / or 122.

In addition, the control circuit 101 may be implemented using various microprocessors, application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). The test command TCM may be a signal combination including a test start signal and one or more clock signals.

The selection unit 142 of the test end interface circuit 140 is used for receiving The foregoing plurality of test signals TEST are used to select a data signal combination DATA required for testing from the plurality of test signals TEST and select from the plurality of test signals TEST according to the first and second control signals CT1 and CT2. The scan control signal combination CTL required for the test.

The connection unit 144 of the test-end interface circuit 140 is configured to receive the first and second control signals CT1 and CT2 from the control chip 130 and the data signal combination DATA and the scan control signal combination CTL from the selection unit 142. The connection unit 144 is further configured to output the first control signal CT1, the second control signal CT2, the data signal combination DATA, and the scan control signal combination CTL to the connection unit 154 of the test-end interface circuit 150.

The connecting unit 154 is configured to output the received first control signal CT1, second control signal CT2, test data signal DATA, and scan control signal combination CTL to the selection unit 152. The selection unit 152 is configured to output the data signal combination DATA and the scan control signal combination CTL to the display area 122 and the gate driving circuit 126 according to the first and second control signals CT1 and CT2, respectively. Therefore, the gate driving circuit 126 of the display substrate 120 under test starts to drive the display area 122 according to the scan control signal combination CTL, and the display area 122 displays a first test pattern according to the data signal combination DATA.

On the other hand, the selection unit 142 of the test-end display substrate 110 also outputs the data signal combination DATA and the scan control signal combination CTL to the display area 112 and the gate driving circuit 116, respectively. Therefore, the gate driving circuit 116 of the test-end display substrate 110 will start to drive the display area 112 based on the scan control signal combination CTL, and the display area 112 will be based on the data signal. No. combination DATA displays a second test pattern.

Since the display areas 112 and 122 perform display operations based on the data signal combination DATA, the second test pattern of the display area 112 will correspond to the first test pattern of the display area 122. The correspondence may be that the images of the first test pattern and the second test pattern are substantially equal. In this way, by comparing the first test pattern and the second test pattern, it can be determined whether the function of the display substrate 120 at the terminal under test is normal.

In the display regions 112 and 122 of this embodiment, the source signal lines of the sub-pixels of the same color are all electrically coupled to each other. That is, the source signal lines of all red sub-pixels are electrically coupled to each other, the source signal lines of all blue sub-pixels are electrically coupled to each other, and the source signal lines of all green sub-pixels are electrically coupled to each other. Pick up. Therefore, the data signal combination DATA may include at least six data signals, that is, the display regions 112 and 122 of any resolution can be illuminated in a manner of polarity reversal.

In detail, three of the aforementioned at least six data signals may be positive data signals, which are respectively used to light up the red, green, and blue sub-pixels in the display regions 112 and 122 that are in a positive driving cycle. The other three of the aforementioned at least six data signals may be negative data signals, which are respectively used to light up the red, green, and blue sub-pixels in the display regions 112 and 122 in a negative driving cycle. In this way, the display panel test system 100 can drive all the sub-pixels in the display areas 112 and 122 by using the driving method of inverting the polarity.

Please note that the number and type of data signals included in the aforementioned data signal combination DATA are only exemplary embodiments, and users can follow The actual demand adjusts the number and type of data signals included in the data signal combination DATA.

For example, in an embodiment, the display regions 112 and 122 include red, green, blue, and white sub-pixels, and the data signal combination DATA may include at least eight data signals. Among them, four of the at least eight data signals are used to light up the red, green, blue, and white sub-pixels in the positive driving cycle, respectively. The other four data signals among the at least eight data signals are used to light up the red, green, blue, and white sub-pixels in the negative driving cycle, respectively.

In the embodiment of FIG. 1, the test-end display substrate 110 and the test-end display substrate 120 are manufactured according to the same circuit layout. In other words, the display area 112 and the display area 122 have the same resolution and the same sub-pixel arrangement.

In one embodiment, the test-end display substrate 110 and the test-end display substrate 120 may be manufactured according to different circuit layout diagrams, so as to omit the test-end interface circuit 126 of the test-end display substrate 120. That is, the test terminal interface circuit 140 can be electrically coupled between the driving chip 130 and the display area 122, and can directly output the data signal combination DATA and the scan control signal combination CTL to the display area 122 and the gate driving circuit 126, respectively. , So that the display area 122 displays the first test pattern.

In another embodiment, the test-end display substrate 110 and the test-end display substrate 120 refer to a substrate below the display device, that is, a substrate provided with an array layer. The display area 122 and the gate driving circuit 126 of the display substrate 120 under test can also be covered by an upper substrate, and The display area 112 may be covered by an upper substrate.

FIG. 2 is a partially enlarged schematic diagram of the display panel test system 100 of FIG. 1. As shown in FIG. 2, in the test terminal interface circuit 140, the selection unit 142 includes a plurality of test terminal switches 210, and the connection unit 144 includes a plurality of test terminal connection pads 220 (connection pads). One end of each test-end switch 210 is electrically coupled to a corresponding one of the test-end connection pads 220, and the other end of each test-end switch 210 is used to receive one of a plurality of test signals TEST.

In the DUT interface circuit 150, the selection unit 152 includes a plurality of DUT switches 230, and the connection unit 154 includes a plurality of DUT connection pads 240. One end of each switch under test 230 is electrically coupled to a corresponding one of the connection pads 240 under test, and the other end of each switch 230 under test is electrically coupled to the display area 122 or the gate driving circuit. 126.

The first control signal CT1 is used to control a switching operation of a part of the test-end switch 210 and the test-end switch 230. That is, the gate ends of some of the test-end switch 210 and the test-end switch 230 are used to receive the first control signal CT1. The second control signal CT2 is used to control the switching operation of the remaining test-end switch 210 and the test-end switch 230. That is, the gate terminals of the remaining test-end switch 210 and the test-end switch 230 are used to receive the second control signal CT2.

When the first control signal CT1 turns on part of the test-end switch 210 and the switch under test 230, the second control signal CT2 turns off the remaining test-end switch 210 and the switch under test 230. By setting the first control signal CT1 and the second control signal CT2, the test-end switch 210 and the test-end switch 230 can be used to select a test signal combination DATA from a plurality of test signals TEST. Combines CTL with scan control signals.

In detail, when the first control signal CT1 turns on the part of the test-end switch 210 and the switch under test 230, the part of the test-end switch 210 turned on by the first control signal CT1 outputs the data signal combination DATA and the scan control signal combination CTL. To connection unit 144. Then, the test unit connection pad 220 receiving the data signal combination DATA and the scan control signal combination CTL in the connection unit 144 outputs the data signal combination DATA and the scan control signal combination CTL to the connection unit 154. The DUT connection pad 240 receiving the data signal combination DATA and the scan control signal combination CTL in the selection unit 154 outputs the received data signal combination DATA and the scan control signal combination CTL to the selection unit 152. The DUT 230 in the selection unit 152 that is turned on by the first control signal CT1 will output the data signal combination DATA and the scan control signal combination CTL to the display area 122 and the gate driving circuit 126, respectively, so that the display area 122 displays The first test pattern.

On the other hand, the remaining test-end switch 210 and the test-end switch 230 that are turned off by the second control signal CT2 can block some unwanted signals among the plurality of test signals TEST to reduce the output current of the driving chip 130. Therefore, it is possible to reduce the chance that the driving chip 130 is damaged due to excessive output current.

In an embodiment, the test-end display substrate 110 and the test-end display substrate 120 are provided with a double-side gate driving circuit. The first control signal CT1 and the second control signal CT2 can be used not only to reduce the output current of the driving chip 130 but also to select a gate driving circuit to be tested. For example, when the first control signal CT1 turns on the test-end switch 210 and the switch under test At 230, the control signal combination CTL is output to a gate driving circuit of the display substrate 110 at the test end and a gate driving circuit of the display substrate 120 at the test end. When the second control signal CT2 turns on the remaining test-end switch 210 and the test-end switch 230, the control signal combination CTL is output to another gate driving circuit of the test-end display substrate 110, and the output of the control signal combination CTL to the test-end display substrate 120. Another gate drive circuit.

In another embodiment, the test-end connection pad 220 of the test-end interface circuit 140 and the test-end connection pad 240 of the test-end interface circuit 150 are connected to each other using a jig equipped with a metal probe.

In another embodiment, in order to ensure that the plurality of test signals TEST output by the test terminal interface circuit 140 have sufficient driving capability, a buffer amplifier circuit is electrically coupled between the test terminal interface circuit 140 and the terminal interface circuit 150 to be tested. The buffer amplifier circuit can be implemented on a printed circuit board (PCB) by an even-numbered inverter.

In yet another embodiment of the display panel test system 100 of the present invention, the backlight unit (not shown) of the test-end display substrate 110 and / or the test-end display substrate 120 may be in a lit state.

In practice, the test-end switch 210 and / or the test-end switch 230 can be implemented by using an n-type MOS transistor or a p-type MOS transistor.

FIG. 3 is a simplified functional block diagram of a display panel test system 300 according to another embodiment of the present disclosure. The display panel test system 300 is similar to the display panel test system 100. The difference is that the test substrate of the display panel test system 300 of the display panel test system 300 will be additionally exposed to lightning when the manufacturing is completed. Laser cutting disconnects the electrical connection between the display area 112 and the driving chip 130, and disconnects the electrical connection between the gate driving circuit 116 and the driving chip 130. Therefore, the test-end display substrate 310 may include a laser cutting area 320, and the laser cutting area 320 is located between the display area 112 and the driving chip 130.

In other words, in the embodiment of FIG. 3, the selection unit 142 of the test terminal interface circuit 140 only outputs the data signal combination DATA and the scan control signal combination CTL to the connection unit 144, and does not combine the data signal with DATA and scan control. The signal combination CTL is output to the display area 112 and the gate driving circuit 116, respectively. Therefore, the display area 112 does not display any test patterns during the test in this embodiment.

Since the laser cutting region 320 disconnects the electrical connection between the display region 112 and the gate driving circuit 116 and the driving chip 130, the display panel test system 300 can further reduce the output current of the driving chip 130 during the test. Therefore, compared with the embodiment shown in FIG. 1, the display panel test system 300 can further reduce the probability that the driving chip 130 is damaged due to excessive output current.

The description of the operations, implementation modes, variations, and related advantages of other corresponding functional blocks in the embodiment of FIG. 1 is also applicable to the embodiment of FIG. 3. For brevity, the description is not repeated here.

FIG. 4 is a simplified flowchart of a display panel test method according to an embodiment of the disclosure. As shown in FIG. 4, in the process s402, a test-end display substrate 110 and a test-end display substrate 120 may be provided. The test-end display substrate 110 includes a display area 112 and a non-display area. The field 114 and a gate driving circuit 116, the display substrate 120 under test includes a display area 122, a non-display area 124 and a gate driving circuit 126.

In the process s404, a driving chip 130 may be set in the non-display area 114 of the test-end display substrate 110.

Then, in process s406, a test command TCM can be input to the driving chip 130.

In process s408, the driving chip 130 may be used to generate a plurality of test signals TEST according to the aforementioned test instruction TCM, and generate a first control signal CT1 and a second control signal CT2.

In the process s410, a test terminal interface circuit 140 disposed in the non-display area 114 of the test terminal display substrate 110 can receive a plurality of test signals TEST, a first control signal CT1, and a second control signal CT2.

In process s412, the test-end interface circuit 140 can be used to select the data signal combination DATA and the scan control signal combination CTL required for the test from the plurality of test signals TEST according to the first control signal CT1 and the second control signal CT2.

Then, in the process s414, a DUT interface circuit 150 provided in the non-display area 124 of the DUT 120 is used to receive the data signal combination DATA and the scan control signal combination CTL.

In the process s416, the display area 122 and the gate driving circuit 126 of the display substrate 120 under test can be used to receive the data signal combination DATA and the scan control signal combination CTL from the test interface interface 150, respectively.

In flow s418, a first test pattern is displayed using the display area 122 according to the data signal combination DATA.

Then, in process s420, the display signal region 122 of the test-end display substrate 110 can be used to receive the data signal combination DATA, and the gate drive circuit 116 of the test-end display substrate 110 can be used to receive the scan control signal combination CTL.

In flow s422, a second test pattern is displayed using the display area 112 according to the data signal combination DATA. The second test pattern in the display area 112 will correspond to the first test pattern in the display area 122. The correspondence may be that the images of the first test pattern and the second test pattern are substantially equal.

Please note that the sequence of execution of the processes in FIG. 4 is only an exemplary embodiment, and does not limit the actual implementation of the present invention.

For example, in one embodiment, when the processes s414 to s418 are executed, the processes s420 to s422 may be executed together.

For another example, in another embodiment, after the execution of the process s402, the display area 112 of the test-end display substrate 110 can be disconnected by laser cutting, and the circuit electrically connected to the control chip 130 can be disconnected, and the test can be disconnected. The gate driving circuit 116 of the end display substrate 110 can be electrically connected to the circuit of the control chip 130. In this case, the display area 112 will not display the aforementioned second test pattern.

From the foregoing, it can be known that the display panel test systems 100 and 300 set the driving chip 130 on the test-side display substrates 110 and 310, and the test-side display substrates 110 and 310 can be based on the same circuit layout diagram as the display-side display substrate 120 on the test side Made by. Therefore, compared with traditional display panel test systems, the display panel test systems 100 and 300 only need to be manufactured to be tested. The manufacturing process of the end display substrate 120 does not need to use an additional process to make a printed circuit board to set a driving chip.

In addition, the test-end display substrates 110 and 310 of the display panel test systems 100 and 300 can be used repeatedly. Therefore, when testing multiple display substrates, it is only necessary to sequentially set the multiple display substrates as the display substrates 120 to be tested for testing, so that the application has high convenience and flexibility.

In addition, the selection units 142 and 152 of the display panel test systems 100 and 300 and the laser cutting area 320 of the display panel test system 300 can limit the output current of the driving chip 130. Therefore, the display panel test systems 100 and 300 can reduce the chance of damage to the driving chip 130 due to excessive output current during the test, thereby achieving the effect of protecting the driving chip 130.

Certain terms are used in the description and the scope of patent applications to refer to specific elements. However, it should be understood by those with ordinary knowledge in the technical field that the same elements may be referred to by different names. The scope of the specification and patent application does not take the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a basis for distinguishing. "Inclusion" mentioned in the specification and the scope of patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "electrical coupling" includes any direct and indirect connection means. Therefore, if the first element is described as being electrically coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or through other elements The connecting means is electrically or signally connected to the second element indirectly.

"And / or" used herein, including Any combination of one or more of these items. In addition, unless otherwise specified in the description, the terms of any singular number also include the meaning of the plural number.

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

A display panel test system includes: a test-end display substrate including a display area and a non-display area; a test-end display substrate including a display area and a non-display area; a driving chip disposed on the test end The non-display area of the display substrate is used to generate at least one test signal according to a test instruction; and a test terminal interface circuit is disposed in the non-display area of the test terminal display substrate to receive the at least one test signal and use The at least one test signal is output to the display substrate of the terminal under test, so that the display area of the display substrate of the terminal under test displays a first test pattern. The display panel test system according to claim 1, wherein the test terminal interface circuit is further configured to output the at least one test signal to the display area of the test terminal display substrate, so that the test terminal displays the display of the display substrate. The area displays a second test pattern corresponding to the first test pattern. The display panel test system according to claim 1, wherein the test terminal interface circuit includes: a selection unit for receiving the at least one test signal and outputting the first test signal according to a first control signal (CT1) And a connection unit coupled to the selection unit for outputting the at least one test signal from the selection unit to the display substrate on the terminal under test. The display panel test system according to claim 3, wherein the selection unit includes: a plurality of switches, one end of the switches is used to receive the at least one test signal, and a control end of some of the switches is used to receive the A first control signal, and the part of the switches output the at least one test signal according to the first control signal. The display panel test system according to claim 1, further comprising: an interface circuit under test to be disposed in the non-display area of the display substrate of the terminal under test to receive the at least one test from the interface circuit under test. And is used to output the at least one test signal to the display area of the display substrate of the terminal under test. The display panel test system according to claim 5, wherein the interface circuit under test includes: a connection unit for receiving the at least one test signal from the interface circuit of the test terminal; and a selection unit for selecting from the test interface circuit. The connection unit receives the at least one test signal and is used to output the at least one test signal to the display area of the display substrate of the terminal under test according to a first control signal. For example, the display panel test system of claim 1, wherein the driving chip is set in the test in a chip-on-film, chip-on-glass, or wire bond manner. The non-display area of the end display substrate. A display panel test method includes: providing a test-end display substrate and a test-end display substrate; setting a driving chip in a non-display area of the test-end display substrate; inputting a test instruction to the driving chip; and using the driving The chip generates at least one test signal according to the test instruction; receives the at least one test signal by using a test terminal interface circuit, wherein the test terminal interface circuit is disposed in a non-display area of the test terminal display substrate; and the test terminal interface circuit is used Outputting the at least one test signal to the display substrate of the terminal under test; and using a display area of the display substrate of the terminal under test to display a first test pattern. The display panel testing method according to claim 8, further comprising: using the test terminal interface circuit to output the at least one test signal to the test terminal display substrate; and using a display area of the test terminal display substrate to display a second Test pattern. The method for testing a display panel according to claim 8, wherein the process of outputting the at least one test signal to the display substrate of the terminal under test comprises: using the test terminal interface circuit to perform a test from the at least one test according to a first control signal. A data signal combination and a scan control signal combination are selected from the signals; and the data signal combination and the scan control signal combination are outputted to the display substrate under test by using the test terminal interface circuit.