TWI625078B - Circuit layout structure for esd protection and electronic device using the same - Google Patents

Abstract

The invention provides a circuit layout structure suitable for electrostatic discharge protection of a miniaturized electronic device. The miniaturized electronic device includes a multi-layer circuit board and a plug-in component. The multilayer circuit board includes at least one signal trace layer and at least one ground layer. The plug-in component includes at least one signal pin that is received in at least a consistent aperture of the multilayer circuit board. The circuit layout structure is set in the board. The circuit layout structure includes a closed trace disposed on the signal trace layer of the multilayer circuit board and surrounding at least a uniform aperture of the multilayer circuit board. The closed trace is electrically connected to the ground plane.

Description

Circuit layout structure for electrostatic discharge protection and electronic device using the same

The present invention relates to an electronic device, and more particularly to an electronic device having a circuit layout structure for electrostatic discharge protection.

In recent years, the design of electronic devices has become lighter and thinner, and driven by the booming of wearable electronic devices, the miniaturization of electronic devices has become a research and development direction of various manufacturers. However, while miniaturization, it is also necessary to comply with various regulations of safety regulations, such as electrostatic discharge (Electrostatic Discharge) protection, which is a problem that needs to be specially considered in today's miniaturized electronic devices, especially wearable electronic devices, because wear Electronic devices are worn by people in certain parts of the body. When the human body is rubbed, a large amount of static electricity is generated, which has a direct and obvious influence on the wearable electronic device. In general, an electronic device is provided with an electrostatic discharge protection element for protection against electrostatic discharge. However, in the case of miniaturization, various electronic components are densely disposed on a circuit board, and sometimes it is difficult to provide an electrostatic discharge protection element due to space limitations.

Therefore, how to use the circuit layout structure to protect against electrostatic discharge has become one of the important topics in the industry.

In view of this, the present invention provides a circuit layout structure suitable for electrostatic discharge protection of a miniaturized electronic device. The miniaturized electronic device includes a multi-layer circuit board and A plug-in component. The multilayer circuit board includes at least one signal trace layer and at least one ground layer. The plug-in component includes at least one signal pin that is received in at least a consistent aperture of the multilayer circuit board. The circuit layout structure is set in the board. The circuit layout structure includes a closed trace disposed on the signal trace layer of the multilayer circuit board and surrounding at least a uniform aperture of the multilayer circuit board. The closed trace is electrically connected to the ground plane.

Wherein the closed trace comprises at least one turning region, the turning region being greater than 90 degrees or having a circular arc.

The first grounding through hole is disposed in the at least one turning region of the closed annular wire, and the closed wire is electrically connected to the grounding layer through the first grounding through hole.

The closed trace includes at least a straight line region, a second ground through hole, a third ground through hole and a fourth ground through hole are disposed in at least a straight line region of the closed trace, and the second ground through hole and the third ground through The first distance of the hole is the same distance as the second distance of the third grounding through hole and the fourth grounding through hole, and the closed wire passes through the second grounding through hole, the third grounding through hole and the fourth grounding through hole Connect the ground plane.

Among them, the line width of the closed trace is greater than or equal to 6 mils.

Wherein the closed trace is at least one distance from the consistent hole greater than 5 mils.

The plug-in component includes a fixed pin, and the fixed pin of the plug-in component is electrically connected to a grounding region through a passive component.

Among them, the closed trace is a circular curve.

Among them, the closed trace is a trace with a large area.

The ground layer is adjacent to the signal trace layer.

Embodiments of the present invention provide a miniaturized electronic device. The miniaturized electronic device includes a multi-layer circuit board and a plug-in component. The multilayer circuit board includes a signal trace layer and a ground layer. The plug-in component includes at least one leg. At least one leg of the plug-in component is received in at least a consistent aperture of the multilayer circuit board. A closed trace is disposed on the signal trace layer of the multilayer circuit board, and surrounds at least the consistent hole of the multilayer circuit board, and the closed trace is electrically connected to the ground layer.

Wherein the closed trace includes at least one turning area, and the turning area is greater than 90 degrees or have a circular arc.

The first grounding through hole is disposed in the at least one turning region of the closed annular wire, and the closed wire is electrically connected to the grounding layer through the first grounding through hole.

The closed trace includes at least a straight line region, a second ground through hole, a third ground through hole and a fourth ground through hole are disposed in at least a straight line region of the closed trace, and the second ground through hole and the third ground through The first distance of the hole is the same distance as the second distance of the third grounding through hole and the fourth grounding through hole, and the closed wire passes through the second grounding through hole, the third grounding through hole and the fourth grounding through hole Connect the ground plane.

Among them, the line width of the closed trace is greater than or equal to 6 mils.

Wherein the closed trace is at least one distance from the consistent hole greater than 5 mils.

The plug-in component includes a fixed pin, and the fixed pin of the plug-in component is electrically connected to a grounding region through a passive component.

Among them, the closed trace is a circular curve.

Among them, the closed trace is a trace with a large area.

The ground layer is adjacent to the signal trace layer.

In summary, the circuit layout structure of the embodiment of the present invention can protect a large amount of static electricity by the surrounding arrangement of the closed wiring, the electrical connection to the grounding layer by using the grounding through hole, and the electrical connection to the grounding layer by using the passive component. Through the pin position of the plug-in component to enter other signal traces, in the design of the miniaturized electronic device, not only can it be implemented accurately, but also the manufacturing cost can be effectively reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

1‧‧‧Small electronic device

10‧‧‧First housing

11‧‧‧ second housing

12‧‧‧Multilayer circuit board

13‧‧‧Plug-in components

120‧‧‧ Grounding area

121‧‧‧through holes

122‧‧‧Closed wiring

123‧‧‧First grounding through hole

124‧‧‧Second grounding through hole

125‧‧‧The third grounding through hole

126‧‧‧fourth grounding through hole

128‧‧‧Fixed through holes

129‧‧‧SMD component setting area

122A‧‧‧First Turning Area

122B‧‧‧Second turning area

122C‧‧‧Third turning area

122D‧‧‧Line area

A1‧‧‧ first area

D‧‧‧distance

D1‧‧‧first distance

D2‧‧‧Second distance

D3‧‧‧ third distance

FIG. 1 is a schematic diagram of a miniaturized electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic view showing the routing of each layer of the multilayer circuit board according to an embodiment of the present invention.

3A is a schematic diagram of a bottom trace of a first region of a multilayer circuit board according to an embodiment of the invention.

FIG. 3B is a schematic diagram of a trace of a signal trace layer in a first region of a multilayer circuit board according to an embodiment of the invention.

FIG. 4 is a schematic diagram of another trace of the signal trace layer of the first region of the multilayer circuit board according to the embodiment of the present invention.

FIG. 5 is a schematic diagram of a closed trace according to an embodiment of the present invention.

6 is a schematic diagram of another bottom trace of a first region of a multilayer circuit board according to an embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

The circuit layout structure of the electrostatic discharge protection of the miniaturized electronic device will be described below with reference to at least one embodiment. However, the following embodiments are not intended to limit the disclosure.

[Embodiment of Circuit Layout Structure of Electrostatic Discharge Protection of Miniaturized Electronic Device of the Present Invention]

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a miniaturized electronic device according to an embodiment of the present invention.

The miniaturized electronic device 1 includes a first housing 10, a second housing 11, a multilayer circuit board 12, and a plug-in component 13. The plug-in component 13 is disposed on the multi-layer circuit board 12, and the multi-layer circuit board 12 and the plug-in component 13 are disposed in a receiving space formed by the first housing 10 and the second housing 11.

In the present embodiment, the plug-in component 13 is an input/output port, such as a USB connector. In other embodiments, the plug-in component 13 can be other connectors, and is not limited in the present invention. The multilayer circuit board 12 has a length and width of about 70 mm*100 mm, and the multi-layer circuit board 12 has other electronic components, such as a microprocessor, a memory, a power conversion module, etc., in addition to the plug-in component 13. It is not illustrated and described in the embodiments.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of the routing of each layer of the multilayer circuit board according to an embodiment of the present invention. In this embodiment, the first layer is the top layer, and the 12th layer is the bottom layer. The two layers are generally provided with a plug-in component or a trace layer of the chip component. The second layer, the fifth layer, the eighth layer, and the eleventh layer are ground layers. The third layer, the fourth layer, the sixth layer, the seventh layer, the ninth layer, and the tenth layer are signal routing layers. The seventh layer is the power layer. The main power traces are set at this level.

In this embodiment, each signal routing layer (3rd, 4th, 6th, 7th, 9th, and 10th layers) is provided with a ground layer on the adjacent side (2nd) Layer, Layer 5, Layer 8, and Layer 11). The following describes the signal routing layer with the third layer as an example, and the ground layer with the second layer as an example, and does not repeat the other common function wiring layers.

Please refer to FIG. 3A, FIG. 3B and FIG. 3A is a schematic diagram of a bottom trace of a first region of a multilayer circuit board according to an embodiment of the invention. FIG. 3B is a schematic diagram of a trace of a signal trace layer in a first region of a multilayer circuit board according to an embodiment of the invention. FIG. 4 is a schematic diagram of another trace of the signal trace layer of the first region of the multilayer circuit board according to the embodiment of the present invention.

3A shows a first area A1 of the multilayer circuit board 12, that is, a schematic diagram of the peripheral circuit traces of the plug-in component 13 at the bottom layer. The plug-in component 13 includes a plurality of signal pins (not shown) housed in a plurality of through holes 121 of the first area A1. After being fixed by the tin, the plug-in component 13 can be fixedly disposed on the multilayer circuit board 12.

As shown in FIG. 3B, in the first area A1 of the signal routing layer (Layer 3), a closed trace 122 is disposed around the plurality of through holes 121. Moreover, the closed trace 122 is electrically connected to the ground layer (the second layer) through a first ground via 123. Although the closed trace 122 can be electrically connected to other ground layers (eg, layer 5) through the first ground via 123, however, due to the basic principle of electrostatic discharge protection, a large amount of static electricity is vented in the shortest path. The reason for the shortest path is because the shorter the path, the smaller the impedance of the trace. Therefore, in the present embodiment, the closed trace 122 of the signal trace layer (3rd layer) is electrically connected to the closest ground layer (the second layer) through the first ground via 123. In the embodiment, the first grounding through hole 123 is disposed on a first turning region 122A of the closed wiring 122. In this embodiment, the through holes or the ground through holes are all provided with a conductive material, which can be connected to circuit traces of a specific layer according to electrical connection requirements.

In the present embodiment, the closed trace 122 is an annular trace, wherein the closed trace 122 further includes a second inflection area 122B and a third inflection area 122C. The second turning area 122B is a line having a circular arc lead angle, and the angle of the third turning area 122C is an obtuse angle, that is, greater than 90 degrees. In this embodiment, the turning area of the closed trace 122 is designed to be an obtuse angle or a circular arc lead angle to prevent static electricity from passing through the tip discharge and then entering other signal traces.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a closed trace according to an embodiment of the present invention. The closed trace 122 of the multi-layer circuit board 12 further includes a straight line region 122D. A second ground via hole 124, a third ground via hole 125, and a fourth ground via hole 126 are disposed in the linear region 122D of the closed trace 122. The second ground through hole 124 is disposed at one side of the first ground through hole 123. The distance between the second grounding through hole 124 and the third grounding through hole 125 is a first distance d1, and the distance between the third grounding through hole 125 and the fourth grounding through hole 126 is a second distance d2. The first distance d1 and the second distance d2 are the same.

In addition, the distance between the first ground through hole 123 and the second ground through hole 124 is a third distance d3. The third distance d3 is equal to the first distance d1 and the second distance d2. The first distance d1, the second distance d2, and the third distance d3 may be designed according to actual needs, and the invention is not limited. The closed traces 122 disposed on the signal trace layer (3rd layer) are electrically connected to the ground layer through the first ground vias 123, the second ground vias 124, the third ground vias 125, and the fourth ground vias 126. (Layer 2). In addition, the number of grounding through holes can be designed according to actual needs, and is not limited in the present invention.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of another bottom trace of the first region of the multilayer circuit board according to the embodiment of the present invention.

In the present embodiment, the bottom layer (12th layer) of the multilayer circuit board 12 is a layer in which a chip component or a plug-in component is disposed as described above, and the plug-in component 13 includes a fixed pin (not shown). A fixing pin (not shown) is provided on the outer casing of the card-type component 13 for reinforcing the plug-in component 13 to be fixed to the multilayer circuit board 12. The plug-in component 13 is received in a fixed through hole 128 of the multilayer circuit board 12, and the fixed through hole 128 is electrically connected to a grounding region 120 through at least one chip component mounting region 129. In this embodiment, the grounding region 120 is a grounding via that is connected to the ground plane (layer 2). In the present embodiment, a passive component such as a 0 ohm resistor, a high voltage capacitor or a magnetic component such as a bead may be disposed in the patch component mounting region 129.

In this embodiment, the line width of the enclosed trace 122 is at least greater than 6 mils to properly vent a large amount of static electricity. If the electronic device requires a higher specification of electrostatic discharge protection, the line width of the closed trace 122 needs to be larger. . If it is possible to lay a whole piece, the electrostatic discharge protection capability can be better, for example, the closed trace 122 shown in Fig. 4, that is, a whole piece of the route having a large area.

In the present embodiment, a distance d between the closed trace 122 and the through hole 121 is at least greater than 5 mils.

[Possible effects of the examples]

In summary, the circuit layout structure of the embodiment of the present invention is closed by The technical solutions such as setting up, electrically connecting the grounding via to the grounding layer, and electrically connecting the passive component to the grounding layer can protect a large amount of static electricity from the pins of the plug-in component into other signal traces, in miniaturized electronic devices. In the design, not only can it be implemented accurately, but also the manufacturing cost can be effectively reduced.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

Claims (20)

A circuit layout structure suitable for electrostatic discharge protection of a miniaturized electronic device, wherein the miniaturized electronic device comprises a multi-layer circuit board and a plug-in component, the multi-layer circuit board comprising at least one signal trace layer and at least one connection In the ground layer, the plug-in component includes at least one signal pin disposed in at least a consistent hole of the multi-layer circuit board, and the circuit layout structure is disposed in the circuit board, the circuit layout structure includes: a closed trace disposed at the The signal trace layer of the multilayer circuit board surrounds the at least one of the plurality of circuit boards; wherein the closed trace is electrically connected to the ground layer. The circuit layout structure of claim 1, wherein the closed trace comprises at least one turn-over region, the turn-over region being greater than 90 degrees or having a circular arc lead. The circuit layout structure of claim 2, wherein a first grounding through hole is disposed in the at least one turning region of the closed annular wire, and the closed wire is electrically connected to the connecting through the first grounding through hole Stratum. The circuit layout structure of claim 3, wherein the closed trace includes at least a straight line region, a second ground via, a third ground via, and a fourth ground via are disposed on the closed trace a first distance between the second grounding through hole and the third grounding through hole and a second distance from the third grounding through hole and the fourth grounding through hole are the same distance, the closed wire The grounding layer is electrically connected through the second grounding through hole, the third grounding through hole, and the fourth grounding through hole. For example, the circuit layout structure of claim 1 is characterized in that the line width of the closed trace is greater than or equal to 6 mils. The circuit layout structure of claim 1, wherein the closed trace has a distance from the at least consistent hole greater than 5 mils. The circuit layout structure of claim 1, wherein the plug-in component comprises a fixed pin, and the fixed pin of the plug-in component is electrically connected to a grounding region through a passive component. The circuit layout structure of claim 1, wherein the closed trace is a circular curve. The circuit layout structure of claim 1, wherein the closed trace is a trace having a large area. The circuit layout structure of claim 1, wherein the ground layer is adjacent to the signal routing layer. A miniaturized electronic device comprising: a multi-layer circuit board including a signal routing layer and a ground layer; and a plug-in component including at least one pin, the at least one pin of the plug-in component being received in the The at least one of the plurality of circuit boards; wherein a closed trace is disposed on the signal trace layer of the multilayer circuit board, surrounding the at least one of the plurality of circuit boards, the closed trace is electrically connected to the ground layer . The miniaturized electronic device of claim 11, wherein the closed trace comprises at least one turn-over region, the turn-over region being greater than 90 degrees or having a circular arc lead. The miniaturized electronic device of claim 12, wherein a first grounding through hole is disposed in the at least one turning region of the closed annular wire, and the closed wire is electrically connected to the first grounding through hole Ground plane. The miniaturized electronic device of claim 13 , wherein the closed trace comprises at least a straight line region, a second ground via, a third ground via, and a fourth ground via are disposed on the closed trace The first distance between the second grounding through hole and the third grounding through hole is equal to a second distance between the third grounding through hole and the fourth grounding through hole, the closed wire Through The second ground through hole, the third ground through hole and the fourth ground through hole are electrically connected to the ground layer. The miniaturized electronic device of claim 11, wherein the closed trace has a line width of 6 mils or more. The miniaturized electronic device of claim 11, wherein the closed trace has a distance from the at least consistent hole greater than 5 mils. The miniaturized electronic device of claim 11, wherein the plug-in component comprises a fixed pin, and the fixed pin of the plug-in component is electrically connected to a grounding region through a passive component. The miniaturized electronic device of claim 11, wherein the closed trace is a circular curve. The miniaturized electronic device of claim 11, wherein the closed trace is a trace having a large area. The miniaturized electronic device of claim 11, wherein the ground layer is adjacent to the signal routing layer.