TWI624772B - Input device and control method thereof - Google Patents

Input device and control method thereof Download PDF

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TWI624772B
TWI624772B TW105111772A TW105111772A TWI624772B TW I624772 B TWI624772 B TW I624772B TW 105111772 A TW105111772 A TW 105111772A TW 105111772 A TW105111772 A TW 105111772A TW I624772 B TWI624772 B TW I624772B
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level
button
processing circuit
signal
pin
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TW105111772A
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TW201737034A (en
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黃順治
張志隆
李延霖
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技嘉科技股份有限公司
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Abstract

一種輸入裝置,包括一按鍵以及一處理電路。處理電路具有一輸入接腳以及一輸出接腳。輸入接腳耦接按鍵。輸出接腳提供一按鍵信號予一主機裝置。處理電路根據輸入接腳的位準控制按鍵信號的位準。當輸入接腳的位準由一第一位準變化至一第二位準時,在一預定時間後,處理電路設定按鍵信號為一第三位準,並在一第一屏蔽期間內,忽略輸入接腳的位準變化,並維持按鍵信號在第三位準。 An input device includes a button and a processing circuit. The processing circuit has an input pin and an output pin. Input pin coupling button. The output pin provides a button signal to a host device. The processing circuit controls the level of the button signal according to the level of the input pin. When the level of the input pin changes from a first level to a second level, after a predetermined time, the processing circuit sets the button signal to a third level, and ignores the input during a first mask period. The level of the pin changes and the button signal is maintained at the third level.

Description

輸入裝置及其控制方法 Input device and control method thereof

本發明係有關於一種輸入裝置,特別是有關於一種具有按鍵的輸入裝置。 The present invention relates to an input device, and more particularly to an input device having a button.

一般而言,電腦系統係由三設備所構成,即一輸入設備、一輸出設備以及一主機設備。輸入設備用以供使用者控制主機設備。常見的輸入設備包括滑鼠、鍵盤、軌跡球、搖桿、觸控板等等。大部分的輸入設備具有至少一按鍵。使用者按下按鍵後,主機設備將進行一相對應的動作,如開啟某個應用程式。在電競遊戲中,使用者對於滑鼠的按鍵反應速度要求越來越高。如果無法及時判斷按鍵是否被按下,將造成使用上的不便。 In general, a computer system is composed of three devices, namely, an input device, an output device, and a host device. The input device is used by the user to control the host device. Common input devices include mice, keyboards, trackballs, joysticks, trackpads, and more. Most input devices have at least one button. After the user presses the button, the host device will perform a corresponding action, such as opening an application. In the esports game, the user's response speed to the mouse's button is getting higher and higher. If it is not possible to judge in time whether the button is pressed, it will cause inconvenience in use.

本發明提供一種輸入裝置,包括一按鍵以及一處理電路。處理電路具有一輸入接腳以及一輸出接腳。輸入接腳耦接按鍵。輸出接腳提供一按鍵信號予一主機裝置。處理電路根據輸入接腳的位準控制按鍵信號的位準。當輸入接腳的位準由一第一位準變化至一第二位準時,在一預定時間後,將處理電路設定按鍵信號為一第三位準,並在一第一屏蔽期間內,忽略輸入接腳的位準變化,並維持按鍵信號在第三位準。 The invention provides an input device comprising a button and a processing circuit. The processing circuit has an input pin and an output pin. Input pin coupling button. The output pin provides a button signal to a host device. The processing circuit controls the level of the button signal according to the level of the input pin. When the level of the input pin changes from a first level to a second level, after a predetermined time, the processing circuit sets the button signal to a third level and ignores during a first mask period. The level of the input pin changes and the button signal is maintained at the third level.

本發明另提供一種應用於如上所述之輸入裝置之控制方法,包括判斷一按鍵的位準變化;當按鍵的位準由一第一位準變化至一第二位準時,在一預定時間後,設定一按鍵信號為一第三位準,並在一第一屏蔽期間內,忽略按鍵的位準變化,並維持按鍵信號在第三位準;以及提供按鍵信號予一主機裝置。主機裝置根據按鍵信號執行按鍵所對應的功能。 The invention further provides a control method applied to the input device as described above, comprising determining a level change of a button; when the level of the button changes from a first level to a second level, after a predetermined time And setting a button signal to a third level, and ignoring the level change of the button during a first masking period, and maintaining the button signal at a third level; and providing a button signal to a host device. The host device performs the function corresponding to the button according to the button signal.

100‧‧‧操作系統 100‧‧‧ operating system

110‧‧‧輸入裝置 110‧‧‧Input device

120‧‧‧主機裝置 120‧‧‧Host device

111‧‧‧處理電路 111‧‧‧Processing Circuit

KY1~KYn‧‧‧按鍵 KY 1 ~KY n ‧‧‧ button

P1~Pn、PO‧‧‧接腳 P 1 ~ P n, PO‧‧‧ pin

SBT、SBT1~SBT4‧‧‧按鍵信號 S BT , S BT1 ~ S BT4 ‧‧‧ button signal

IM‧‧‧阻抗 IM‧‧‧ impedance

LV、SP1‧‧‧位準 LV, S P1 ‧‧‧

T1、T2‧‧‧時間點 T1, T2‧‧‧ time points

H‧‧‧高位準 H‧‧‧ high standard

L‧‧‧低位準 L‧‧‧low standard

311~314‧‧‧屏蔽期間 311~314‧‧‧Shielding period

315‧‧‧預設時間 315‧‧‧Preset time

S411~S417‧‧‧步驟 S411~S417‧‧‧Steps

為讓本發明之特徵和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:第1圖為本發明之操作系統之示意圖;第2A圖為理想狀態下按鍵的位準變化示意圖;第2B圖為實際狀態下按鍵的位準變化示意圖;第3A~3D圖為按鍵信號與接腳的位準示意圖;第4圖為本發明的控制方法之示意圖。 In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a schematic diagram of an operating system of the present invention; FIG. 2B is a schematic diagram showing the level change of the button in the actual state; FIG. 3A to FIG. 3D are diagrams showing the level of the button signal and the pin; FIG. 4 is a control method of the present invention; Schematic diagram.

第1圖為本發明之操作系統之示意圖。如圖所示,操作系統100包括一輸入裝置110以及一主機裝置120。輸入裝置110可能是滑鼠、鍵盤、軌跡球、搖桿或是觸控板,但並非用以限制本發明。其它具有按鍵的電腦週邊設備(如印表機或掃描器)亦可作為輸入裝置110。主機裝置120根據輸入裝置110所提供的訊息,執行相對應的服務程式。 Figure 1 is a schematic diagram of the operating system of the present invention. As shown, the operating system 100 includes an input device 110 and a host device 120. The input device 110 may be a mouse, a keyboard, a trackball, a joystick or a touchpad, but is not intended to limit the invention. Other computer peripherals (such as printers or scanners) with buttons can also be used as the input device 110. The host device 120 executes a corresponding service program according to the information provided by the input device 110.

在本實施例中,輸入裝置110包括按鍵KY1~KYn以及一處理電路111,n為正整數。當按鍵KY1~KYn之一者被按下 時,處理電路111輸出相對應的按鍵信號SBT予主機裝置120。主機裝置120再執行相對於被按壓的按鍵的功能或服務程式。本發明並不限定按鍵的數量。在一可能實施例中,輸入裝置110僅具有單一按鍵。本發明亦不限定按鍵KY1~KYn的種類。在其它實施例中,按鍵KY1~KYn係為機械式開關,如微動開關。 In the present embodiment, the input device 110 includes buttons KY 1 -KY n and a processing circuit 111, n being a positive integer. When one of the buttons KY 1 to KY n is pressed, the processing circuit 111 outputs a corresponding button signal S BT to the host device 120. The host device 120 then performs a function or service program with respect to the pressed button. The invention does not limit the number of buttons. In a possible embodiment, the input device 110 has only a single button. 1 to the present invention does not limit the type of keys KY KY n. In other embodiments, the buttons KY 1 -KY n are mechanical switches, such as micro switches.

處理電路111具有接腳P1~Pn以及PO。接腳P1~Pn分別耦接按鍵KY1~KYn。處理電路111根據按鍵KY1~KYn的按壓狀態,產生按鍵信號SBT,再透過接腳PO輸出按鍵信號SBT予主機裝置120。主機裝置120根據按鍵信號SBT執行被按下的按鍵所對應的功能或服務程式。本發明並不限定處理電路111如何判斷出按鍵KY1~KYn的按壓狀態。在一可能實施例中,處理電路111係根據按鍵KY1~KYn的位準變化,判斷出是否有按鍵被按下。舉例而言,當按鍵KY1~KYn之一者被按下時,被按下的按鍵的位準將發生變化,而其它未被按下的按鍵的位準固定不變。因此,藉由偵測按鍵KY1~KYn的位準,便可得知是否有按鍵被按下。 The processing circuit 111 has pins P 1 to P n and PO. Pins P 1 ~ P n are respectively coupled to key KY 1 ~ KY n. The processing circuit 111 generates a button signal S BT according to the pressed state of the buttons KY 1 to KY n , and outputs a button signal S BT to the host device 120 through the pin PO. The host device 120 executes a function or a service program corresponding to the pressed button in accordance with the key signal S BT . The present invention does not limit how the processing circuit 111 determines the pressed state of the buttons KY 1 to KY n . In a possible embodiment, the processing circuit 111 determines whether a button has been pressed according to the level change of the buttons KY 1 -KY n . For example, when one of the buttons KY 1 -KY n is pressed, the level of the pressed button will change, while the level of the other unpressed button will be fixed. Therefore, by detecting the level of the buttons KY 1 to KY n , it is possible to know whether or not a button has been pressed.

第2A圖為理想狀態下按鍵的阻抗及位準變化示意圖。第2B圖為實際狀態下按鍵的阻抗及位準變化示意圖。由於按鍵KY1~KYn的特性相同,故以下係以按鍵KY1為例。如第2A圖所示,在理想狀態下,在對按鍵KY1進行一次按壓與鬆開過程中,當按鍵KY1被按下時(即時間點T1),按鍵KY1的阻抗IM將由高阻抗變化至低阻抗,並維持在低阻抗;當按鍵KY1被放開時(時間點T2),按鍵KY1的阻抗IM由低阻抗變化至高阻抗。 Figure 2A is a schematic diagram showing the impedance and level changes of the button in an ideal state. Figure 2B is a schematic diagram showing the impedance and level change of the button in the actual state. Since the characteristics of the buttons KY 1 to KY n are the same, the following is an example of the button KY 1 . Shown, in an ideal state, the keys KY to be pressed once and a release process, when the button 1 is pressed KY (i.e. time Tl), the impedance of keys KY IM 1 by a high impedance as in FIG. 2A Change to low impedance and maintain low impedance; when button KY 1 is released (time point T2), the impedance IM of button KY 1 changes from low impedance to high impedance.

當按鍵KY1為高阻抗時,按鍵KY1的位準LV係為一 低位準L。當按鍵KY1為低阻抗時,按鍵KY1的位準LV係為一高位準H。因此,藉由測量按鍵KY1的位準LV,便可判斷出按鍵KY1的按壓狀態。舉例而言,當按鍵KY1的位準LV在低位準L時,表示按鍵KY1未被按壓。相反地,當按鍵KY1的位準LV在高位準H時,表示按鍵KY1被按壓。 When the button KY 1 is high impedance, the level LV of the button KY 1 is a low level L. When the button KY 1 is low impedance, the level LV of the button KY 1 is a high level H. Thus, by measuring the level of the LV KY key 1, the key can be determined in a depressed state KY. For example, when the level LV of the button KY 1 is at the low level L, it indicates that the button KY 1 is not pressed. Conversely, when the level LV of the button KY 1 is at the high level H, it indicates that the button KY 1 is pressed.

然而,實際上,當按鍵KY1被按下或放開時,阻抗及位準的切換狀態不是瞬時完成,而是伴有振動的過程,即按鍵KY1的阻抗IM會發生一抖動現象(bounce),如第2B圖所示。在按鍵KY1被按下的一短暫時間內,按鍵KY1的阻抗IM發生一抖動現象,如符號210所示。同樣地,在按鍵KY1被放開時,按鍵KY1的阻抗IM也會發生一抖動現象,如符號220所示。 However, in fact, when the button KY 1 is pressed or released, the switching state of the impedance and the level is not instantaneously completed, but is accompanied by a process of vibration, that is, a jitter phenomenon occurs in the impedance IM of the button KY 1 (bounce ), as shown in Figure 2B. A short period of time during which the button KY 1 is pressed, the impedance IM of the button KY 1 is dithered as indicated by symbol 210. Similarly, when the button KY 1 is released, a jitter phenomenon occurs in the impedance IM of the button KY 1 , as indicated by the symbol 220.

當按鍵KY1的阻抗IM發生抖動現象210與220時,按鍵KY1所輸出的位準也會隨著發生抖動。如第2B圖所示,在時間點T1之後的一段時間,按鍵KY1所輸出的位準在高位準H與低位準L之間變化,然後才會穩定在高位準H。在時間點T2後的一段時間內,按鍵KY1所輸出的位準也在高位準H與低位準L之間變化,然後才會穩定在低位準L。 When the key KY impedance IM 1 jitters 210 and 220, output bit key KY. 1 also with quasi jitter occurs. As shown in FIG. 2B, at a time after the time point T1, the level output by the button KY 1 changes between the high level H and the low level L, and then stabilizes at the high level H. During a period of time after the time point T2, the level output by the button KY 1 also changes between the high level H and the low level L, and then stabilizes at the low level L.

按鍵KY1的位準抖動現象會讓處理電路111誤以為按鍵KY1被按下數次,因而輸出錯誤的按鍵信號予主機裝置120,使主機裝置120執行錯誤的功能或服務程式。因振動現象的存在,傳統輸入設備的按鍵控制方式通常提供一防抖動(debounce)功能,即處理電路的接腳(如P1)在讀到按鍵KY1的信號變化時,暫時不發送按鍵信號SBT至主機裝置,而是在一預定時間後確認信號是變化後的狀態(如按鍵KY1所輸出的 位準從低位準變化到高位準並維持為高位準)後,再發送按鍵信號SBT至主機裝置,以此來防止送出多次連續的按鍵信號。該傳統的輸入設備中的防抖動預定時間通常依據輸入設備的產品規格而定,一般時間都較長(例如10ms),故而傳統輸入設備的按鍵反應較慢。而本發明提出兩種按鍵控制方案使按鍵信號提前送出,相較於現有傳統輸入設備,按鍵反應時間縮短,按鍵反應更快。 The level jitter phenomenon of the button KY 1 causes the processing circuit 111 to mistake the button KY 1 for several times, thereby outputting an erroneous button signal to the host device 120, causing the host device 120 to execute an erroneous function or service program. Due to the existence of vibration phenomenon, the button control mode of the conventional input device usually provides a debounce function, that is, the pin of the processing circuit (such as P 1 ) temporarily does not send the button signal when the signal of the button KY 1 is changed. S after the BT device to the host, but will be confirmed after a predetermined time after the change is the status signal (eg key KY 1 level output changes from low level to high level and is maintained at a high level), and then transmits the key signal S BT to the host device to prevent multiple consecutive button signals from being sent. The predetermined anti-shake time in the conventional input device is usually determined according to the product specifications of the input device, and the general time is long (for example, 10 ms), so the button response of the conventional input device is slow. The present invention proposes two button control schemes to enable the button signals to be sent out in advance. Compared with the existing conventional input devices, the button reaction time is shortened, and the button response is faster.

本發明一種輸入設備按鍵控制方案是:當處理電路的接腳(如P1)在讀到按鍵KY1的信號變化(如按鍵KY1所輸出的位準從低位準變化到高位準)時,立即送出按鍵信號SBT至主機裝置,之後的一預定時間內的任何信號均不做動作,在一可能實施例中,這一預定時間可以是小於按鍵於操作中被按壓與鬆開間隔的極限,並大於按鍵的開關振動時間。 The present invention is an input device key control scheme is: when the pin processing circuit (e.g., P 1) when the read signal change key KY 1 (the level The key KY 1 outputted from the low level changes to high level), immediately The button signal S BT is sent to the host device, and any signal for a predetermined period of time is not actuated. In a possible embodiment, the predetermined time may be less than the limit of the pressed and released interval of the button in the operation. And greater than the switch vibration time of the button.

本發明另一種輸入裝置按鍵控制方案是:當處理電路的接腳(如P1)在讀到按鍵KY1的信號變化(如按鍵KY1所輸出的位準從低位準變化到高位準)時,在一第一預定時間內進行一防抖動處理。在一可能實施例中,該第一預定時間小於按鍵的原始規格設定的防抖動時間。在另一可能實施例中,該防抖動處理的預定時間設置為小於傳統輸入裝置的防抖動預定時間(例如10ms),例如設置為2ms,處理電路確認按鍵所輸出的位準仍處於振動狀態或者變化後的狀態,則發送按鍵信號SBT至主機裝置,之後的一第二預定時間(例如8ms)內的任何信號均不做動作,一種實現中這一第二預定時間為按鍵原始規格設定的防抖動時間減去第一預定時間。 The present invention provides another apparatus button control program inputs are: when the pin processing circuit (e.g., P 1) when the read signal change key KY 1 (e.g. key KY 1 output level registration is changed from low to high level), An anti-shake process is performed for a first predetermined time. In a possible embodiment, the first predetermined time is less than the anti-shake time set by the original specification of the button. In another possible embodiment, the predetermined time of the anti-shake processing is set to be smaller than the anti-shake predetermined time (for example, 10 ms) of the conventional input device, for example, set to 2 ms, and the processing circuit confirms that the level output by the button is still vibrating. The state or the changed state sends a key signal S BT to the host device, and any signal within a second predetermined time (for example, 8 ms) does not perform an action. In an implementation, the second predetermined time is the original specification of the button. The set anti-shake time is subtracted from the first predetermined time.

該預定時間小於該按鍵的原始規格設定的防抖動時間。 The predetermined time is less than the anti-shake time set by the original specification of the button.

相較於傳統輸入裝置的按鍵控制方式,無論上述任一種輸入裝置案件處理方案中,因降低由壓下按鍵至送出信號之間的響應延遲,從而可提高按鍵反應速度,例如前一處理方式可減少例如10ms以上的延遲,後一處理方式可減少8ms以上的延遲。 Compared with the button control mode of the conventional input device, in any of the above-mentioned input device case processing schemes, the response speed of the button can be increased by reducing the response delay between pressing the button and the sending signal, for example, the previous processing mode can be improved. The delay of, for example, 10 ms or more is reduced, and the latter processing mode can reduce the delay of 8 ms or more.

以下透過具體實施例描述本發明前述兩種輸入裝置案件處理方案。 The foregoing two input device case processing schemes of the present invention are described below through specific embodiments.

在一實施例中,當接腳P1的位準由一第一位準(如低位準L)變化至一第二位準(如高位準H)時,處理電路111設定按鍵信號SBT為一第三位準(如高位準H)。應理解,一旦按鍵信號SBT被處理電路111設定,表示處理電路立即將該設定的按鍵信號SBT發送予主機裝置。接著在一屏蔽期間內,忽略接腳P1的位準變化,並將按鍵信號SBT的位準維持在第三位準。在屏蔽期間後,處理電路111才根據接腳P1的位準設定按鍵信號SBT的位準。 In an embodiment, when the level of the pin P 1 is changed from a first level (such as a low level L) to a second level (such as a high level H), the processing circuit 111 sets the key signal S BT to A third level (such as high level H). It should be understood that once the button signal S BT is set by the processing circuit 111, the processing circuit immediately transmits the set button signal S BT to the host device. Then, during a masking period, the level change of the pin P 1 is ignored, and the level of the button signal S BT is maintained at the third level. After the masking period, the processing circuit 111 sets the level of the key signal S BT according to the level of the pin P 1 .

舉例而言,在屏蔽期間後,如果接腳P1的位準維持在第二位準,處理電路111將按鍵信號SBT的位準設定在第三位準。相反地,在屏蔽期間後,如果接腳P1的位準已回到第一位準時,處理電路111將按鍵信號SBT的位準設定在一第四位準(如低位準L)。 For example, after the masking period, if the level of the pin P 1 is maintained at the second level, the processing circuit 111 sets the level of the button signal S BT at the third level. In contrast, after the mask period, if the pin P 1 has been returned to level the first time, the key signal processing circuit 111 S BT is set at a level fourth level (e.g., the low level L).

本發明並不限定第一至第四位準之間的關係。在本實施例中,第一位準不同第二位準,第三位準不同於第四位 準。舉例而言,第一位準為一低位準,第二位準為一高位準。在另一可能實施例中,第一位準可能相同或不同於第三位準,第二位準可能相同或不同於第四位準。 The present invention does not limit the relationship between the first to fourth levels. In this embodiment, the first level is different from the second level, and the third level is different from the fourth level. quasi. For example, the first level is a low level and the second level is a high level. In another possible embodiment, the first level may be the same or different from the third level, and the second level may be the same or different from the fourth level.

第3A圖為按鍵信號SBT與接腳P1的位準示意圖。在本實施例中,當接腳P1的位準SP1不等於第一位準時(如不等於低位準L),處理電路111將按鍵信號SBT1的位準設定在第三位準(如高位準H)。在一可能實施例中,當接腳P1的位準SP1不等於低位準時(如在時間點T1),處理電路111立即將按鍵信號SBT1的位準設定成高位準H。 FIG. 3A is a schematic diagram of the level of the button signal S BT and the pin P 1 . In this embodiment, when the level S P1 of the pin P 1 is not equal to the first level (if not equal to the low level L), the processing circuit 111 sets the level of the button signal S BT1 at the third level (eg, High level H). In a possible embodiment, when the level S P1 of the pin P 1 is not equal to the low level (eg, at the time point T1), the processing circuit 111 immediately sets the level of the key signal S BT1 to the high level H.

接著,在屏蔽期間311內,不論接腳P1的位準為第一或第二位準,處理電路111將按鍵信號SBT維持在第三位準(如高位準H)。在屏蔽期間311後,處理電路111才會根據接腳P1的位準設定按鍵信號的位準。在本實施例中,在屏蔽期間311後,由於接腳P1的位準SP1仍維持在第二位準(如高位準H),因此,處理電路111設定按鍵信號SBT1的位準維持在第三位準(如高位準H)。在其它實施例中,在屏蔽期間311後,如果接腳P1的位準SP1已回到第一位準(如虛線所示)時,處理電路111立即將按鍵信號SBT1的位準由第三位準(如高位準H)改變至第四位準(如低位準L)。 Next, during the masking period 311, the processing circuit 111 maintains the key signal S BT at a third level (eg, a high level H) regardless of whether the level of the pin P 1 is the first or second level. During the shield 311, the processing circuit 111 will set the level of the key signal level in accordance pin P 1. In this embodiment, after the mask period 311, since the level S P1 of the pin P 1 is still maintained at the second level (such as the high level H), the processing circuit 111 sets the level of the button signal S BT1 to be maintained. In the third level (such as high level H). In other embodiments, after the mask period 311, if the level S P1 of the pin P 1 has returned to the first level (as indicated by the dashed line), the processing circuit 111 immediately sets the level of the button signal S BT1 The third level (such as the high level H) changes to the fourth level (such as the low level L).

在時間點T2,接腳P1的位準SP1由第二位準(如高位準H)回到第一位準(如低位準L)。由於接腳P1的位準SP1發生變化,因此,處理電路111立即設定按鍵信號SBT1由第三位準(如高位準H)改變至第四位準(如低位準L)。接著在一屏蔽期間312內,處理電路111忽略接腳P1的位準SP1變化,並將按鍵信號SBT1 維持在第四位準(如低位準L)。在屏蔽期間312後,處理電路111才會再度根據接腳P1的位準SP1設定按鍵信號SBT1的位準。 At time T2, the level S P1 of the pin P 1 is returned to the first level (eg, the low level L) by the second level (eg, the high level H). Since the level S P1 of the pin P 1 changes, the processing circuit 111 immediately sets the key signal S BT1 to change from the third level (eg, the high level H) to the fourth level (eg, the low level L). Then, during a masking period 312, processing circuit 111 ignores the change in level S P1 of pin P 1 and maintains button signal S BT1 at a fourth level (e.g., low level L). During the shield 312, the processing circuit 111 would again set level in accordance with a key signal S BT1 pin P S 1 level of P1.

本發明並不限定屏蔽期間311與312的長短。屏蔽期間311可能相同或不同於屏蔽期間312。在一可能實施例中,屏蔽期間311長於屏蔽期間312。在其它可能實施例中,屏蔽期間311與312大於按鍵的阻抗抖動時間。另外,在使用者按下並放開按鍵後,通常最快也要隔70~80ms後,才會再按下一次。因此,屏蔽期間311與312需小於70~80ms。在一些實施例中,屏蔽期間312係被省略。 The invention does not limit the length of the shielding periods 311 and 312. The mask period 311 may be the same or different than the mask period 312. In a possible embodiment, the masking period 311 is longer than the masking period 312. In other possible embodiments, the masking periods 311 and 312 are greater than the impedance jitter time of the button. In addition, after the user presses and releases the button, it usually takes 70 to 80 ms at a time, and then presses again. Therefore, the shielding periods 311 and 312 need to be less than 70 to 80 ms. In some embodiments, the masking period 312 is omitted.

第3B圖為按鍵信號SBT與接腳P1的位準的另一示意圖。第3B圖相似第3A圖,不同之處在於,在時間點T2,雖然接腳P1的位準SP1發生變化(由高位準變化至低位準),但處理電路111等待一預設時間315後,才將按鍵信號SBT2的位準由第三位準(如高位準H)改變至第四位準(如低位準L)。在此例中,在屏蔽期間312內,處理電路111忽略接腳P1的位準SP1變化,並維持按鍵信號SBT2在第四位準(如低位準L)。在屏蔽期間312後,處理電路111根據接腳P1的位準SP1設定按鍵信號SBT2的位準。在一可能實施例中,屏蔽期間312後,處理電路111可能根據接腳P1的位準SP1立即設定按鍵信號SBT2的位準或等待一段時間後才設定按鍵信號SBT2的位準。 FIG. 3B is another schematic diagram of the level of the button signal S BT and the pin P 1 . 3B is similar to FIG. 3A except that at time T2, although the level S P1 of the pin P 1 changes (from a high level to a low level), the processing circuit 111 waits for a preset time 315. After that, the level of the key signal S BT2 is changed from the third level (such as the high level H) to the fourth level (such as the low level L). In this example, during masking period 312, processing circuit 111 ignores the change in level S P1 of pin P 1 and maintains button signal S BT2 at a fourth level (e.g., low level L). After the mask period 312, the processing circuit 111 sets the level of the key signal S BT2 according to the level S P1 of the pin P 1 . In a possible embodiment, after the mask period 312, the processing circuit 111 may immediately set the level of the button signal S BT2 according to the level S P1 of the pin P 1 or wait for a period of time before setting the level of the button signal S BT2 .

第3C圖為按鍵信號SBT與接腳P1的位準的另一示意圖。在本實施例中,當接腳P1的位準發生變化時,處理電路111等待一段時間315後,才會設定按鍵信號SBT3的位準,並在設定後的一屏蔽期間313,忽略接腳P1的位準變化,直到屏蔽 期間313後,才會根據接腳P1的位準設定按鍵信號SBT3的位準。 Figure 3C is another schematic diagram of the level of the button signal S BT and the pin P 1 . In this embodiment, when the level of the pin P 1 changes, the processing circuit 111 waits for a period of time 315 to set the level of the button signal S BT3 , and ignores the set period 313 after the setting. The level of the pin P 1 changes until the mask period 313 is reached, and the level of the button signal S BT3 is set according to the level of the pin P 1 .

舉例而言,在時間點T1,接腳P1的位準SP1由第一位準(如低位準L)變化至第二位準(如高位準H)。雖然接腳P1的位準SP1發生變化,但處理電路111等待一預設時間315後,才會將按鍵信號SBT3的位準設定在第三位準(如高位準H)。接著,在屏蔽期間313,處理電路111無視接腳P1的位準SP1變化,將按鍵信號SBT3的位準維持在第三位準(如高位準H)。 For example, at the time point Tl, pin P level S 1 is a first quasi-P1 (e.g., the low level L) changes to a second level (e.g., high level H). Although the level S P1 of the pin P 1 changes, the processing circuit 111 waits for a preset time 315 before setting the level of the key signal S BT3 to the third level (eg, the high level H). Next, during the mask period 313, the processing circuit 111 maintains the level of the button signal S BT3 at the third level (eg, the high level H) regardless of the level S P1 of the pin P 1 .

在屏蔽期間313後,當接腳P1的位準SP1由第二位準(如高位準H)回到第一位準(如低位準L)時,處理電路111仍會等待一預設時間315後,才會將按鍵信號SBT3的位準由第三位準(如高位準H)改變至第四位準(如低位準L),接著在另一屏蔽期間314,處理電路111忽略接腳P1的位準SP1變化,並維持按鍵信號SBT3在第四位準(如低位準L)。在屏蔽期間314後,處理電路111根據接腳P1的位準SP1設定按鍵信號SBT3的位準。 During the shield 313, when the pin P level S 1 when the first level P1 (e.g., the low level L) by a second level (e.g., high level H) back, the processing circuit 111 will wait for a predetermined After time 315, the level of the key signal S BT3 is changed from the third level (e.g., high level H) to the fourth level (e.g., low level L), and then during another mask period 314, the processing circuit 111 ignores The level S P1 of the pin P 1 changes, and the key signal S BT3 is maintained at the fourth level (such as the low level L). After the mask period 314, the processing circuit 111 sets the level of the key signal S BT3 according to the level S P1 of the pin P 1 .

屏蔽期間314可能相同或不同於屏蔽期間313。在一可能實施例中,屏蔽期間314短於屏蔽期間313。在其它實施例中,屏蔽期間314可能相同、短於或長於於屏蔽期間312。屏蔽期間313也可能相同、短於或長於屏蔽期間311。 The mask period 314 may be the same or different than the mask period 313. In a possible embodiment, the mask period 314 is shorter than the mask period 313. In other embodiments, the masking period 314 may be the same, shorter, or longer than the masking period 312. The masking period 313 may also be the same, shorter or longer than the masking period 311.

第3D圖為按鍵信號SBT與接腳P1的位準的另一示意圖。第3D圖相似第3C圖,不同之處在於,在屏蔽期間313後,當接腳P1的位準SP1由第二位準(如高位準H)回到第一位準(如低位準L)時(即時間點T2),處理電路111立即將按鍵信號SBT4的位準由第三位準(如高位準H)改變至第四位準(如低位準L),接著在一屏蔽期間314內,忽略接腳P1的位準SP1變化,並維持 按鍵信號SBT4的位準在第四位準(如低位準L),在屏蔽期間314後,處理電路111根據接腳P1的位準SP1設定按鍵信號SBT4的位準。 Fig. 3D is another schematic diagram of the level of the button signal S BT and the pin P 1 . The first 3D view similar to FIG. 3C, except that, after 313, when the pin P is P1 S 1 level from the second level (e.g., high level H) back to the first level (e.g., a low level during the mask When L) (ie, time point T2), the processing circuit 111 immediately changes the level of the key signal S BT4 from the third level (eg, high level H) to the fourth level (eg, low level L), followed by a mask. During the period 314, the level S P1 of the pin P 1 is ignored, and the level of the button signal S BT4 is maintained at the fourth level (eg, the low level L). After the mask period 314, the processing circuit 111 is based on the pin P. 1 P1 level setting button S of the signal S of the level BT4.

第4圖為本發明之控制方法的一可能實施例之流程圖。本發明的控制方法用以判斷一按鍵是否被按下,並根據按鍵的按壓狀態,設定一按鍵信號的位準,使得一主機裝置根據該按鍵信號執行相對應的服務程式。 Figure 4 is a flow chart of a possible embodiment of the control method of the present invention. The control method of the present invention is for determining whether a button is pressed, and setting a level of a button signal according to a pressing state of the button, so that a host device executes a corresponding service program according to the button signal.

在步驟S411中,判斷是否有按鍵被按下。在一可能實施例,步驟S411係根據按鍵位準判斷按鍵是否被按下,但並非用以限制本發明。在其它實施例中,步驟S411可能係根據按鍵的阻抗變化判斷按鍵是否被按下。為方便說明,以下的說明係以按鍵的位準為例。 In step S411, it is determined whether or not a button has been pressed. In a possible embodiment, step S411 determines whether the button is pressed according to the button level, but is not intended to limit the present invention. In other embodiments, step S411 may determine whether the button is pressed according to the impedance change of the button. For convenience of explanation, the following description takes the level of the button as an example.

當按鍵的位準發生變化時,如由一第一位準變化至一第二位準,表示按鍵被按下,因此,設定按鍵信號的位準為一第三位準(步驟S412)。在一可能實施例中,當按鍵的位準第一位準變化至第二位準時,立即將按鍵信號的位準設定在第三位準。在又一可能實施例中,當按鍵的位準由第一位準變化至第二位準,立即將按鍵信號的位準設定在第三位準,並屏蔽一段時間內的任何信號。在另一可能實施例中,當按鍵的位準由第一位準變化至第二位準,等待一第一預設時間(如2ms)後,才將按鍵信號的位準設定在第三位準。 When the level of the button changes, such as changing from a first level to a second level, indicating that the button is pressed, therefore, the level of the button signal is set to a third level (step S412). In a possible embodiment, when the level of the button changes to the second level, the level of the button signal is immediately set to the third level. In a further possible embodiment, when the level of the button changes from the first level to the second level, the level of the button signal is immediately set to the third level, and any signal for a period of time is masked. In another possible embodiment, when the level of the button changes from the first level to the second level, the level of the button signal is set to the third position after waiting for a first preset time (eg, 2 ms). quasi.

在本實施例中,第一位準不同於第二位準。舉例而言,第一位準為一低位準或一高位準,第二位準為一高位準或一低位準。另外,本發明亦不限定第三位準的大小。在一可 能實施例中,第三位準可能相同於第一或第二位準。 In this embodiment, the first level is different from the second level. For example, the first level is a low level or a high level, and the second level is a high level or a low level. In addition, the present invention also does not limit the size of the third level. In one In an embodiment, the third level may be the same as the first or second level.

接著,在一屏蔽期間內,忽略按鍵的位準變化,並維持按鍵信號在第三位準(步驟S413)。屏蔽期間必須長於按鍵的位準發生抖動的時間。另外,屏蔽期間需短於使用者連續兩次按壓的間隔時間。舉例而言,如果使用者約每隔70~80ms才會再度按壓按鍵時,則屏蔽時間需短於70~80ms。 Then, during a masking period, the level change of the button is ignored, and the button signal is maintained at the third level (step S413). The time during which the mask must be jittered longer than the level of the button. In addition, the shielding period should be shorter than the interval between two consecutive presses by the user. For example, if the user presses the button again every 70~80ms, the masking time should be shorter than 70~80ms.

在屏蔽期間後,根據按鍵的位準設定按鍵信號的位準(步驟S414)。在本實施例中,步驟S414包括步驟S415~S417。在步驟S415中,判斷按鍵的位準是否發生變化。當按鍵的仍位準維持在第二位準時,維持按鍵信號的位準在第三位準(步驟S416),並再回到步驟S415,繼續判斷按鍵信號的位準是否發生變化。 After the masking period, the level of the button signal is set according to the level of the button (step S414). In the embodiment, step S414 includes steps S415 to S417. In step S415, it is judged whether or not the level of the button has changed. When the still level of the button is maintained at the second level, the level of the button signal is maintained at the third level (step S416), and the process returns to step S415 to continue to determine whether the level of the button signal has changed.

當按鍵信號的位準從第二位準變化至第一位準時,表示按鍵被放開。因此,改變按鍵信號的位準,由第三位準至第四位準(步驟S417)。在一可能實施例中,按鍵信號的位準係立即從第三位準改變至第四位準。在其它實施例,等待一第二預設時間後,才將按鍵信號的位準從第三位準改變至第四位準。 When the level of the button signal changes from the second level to the first level, it indicates that the button is released. Therefore, the level of the key signal is changed from the third level to the fourth level (step S417). In a possible embodiment, the level of the button signal is immediately changed from the third level to the fourth level. In other embodiments, the level of the button signal is changed from the third level to the fourth level after waiting for a second predetermined time.

本發明並不限定第三及第四位準的大小。在一實施例中,第四位準不同於第三位準。舉例而言,第三位準為一高位準或一低位準時,第四位準為一低位準或一高位準。在其它實施例中,第四位準可能等於第二或第一位準。 The invention does not limit the size of the third and fourth levels. In an embodiment, the fourth level is different from the third level. For example, the third level is a high level or a low level, and the fourth level is a low level or a high level. In other embodiments, the fourth level may be equal to the second or first level.

在一可能實施例中,每當按鍵信號的位準需要改變時(如由第三位準改變至第四位準或是由第四位準改變至第 三位準),可立即改變按鍵信號的位準,或是等待一段預設時間後才改變按鍵信號的位準。 In a possible embodiment, whenever the level of the button signal needs to be changed (eg, changing from the third level to the fourth level or from the fourth level to the first level) The three-level can change the level of the button signal immediately, or wait for a preset time to change the level of the button signal.

以第3A圖為例,按鍵信號的位準立即由低位準改變至高位準,並立即由高位準改變至低位準。在第3B圖中,按鍵信號的位準立即由低位準改變至高位準,但等待一預設時間後才由高位準改變至低位準。在第3C圖中,按鍵信號等待一第一預設時間後才由低位準改變至高位準,並等待一第二預設時間後才由高位準改變至低位準。第一預設時間可能等於、長於或短於第二預設時間。在第3D圖中,按鍵信號等待一預設時間後才由低位準改變至高位準,但立即才由高位準改變至低位準。 Taking Figure 3A as an example, the level of the button signal is immediately changed from a low level to a high level, and immediately changes from a high level to a low level. In Fig. 3B, the level of the button signal is immediately changed from the low level to the high level, but waits for a preset time to change from the high level to the low level. In FIG. 3C, the button signal is changed from the low level to the high level after waiting for a first preset time, and waits for a second preset time to change from the high level to the low level. The first preset time may be equal to, longer or shorter than the second preset time. In the 3D picture, the button signal waits for a preset time to change from the low level to the high level, but immediately changes from the high level to the low level.

在本實施例中,由於按鍵信號的位準並不會受到按鍵的抖動位準所影響,故可避免主機裝置誤以為按鍵被按下數次。另外,當按鍵被按下時,按鍵信號的位準立即隨之改變,則可使主機裝置立即做出反應,執行相對應的服務程式。 In this embodiment, since the level of the button signal is not affected by the jitter level of the button, the host device can be prevented from erroneously thinking that the button has been pressed several times. In addition, when the button is pressed, the level of the button signal is immediately changed, and the host device can immediately react to execute the corresponding service program.

除非另作定義,在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外,除非明白表示,詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致,而不應解釋為理想狀態或過分正式之語態。 Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

一種輸入裝置,包括:一按鍵;以及一處理電路,具有一輸入接腳以及一輸出接腳,該輸入接腳耦接該按鍵,該輸出接腳提供一按鍵信號予一主機裝置,該處理電路根據該輸入接腳的位準控制該按鍵信號的位準;其中,當該輸入接腳的位準由一第一位準變化至一第二位準時,在一預定時間後,該處理電路設定該按鍵信號為一第三位準,並在一第一屏蔽期間內,忽略該輸入接腳的位準變化,並維持該按鍵信號在該第三位準。 An input device includes: a button; and a processing circuit having an input pin and an output pin, the input pin is coupled to the button, and the output pin provides a button signal to a host device, the processing circuit Controlling the level of the button signal according to the level of the input pin; wherein, when the level of the input pin changes from a first level to a second level, after a predetermined time, the processing circuit sets The button signal is at a third level, and during a first masking period, the level change of the input pin is ignored, and the button signal is maintained at the third level. 如申請專利範圍第1項所述之輸入裝置,其中該預定時間為零,在該輸入接腳的位準由該第一位準發生改變時,該處理電路立即設定該按鍵信號為該第三位準。 The input device of claim 1, wherein the predetermined time is zero, and when the level of the input pin is changed by the first level, the processing circuit immediately sets the button signal to the third Level. 如申請專利範圍第2項所述之輸入裝置,該第一屏蔽期間的時間間隔小於該按鍵於操作中被按壓與鬆開間隔的極限,且大於該按鍵的開關振動時間。 The input device of claim 2, wherein the time interval of the first shielding period is less than a limit of the pressing and releasing interval of the button in operation, and is greater than a switching vibration time of the button. 如申請專利範圍第1項所述之輸入裝置,其中該預定時間不為零,在該預定時間內,該處理電路進行對該按鍵的一防抖動處理。 The input device of claim 1, wherein the predetermined time is not zero, and the processing circuit performs an anti-shake processing on the button within the predetermined time. 如申請專利範圍第4項所述之輸入裝置,其中該預定時間小於該按鍵的原始規格設定的防抖動時間。 The input device of claim 4, wherein the predetermined time is less than an anti-shake time set by an original specification of the button. 如申請專利範圍第1項所述之輸入裝置,其中在該第一屏蔽期間後,當該輸入接腳的位準變為該第一位準時,該 處理電路設定該按鍵信號為一第四位準。 The input device of claim 1, wherein after the first shielding period, when the level of the input pin becomes the first level, the The processing circuit sets the button signal to a fourth level. 如申請專利範圍第2項所述之輸入裝置,其中在該第一屏蔽期間後,當該輸入接腳的位準由該第二位準回到該第一位準時,該處理電路立即設定該按鍵信號由該第三位準改變至一第四位準,並在一第二屏蔽期間內,忽略該輸入接腳的位準變化,並維持該按鍵信號在該第四位準。 The input device of claim 2, wherein, after the first shielding period, when the level of the input pin returns from the second level to the first level, the processing circuit immediately sets the The button signal is changed from the third level to a fourth level, and during a second masking period, the level change of the input pin is ignored, and the button signal is maintained at the fourth level. 如申請專利範圍第2項所述之輸入裝置,其中在該第一屏蔽期間後,當該輸入接腳的位準由該第二位準回到該第一位準時,該處理電路等待一預設時間後,設定該按鍵信號由該第三位準改變至一第四位準,並在一第二屏蔽期間內,忽略該輸入接腳的位準變化,並維持該按鍵信號在該第四位準。 The input device of claim 2, wherein after the first shielding period, when the level of the input pin returns from the second level to the first level, the processing circuit waits for a pre- After the time is set, the button signal is changed from the third level to a fourth level, and during a second masking period, the level change of the input pin is ignored, and the button signal is maintained at the fourth Level. 一種應用於如申請專利範圍第1-8項任一項所述之輸入裝置之控制方法,包括:判斷一按鍵的位準變化;當該按鍵的位準由一第一位準變化至一第二位準時,在一預定時間後,設定一按鍵信號為一第三位準,並在一第一屏蔽期間內,忽略該按鍵的位準變化,並維持該按鍵信號在該第三位準;以及提供該按鍵信號予一主機裝置,該主機裝置根據該按鍵信號執行該按鍵所對應的功能。 A control method for an input device according to any one of claims 1-8, comprising: determining a level change of a button; and changing a level of the button from a first level to a first level After two predetermined times, after a predetermined time, a button signal is set to a third level, and during a first masking period, the level change of the button is ignored, and the button signal is maintained at the third level; And providing the button signal to a host device, and the host device performs a function corresponding to the button according to the button signal. 如申請專利範圍第9項所述之控制方法,其中該預定時間為零,在該按鍵的位準由該第一位準發生改變時,該 處理電路立即設定該按鍵信號為該第三位準;或者,該預定時間不為零且小於按鍵原始規格設定的防抖動時間,在該預定時間內,該處理電路進行對該按鍵的防抖動處理。 The control method of claim 9, wherein the predetermined time is zero, and when the level of the button is changed by the first level, The processing circuit immediately sets the button signal to the third level; or, the predetermined time is not zero and is less than an anti-shake time set by the original specification of the button, during which the processing circuit performs anti-shake on the button Dynamic processing.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
US6833741B2 (en) * 2002-07-09 2004-12-21 Hynix Semiconductor Inc. Circuit for controlling an initializing circuit in a semiconductor device
TW201304412A (en) * 2011-07-04 2013-01-16 Pegatron Corp Power switching circuit
TWI466444B (en) * 2009-08-12 2014-12-21 Hon Hai Prec Ind Co Ltd Switching circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833741B2 (en) * 2002-07-09 2004-12-21 Hynix Semiconductor Inc. Circuit for controlling an initializing circuit in a semiconductor device
TWI466444B (en) * 2009-08-12 2014-12-21 Hon Hai Prec Ind Co Ltd Switching circuit
TW201304412A (en) * 2011-07-04 2013-01-16 Pegatron Corp Power switching circuit

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