TWI466444B - Switching circuit - Google Patents

Description

Switch circuit

The invention relates to a switching circuit.

Most of the conventional switch circuit designs have only a single function. Generally speaking, a switch circuit can only control whether a function is turned on or off. For example, in a system, both soft weight and hard weight setting, a switch circuit is required to control the soft weight setting, and another switching circuit controls the hard weight setting to open, which does not allow a switching circuit to control both the soft weight and the hard control. Weight is fixed.

In view of the foregoing, it is necessary to provide a switching circuit that can control both soft weight and hard weight.

A switching circuit includes a power input terminal, a first switch module, a second switch module, a first delay comparison module, a second delay comparison module, a soft weight signal terminal, a hard weight signal terminal, and a a processing module, the first switch module includes a button and a PNP type triode, the power input end is grounded through a first resistor and the button, and the power input end further transmits a second resistor and a third resistor The input end and the output end of the second delay comparison module are connected, the base of the PNP type triode is connected to the node of the first resistor and the button, and the soft weight signal end, the emitter is connected to the power input end, and the first connection of the collector is connected. Comparing the input end of the module and grounding through a fourth resistor, the control end of the second switch module is connected to the soft weight signal end, the first end is connected to the output end of the first delay comparison module, and the second end is connected to the second resistor And the node of the second delay comparison module, the hard weight signal end is connected to the output of the second delay comparison module, and the soft weight signal end and the hard weight signal end are both The processing module is connected, and the processing module stores a preset time. When the button is not pressed, the first delay comparison module outputs a high voltage, and the soft weight signal end and the hard weight signal end are all high voltage, and the button is pressed. When the soft weight is fixed to the low voltage, the hard weight is still high voltage, the first delay comparison module outputs a low voltage, and the second switch module disconnects the first delay comparison module and the second delay comparison module. After the release button is pressed, the first delay comparison module outputs a low voltage and then outputs a high voltage, the soft weight signal terminal becomes a high voltage, and the second switch module is turned on, and is delayed by the second delay comparison module after the release button is pressed. After the hard weight signal is turned to a low voltage, the hard weight signal is turned to a high voltage again. If the button is pressed for a preset time stored in the processing module, the processing module controls the computer. The soft weight is fixed, otherwise the hard weight is determined.

The switch circuit of the present invention first generates a low voltage on the soft weight signal terminal every time the button is pressed, and releases a button to generate a signal from a high voltage to a low voltage to a high voltage on the hard weight signal terminal. If the button is pressed for the set time set by the processing module, the soft weight is executed, otherwise the hard weight is executed. The switch circuit is configured to set a first delay comparison module for outputting a first low and then high voltage to the second delay comparison module, and the second delay comparison module is configured to ensure that the hard weight fixed terminal voltage is delayed after a period of time when the switch is released. From high to low, then from low to high. The aforementioned switch circuit can control the soft weight of the system and control the hard weight of the system through a button.

Referring to FIG. 1 and FIG. 2 , a preferred embodiment of the switch circuit 100 of the present invention includes a first switch module 10 , a first delay comparison module 20 , a second switch module 30 , and a second delay comparison module 40 . A processing module 50, a soft weight signal terminal 60, a hard weight signal terminal 70 and a power input terminal 80.

The first switch module 10 includes a PNP-type triode Q1, a switch button P, and two resistors R1 and R2. The emitter of the triode Q1 is connected to the power input terminal 80. The base of the triode Q1 is connected to the power input terminal 80 through the resistor R1, and is also grounded through the switch button P and directly connected to the soft weight signal terminal 60 and the control terminal of the second switch module 30. The collector of the triode Q1 is grounded through the resistor R2 and is also connected to the input of the first delay comparison module 20.

The first delay comparison module 20 includes a resistor R3, a capacitor C1, a dual operational amplifier OP1, and a reference power supply V1. One end of the resistor R3 is connected between the collector of the triode Q1 and the resistor R2. The other end of the resistor R3 is grounded through the capacitor C1. The negative input terminal of the dual operational amplifier OP1 is connected between the resistor R3 and the capacitor C1. The positive input terminal is connected to the reference power source V1 and grounded. The output terminal of the dual operational amplifier OP1 is grounded through a capacitor C2, and The second switch module 30 is connected. The resistor R3 and the capacitor C1 form an RC delay circuit to delay the voltage of the collector output of the triode Q1; the reference power source V1 serves as a reference power source of the dual operational amplifier OP1; the capacitor C2 is used for filtering The voltage output from the output of the dual op amp OP1.

The second switch module 30 includes a resistor R4 and an NPN-type triode Q2. The collector (first end) of the triode Q2 is connected between the output terminal of the dual operational amplifier OP1 and the capacitor C2. The pole (control terminal) is connected to the base of the three-pole body Q1 through the resistor R4, and the emitter (second terminal) is connected to the power input terminal 80 through a resistor R5 and grounded through a capacitor C3. The capacitor C3 is used to filter the output voltage of the emitter of the triode Q2. The emitter of the triode Q2 is also coupled to the input of the second delay comparison module 40.

The second delay comparison module 40 includes a resistor R6, a capacitor C4, a dual operational amplifier OP2, and a reference power supply V2. One end of the resistor R6 is connected between the resistor R5 and the emitter of the triode Q2. The other end of the resistor R6 is grounded through the capacitor C4. The positive input terminal of the dual operational amplifier OP2 is connected between the resistor R6 and the capacitor C4, and the negative input terminal is connected to the reference power source V2 and grounded. The output terminal of the dual operational amplifier OP2 is transmitted through a resistor R7 and the power input terminal. The 80 connection and grounding through a capacitor C5, the output of the dual operational amplifier OP2 is also directly connected to the hard weight signal terminal 70. The resistor R6 and the capacitor C4 form an RC delay circuit for delaying the input voltage. The reference power source V2 serves as a reference power source for the OP2, and the capacitor C5 is used to filter the voltage outputted by the output terminal of the dual operational amplifier OP2.

The soft weight signal terminal 60 and the hard weight signal terminal 70 are both connected to the processing module 50. The processor 50 includes a reading unit 52, a determining unit 54, a setting unit 56, and an executing unit 58. The reading unit 52 reads the voltage of the soft weight signal terminal 60 and the hard weight signal terminal 70. When the determining unit 54 determines the soft weight signal terminal 60 and the hard weight signal terminal 70 read by the reading unit 52, When the voltages are all high voltages, the execution unit 58 does not reset the system. When the voltage of the soft weight signal terminal 60 read by the determining unit 54 is a low voltage, the determining unit 54 continues to determine whether the low voltage duration has reached the preset time set by the setting unit 56, if the preset time is reached. The execution unit 58 determines the soft weight of the system, and the determining unit 54 does not care about the voltage of the hard weight signal terminal 70; if the low voltage duration of the soft weight signal terminal 60 does not reach the preset time, the determining unit 54 determines The voltage of the hard weight signal terminal 70 has a process of changing from a high voltage to a low voltage and then to a high voltage. If the foregoing process is performed, the execution unit 58 hard-weights the system.

The specific operation of the switch circuit 100 will be described below.

When the button P is not pressed, the triode Q1 is not turned on, the base voltage of the triode Q1 is a high voltage, the soft weight signal terminal 60 is at a high voltage, and the triode Q2 is turned on. Since the triode Q1 is non-conducting, its collector output voltage is 0, so the negative input terminal voltage of the dual operational amplifier OP1 is 0, and the positive input terminal voltage of the dual operational amplifier OP1 is V1, so the dual operational amplifier OP1 output The terminal outputs a high voltage to the collector of the triode Q2. Since the triode Q2 is turned on at this time, the triode Q2 transmits the high voltage outputted from the output terminal of the dual operational amplifier to the second delay comparison module. 40. The voltage at the positive input terminal of the dual operational amplifier OP2 is a high voltage. Since the voltage of the negative input terminal of the dual operational amplifier OP2 is the voltage of the reference power supply V2, and the voltage value of the reference power supply V2 is smaller than the high voltage, the dual operational amplifier OP2 outputs a high voltage, that is, the hard weight signal end The voltage of 70 is a high voltage. At this time, the voltages of the soft weight signal end 60 and the hard weight signal end 70 read by the reading unit 52 of the processing module 50 are both high voltages, and the processing module 50 does not reset the system.

When the button P is pressed, the triode Q1 is turned on, the base voltage of the triode Q1 instantaneously changes from a high voltage to a low voltage, and the voltage of the soft weight signal terminal 60 instantaneously changes from a high voltage to a low voltage. After the button P is turned on, the triode Q1 is not turned on, and the voltage of the soft weight signal terminal 60 is instantaneously changed from a low voltage to a high voltage. That is, when the button P is pressed, the voltage of the soft weight signal terminal 60 read by the reading unit 52 of the processing module 50 is a low voltage. After the button P is released, the voltage of the soft weight signal terminal 60 is a high voltage. Therefore, the low voltage duration of the soft weight signal terminal 60 is the time when the button P is pressed, and this period is recorded as T1. If the time T1 of pressing the button P reaches the set time of the setting unit 56, the processing module 50 determines the soft weight of the system and ignores the voltage of the hard weight signal terminal 70. If the time T1 of pressing the button P does not reach the time set by the setting unit 54, the processing module 50 will control the voltage control system of the hard weight signal terminal 70.

When the button P is pressed, since the triode Q1 is turned on, the collector of the triode Q1 outputs a high voltage, the base outputs a low voltage, and the capacitor C1 and the resistor R3 constitute an RC delay circuit, so that the dual operational amplifier The voltage at the negative input terminal of OP1 is higher than the voltage of the reference power supply V1 at the positive input terminal of the dual operational amplifier OP1 after a period of delay, that is, the output of the dual operational amplifier OP1 will be changed from high to low after a delay. Voltage. The triode Q2 is non-conducting, and the triode Q2 does not transmit the low voltage outputted from the output of the dual operational amplifier OP1 to the second delay comparison module 40. At this time, the positive input terminal voltage of the dual operational amplifier OP2 directly receives the high voltage supplied from the power input terminal 80, so that the voltage of the positive input terminal is still higher than the voltage of the reference power supply V2 of the negative input terminal, and the dual operational amplifier OP2 continues to output high. The voltage, that is, the hard weight signal terminal 70 is still at a high voltage. That is, the voltage of the hard weight signal terminal 70 read by the reading unit 52 of the processing module 50 during the time T1 when the button P is pressed is still a high voltage, and the processing module 50 does not perform hard weight setting on the system.

After the button P is released, the triode Q2 is turned on, and since the capacitor C1 resistor R3 constitutes a delay circuit, the output terminal of the dual operational amplifier OP1 continues to output a low voltage for a period of time and continues to output a high voltage. The triode Q2 transmits the voltage outputted from the output terminal of the dual operational amplifier OP1 to the second delay comparison module 40. The second delay comparison module 40 first receives a low voltage for a period of time and continuously receives the high voltage. Since the capacitor C4 resistor R6 constitutes a delay circuit, the voltage of the positive input terminal of the dual operational amplifier OP2 is delayed by a period of time and lower than the voltage of the reference power source V2 of the negative input terminal. This period is recorded as T2, and the dual operational amplifier OP2 The output voltage is delayed from high voltage to low voltage after T2. Then, the capacitor C4 is charged again, so that the voltage of the positive input terminal of the dual operational amplifier OP2 is higher than the voltage of the reference power supply V2 of the negative input terminal, and the output voltage of the dual operational amplifier OP2 is changed from a low voltage to a high voltage. Therefore, after the button P is released, the output voltage of the dual operational amplifier is delayed by T2, and then the high voltage becomes a low voltage, and then the low voltage becomes a high voltage.

Please refer to FIG. 3a, which is a voltage simulation waveform diagram of the soft weight signal terminal 60. Press button P at 0.1 s and release button P at 0.6 s, which is T1. The voltage of the soft weight signal terminal 60 is a high voltage before the button P is pressed, that is, 0.1 s. When the button P is pressed to release between 0.1s and 0.6s, the voltage of the soft weight signal terminal 60 is a low voltage. When the button P is released, that is, 0.6 s, the voltage of the soft weight signal terminal 60 instantaneously becomes a high voltage.

Please refer to FIG. 3b, which is a voltage simulation waveform diagram of the hard weight signal terminal 70. During the period of T1, the voltage of the hard weight signal terminal 70 is always a high voltage, and after the button P is released, after a short period of time (compared with the time T2 in FIG. 3a and FIG. 3b), the The voltage of the hard weight signal terminal 70 becomes a low voltage, which becomes a high voltage after about 0.1 second.

Since the voltage of the hard weight signal terminal 70 is delayed from high to low over the T2 period, the falling edge of the voltage of the hard weight signal terminal 70 does not coincide with the rising edge of the voltage of the soft weight signal terminal 60. This can prevent the processing module 50 from working properly due to the overlap of the read voltages.

The switch circuit 100 generates a low voltage on the soft weight signal terminal 60 every time the button P is pressed, and then generates a signal from the high voltage to the low voltage to the high voltage on the hard weight signal terminal 70. If the button P is pressed for the set time of the processing module 50 to be set, the soft weight setting is performed, otherwise the hard weight setting is performed. The first delay comparison module 20 is configured to output a first low-to-high voltage to the second delay comparison module 40. The second delay comparison module 40 is configured to ensure that the hardware is delayed for a period of time T2 after the switch is released. The voltage at the fixed end is changed from high to low, and then from low to high. The aforementioned switch circuit 100 can control the soft weight of the system and control the hard weight of the system through a button P.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

10‧‧‧First switch module
20‧‧‧First Delay Comparison Module
30‧‧‧Second switch module
40‧‧‧Second Delay Comparison Module
50‧‧‧Processing module
52‧‧‧Reading unit
54‧‧‧judging unit
56‧‧‧Setting unit
58‧‧‧Execution unit
60‧‧‧ soft weight fixed signal end
70‧‧‧ Hard weight signal
80‧‧‧Power input
100‧‧‧Switch circuit
Q1‧‧‧PNP type triode
Q2‧‧‧NPN type triode
P‧‧‧ switch button
OP1, OP2‧‧‧ dual operational amplifier
V1, V2‧‧‧ reference power supply
R1, R2, R3, R4, R5, R6, R7‧‧‧ resistance
C1, C2, C3, C4, C5‧‧‧ capacitors

1 is a circuit diagram of a preferred embodiment of a switching circuit of the present invention.

2 is a block diagram of a processing module.

FIG. 3a is a voltage simulation waveform diagram of the soft body weight signal end of the switch circuit of the present invention.

FIG. 3b is a voltage simulation waveform diagram of the hard weight fixed signal end of the switch circuit of the present invention.

10‧‧‧First switch module

20‧‧‧First Delay Comparison Module

30‧‧‧Second switch module

40‧‧‧Second Delay Comparison Module

50‧‧‧Processing module

60‧‧‧ soft weight fixed signal end

70‧‧‧ Hard weight signal

80‧‧‧Power input

100‧‧‧Switch circuit

Q1‧‧‧PNP type triode

Q2‧‧‧NPN type triode

P‧‧‧ switch button

OP1, OP2‧‧‧ dual operational amplifier

V1, V2‧‧‧ reference power supply

R1, R2, R3, R4, R5, R6, R7‧‧‧ resistance

C1, C2, C3, C4, C5‧‧‧ capacitors

Claims (8)

A switching circuit includes a power input terminal, a first switch module, a second switch module, a first delay comparison module, a second delay comparison module, a soft weight signal terminal, a hard weight signal terminal, and a a processing module, the first switch module includes a button and a PNP type triode, the power input end is grounded through a first resistor and the button, and the power input end further transmits a second resistor and a third resistor The input end and the output end of the second delay comparison module are connected, the base of the PNP type triode is connected to the node of the first resistor and the button, and the soft weight signal end, the emitter is connected to the power input end, and the first connection of the collector is connected. Comparing the input end of the module and grounding through a fourth resistor, the control end of the second switch module is connected to the soft weight signal end, the first end is connected to the output end of the first delay comparison module, and the second end is connected to the second resistor And the node of the second delay comparison module, the hard weight signal end is connected to the output of the second delay comparison module, and the soft weight signal end and the hard weight signal end are both The processing module is connected, and the processing module stores a preset time. When the button is not pressed, the first delay comparison module outputs a high voltage, and the soft weight signal end and the hard weight signal end are all high voltage, and the button is pressed. When the soft weight is fixed to the low voltage, the hard weight is still high voltage, the first delay comparison module outputs a low voltage, and the second switch module disconnects the first delay comparison module and the second delay comparison module. After the release button is pressed, the first delay comparison module outputs a low voltage and then outputs a high voltage, the soft weight signal terminal becomes a high voltage, and the second switch module is turned on, and is delayed by the second delay comparison module after the release button is pressed. After the hard weight signal is turned to a low voltage, the hard weight signal is turned to a high voltage again. If the button is pressed for a preset time stored in the processing module, the processing module controls the computer. The soft weight is fixed, otherwise the hard weight is determined. The switching circuit of claim 1, wherein the processing module comprises a reading unit, a setting unit, a determining unit and an executing unit, wherein the reading unit reads the soft weight signal end and the hard weight setting The voltage at the signal end, the setting unit sets the preset time, the determining unit determines the voltage of the soft weight signal end and the hard weight signal end, and the execution unit operates the system according to the result of the determination by the determining unit. The switch circuit of claim 1, wherein the first delay comparison module comprises a resistor, a capacitor, a dual operational amplifier and a reference power supply, and one end of the resistor is connected to the emitter of the PNP type triode. The other end is grounded through the capacitor. The negative input terminal of the dual operational amplifier is connected to the resistor and the node of the capacitor. The positive input terminal of the dual operational amplifier is grounded through the reference power supply. The switching circuit of claim 1, wherein the second switching module comprises an NPN-type triode and a resistor, and a base of the NPN-type triode is transmitted through the resistor and the PNP-type triode. The base is connected, and the collector of the triode is connected to the output of the first delay comparison module, and the emitter of the triode is connected to the input end of the second delay comparison module and the node of the second resistor. The switching circuit of claim 4, wherein the collector of the NPN type triode is also grounded through a capacitor. The switching circuit of claim 4, wherein the NPN triode emitter is grounded through a capacitor. The switch circuit of claim 1, wherein the second delay comparison module comprises a capacitor, a resistor, a dual operational amplifier and a reference power supply, and one end of the resistor serves as an input end of the second delay comparison module. The other end is grounded through the capacitor. The positive input terminal of the dual operational amplifier is connected to the node of the resistor and the capacitor. The negative input terminal of the dual operational amplifier is connected to the reference power supply and grounded. The output of the dual operational amplifier serves as the The second delay compares the output of the module. The switching circuit of claim 7, wherein the output of the dual operational amplifier is also grounded through a capacitor.