TWI624205B - Circuit board and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a circuit board, comprising: providing a first core layer, the first core layer comprising a core dielectric layer and a core circuit layer; forming a first metal layer covering the first core layer; forming a a second metal layer on the first metal layer and covering a portion of the first metal layer; removing the first metal layer not covered by the second metal layer; forming a central dielectric material layer covering the first core layer and the second a metal layer; a second core material layer disposed on the central dielectric material layer; removing a portion of the central dielectric material layer over the second metal layer and the second core material layer a portion to form a recess that exposes the second metal layer; removes the second metal layer; and removes the first metal layer at the bottom of the recess.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a recess and a method of fabricating the same.

In recent years, with the development of the technology industry, electronic products such as notebook computers, tablet computers and smart phones have frequently appeared in daily life. The types and functions of electronic products are becoming more and more diverse, so the circuit boards used in electronic products have also become an important role in related technologies. In addition, in order to increase the application of the board, the board can also be designed as a multi-layer board according to requirements to increase the space for wiring layout inside, and many different kinds of electronic components, such as connectors, wafers or optoelectronic components. It can be configured on a multi-layer circuit board according to requirements to increase its use function.

Conventional techniques reduce the assembly thickness of electronic components and circuit boards by forming a recess in a circuit board and disposing electronic components such as a chip package structure in the recesses. Before the groove is formed, a laser blocking layer having a laser depth function is formed at the edge of the predetermined area of the groove, but the laser blocking layer is formed after the groove is formed. It will still be retained, which will affect the freedom of circuit design, so other processes are needed to improve.

According to various embodiments of the present invention, there is provided a method of fabricating a circuit board, the method comprising: providing a first core layer, the first core layer comprising a core dielectric layer and a core circuit layer; forming a first metal a layer covering the first core layer; forming a second metal layer on the first metal layer and covering a portion of the first metal layer; removing the first metal layer not covered by the second metal layer; forming a center a layer of dielectric material covering the first core layer and the second metal layer; forming a second core material layer, the second core material layer being disposed on the central dielectric material layer; removing the center above the second metal layer a portion of the dielectric material layer and a portion of the second core material layer to form a recess that exposes the second metal layer; removing the second metal layer; and removing the first metal layer at the bottom of the recess .

In some embodiments, the step of forming a central dielectric material layer includes: providing a central dielectric material layer, the central dielectric material layer being disposed on the first core layer; and pressing the first core layer and the central dielectric material Floor.

In some embodiments, the step of removing the central dielectric material layer and the second core material layer over the second metal layer to form a recess comprises: cutting a portion of the central layer above the edge of the second metal layer with a beam of light a layer of electrically material and a portion of the second core material layer; and removing a residual portion of the central dielectric material layer that is not removed above the second metal layer and a residual portion of the second core material layer.

In some embodiments, the method of manufacturing the circuit board is further included in the pressure The surface of the core circuit layer in the first core layer is oxidized before the first core layer and the central dielectric material layer.

In some embodiments, the method of fabricating the circuit board further includes forming a protective barrier film covering the second metal layer after removing the first metal layer not covered by the second metal layer.

In certain embodiments, the material of the second metal layer is gold, silver, copper, nickel, tin, titanium, aluminum, or a combination thereof.

In certain embodiments, the second metal layer has a thickness of between 10 and 50 μm .

In certain embodiments, the first metal layer has a thickness of less than 4 μm .

A plurality of embodiments of the present invention provide a circuit board comprising: a first core layer comprising a core dielectric layer and a core circuit layer, the core circuit layer 114 being disposed on the core dielectric layer; a central dielectric a layer disposed on the first core layer; a second core layer disposed on the central dielectric layer; and a recess extending through the second core layer and the central dielectric layer and exposing a portion of the core circuit layer, wherein The portion of the central dielectric layer adjacent the bottom edge of the recess has no laser blocking pattern.

In some embodiments, the circuit board further includes a line pattern located in a portion of the core circuit layer exposed by the recess.

The above and other objects, features, and advantages of the invention will be apparent from

110‧‧‧First core layer

112‧‧‧ core dielectric layer

114‧‧‧core circuit layer

116‧‧‧core circuit layer

120‧‧‧First line structure

122‧‧‧ dielectric layer

124‧‧‧Line layer

126‧‧‧ dielectric layer

128‧‧‧Line layer

130‧‧‧First metal layer

140‧‧‧Second metal layer

150‧‧‧Protection barrier

160‧‧‧Center dielectric material layer

162‧‧‧ dielectric layer

172‧‧‧ Conductive layer

180‧‧‧Second core material layer

182‧‧‧core dielectric layer

184‧‧‧ core circuit layer

186‧‧‧ Conductive layer

190‧‧‧Second line structure

192‧‧‧ dielectric layer

194‧‧‧Line layer

R‧‧‧ groove

1A-1I is a cross-sectional view showing each process stage of a method of manufacturing a circuit board according to an embodiment of the present invention.

The manufacture and use of the present embodiments will be discussed in detail below, however, it should be appreciated that the present invention provides an innovative concept of practice in which a wide variety of specific content can be presented. The embodiments or examples described below are illustrative only and are not intended to limit the scope of the invention.

In addition, in this document, spatially relative terms such as "below", "under", "below" may be used in order to facilitate a description of the relationship between a component or feature and other components or features depicted in the drawings. ", above", "above" and similar terms. These spatially relative terms are intended to cover all the different orientations of the component in use or operation, and are not limited to the orientation depicted in the drawings. The device can be oriented in other ways (rotated 90 degrees or in the other direction), and the spatially relative descriptors used herein can be interpreted accordingly.

Various embodiments relating to a circuit board and a method of fabricating the same are provided below, in which the structure and nature of the circuit board and the preparation steps or operations of the circuit board are described in detail.

1A-1I are schematic cross-sectional views showing respective process stages in a method of manufacturing a circuit board according to various embodiments of the present invention. In FIG. 1A, a first core layer 110 is provided. The first core layer 110 includes a core dielectric layer 112 and two. The core circuit layers 114, 116, in one embodiment, the first core layer 110 may include only one core circuit layer 114. In an embodiment, in some embodiments, a first line structure 120 can be selectively disposed on a side of the first core layer 110 away from the core line layer 114. In an embodiment, the first wiring structure 120 includes two dielectric layers 122, 126 and two wiring layers 124, 128 stacked on each other. The dielectric layer 122 is disposed on a side of the first core layer 110 away from the core circuit layer 114. The circuit layer 124 is disposed on the dielectric layer 122 and located between the dielectric layers 122 and 126. The circuit layer 128 and the circuit layer 124 are respectively They are disposed on opposite sides of the dielectric layer 126. Certainly, the embodiment does not limit the number of circuit layers and dielectric layers of the first circuit structure 120. In other words, the number of circuit layers or dielectric layers may be one or more. Each of the circuit layers may also be electrically connected to each other by a plurality of via holes, and the via holes may be buried holes, blind holes, through holes or any conventional type of via holes.

In FIG. 1B, a first metal layer 130 is formed overlying the first core layer 110. In an embodiment, the material of the first metal layer 130 may be gold, silver, copper, or a combination thereof. In another embodiment, the first metal layer 130 has a thickness of less than 4 μm, such as 3 μm, 2 μm, 1 μm, 0.5 μm, 0.1 μm, or 0.05 μm, preferably less than 3 μm.

As shown in FIG. 1C, a second metal layer 140 is formed on the first metal layer 130 and covers a portion of the first metal layer 130. In one embodiment, the second metal layer 140 is a laser barrier layer that protects the underlying regions from laser etch. The size and position of the area covered by the second metal layer is the size and position of the bottom of the groove which is to be formed later. In an embodiment, the material of the second metal layer 140 is gold, silver, copper, nickel, tin, titanium, aluminum, or a combination thereof. The second metal layer 140 has a thickness of 10 to 50 μm, for example, 12 μm, 15 μm, 17 μm, 20 μm, 25 μm, 30 μm, and 35 μm. Or 40 μm, preferably 12-25 μm. In one embodiment, the second metal layer 140 can be formed using sputtering or evaporation, such as using plasma plating, physical vapor deposition, or chemical vapor deposition.

In FIG. 1D, the first metal layer 130 not covered by the second metal layer 140 may be removed using, for example, dry etching or wet etching. For example, using an isotropic dry etch, the etch must be selective at the same time, and the second metal layer 140 is hardly etched when the first metal layer 130 not covered by the second metal layer 140 is removed. In other embodiments, the first metal layer 130 is copper, and the second metal layer 140 is other metals. The wet etching can be used, and the etching liquid has a high etching selectivity, that is, the etching rate of copper is greater than the etching rate of other metals, and etching The liquid may comprise sulfuric acid, hydrogen peroxide, phenyltetrazole, chloride, or benzenesulfonic acid or a combination thereof.

As shown in FIG. 1E, in some embodiments, after removing the first metal layer 130 not covered by the second metal layer 140, a protection and masking film (PMF) 150 may be formed. Two metal layers 140. In an embodiment, the next step can be performed without forming the protective barrier film 150 covering the second metal layer 140. In another embodiment, the protective barrier film 150 can be a release layer that facilitates removal of material over the protective set of membranes.

As shown in FIG. 1F, a central dielectric material layer 160 is formed to cover the first core layer 110, the protective barrier film 150, and the second metal layer 140. In an embodiment in which the protective barrier film 150 is not formed to cover the second metal layer 140, the central dielectric material layer 160 is formed to cover the first core layer 110 and the second metal layer 140.

In one embodiment, the step of forming a layer of central dielectric material 160 A layer 160 of central dielectric material is disposed on the first core layer 110 to press the first core layer 110 and the central dielectric material layer 160. In an embodiment, an additional blackening or browning process may be performed before the pressing process to oxidize the surface of the line to form a high tear strength black/brown oxidized copper nitrite, thereby increasing the inner layer and the film (not Shown in the figure) The ability to bond when pressed.

As shown in FIG. 1G, a second core material layer 180 is formed, and the second core material layer 180 is disposed on the central dielectric material layer 160. The second core material layer 180 may include a core dielectric layer 182, a core circuit layer 184, and a conductive layer 186, wherein the core circuit layer 184 and the conductive layer 186 may be electrically connected by via holes in the core dielectric layer 182. A dielectric layer 162 and a conductive layer 172 may also be selectively formed on a side of the first line structure 120 away from the first core layer 110. A second wiring structure 190 is further selectively formed, and the second wiring structure 190 includes a dielectric layer 192 and a wiring layer 194. Of course, this embodiment does not limit the number of circuit layers and dielectric layers of the second circuit structure 190. In other words, the number of circuit layers or dielectric layers may be one or more. There may also be electrical connections between the circuit layers.

As shown in FIG. 1H, portions of the central dielectric material layer 160 and the second core material layer 180 positioned above the second metal layer 140 are removed by, for example, stripping to form a recess R. In an embodiment, the method of forming a recess R comprises the following steps. First, the central dielectric material layer 160 and the second core material layer 180 located above the edge of the second metal layer 140 are cut using, for example, a laser beam, and then the center that is not removed by the laser above the second metal layer 140 is removed. The residual portion of the dielectric material layer 160 and the remaining portion of the second core material layer 180. In an embodiment, if the manufacturing process The protective barrier film 150 is formed to cover the second metal layer 140, and the protective barrier film 150 can be removed after the recess R is formed.

As shown in FIG. 1I, the second metal layer 140 is removed, and the second metal layer 140 can be removed using selective etching. The first metal layer 130 at the bottom of the recess R is then removed.

As shown in FIG. 1I, in accordance with one embodiment of the present invention, a circuit board is provided that includes a first core layer, a central dielectric layer, a second core layer, and a recess. The first core layer includes a core dielectric layer and a core circuit layer, and the core circuit layer is disposed on the core dielectric layer. The central dielectric layer is disposed on the first core layer, and the second core layer is disposed on the central dielectric layer. The recess extends through the second core layer and the central dielectric layer and exposes a portion of the core wiring layer. The portion of the central dielectric layer adjacent the bottom edge of the recess has no laser blocking pattern.

In some embodiments, because the bottom edge of the recess R of the circuit board has no laser blocking pattern, the core circuit layer 114 exposed at the bottom of the recess R can be designed to be electrically connected to the outside of the recess R. In the prior art, since the laser blocking pattern hinders the electrical connection of the line patterns in the bottom of the groove R, the area in the groove R is usually not designed.

An advantage of an embodiment of the present invention is that the bottom edge of the recess of the circuit board has no laser blocking pattern, which greatly increases the degree of freedom in circuit design.

The various embodiments are summarized above to enable those skilled in the art to understand the various aspects of the disclosure. Those skilled in the art should understand and rely on this basis to design or modify other compositions and structures for the same purpose. / or embodiments with the same advantages as described herein. Those skilled in the art will appreciate that any substitution, substitution, or alteration can be made without departing from the spirit and scope of the invention.

Claims (9)

A method of manufacturing a circuit board, comprising: providing a first core layer, the first core layer comprising a core dielectric layer and a core circuit layer; forming a first metal layer overlying the core circuit layer; forming a a second metal layer on the first metal layer covering a portion of the first metal layer; removing the first metal layer not covered by the second metal layer; forming a central dielectric material layer covering the first a core layer and the second metal layer; forming a second core material layer disposed on the central dielectric material layer; removing the central dielectric material layer above the second metal layer a portion and a portion of the second core material layer to form a recess, the recess exposing the second metal layer; removing the second metal layer; and removing the first metal layer at the bottom of the recess, exposing A portion of the core circuit layer is formed, wherein the bottom of the core circuit layer is on the same plane as the bottom of the groove. The method of manufacturing the circuit board of claim 1, wherein the forming the central dielectric material layer comprises: providing a central dielectric material layer, the central dielectric material layer being disposed on the first core layer; The first core layer and the central dielectric material layer are laminated. The method of manufacturing a circuit board according to claim 1, wherein the step of removing the portion of the central dielectric material layer and the portion of the second core material layer over the second metal layer to form the groove The method includes: cutting the central dielectric material layer and the second core material layer over an edge of the second metal layer by a beam; and removing a residual portion of the central dielectric material layer above the second metal layer And a residual portion of the second core material layer. The method of manufacturing a circuit board according to claim 2, further comprising: oxidizing a surface of the core circuit layer in the first core layer before pressing the first core layer and the central dielectric material layer. The method for manufacturing a circuit board according to claim 1, further comprising: forming a protection and masking film (PMF) covering the first metal layer not covered by the second metal layer The second metal layer. The method of manufacturing a circuit board according to claim 1, wherein the material of the second metal layer is gold, silver, copper, nickel, tin, titanium, aluminum or a combination thereof. The method of manufacturing a circuit board according to claim 1, wherein the second metal layer has a thickness of 10 to 50 μm. The method of manufacturing a circuit board according to claim 1, wherein the first metal layer has a thickness of less than 4 μm. A circuit board comprising: a first core layer comprising a core dielectric layer and a core circuit layer, the core circuit layer being disposed on the core dielectric layer; a central dielectric layer disposed on the first core layer a second core layer disposed on the central dielectric layer; and a recess extending through the second core layer and the central dielectric layer and exposing a portion of the core circuit layer, wherein the core The bottom of the circuit layer is on the same plane as the bottom of the recess, and the core circuit layer of the portion includes a first line pattern that is completely exposed and a second line pattern that is partially exposed.