TWI623197B - Programmable method of transmitting signal - Google Patents

Abstract

A programmable signal transmission method suitable for multiple circuit boards and multiple transmission lines. The programmable signal transmission method includes a circuit board selecting one of a plurality of output signals according to the first conversion signal. A circuit board outputs a selected output signal from one of the pins to a transmission line electrically connected to the pin according to the configuration signal. A transmission line transmits an output signal to each of the boards electrically connected to the transmission line. Each board selectively receives or ignores the output signal on the transmission line according to the configuration signal from one of the pins. The circuit board that has selected to receive the output signal sets the transmission channel of the output signal according to the second conversion signal.

Description

Programmable signal transmission method

The present invention relates to a programmable signal transmission method, and more particularly to a signal transmission method for use between a plurality of circuit boards.

Under the evolution of information processing technology, a large amount of data can be transmitted between the circuit board and the circuit board through the transmission line, thereby achieving the purpose of data input, output or control. In the prior art, the signal is transmitted between the circuit board and the circuit board by directly connecting the signal source circuit board to the circuit board of the signal destination, so as to achieve signal communication between the circuit board and the circuit board. The purpose of the transfer.

As the amount of information processing increases, so does the number of circuit components and processing functions on the board. In the conventional technical method, when the function is increased or the signal transmitted is increased, it is often necessary to increase the number of pins of the board and the number of transmission lines to satisfy the amplification function and the increased signal.

The present invention provides a programmable signal transmission method for solving the problem of increasing the number of pins and the number of transmission lines in the prior art in order to satisfy the amplification function or increase the signal.

The programmable signal transmission method disclosed in the present invention is applicable to multiple circuit boards and multiple transmission lines. The programmable signal transmission method includes a circuit board selecting one of a plurality of output signals according to the first conversion signal. A circuit board outputs a selected output signal from one of the pins to a transmission line electrically connected to the pin according to the configuration signal. A transmission line transmits an output signal to each of the boards electrically connected to the transmission line. Each board selectively receives or ignores the output signal on the transmission line according to the configuration signal from one of the pins. The circuit board that has selected to receive the output signal sets the transmission channel of the output signal according to the second conversion signal.

According to the programmable signal transmission method disclosed in the above, the programmed first and second conversion signals can be used to select the signal to be output and the purpose of the signal to be transmitted, and the transmission is configured by configuring the signal. The signal transmission line allows signals to be transmitted more efficiently between boards. In this way, new functions or newly added signals can communicate with each other through stylized transmission methods. There is no need to increase the number of board pins and the number of transmission lines, so that the content that can be communicated between the boards is more Flexible for multiples.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a plurality of circuit boards electrically connected to a transmission line according to an embodiment of the invention. As shown in FIG. 1, a plurality of circuit boards are electrically connected to a plurality of transmission lines. Taking three circuit boards 1 and three transmission lines tr1, tr2, and tr3 as an example, each circuit board 1 has a pin pin1, a pin pin2, and a pin pin3, and the pin 1 of each circuit board 1 is electrically The transmission pin tr1 is connected, and the pin pin 2 of each circuit board 1 is electrically connected to the transmission line tr2, and the pin pin 3 of each circuit board 1 is electrically connected to the transmission line tr3. The number of transmission lines usually matches the number of pins of the board 1, but is not limited thereto. The transmission line is, for example, a cable, a trace on the casing, or other suitable transmission signal component. A plurality of circuit boards transmit signals through a plurality of transmission lines for communication. For example, one of the circuit boards outputs signals to control other circuit boards and circuit boards of the group to jointly generate test signals or perform other signal communication operations. No restrictions.

Each of the pins of the circuit board 1 has a transmission module 10 and a receiving module 12. More specifically, the pin 1 of the circuit board 1 outputs the signal of the circuit board 1 through the transmission module 10, and receives the signal on the transmission line by the receiving module 12. For example, the signal outputted by the transmission module 10 is transmitted to the transmission line tr1, and the signal on the transmission line tr1 can also be transmitted to the receiving module 12. The transmission module 10 and the receiving module 12 of the pin 2 and the pin 3 are similar and will not be described again. Each of the transmission modules 10 of the circuit board 1 has a plurality of input terminals, and the plurality of input terminals are electrically connected to other circuit components in the circuit board 1 for receiving output signals generated by other circuit components. In practice, the output signals generated by different circuit components or the output signals generated by different output terminals of the same circuit component are not necessarily the same. In other words, the type, purpose, definition, or destination of each output signal is different, and the embodiment is not limited.

In one embodiment, the transmission module 10 and the receiving module 12 are, for example, a Field-programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or other programmable A circuit component that implements a logic circuit. Referring to FIG. 1 and FIG. 2, FIG. 2 is a schematic diagram of a transmission module according to an embodiment of the present invention. As shown in FIG. 2, the transmission module 10 has a multiplexer 101, for example. A delay unit 103, an Arithmetic Logic Unit (ALU) 105, an encoder 107, a flip-flop 108, and a buffer 109 are provided. The multiplexer 101 is electrically connected to other circuit components in the circuit board 1 for selecting an output signal from the plurality of output signals according to the first conversion signal. The delay device 103 is configured to delay the selected output signal according to the delay adjustment signal. In practice, when the multiplexer 101 receives the output signal provided by other circuit components inside the circuit board 1, other circuit boards are still performing other signal transmission, or other circuit boards are not ready to receive the circuit board 1 output. Signal. Therefore, the delay device 103 indicates the delay time according to the delay adjustment signal, for example, waiting for one or more clock cycles or waiting for other types of time lengths, and triggering the multiplexer 101 to output the delayed output signals to the arithmetic logic device 10, However, the multiplexer 101 is not limited to delay outputting the output signal to the arithmetic logic 10.

The arithmetic logic 105 receives the output signal output by the multiplexer 101, such as a delayed output signal. The arithmetic logic 105 selectively logically operates the delayed output signal and the first data signal according to the logic selection signal. That is to say, when the arithmetic logic 105 selects the signal according to the logic and does not logically operate the delayed output signal and the first data signal, the arithmetic logic unit 105 directly outputs the delayed output signal. When the arithmetic logic 105 logically operates the delayed output signal and the first data signal according to the logic selection signal, the arithmetic logic unit 105 outputs the output signal that has been logically operated with the first data signal. The first data signal is, for example, a signal received by other pins in the circuit board 1 or a signal generated by another circuit component or other possible signals, which is not limited in this embodiment. The logic operation combines the output signal with the first data signal, for example, by logical complement (NOT), logical multiplication (AND), logical addition (OR), or a combination of these operational logics.

The encoder 107 is configured to generate the first forced signal F0 and the enable signal according to the first control signal. The arithmetic logic 105 selectively outputs a logic operation signal, a logic high level or a logic low level according to the first forced signal F0. Specifically, when the encoder 107 does not output the first forced signal F0 to the arithmetic logic 105, the arithmetic logic 105 selectively outputs a logical operation signal according to the logic selection signal, and the logical operation signal is the output after the logic operation. Signal or output signal that is not logically operated. When the encoder 107 outputs the first forced signal F0 to the arithmetic logic 105, the first forced signal F0 is, for example, high or low. When the first forced signal F0 is low, the arithmetic logic 105 outputs a logic low. When the first forced signal F0 is high, the arithmetic logic 105 outputs a logic high potential. In other words, the first forced signal F0 is used to control the arithmetic logic 105 to output a logic operation signal, a logic high level or a logic low level.

The flip-flop 108 receives the signal output by the arithmetic logic device 105, that is, receives one of the logically output signal, the unlogic output signal, the logic low potential, and the logic high potential, and is enabled in the first clock. When the signal is triggered, the received signal is output to the buffer 109. The buffer 109 selectively outputs the signal received from the flip-flop 108 to the transmission line according to the enable signal generated by the encoder 107, or does not output the signal received from the flip-flop 108, and sets the transmission line to an electrical high resistance. High resistance state (HRS).

On the other hand, the circuit board 1 selects to output the selected output signal from a specific pin according to the configuration signal, and transmits the output signal to each of the circuit boards electrically connected to the transmission line through the transmission line electrically connected to the pin. Pin to receive the output signal. When the board selects the pin to output the signal according to the configuration signal, the enable signal of each pin controls whether the buffer 109 outputs the signal received from the flip-flop 108. That is to say, when the pin is selected to output a signal, the pin buffer is enabled to enable the signal received from the flip-flop 108 to the transmission line, and the transmission line is set as the flip-flop 108. The output signal. When the pin is not selected for the output signal, the pin buffer is not enabled by the enable signal, and the buffer 109 does not output the signal received from the flip-flop 108 to the transmission line, that is, the transmission line is set to be electrically High resistance state. In practice, when one of the boards outputs a signal on the transmission line, the other board sets the transmission line to an electrical high-impedance state to prevent multiple boards, or even all boards, from simultaneously outputting the same line. Causes damage to the transmission line.

In the example of FIG. 2, the transmission module 10 is implemented by a multiplexer 101, a delay 103, an arithmetic logic 105, an encoder 107, a flip-flop 108, and a buffer 109, but the example of FIG. 2 is only convenient. For the purposes of illustration, the present embodiment does not actually limit the circuit architecture of the transmission module 10. In other embodiments, the transmission module 10 can also be implemented by other circuits or by canceling some components. For example, the delay decoder 103 is cancelled or the encoder 107 is controlled by other controllers to control the arithmetic logic 105 and the buffer 109. This embodiment does not allow limit.

Next, please refer to FIG. 1 and FIG. 3 together. FIG. 3 is a schematic diagram of a receiving module according to an embodiment of the invention. As shown in FIG. 3, the receiving module 12 has a buffer 121 and a flip-flop. 123. A demultiplexer 125 and an encoder 127 are demultiplexed. The buffer 121 receives the signal on the transmission line according to the configuration signal. That is to say, when one of the plurality of circuit boards transmits the selected output signal from the transmission module 10 and the transmission line of the specific pin according to the configuration signal, each of the circuit boards is electrically connected to the specific transmission line. The receiving module 12 receives the output signal on the transmission line, that is, the buffer 121 of the receiving module 12 receives the signal on the transmission line according to the configuration signal. Since the buffer 121 of the receiving module 12 receives the output signal when the output signal is received on the transmission line, the receiving module 12 passively receives the output signal. Therefore, when the output signal is transmitted by one of the boards 1 When the group 10 outputs, the receiving module of the same board will also receive the output signal, but not limited to this.

Then, the flip-flop 123 of the receiving module 12 outputs the output signal to the demultiplexer 125 when the second clock enable signal is triggered. The demultiplexer 125 sets the transmission channel of the output signal according to the second conversion signal. The transmission channel is a channel through which the receiving module 12 is electrically connected to other components of the circuit board 1. The receiving module 12 can transmit the output channel to a specific circuit component in the circuit board 1 by setting a transmission channel of the output signal, and provide the output signal to a specific circuit component for use. In other words, the second conversion signal defines the type, purpose, and transmission destination of the output signal, and the demultiplexer 125 transmits the output signal to the specific circuit component according to the second conversion signal, so that the specific circuit component can operate according to the output signal. .

The encoder 127 is configured to generate a second forced signal F1 according to the second control signal. The demultiplexer 125 selectively sets the transmission channel in one of a logic high level and a logic low level according to the second forced signal F1. Specifically, when the encoder 127 does not output the second forced signal F1 to the demultiplexer 125, the demultiplexer 125 sets the transmission channel of the output signal according to the second conversion signal, that is, the circuit board 1 receives the mode. Group 12 receives the output signal on the transmission line. When the encoder 127 outputs the second forced signal F1 to the encoder 127, the second forced signal F1 is, for example, high or low. When the second forced signal F1 is low, the demultiplexer 125 sets the selected transmission channel to be logic low according to the output channel selected by the second conversion signal. When the second forced signal F1 is high, the demultiplexer 125 sets the selected transmission channel to a logic high level according to the output channel selected by the second conversion signal. In other words, when the demultiplexer 125 sets the selected transmission channel to logic low or logic high, that is, the board 1 ignores the output signal on the transmission line.

In the embodiment, the flip-flop 123 outputs the output signal to the demultiplexer 125 in addition to the second clock-enabled signal, and the output signal can also be output to the previous pin or the next pin. In the transmission module, as the second data signal. In other words, the second data signal is, for example, the first data signal received by the arithmetic logic of the next pin, but is not limited thereto. In addition, in the example of FIG. 3, the receiving module 12 is implemented by a buffer 121, a flip-flop 123, a demultiplexer 125, and an encoder 127, but the example of FIG. 3 is for convenience of explanation. This embodiment does not actually limit the circuit architecture of the receiving module 12. In other embodiments, the receiving module 12 can also be implemented by other circuits or by canceling some components. This embodiment is not limited.

1 and FIG. 4, FIG. 4 is a flow chart showing the steps of the method for transmitting a programmable signal according to an embodiment of the present invention. As shown in FIG. 4, in step S201, multiple One of the boards of the circuit board selects one of the plurality of output signals according to the first conversion signal, that is, selects an output signal generated by other circuit components inside the circuit board according to the first conversion signal. In step S203, one of the boards selects one of the plurality of pins according to the configuration signal, and outputs the output signal selected in step S201 from the selected pin, and outputs the transmission line electrically connected to the pin. In step S205, one of the transmission lines transmits an output signal to each of the boards electrically connected to the transmission line. In step S207, each circuit board electrically connected to the transmission line selectively receives or ignores the output signal on the transmission line from one of the pins according to the configuration signal. In step S209, the circuit board that has selected to receive the output signal sets the transmission channel of the output signal according to the second conversion signal.

In this embodiment, the circuit boards in each step are not necessarily the same circuit board or different circuit boards. For the purpose of more specific description, the following embodiments are illustrated by the first circuit board, the second circuit board, and the third circuit board illustrated in the drawings, but are not intended to limit the number and transmission manner of the circuit boards of this embodiment.

Referring to FIG. 1 and FIG. 5, FIG. 5 is a flow chart showing the steps of a method for transmitting a programmable signal according to another embodiment of the present invention. As shown in FIG. 5, in the embodiment, the output signal is, for example, It is generated by the first circuit board, and the output signal is to be transmitted to the third pin pin3 of the second circuit board. In step S301, the first circuit board selects one of the plurality of output signals according to the first conversion signal. In step S303, the first circuit board selectively delays the selected output signal according to the delay adjustment signal, and in step S305, the first circuit board selectively selects the delayed output signal according to the logic selection signal. The data signal is logically operated.

The first circuit board selectively logically operates the delayed output signal and the first data signal according to the logic selection signal when the delay adjustment signal is triggered. In step S307, when the logic selection signal instructs the first circuit board to perform a logic operation, the first circuit board is combined into, for example, a logical complement (NOT), a logical multiplication (AND), a logical addition (OR), or the like. The logic combines the output signal with the first data signal. The first circuit board selects the third pin 3 according to the configuration signal, and causes the third pin 3 to output the logically output signal when the first clock enable signal is triggered. In step S309, when the first circuit board does not logically calculate the output signal and the first data signal, the first circuit board selects the third pin 3 according to the configuration signal, and causes the third pin 3 to be in the first clock. When the enable signal is triggered, the output signal is directly output.

Then, in step S311, the third transmission line tr3 electrically connected to the third pin 3 of the first circuit board transmits the output signal to each circuit board electrically connected to the third transmission line tr3, that is, to the first circuit. The circuit board, the second circuit board, and the third circuit board. In step S313, each of the boards receives the output signal on the third transmission line tr3 from the third pin 3 . In other words, when the first circuit board selects the output signal from the third pin 3 and outputs the output signal to the third transmission line tr3 according to the configuration signal, each of the circuit boards is electrically connected to the third pin 3 of the third transmission line tr3. The output signal on the third transmission line tr3 is selected to be received, and the output signal on the third transmission line tr3 may also be selected to be ignored.

In this embodiment, since the second circuit board is to receive the output signal, in step S315, the second circuit board sets the transmission channel of the output signal according to the second conversion signal. That is to say, the second circuit board receives the output signal, and according to the indication of the second conversion signal, outputs the signal from the specific transmission channel to other circuit components in the second circuit board. However, in other embodiments, when the output signal is not to be transmitted to the third pin 3 of the second circuit board, the second circuit board may choose to ignore the output signal on the third transmission line tr3. For convenience of explanation, the following steps are The third circuit board that receives the output signal is not preset to replace the second circuit board description, that is, the third circuit board selects to ignore the output signal on the third transmission line tr3, and the third circuit board is connected to the third transmission line tr3. The receiving module determines whether the set transmission channel is logic high or logic low according to the potential of the second forced signal. Specifically, in step S317, the third circuit board determines whether the second forced signal is high. In step S319, when the second forced signal is high, the third circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic high level. In step S321, when the second forced signal is low, the third circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic low level.

In this embodiment, since the output signal is generated by the first circuit board, and the output signal is to be transmitted to the third pin 3 of the second circuit board. At this time, other pins other than the third pin 3 of the first circuit board or other circuit boards can simultaneously output a logic potential to the electrically connected transmission line. For example, please refer to FIG. 1 and FIG. 6. FIG. 6 is a flowchart of steps of a method for transmitting a programmable signal according to another embodiment of the present invention. As shown in FIG. 6, in step S401, The first pin pin1 of the first circuit board selects one of a logic high level and a logic low level according to the first forced signal. Taking the logic high potential as an example, in step S403, when the first circuit board is triggered by the first clock enable signal of the first pin 1 , the first pin 1 is selectively output according to the enable signal. The logic is high to the first transmission line tr1 to which the first pin 1 is electrically connected.

In step S405, the first transmission line tr1 transmits a logic high potential to each of the circuit boards electrically connected to the first transmission line tr1, that is, a logic high potential is transmitted to the first pin pin1 and the second circuit board of the first circuit board. The first pin pin1 and the first pin pin1 of the third circuit board. In step S407, whether each circuit board receives the output signal on the first transmission line tr1 from the first pin pin1, that is, the first circuit board selects the first pin pin1 according to the configuration signal, and outputs the signal from the first After the pin 1 is output to the first transmission line tr1, the first pin 1 of each board can choose to ignore or receive the logic high potential on the first transmission line tr1. For example, when the third circuit board receives the logic high potential on the first transmission line tr1, in step S409, the third circuit board sets the specific transmission channel to a logic high level according to the second conversion signal. When the third circuit board ignores the logic high potential on the first transmission line tr1, in step S411, it is determined whether the second forced signal of the third circuit board is high, and when the second forced signal is high, in step S413 The third circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic high level. When the second forced signal is low, in step S415, the third circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic low level.

In this embodiment, although the third circuit board ignores the logic high potential on the first transmission line tr1 in step S411, the second forced signal of the third circuit board can still make the third circuit board according to the second conversion signal. Setting the transmission channel to a logic high potential may have the same result as the third board receiving the logic high potential on the first transmission line tr1. However, in practice, whether the signal received by the third circuit board on the transmission line is set by the configuration signal, that is, the third circuit board selects which pins receive the signal on the transmission line according to the configuration signal. In other words, the configuration signal is used to group the first circuit board and the third circuit board to perform signal transmission on the first circuit board and the third circuit board. In this embodiment, the first pin pin1 of the first circuit board and the first pin pin1 of the third circuit board are connected through the first transmission line tr1 as an example. In other embodiments, if the first circuit When the pins of the board and the third circuit board are matched, that is, for example, the first pin pin1 of the first circuit board is connected to the third pin pin3 of the third circuit board, and the stylized configuration signal can be conveniently set. The third pin pin3 of the three circuit board receives the signal output by the first pin pin1 of the first circuit board.

In another embodiment, the output signal is, for example, a logic high potential generated by the second circuit board and is transmitted to the second pin 2 of the third circuit board. Please refer to FIG. 1 and FIG. 7. FIG. 7 is a flow chart showing the steps of the method for transmitting a programmable signal according to another embodiment of the present invention. As shown in FIG. 7, in step S501, the second circuit board is shown in FIG. One of the plurality of output signals is selected according to the first conversion signal. In step S503, the second circuit board delays the selected output signal, and in step S505, the second circuit board logically operates the delayed output signal and the data signal. In step S507, the second circuit board selects a logic high level from the logic high level and the logic low level according to the first forced signal, and outputs the signal according to the configuration signal from the second pin 2 when the first clock enable signal is triggered. The logic is high to the second transmission line tr2.

In step S509, the second transmission line tr2 transmits a logic high potential to each of the circuit boards electrically connected to the second transmission line tr2. In step S511, whether each of the boards receives the output signal on the second transmission line tr2 from the second pin 2, that is, the first board selects the second pin 1 according to the configuration signal, and the output signal is connected from the second After the pin 1 is output to the second transmission line tr2, the second pin 2, which is electrically connected to the second transmission line tr2, can selectively receive or ignore the output signal on the second transmission line tr2. When the third circuit board receives the output signal on the second transmission line tr2, in step S513, the third circuit board sets the transmission channel of the output signal according to the second conversion signal, that is, sets the selected transmission channel to a logic high level.

In this embodiment, since the third circuit board is configured to receive the output signal, in step S513, the third circuit board receives the output signal, and according to the indication of the second conversion signal, outputs the output signal to the specific transmission channel to Other circuit components within the third board. However, in other embodiments, when the output signal is not to be transmitted to the second pin 2 of the third circuit board, the third circuit board may choose to ignore the output signal on the second transmission line tr2. For convenience of explanation, the following steps replace the third circuit board description with the first circuit board that does not preset to receive the output signal, that is, at this time, the first circuit board ignores the output signal on the second transmission line tr2, and therefore, In step S515, it is determined whether the second forced signal of the first circuit board is high. When the second forced signal of the first circuit board is high, in step S517, the first circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic high level. When the second forced signal of the first circuit board is low, in step S519, the first circuit board selects a transmission channel according to the second conversion signal, and sets the transmission channel to a logic low level.

In practice, the transmission module 10 of each pin of the circuit board 1 is the same, and the receiving module 12 of each pin is the same, but does not limit the form of the transmission module 10 and the receiving module 12, FIG. 2 and The embodiment of FIG. 3 is only one of the circuit architectures for implementing the programmable signal transmission method of the present invention. Other transmission modules 10 and receiver modules 12 that can perform the programmable signal transmission method of the present invention are all covered by the present invention. The scope of the programmable signal transmission method.

In summary, the embodiments of the present invention provide a programmable signal transmission method, in which a circuit board selects a signal to be output to another circuit board through a programmed first conversion signal, and a programmable configuration signal can configure the circuit board. The pin and transmission line used to transmit the signal, and the destination of the stylized second conversion signal selection signal, so as to efficiently transfer signals between the boards. Accordingly, the number or type of signals transmitted between the boards is no longer limited to the number of transmission lines. That is, signals newly added between the boards due to new functions or programs can communicate with each other through such transmission methods. There is no need to increase the number of pins on the board and the number of transmission lines, so that the content that can be communicated between the boards is more diverse and flexible.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧‧ boards

10‧‧‧Transmission module

101‧‧‧Multiplexer

103‧‧‧ retarder

105‧‧‧Arithmetic Logic

107‧‧‧Encoder

108, 123‧‧‧ forward and reverse

109, 121‧‧‧ buffer

12‧‧‧ receiving module

125‧‧‧Solution multiplexer

127‧‧‧Encoder

Tr1, tr2, tr3‧‧‧ transmission line

Pin1, pin2, pin3‧‧‧ pin

F0‧‧‧First mandatory signal

F1‧‧‧second mandatory signal

FIG. 1 is a schematic diagram of a plurality of circuit boards electrically connected to a transmission line according to an embodiment of the invention. 2 is a schematic diagram of a transmission module according to an embodiment of the invention. FIG. 3 is a schematic diagram of a receiving module according to an embodiment of the invention. FIG. 4 is a flow chart showing the steps of a method for transmitting a programmable signal according to an embodiment of the invention. FIG. 5 is a flow chart showing the steps of a method for transmitting a programmable signal according to another embodiment of the present invention. FIG. 6 is a flow chart showing the steps of a method for transmitting a programmable signal according to still another embodiment of the present invention. FIG. 7 is a flow chart showing the steps of a method for transmitting a programmable signal according to still another embodiment of the present invention.

Claims (9)

A programmable signal transmission method is applicable to a plurality of circuit boards and a plurality of transmission lines, and each of the circuit boards has a plurality of pins. The programmable signal transmission method includes: one of the circuit boards is based on a first The switching signal selects one of the plurality of output signals; one of the circuit boards outputs the selected output signal to the transmission line electrically connected to the pin from one of the pins according to a configuration signal; One of the transmission lines transmits the output signal to each of the circuit boards electrically connected to the transmission line; each of the circuit boards selectively receives or ignores the one of the pins according to the configuration signal. The output signal on one of the transmission lines; and the circuit board that has selected to receive the output signal, according to a second conversion signal, setting a transmission channel of the output signal; wherein each of the circuit boards is configured according to the configuration signal The step of selectively receiving or ignoring the output signal includes: when a second clock enable signal is triggered, selecting according to a second forced signal The output signal of the received or ignored. The method of claim 1, wherein one of the plurality of boards outputs the selected output signal to the transmission line from one of the pins according to the configuration signal. The method includes: when each of the pins of the circuit board is triggered by a first clock enable signal, selectively outputting the output signal according to the consistent energy signal. The method for transmitting a programmable signal according to claim 2, further comprising: one of the circuit boards selectively logically calculating the selected output signal and a data signal according to a logic selection signal; When the selected output signal is logically operated with the data signal, one of the circuit boards outputs a selected output signal to the transmission line from one of the pins according to the configuration signal, The circuit board outputs the output signal after the logic operation. The method for transmitting a programmable signal according to claim 3, further comprising: delaying the selected output signal according to a delay adjustment signal, and selectively selecting the output signal according to the logic selection signal; The step of performing a logic operation on the data signal includes selectively performing a logical operation on the delayed output signal and the data signal according to the logic selection signal. The method for transmitting a programmable signal according to claim 1, further comprising: one of the circuit boards outputting a logic potential from one of the pins to the electrical connection of the pin according to the configuration signal Transmission line. The method for transmitting a programmable signal according to claim 5, wherein each of the pins of the circuit board selectively outputs or not outputs the logic according to the consistent energy signal when triggered by a first clock enable signal. Potential. The method for transmitting a programmable signal according to claim 6, further comprising determining whether the logic potential is a logic high level or a logic low level according to a first forced signal. The method for transmitting a programmable signal according to claim 7 further includes encoding a control signal to generate the first mandatory signal and the enabling signal. The method for transmitting a programmable signal according to claim 1, wherein the circuit board that has selected to ignore the output signal selects one of the plurality of transmission channels according to the second conversion signal, and sets the second forced signal according to the second forced signal. The selected transmission channel is a logic high or a logic low.