TWI622052B - Non-volatile memory and accessing method thereof - Google Patents

Abstract

Non-volatile memory and its access method. The non-volatile memory includes at least one memory block. The at least one memory block includes a plurality of first memory pages, a plurality of second memory pages, and a buffer. The first memory pages respectively correspond to a plurality of character lines and each include a plurality of first memory sub-blocks, wherein the first memory sub-block corresponding to the zero-th character line stores a protection pattern. The second memory pages respectively correspond to the character lines and each include a plurality of second memory sub-blocks. The buffer stores a protection pattern. When one of the first memory sub-blocks is set as a protected memory sub-block, the buffer provides a protection pattern to write into the second memory sub-block corresponding to the protected memory sub-block in the second memory page. To generate page protection information.

Description

Non-volatile memory and access method thereof

The present invention relates to a non-volatile memory and an access method thereof, and in particular, to a one-time write access method for a non-volatile memory capable of reducing write disturb.

In the technical field of using flash memory to implement one-time programmable memory, the protection action is to achieve the purpose of page protection or block protection by writing a protection pattern to a page storing a protection message.

In the conventional technical field, the execution of the page protection of the one-time programmable memory is to control the paged buffer to generate data of logic 0, and write the data of logic 0 to the target by a write operation. Select all the memory cells on the ZigZag page and complete the page protection action. In order to write all the data stored in the memory cells on the selected zigzag page to logic 0, the write operation often requires multiple high-voltage pulses to complete. Therefore, the selected zigzag line Memory cells on even pages are also disturbed by more and more writes. In addition, memory cells on adjacent character lines will also be written by the character line coupling effect (Coupling Effect). interference. Resulting in the destruction of stored data.

If the protection pattern to be written is not a digital signal with logic 0, the one-time programmable memory in the conventional art needs to individually control multiple page buffers corresponding to different bits, increasing the design. Difficulty.

The invention provides a non-volatile memory and an access method thereof, which can effectively reduce the writing interference phenomenon.

The non-volatile memory of the present invention includes at least one memory block. The at least one memory block includes a plurality of first memory pages, a plurality of second memory pages, and a buffer. The first memory pages respectively correspond to a plurality of character lines and each include a plurality of first memory sub-blocks, wherein the first memory sub-block corresponding to the zero-th word line (WL0) stores a protection pattern. The second memory pages respectively correspond to the character lines and each include a plurality of second memory sub-blocks. The buffer is coupled to the first memory page and the second memory page, and stores a protection pattern. When one of the first memory sub-blocks is set as a protected memory sub-block, the buffer provides a protection pattern to write into the second memory sub-block corresponding to the protected memory sub-block in the second memory page. To generate page protection information.

The non-volatile memory access method of the present invention includes: providing at least one memory block a plurality of first memory pages respectively corresponding to a plurality of character lines, wherein the first memory pages each include a plurality of first memory pages; Memory sub-blocks; the first memory sub-block corresponding to the zeroth character line stores a protection pattern; providing a plurality of second memory pages respectively corresponding to the character line, wherein the first memory page includes a plurality of first memory sub-blocks Block; provide The buffer stores a protection pattern, sets one of the first memory sub-blocks as a protected memory sub-block, and provides a protection pattern to write a second memory sub corresponding to the protected memory sub-block in the second memory page. Block to generate page protection information.

Based on the above, the present invention stores a protection pattern in the first memory sub-block corresponding to the zeroth character line, and sets the protected memory sub-block after writing data of any first memory sub-block, and The protection pattern is written into the second memory sub-block corresponding to the protected memory sub-block through the buffer. In this way, it is not necessary to perform an individual control operation on the circuit corresponding to each data bit in the buffer to reduce the phenomenon of write interference.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100‧‧‧Non-volatile memory

101‧‧‧Memory block

130‧‧‧Buffer

111-11N‧‧‧First memory page

121-12N‧‧‧Second Memory Page

WL0-WLN‧‧‧Character line

BLex, BLox‧‧‧Bit Line

200‧‧‧Non-volatile memory

201‧‧‧memory cell array

210‧‧‧Buffer

220‧‧‧I / O buffer

SGS, SGD‧‧‧Selection brake signal

SL‧‧‧Source Line

WL00-WL31‧‧‧Character line

DWL_D, DWL_S‧‧‧Virtual Character Line

BLe‧‧‧Even bit line

BLo‧‧‧Odd Bit Line

2111-211N‧‧‧First latch

2121-212N‧‧‧Second latch

SW0-SW4095‧‧‧Transistor

CSL0-CSL4095‧‧‧Control signal

300‧‧‧Non-volatile memory

310‧‧‧Memory cell array

320‧‧‧Sense Amplifier

330‧‧‧Buffer

331, 332‧‧‧bolt

400‧‧‧Non-volatile memory

410‧‧‧Memory cell array

420‧‧‧column decoder

430‧‧‧Sense Amplifier

440‧‧‧Buffer

450‧‧‧line decoder

460‧‧‧I / O buffer

470‧‧‧controller

S510-S540, S610-S650, S710-S760‧‧‧Access method steps for non-volatile memory

FIG. 1 is a schematic diagram of a non-volatile memory according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention.

5 to 7 are flowcharts of a method for accessing a non-volatile memory according to an embodiment of the present invention.

Please refer to FIG. 1, which is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. The non-volatile memory 100 is used as a One Time Programmable (OTP) memory. In this embodiment, the non-volatile memory 100 may be a NAND flash memory. The non-volatile memory 100 includes one or more memory blocks 101 and a buffer 130. The memory block 101 includes a plurality of first memory pages 111-11N and a plurality of second memory pages 121-12N. The first memory pages 111-11N correspond to and are coupled to the character lines WL0-WLN, respectively, and the second memory pages 121-12N also correspond to and are coupled to the character lines WL0-WLN, respectively. The first memory pages 111-11N and the second memory pages 121-12N include a first memory sub-block and a second memory sub-block, respectively. It is worth mentioning that the first memory sub-block in the first memory page 111 corresponding to the zeroth character line (for example, the character line WL0) in the first memory pages 111-11N stores a set of preset protection patterns. The protection pattern may have multiple bits, and the logical values of these bits may be different (partially 0 and partly 1).

On the other hand, the first memory pages 111-11N in this embodiment are coupled to the bit line BLex, and the second memory pages 121-12N are coupled to the bit line BLox. The bit line BLox may be an odd number of bit lines in the non-volatile memory 100, and the bit line BLex may be an even number of bit lines in the non-volatile memory 100. In an actual circuit layout, there may be a plurality of bit lines BLox and a plurality of bit lines BLex, and each of the bit lines BLox and each of the bit lines BLex are sequentially staggered with each other.

The buffer 130 is coupled to the bit line BLex and the bit line BLox, and is coupled to the first memory pages 111-11N and the second memory pages 121-12N. The buffer 130 may include a first memory corresponding to the zeroth character line (for example, the character line WL0). The first memory sub-block in page 111 reads the protection pattern and stores it. When one of the first memory pages 111-11N (taking the first memory page 112 as an example) is set as a protected memory sub-block, the buffer 130 may provide the stored Protect the pattern to write the protection pattern into the second memory sub-block in the second memory page 122 corresponding to the first memory page 112, and generate page protection in the second memory sub-block in the second memory page 122 Information.

In this way, when a rewrite operation is performed on the first memory page 112, it is possible to check whether page protection information exists in the second memory page 122 corresponding to the first memory page 112. If the check result is yes, it means that the A memory page 112 is in a protected state and a write operation will be aborted without execution. In contrast, if the check result is negative, it indicates that the first memory page 112 is not in a protected state, and a write operation can be performed.

Incidentally, the page protection action in the embodiment of the present invention may be performed after the first memory page is executed after the first write operation is completed. And effectively protect the write-once data in the first memory page.

Please note that the protection pattern in the embodiment of the present invention is provided by the first memory page 111 of the zeroth character line (for example, the character line WL0), and it is not necessary to store a plurality of different ones through the respective control buffers 130. A bit circuit effectively simplifies the complexity of the circuit. In addition, in the embodiment of the present invention, a page protection operation can be performed by setting a protection pattern with a non-all logic 0, which can reduce the number of application times required for a high voltage pulse and reduce write interference.

In another aspect, this embodiment corresponds to the last character line (character line WLN) The first memory page of 11N can be used to store block protection information. After all the first memory pages (except the first memory page 11N) have completed writing data, the buffer 130 can receive the block protection pattern and write the block protection pattern to the corresponding last word line ( Word line WLN) in the first memory page 11N, and generates block protection information. When a write operation for the memory block 101 occurs, the buffer 130 can read data from the first memory sub-block in the first memory page 11N, and judge the first memory in the first memory page 11N by Whether there is storage block protection information in the sub-blocks to decide whether to continue the write operation. When there is storage block protection information in the first memory sub-block in the first memory page 11N, it indicates that the memory block 101 is in a protected state, and a write operation is not performed. In contrast, when there is no storage block protection information in the first memory sub-block in the first memory page 11N, it indicates that the memory block 101 is not in a protected state, and a write operation can be performed.

Incidentally, after the block protection pattern is written to the first memory page 11N corresponding to the last word line (word line WLN), the writing operation performed on the memory block 101 will be ended.

Please refer to FIG. 2, which is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. The non-volatile memory 200 includes a memory cell array 201, a buffer 210, and an input-output buffer 220. The memory cell array 201 includes memory cells formed by a plurality of transistor switches and a plurality of floating gate moving crystals. The memory cell array 201 receives the selection gate signals SGS and SGD, and is coupled to the source line SL, the word lines WL00-WL31, the dummy word lines DWL_D and DWL_S, the even bit line BLe, and the odd bit line BLo.

The buffer 210 is coupled to the even bit line BLe and the odd bit line BLo, and the buffer 210 includes a plurality of first latches 2112-1111 and a plurality of second latches 2112-1212N. The first latch 2112-1111N can be used to store a protection pattern, and when performing a write protection operation, the first latch 2112-1111N can provide a protection pattern to the odd bit line BLo and cause the protection pattern to be written into the memory In the second memory sub-block of the second memory page of one of the cell arrays 201.

The second latch 2112-1212N can be used to transmit read data or receive written data through the input-output buffer 220. When the input / output buffer 220 performs an operation of transmitting read data or receiving write data, some of the transistor switches SW0-SW4095 can be turned on according to the control signals CSL0-CSL4095.

Please refer to FIG. 3, which is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. The non-volatile memory 300 includes a memory cell array 310, a sense amplifier 320, and a buffer 330. The memory cell array 310 is coupled to the sense amplifier 320, and the sense amplifier 320 is coupled to the buffer 330. The bumper 330 includes latches 331 and 332. When the normal data writing operation is performed, the latch 332 can receive the written data from the outside and provide the written data to the sense amplifier 320. The sense amplification operation is performed through the sense amplifier 320, and the written data can be written into the memory cell array 310. In addition, when a normal data reading operation is performed, the sense amplifier 310 performs a sensing amplification operation on the information transmitted from the memory cell array 310. The amplified data is stored in the latch 332 and passed through the latch. 332 is provided to the outside to generate readout data.

Regarding the latch 331, when the memory cell array 310 is to be When one of the first memory pages performs a protection operation, a reading operation may be performed on the first memory sub-block of the first memory page corresponding to a zero character line, and the read protection pattern is stored in the latch.器 331. In addition, when the character line corresponding to the protected first memory page is turned on, the latch 331 may provide a protection pattern to the bit line BLo so that the protection pattern is written into the corresponding first memory page. In the second memory page.

Please refer to FIG. 4, which is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. The non-volatile memory 400 includes a memory cell array 410, a column decoder 420, a sense amplifier 430, a buffer 440, a row decoder 450, an input-output buffer 460, and a controller 470. In this embodiment, a part of the memory blocks in the memory cell array 410 is cut out to be used as a one-time programming memory block 411. In this embodiment, in the write protection operation, the controller 470 is configured to read each second memory sub-block in the one-time programming memory block 411 during the write operation and determine each second Whether the information in the memory sub-block is page protection information; and based on whether the information in each second memory sub-block is page protection information to determine whether it is for each first memory sub-region corresponding to each second memory sub-block The block performs a write operation.

In addition, after the controller 470 performs a write operation for each of the first memory sub-blocks, the controller 470 may cause the buffer 440 to store a protection pattern, and write the protection pattern into each of the first-time programming memory blocks 411. Each second memory sub-block of a memory sub-block. In addition, the controller 470 may read the first memory sub-block corresponding to a last word line in the first memory page in the writing operation, and according to whether the first memory sub-block corresponding to the last word line has a storage area Block protection information to decide whether to continue the write operation.

Of course, the controller 470 may also perform other data access operations performed on the memory that are well known to those having ordinary knowledge in the art, which is not described in detail here.

Please refer to FIG. 5 to FIG. 7. FIG. 5 to FIG. 7 are flowcharts of a non-volatile memory access method according to an embodiment of the present invention. In FIG. 5, when a write operation is to be performed on a memory block, first, step S510 reads a first memory sub-block corresponding to a last word line in a first memory page in the memory block, and judges Whether the memory block is block protected. If the determination result is yes, step S511 is executed to stop the writing operation. If the determination result is no, step S520 is performed. In step S520, it is determined whether the first memory page to be written is in a page protection state by reading whether there is stored page protection information in the second memory page corresponding to the first memory page to be written. If the determination result is yes, Step S521 is executed to stop the writing operation. If the determination result is no, step S530 is performed. Step S530 includes sub-steps S531 and S532. Sub-step S531 writes the write data to the first sub-memory block (OTP area) of the first memory page to be written, and, in sub-step S532, writes the protection pattern to the corresponding written first A second memory page of a memory page to perform a page protection action.

Next, step S540 determines whether the writing operations of all the first memory pages in the memory block have been completed. If the writing operations of not all the first memory pages have been completed, the value of the next first memory page is continuously measured. The writing operation is repeatedly performed in step S530. If all the writing operations of the first memory page have been completed, the writing operation is ended.

Please refer to FIG. 6. FIG. 6 is the execution details of step S532 in FIG. 5. Among them, when the page protection action is to be performed, the protection pattern can be read into the buffer first. The first latch (step S610), and in step S620, the protection pattern is transmitted to the second memory page corresponding to the selected character line. Next, the protection pattern is written to the second memory page corresponding to the selected word line in step S630. In step S640, the writing verification operation of the protection pattern is performed, and the writing operation in step S630 is continuously performed. After confirming that the protection pattern is successfully written to the second memory page corresponding to the selected word line, the page protection operation is completed (step S650). ).

FIG. 7 is a flowchart of the block protection operation. In step S710, an execution block protection instruction is input. Then, in step S720, the second latch in the buffer generates a block protection pattern that is all logic 0. In step S730, the block protection pattern is transmitted to the first memory page corresponding to the last character line (for example, the character line 31), and the block protection pattern writing operation is performed in step S740. Step S750 executes the write verification action corresponding to step S740, and continues to execute the write action of step S740. After the write verification action passes, step S760 is performed to end the block protection action.

In summary, the present invention stores the protection pattern in the first memory sub-block corresponding to the zeroth character line, and uses the buffer to store and provide the protection pattern to be written to the first memory page corresponding to the protected first memory page. Second memory page. In this way, without increasing the complexity of the hardware, a protection pattern that is not all logic 0 can be used. In addition, in the process of performing the writing operation of the protection pattern, the number and time of applying high-voltage pulses can be reduced, and the phenomenon of writing interference can be effectively reduced.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field will not depart from the present invention. Within the spirit and scope, some modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (14)

A non-volatile memory includes: at least one memory block, including: a plurality of first memory pages, respectively corresponding to a plurality of character lines, and respectively including a plurality of first memory sub-blocks, which corresponds to a zero word The first memory sub-block of the meta-line stores a protection pattern; and a plurality of second memory pages, respectively corresponding to the character lines, and each includes a plurality of second memory sub-blocks; and a buffer, coupled to the The first memory pages and the second memory pages store the protection pattern, and when one of the first memory sub-blocks is set as a protected memory sub-block, the buffer provides the protection pattern The second memory page is written into the second memory sub-block corresponding to the protected memory sub-block to generate a page protection information. The non-volatile memory according to item 1 of the patent application scope, wherein the buffer stores a block protection pattern, and the block protection pattern is provided to be written to a corresponding last character in the first memory pages. The first memory sub-block of the line to generate a block protection information. The non-volatile memory according to item 1 of the scope of patent application, wherein after the block protection information is generated, a write operation of the at least one memory block is ended. The non-volatile memory according to item 1 of the patent application scope, further comprising: a controller coupled to the buffer, The controller is configured to read each of the second memory sub-blocks during a write operation, and determine whether the information in each of the second memory sub-blocks is the page protection information; and according to each of the first Whether the information in the two memory sub-blocks is the page protection information is used to determine whether a write operation is performed on each of the first memory sub-blocks corresponding to each of the second memory sub-blocks. The non-volatile memory according to item 4 of the scope of patent application, wherein after the controller performs a write operation for each of the first memory sub-blocks, the controller causes the buffer to store the protection pattern and causes the buffer to The protection pattern is written into each of the second memory sub-blocks corresponding to each of the first memory sub-blocks. The non-volatile memory according to item 4 of the patent application scope, wherein the controller further reads the first memory sub-block corresponding to a last word line in the first memory pages during the write operation. And according to whether the first memory sub-block corresponding to the last character line stores the block protection information to determine whether to continue the writing operation. The non-volatile memory according to item 1 of the scope of patent application, further comprising: a sense amplifier coupled between the buffer and the first memory pages and the second memory pages to receive and amplify Information received by the buffer, the first memory pages, or the second memory pages. The non-volatile memory according to item 1 of the scope of patent application, wherein the first memory pages are respectively coupled to a plurality of coupled digit lines, and the second memory pages are respectively coupled to a plurality of odd digit lines. . The non-volatile memory according to item 1 of the patent application scope, wherein the protection pattern includes a plurality of logic bits with different levels. The non-volatile memory according to item 1 of the patent application scope, wherein the buffer comprises: a first latch for storing the protection pattern; and a second latch for receiving and storing a Write data. A method for accessing non-volatile memory includes: providing a plurality of first memory pages respectively corresponding to a plurality of word lines in at least one memory block, wherein the first memory pages each include a plurality of first memory pages; A memory sub-block; causing a first memory sub-block corresponding to a zero character line to store a protection pattern; providing a plurality of second memory pages respectively corresponding to the character lines, wherein the second memory pages Including a plurality of second memory sub-blocks; and providing a buffer to store the protection pattern, setting one of the first memory sub-blocks as a protected memory sub-block, and providing the protection pattern for writing Enter the second memory sub-blocks corresponding to the protected memory sub-blocks in the second memory pages to generate a page protection information. The method for accessing non-volatile memory according to item 11 of the scope of patent application, further comprising: providing the buffer to store a block protection pattern, and providing the block protection pattern for writing to the first The first memory sub-block corresponding to a last character line in the memory page generates a block protection information. The method for accessing non-volatile memory according to item 11 of the scope of patent application, wherein after the block protection information is generated, a write operation of the at least one memory block is ended. The method for accessing non-volatile memory according to item 11 of the scope of patent application, further comprising: providing a controller to read each of the second memory sub-blocks during a write operation, and judge each Whether the information in the second memory sub-block is the page protection information; and according to whether the information in each of the second memory sub-blocks is the page protection information to determine whether it is for the corresponding second memory sub-block Each of the first memory sub-blocks performs a write operation.