KR102504291B1 - Method for managing buffer memory and method for performing write operation using the same - Google Patents

Abstract

A method for managing a buffer memory and a method for performing a write operation using the same are disclosed. A method of performing a write operation includes comparing a data pattern of a command instructing a currently received write operation with a data pattern of previously received commands, and comparing the data pattern of a command instructing a write operation with data of previously received commands. and performing a write operation according to a command instructing the write operation by reusing the data pattern of the previously received commands when the pattern is the same.

Description

Method for managing buffer memory and method for performing write operation using the same}

The present invention relates to a storage device and a command execution method in the storage device, and more particularly, to a buffer memory management method and a write operation execution method using the same.

A flash memory device, which is one of non-volatile memory devices, has been spotlighted as a storage device due to its high speed and low power consumption. A storage device employing a flash memory device is used in a web server, a file server, or a DB server where many accesses occur. In such a server environment, a technology for quickly processing a back patterning operation of writing a certain storage area of a storage device in the same pattern while reducing firmware overhead is required.

An object of the present invention is to provide a buffer memory management method for reducing firmware overhead in an operation of writing the same pattern.

Another object of the present invention is to provide a method for performing a write operation to reduce firmware overhead in an operation of writing the same pattern.

According to one aspect of the technical idea of the present invention, a method for performing a write operation includes comparing a data pattern of a command instructing a currently received write operation with a data pattern of previously received commands, and data of a command instructing the write operation. and performing a write operation according to a command instructing the write operation by reusing the data pattern of the previously received commands when the pattern is the same as the data pattern of previously received commands.

According to another aspect of the technical concept of the present invention, a buffer memory management method includes sequentially copying data of a command received from a host to a buffer memory, and in a state in which all page buffers in the buffer memory are copied with the same data pattern. skipping an operation of copying data of the write same command to the buffer memory when a write same command having the same data pattern as a data pattern copied to the buffer memory is received; It is characterized in that a write operation according to the write same command is performed using the data copied to the buffer memory.

According to the present invention, when a command that repeatedly writes the same data pattern is processed, an operation of copying the data pattern of the command to the buffer memory is skipped and the buffer memory is managed to reuse the data pattern of previous commands, thereby enabling write same command. An effect capable of improving processing performance is generated.

In addition, by parallelly performing an operation of copying a data pattern of a command to a buffer memory using a direct memory access function and a command processing operation in firmware, an effect of improving write same command processing performance occurs.

1A shows an example of a configuration of a computing system according to the technical spirit of the present invention.
Figure 1b shows another example of a configuration of a computing system according to the technical idea of the present invention.
2a shows another example of a configuration of a computing system according to the technical idea of the present invention.
2b shows another example of a configuration of a computing system according to the technical idea of the present invention.
FIG. 3A is a diagram showing an example of a detailed configuration of the storage device shown in FIG. 1A or 2A.
FIG. 3B is a diagram showing an example of a detailed configuration of the storage device shown in FIG. 1B or 2B.
4A shows an example of a memory controller configuration shown in FIG. 3A.
FIG. 4B shows an example of the configuration of the memory controller shown in FIG. 3B.
5 shows an example of a detailed configuration of the memory device shown in FIG. 3A or 3B.
FIG. 6 shows an example of the memory cell array shown in FIG. 5 .
FIG. 7 is a circuit diagram illustrating an example of a first memory block included in the memory cell array shown in FIG. 6 .
8 is a diagram illustrating a process of processing data of a write same command in a memory controller according to an embodiment of the present invention.
9 is a diagram illustrating an example of a process of copying data of a write same command to a buffer memory of a memory controller according to an embodiment of the present invention.
10 is a diagram illustrating another example of a process of copying data of a write same command to a buffer memory of a memory controller according to an embodiment of the present invention.
11 is a diagram illustrating a method of checking unity of data in a buffer memory of a memory controller according to an embodiment of the present invention.
12 is a diagram illustrating an example of a process of executing a write same command in a memory controller according to an embodiment of the present invention.
13 is a diagram showing another example of a process of executing a write same command in a memory controller according to an embodiment of the present invention.
14 is a diagram illustrating an example of a process of executing a write same command without using a direct memory access module in a memory controller according to an embodiment of the present invention.
15 is a diagram illustrating an example of a process of executing a write same command using a direct memory access module in a memory controller according to an embodiment of the present invention.
16 is a diagram illustrating an example of a process of executing a write same command when consistency of data in a memory buffer is confirmed in a memory controller according to an embodiment of the present invention.
17 is a flowchart of a method for performing a write operation according to an embodiment of the present invention.
18 is a flowchart of a buffer memory management method according to an embodiment of the present invention.
19 is a flowchart of a light operation method performed in a computing system according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Since the present invention can have various changes and various forms, specific embodiments will be illustrated in the drawings and described in detail. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numbers are used for like elements. In the accompanying drawings, the dimensions of the structures are shown enlarged or reduced than actual for clarity of the present invention.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "comprise" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this application, they are not interpreted in an ideal or excessively formal meaning. .

1A shows an example 1000A of a configuration of a computing system according to the technical spirit of the present invention.

As shown in FIG. 1A , a computing system 1000A includes a host 100 and a storage device 200A.

By way of example, computing system 1000A may be a personal computer, set-top-box, digital camera, navigation device, mobile device, smart card system, or the like. Also, the storage device 200A may be a memory device, a solid state drive (SSD), a smart card, a hard disk drive, or the like.

The host 100 and the I/O device 200A are electrically connected. Interface used between the host 100 and the storage device 200A Various interface standards may be applied. For example, Universal Flash Storage (UFS) interface, embedded Multi-Media Card (eMMC) interface, Serial Advanced Technology Attachment (SATA) interface, Serial Advanced Technology Attachment express (SATAe) interface, Small Computer System Interface (SCSI), SCSIe ( Small Computer System Interface express), NVMe (Non-Volatile Memory express) interface, PCI (Peripheral Component Interconnect) interface, PCIe (Peripheral Component Interconnect Express) interface, etc. may be applied.

The host 100 may transmit a command CMD to the storage device 200A. In addition, data DATA may be exchanged between the host 100 and the storage device 200A. For example, the storage device 200A may be implemented in various ways, such as an embedded Multi-Media Card (eMMC) type or a universal flash storage type.

The host 100 transmits a command CMD issued based on a task to be performed to the storage device 200A. For example, the command CMD generated by the host 100 may include a command instructing a write operation or a command instructing a read operation. Also, a command instructing a write operation may include a write command or a write same command.

For example, the write same command may include data pattern, start LBA, and length information. As an example, the data pattern of the write same command may consist of one sector size. The write same command is a command instructing to write a corresponding data pattern as much as length information from the start LBA.

For example, the write same command may be used to perform a back patterning operation of writing a specific storage area of the storage device 200A with the same data pattern.

Also, the host 100 transmits data DATA to be stored in the storage device 200A or receives data DATA read from the storage device 200A.

For example, the host 100 transmits a read command to the storage device 200A when data to be processed is stored in the storage device 200A. In addition, the host 100 transmits a write command or a write same command to the storage device 200A when storing the processed data in the storage device 200A.

As another example, when a page fault occurs, the host 100 transmits a read command or a write command for performing at least one of a page-in operation and a page-out operation for a memory swapping operation to the storage device 200A. A page fault occurs when a page to be read to execute an application process in the host 100 is not stored in the host 100 .

The storage device 200A performs a read operation or a write operation according to a command received from the host 100 . For example, the storage device 200A may perform some operations performed by hardware in a write command by software in a write same command.

The storage device 200A includes a buffer memory 201 and a buffer management module 202 . Data to be written to the storage device is copied to the buffer memory 202 or data read from the storage device is copied. For example, the buffer memory 201 may be implemented as a ring buffer memory type. The buffer management module 202 manages an operation of copying data of a write command or a write same command to the buffer memory 201 .

For example, the buffer management module 202 sequentially copies command data received from the host 100 to the buffer memory 201 . In addition, the buffer management module 202 receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 in a state in which all page buffers in the buffer memory 201 are copied with the same data pattern. In this case, an operation of copying data of the write same command to the buffer memory 201 is skipped. Accordingly, it is possible to reduce the overhead of firmware processing used to copy data of the write same command to the buffer memory 201 .

The storage device 200 receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 while all page buffers in the buffer memory 201 are copied with the same data pattern. An operation of copying data of the same write command to the buffer memory 201 is skipped, and a write operation according to the same write command is performed using the data copied to the buffer memory 201 . Accordingly, it is possible to perform a write operation according to the write same command by reusing data patterns of previously received commands.

For example, the buffer management module 202 may include program codes for performing a write operation execution method or a flowchart of a buffer memory management method as shown in FIGS. 17 to 19 .

1B shows another example 1000B of a configuration of a computing system according to the technical idea of the present invention.

As shown in FIG. 1B , a computing system 1000B includes a host 100 and a storage device 200B.

Since the host 100 has already been described in FIG. 1A, redundant description will be avoided. The storage device 200B has a configuration in which a direct memory access module 203 is added to the storage device 200A shown in FIG. 1 .

The storage device 200B includes a buffer memory 201, a buffer management module 202 and a direct memory access module (DMA module) 203. Since the buffer memory 201 and the buffer management module 202 have been described with reference to FIG. 1A, redundant description will be avoided.

The direct memory access module 203 supports an operation of copying data to the buffer memory 201 without executing a program by a central processing unit (CPU) of the storage device 200B. Accordingly, the direct memory access module 203 may perform an operation of copying data to the buffer memory 201 in parallel with an operation of processing a write command or a write same command in firmware. Accordingly, it is possible to shorten the processing time of a write command or a write same command.

2A shows another example 2000A of a configuration of a computing system according to the technical spirit of the present invention.

As shown in FIG. 2A , a computing system 2000A includes a host 2100 and an I/O device block 2200A.

The host 2100 includes a processor 2110, a memory 2120, an I/O controller 2130, an I/O bridge 2140, and an I/O bus 2150. The I/O device block 2200A includes a plurality of storage devices 2210-1 to 2210-M, where M is an integer greater than or equal to 2.

By way of example, computing system 2000A may be a personal computer, set-top-box, digital camera, navigation device, mobile device, smart card system, server system, or the like. Also, the storage devices 2210-1 to 2210-M included in the I/O device block 2200A may include a memory device, a solid state drive (SSD), a smart card, a hard disk drive, and the like.

The processor 2110 may include circuitry, interfaces, or program codes for controlling operations of components of the computing system 2000A. As an example, the processor 2110 may include a CPU, an ARM, or an application specific integrated circuit (ASIC).

The memory 2120 may include SRAM or DRAM for storing data, instructions, or program codes necessary for the operation of the computing system 2000A. Also, it may include non-volatile memory.

The processor 2110 may control operations of components of the computing system 2000A by driving programs stored in the memory 2120 .

The I/O controller 2130 controls the storage devices 2210-1 to 2210-M of the I/O device block 2200A. The I/O controller 2130 receives an I/O command from the processor 2110 and controls the storage devices 2210-1 to 2210-M based on the received I/O command.

Components of the host 2100 are electrically connected to the host bus 2150 . Through the host bus 2150, data and signals may be exchanged between elements of the host 2100.

The I/O bridge 2140 controls a channel for data communication between the host 2100 and the storage devices 2210-1 to 2210-M. As an example, I/O bridge 2140 may be implemented as a PCIe bridge, a SAS bridge, a network bridge, or the like.

For example, each of the storage devices 2210-1 to 2210-M included in the I/O device block 2200A may be implemented as a storage device 200A as shown in FIG. 1A. As another example, each of the storage devices 2210-1 to 2210-M may be implemented as a solid state drive (SSD) or hard disk drive (HDD). Each of the storage devices 2210-1 to 2210-M includes a buffer memory 201-M and a buffer management module 202-M. Since the operations of the buffer memory 201-M and the buffer management module 202-M are substantially the same as those of the buffer memory 201 and buffer management module 202 mentioned in FIG. 1A, redundant description will be avoided. do.

2B shows another example 2000B of a configuration of a computing system according to the technical concept of the present invention.

As shown in FIG. 2B , a computing system 2000B includes a host 2100 and an I/O device block 2200B. Since operation of the host 2100 has already been described in FIG. 1A , redundant description will be avoided.

The I/O device block 2200B includes a plurality of storage devices 2210'-1 to 2210'-M, where M is an integer greater than or equal to 2.

For example, each of the storage devices 2210'-1 to 2210'-M included in the I/O device block 2200B may be implemented as a storage device 200B as shown in FIG. 1B. As another example, each of the storage devices 2210'-1 to 2210'-M may be implemented as a solid state drive (SSD) or a hard disk drive (HDD). Each of the storage devices 2210'-1 to 2210'-M includes a buffer memory 201-M, a buffer management module 202-M, and a direct memory access module 203-M. The operations of the buffer memory 201-M, the buffer management module 202-M, and the direct memory access module 203-M are the same as the buffer memory 201, the buffer management module 202, and the direct memory access mentioned in FIG. 1B. Since the operation of module 203 is substantially the same, redundant description will be avoided.

FIG. 3A is a diagram showing an example of a detailed configuration of the storage device shown in FIG. 1A or 2A.

As shown in FIG. 3A , the storage device 200A or 2210 -M includes a memory controller 210A and a memory device 220 .

The memory device 220 may include one or more non-volatile memory (NVM) 220-1. For example, the nonvolatile memory 220 - 1 applied to the memory device 220 may include not only a flash memory but also a phase change RAM (PRAM), a ferroelectric RAM (FRAM), and a magnetic RAM (MRAM). As another example, the memory device 220 may be configured in a mixed form of one or more nonvolatile memories and one or more volatile memories, or may be configured in a mixed form of at least two or more types of nonvolatile memories. For example, when the memory device 220 is implemented as a non-volatile memory device such as a flash memory, the storage device 200A or 2210-M may be a solid state drive (SSD).

The memory controller 210A may perform a control operation on the memory device 220 based on a command received from the host. The memory controller 210A controls program (or write), read, and erase operations of the memory device 220 connected through a plurality of channels CH1 to CHM according to commands received from the host.

Channels for I/O processing of signals required for operation are formed between the memory controller 210A and the memory device 220 . Signals necessary for performing an operation may be, for example, a command, an address, and data.

The memory controller 210A includes a buffer memory 201 and a buffer management module 202 . Since operations of the buffer memory 201 and the buffer management module 202 have already been described with reference to FIG. 1A , redundant description will be avoided.

The memory controller 210A copies data to be written to the memory device 220 to the buffer memory 201 using the buffer management module 202 or data read from the memory device 220 to the buffer memory 201. ) is copied to For example, the memory controller 210A receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 in a state in which all page buffers in the buffer memory 201 are copied with the same data pattern. In this case, the operation of copying data of the write same command to the buffer memory 201 is skipped. Accordingly, the overhead of firmware processing in the memory controller 210A used to copy data of the write same command to the buffer memory 201 can be reduced.

The memory controller 210A transmits the data copied to the buffer memory 201 to the memory device 220 and performs a write operation according to the write same command. Accordingly, the memory controller 210A can perform a write operation according to the write same command by reusing data patterns of previously received commands.

FIG. 3B is a diagram showing an example of a detailed configuration of the storage device shown in FIG. 1B or 2B.

As shown in FIG. 3B , the storage device 200B or 2210'-M includes a memory controller 210B and a memory device 220 . Since the memory device 220 has already been described with reference to FIG. 3A , redundant description will be avoided.

The memory controller 210B may perform a control operation on the memory device 220 based on a command received from the host. The memory controller 210B controls program (or write), read, and erase operations for the memory device 220 connected through a plurality of channels CH1 to CHM according to commands received from the host.

The memory controller 210B includes a buffer memory 201 , a buffer management module 202 and a direct memory access module 203 . Since operations of the buffer memory 201, the buffer management module 202, and the direct memory access module 203 have already been described in FIG. 1B, redundant description will be avoided.

The memory controller 210B performs an operation of copying data to the buffer memory 201 in parallel with an operation of processing a write command or a write same command in the firmware using the buffer management module 202 and the direct memory access module 203. Do it.

In detail, the memory controller 210B copies data to be written to the memory device 220 to the buffer memory 201 using the buffer management module 202 or buffers data read from the memory device 220. copied to the memory 201. In particular, an operation of copying data to the buffer memory 201 using the direct memory access module 203 and an operation of processing a command in the firmware may be performed in parallel.

For example, the memory controller 210B receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 in a state in which all page buffers in the buffer memory 201 are copied with the same data pattern. In this case, the operation of copying data of the write same command to the buffer memory 201 is skipped.

The memory controller 210B transmits the data copied to the buffer memory 201 to the memory device 220 and performs a write operation according to the write same command. Accordingly, the memory controller 210B can reuse data patterns of previously received commands to perform a write operation according to the write same command.

FIG. 4A shows an example of a configuration of the memory controller 210A shown in FIG. 3A.

As shown in FIG. 4A , the memory controller 210A includes a processor 211A, a random access memory (RAM) 212A, a host interface 213, a memory interface 214, a read only memory (ROM) 215) and a bus (216).

Elements of the memory controller 210A exchange data and various signals through the bus 216 .

The processor 211A may generally control the operation of the storage device 200A or 2210-M using program codes and data stored in the RAM 212A. When the storage device 200A or 2210-M is initialized, the processor 211A reads program codes and data necessary for controlling operations performed in the storage device 200A or 2210-M stored in the memory device 220 to RAM. (212A) can be loaded.

The RAM 212A operates under the control of the processor 211A, and an area of the buffer memory 201 may be allocated. Also, software for the buffer management module 202 may be loaded into the RAM 212A. In addition, program codes for processes executed in the host interface layer (HIL) and program codes for processes executed in the flash translation layer (FTL) may be loaded into the RAM 212A.

The host interface 213 has a data exchange protocol with a host connected to the memory controller 210A and performs an interface between the memory controller 210A and the host. The host interface 213 is, for example, an Advanced Technology Attachment (ATA) interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, a Universal Serial Bus (USB) or a Serial Attached Small Computer System (SAS) interface. , SCSI (Small Computer System Interface), eMMC (embedded Multi Media Card) interface, UFS (Universal Flash Storage) interface, PCI (Peripheral Component Interconnect) interface, PCIe (Peripheral Component Interconnect Express) interface can be implemented. However, this is only an example and is not limited thereto. The host interface 213 may receive commands and data from the host or transmit data to the host under the control of the processor 211A.

The memory interface 214 is electrically connected to the memory device 220 . The memory interface 214 may transmit commands, addresses, and data to the memory device 220 or receive data from the memory device 220 under the control of the processor 211A. Memory interface 214 may be configured to support NAND flash memory or NOR flash memory. The memory interface 214 may be configured to perform software or hardware interleaved operations over a plurality of channels.

The ROM 215 may store code information necessary for initial booting of a device employing a storage device.

The processor 211A runs the software for the buffer management module 202 loaded in the RAM 212A to copy data to be written to the memory device 220 to the buffer memory 201 or to the memory device 220. The read data is copied to the buffer memory 201. For example, the processor 211A receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 while all page buffers in the buffer memory 201 are copied with the same data pattern. In this case, the operation of copying data of the write same command to the buffer memory 201 is skipped.

Also, the processor 211A performs firmware processing in a host interface layer (HIL) and a flash translation layer (FTL) with respect to commands received from the host. The processor 211A transmits the data copied to the buffer memory 201 to the memory device 220 together with commands based on firmware processing in HIL and FTL. Accordingly, the write operation according to the write same command is performed in the memory device 220 .

FIG. 4B shows an example of a configuration of the memory controller 210B shown in FIG. 3B.

As shown in FIG. 4B , the memory controller 210B includes a processor 211B, a random access memory (RAM) 212B, a host interface 213, a memory interface 214, a read only memory (ROM) 215) and a bus (216).

Operations of the host interface 213, the memory interface 214, the read only memory (ROM) 215, and the bus 216 have been described with reference to FIG. 4A, so redundant description will be avoided.

The RAM 212B operates under the control of the processor 211B, and an area of the buffer memory 201 may be allocated. Also, software for the buffer management module 202 and software for the direct memory access module 203 may be loaded into the RAM 212B. In addition, program codes for processes executed in the host interface layer (HIL) and program codes for processes executed in the flash translation layer (FTL) may be loaded into the RAM 212A.

The processor 211B runs the software for the buffer management module 202 loaded in the RAM 212B to copy data to be written to the memory device 220 to the buffer memory 201 or to the memory device 220. The read data is copied to the buffer memory 201. In particular, the processor 211B may perform an operation of copying data to the buffer memory 201 using the direct memory access module 203 and an operation of processing a command in firmware in parallel. For example, the processor 211B receives a write same command having the same data pattern as the data pattern copied to the buffer memory 201 while all page buffers in the buffer memory 201 are copied with the same data pattern. In this case, the operation of copying data of the write same command to the buffer memory 201 is skipped.

Also, the processor 211B performs firmware processing in HIL and FTL with respect to commands received from the host. The processor 211B transmits the data copied to the buffer memory 201 to the memory device 220 together with commands based on firmware processing in HIL and FTL. Accordingly, the write operation according to the write same command is performed in the memory device 220 .

5 shows an example of a detailed configuration of the memory device 220 shown in FIG. 3A or 3B.

Referring to FIG. 5 , the memory device 220 may include a memory cell array 11, a control logic 12, a voltage generator 13, a row decoder 14, and a page buffer 15. there is. Hereinafter, components included in the memory device 220 will be described in detail.

The memory cell array 11 may be connected to one or more string select lines SSL, a plurality of word lines WL, and one or more ground select lines GSL, and may also be connected to a plurality of bit lines BL. there is. The memory cell array 11 may include a plurality of memory cells MC disposed in regions where a plurality of word lines WL and a plurality of bit lines BL intersect.

When an erase voltage is applied to the memory cell array 11, the plurality of memory cells MC are in an erase state, and when a program voltage is applied to the memory cell array 11, the plurality of memory cells MC are in a program state. In this case, each memory cell MC may have one of an erase state and first to n th program states P1 to Pn classified according to a threshold voltage.

Here, n may be a natural number of 2 or more. For example, n may be 3 when the memory cell MC is a 2-bit level cell. In another example, when the memory cell MC is a 3-bit level cell, n may be 7. In another example, n may be 15 when the memory cell MC is a 4-bit level cell. As such, the plurality of memory cells MC may include multi-level cells. However, the technical idea of the present invention is not limited thereto, and the plurality of memory cells MC may include single-level cells.

The control logic 12 writes data into the memory cell array 11 or operates the memory cell array 11 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 210A. ), various control signals for reading data can be output. As such, the control logic 12 may overall control various operations within the memory device 220 .

Various control signals output from the control logic 12A may be provided to the voltage generator 13 , the row decoder 14 , and the page buffer 15 . Specifically, the control logic 12 may provide the voltage control signal CTRL_vol to the voltage generator 13, may provide the row address X_ADDR to the row decoder 14, and may provide the page buffer 15 A column address (Y_ADDR) can be provided.

The voltage generator 13 may generate various types of voltages for performing program, read, and erase operations on the memory cell array 11 based on the voltage control signal CTRL_vol. Specifically, the voltage generator 13 generates a first driving voltage VWL for driving a plurality of word lines WL and a second driving voltage VSSL for driving a plurality of string select lines SSL. and a third driving voltage VGSL for driving the plurality of round select lines GSL.

In this case, the first driving voltage VWL may be a program voltage (or write voltage), a read voltage, an erase voltage, a pass voltage, or a program verify voltage. Also, the second driving voltage VSSL may be a string selection voltage, that is, an on voltage or an off voltage. Furthermore, the third driving voltage VGSL may be a ground selection voltage, that is, an on voltage or an off voltage.

The row decoder 14 is connected to the memory cell array 11 through a plurality of word lines WL, and in response to the row address X_ADDR received from the control logic 12, the plurality of word lines WL Some of the word lines can be activated. Specifically, during a read operation, the row decoder 14 may apply a read voltage to a selected word line and a pass voltage to a non-selected word line.

Meanwhile, during a program operation, the row decoder 14 may apply a program voltage to a selected word line and a pass voltage to an unselected word line. In this embodiment, in at least one of the program loops, the row decoder 14 may apply a program voltage to the selected word line and the additional selected word line.

The page buffer 15 may be connected to the memory cell array 11 through a plurality of bit lines BL. Specifically, during a read operation, the page buffer 15 may operate as a sense amplifier to output data DATA stored in the memory cell array 11 . Meanwhile, during a program operation, the page buffer 15 operates as a write driver to input data DATA to be stored into the memory cell array 11 . In the process of processing a write command or a write same command, data copied to the buffer memory 201 of the memory controller 210A or 210B is loaded into the page buffer 15 .

FIG. 6 shows an example of the memory cell array 11 shown in FIG. 5 .

Referring to FIG. 6 , the memory cell array 11 may be a flash memory cell array. At this time, the memory cell array 11 includes a (a is an integer greater than or equal to 2) memory blocks BLK1 to BLKa, and each memory block BLK1 to BLKa includes b (b is an integer greater than or equal to 2) pages. (PAGE1 to PAGEb), and each of the pages (PAGE1 to PAGEb) may include c (c is an integer of 2 or more) number of sectors (SEC1 to SECc). For convenience of illustration, in FIG. 6, pages PAGE0 to PAGEb and sectors SEC1 to SECc are shown only for the memory block BLK1, but other memory blocks BLK2 to BLKa have the same structure as the block BLK1. can have

FIG. 7 is a circuit diagram illustrating an example BLK1a of a first memory block included in the memory cell array shown in FIG. 6 .

Referring to FIG. 7 , the first memory block BLK1a may be a NAND flash memory having a vertical structure. At this time, each of the blocks BLK1 to BLKa shown in FIG. 6 may be implemented as shown in FIG. 7 . In FIG. 7 , the first direction is referred to as the x direction, the second direction as the y direction, and the third direction as the z direction. However, the present invention is not limited thereto, and the first to third directions may be changed.

The first memory block BLK1a includes a plurality of cell strings CST, a plurality of word lines WL, a plurality of bit lines BL, a plurality of ground select lines GSL1 and GSL2, and a plurality of strings. It may include select lines SSL1 and SSL2 and a common source line CSL. Here, the number of cell strings CST, the number of word lines WL, the number of bit lines BL, the number of ground select lines GSL1 and GSL2, and the number of string select lines SSL1 and SSL2 The number of may be variously changed according to embodiments.

The cell string CST may include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST connected in series between the corresponding bit line BL and the common source line CSL. there is. However, the present invention is not limited thereto, and in another embodiment, the cell string CST may further include at least one dummy cell. In another embodiment, the cell string CST may include at least two string select transistors or at least two ground select transistors.

In addition, the cell string CST may extend in a third direction (z direction), specifically, in a vertical direction (z direction) on the substrate. Accordingly, the memory block BLK1a including the cell string CST may be referred to as a vertical NAND flash memory. In this way, the degree of integration of the memory cell array 11 can be improved by extending the cell string CST in the vertical direction z on the substrate.

The plurality of word lines WL extend in the first direction x and the second direction y, and each word line WL may be connected to corresponding memory cells MC. Accordingly, a plurality of memory cells MC adjacently arranged along the first direction (x) and the second direction (y) on the same layer may be connected to the same word line (WL). Specifically, each word line WL may be connected to a gate of the memory cell MC to control the memory cell MC. In this case, the plurality of memory cells MC may store data and may be programmed, read, or erased according to the control of the connected word line WL.

The plurality of bit lines BL may extend in the first direction (x) and may be connected to the string select transistor SST. Accordingly, the plurality of string select transistors SST arranged adjacently along the first direction x may be connected to the same bit line BL. Specifically, each bit line BL may be connected to the drain of the string select transistor SST.

The plurality of string select lines SSL1 and SSL2 may extend in the second direction y and be connected to the string select transistor SST. Accordingly, the plurality of string select transistors SST arranged adjacently along the second direction y may be connected to the same string select line SSL1 or SSL2. Specifically, each string select line SSL1 or SSL2 may be connected to the gate of the string select transistor SST to control the string select transistor SST.

The plurality of ground select lines GSL1 and GSL2 may extend in the second direction y and be connected to the ground select transistor GST. Accordingly, the plurality of ground select transistors GST arranged adjacently along the second direction y may be connected to the same ground select line GSL1 or GSL2. Specifically, each ground select line GSL1 or GSL2 is connected to the gate of the ground select transistor GST to control the ground select transistor GST.

Also, the ground select transistors GST included in each cell string CST may be connected in common to the common source line CSL. Specifically, the common source line CSL may be connected to the source of the ground select transistor GST.

Here, a plurality of memory cells MC that are commonly connected to the same word line WL and the same string select line SSL1 or SSL2 and disposed adjacently along the second direction y are referred to as pages. can do. For example, a plurality of memory cells MC connected in common to the first word line WL1, connected in common to the first string select line SSL1, and disposed adjacently along the second direction y may be referred to as a first page PAGE1. In addition, a plurality of memory cells MC connected in common to the first word line WL1, connected in common to the second string select line SSL2, and disposed adjacently along the second direction y are It may be referred to as page 2 (PAGE2).

To perform a program operation on the memory cell MC, 0 V is applied to the bit line BL, an on voltage is applied to the string select line SSL, and an off (off) voltage is applied to the ground select line GSL. off) voltage can be applied. The on voltage may be greater than or equal to the threshold voltage to turn on the string select transistor SST, and the off voltage to turn off the ground select transistors GST. may be less than the threshold voltage. Also, a program voltage may be applied to a selected memory cell among the memory cells MC, and a pass voltage may be applied to the remaining memory cells. When the program voltage is applied, charges may be injected into the memory cells MC by F-N tunneling. The pass voltage may be greater than the threshold voltage of the memory cells MC.

To perform an erase operation on the memory cells MC, an erase voltage may be applied to bodies of the memory cells MC and 0V may be applied to the word lines WL. Accordingly, the data of the memory cells MC may be erased at one time.

8 is a diagram showing a process of processing data of a write same command in the memory controller 210A or 210B of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

A data pattern of a write same command received from the host 100 has a sector size. For example, the processor 211A or 211B stores the sector-sized data pattern Ds received together with the write same command in buffer 1. As an example, buffer 1 may be allocated to a storage area of RAM 212A or 212B. Buffer 1 has sector size.

Then, the processor 211A or 211B copies the sector-sized data Ds stored in the buffer 1 to the buffer 2 in page units. As an example, buffer 2 may be allocated to a storage area of RAM 212A or 212B. Buffer2 has page size. The processor 211A or 211B may configure data A in page units with a plurality of identical sector data Ds and store the data A in the buffer 2 . For example, the processor 211A or 211B may add protect information (PI) to sector data Ds and store it in buffer 2. As an example, PI may consist of Logical Block Address (LBA) information.

Then, the processor 211A or 211B repeatedly copies the page size data A stored in the buffer 2 to the buffer 3 by the number of pages corresponding to the length information of the write same command. As an example, buffer 3 may be allocated to a storage area of RAM 212A or 212B. In the embodiment of the present invention, buffer 3 is indicated as a buffer memory 201. For example, when the sector size is 512 bytes, the page size is 8K bytes, and the length information of the write same command is “48”, the processor 211A or 211B repeats data A three times Copy to buffer 3. This is because one page is composed of 16 sectors, and the data size of "48" corresponding to sector length information corresponds to 3 pages.

9 is a diagram illustrating an example of a process of copying data of a write same command to the buffer memory 201 of the memory controller 210A or 210B according to an embodiment of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

As an example, assume that the command WriteSame A is a command instructing to repeatedly write data pattern A to 13 pages, and WriteSame B is a command instructing to repeatedly write data pattern B to 12 pages.

When the command WriteSame A is received by the memory controller 210A or 210B, the processor 211A or 211B writes data pattern A into the 13 page buffer of the buffer memory 201 as shown in (a) of FIG. Copy repeatedly. The processor 211A or 211B processes the command WriteSame A and then flushes the buffer memory 201.

Therefore, when the command WriteSame A is processed and then the command WriteSame B is received by the memory controller 210A or 210B, the processor 211A or 211B processes 12 of the buffer memory 201 as shown in FIG. Repeatedly copy data pattern B to each page buffer. Referring to (b) of FIG. 9 , the data pattern A according to the previously processed command WriteSame A is not stored in the buffer memory 201 .

10 is a diagram showing another example of a process of copying data of a write same command to the buffer memory 201 of the memory controller 210A or 210B according to an embodiment of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

As an example, it is assumed that the commands WriteSame A, WriteSame B, and WriteSame C are sequentially received by the memory controller 210A or 210B. Here, the command WriteSame A is a command for repeatedly writing data pattern A to 13 pages, WriteSame B is a command for repeatedly writing data pattern B to 12 pages, and WriteSame C is a command for repeatedly writing data pattern B to 12 pages. Assume that it is a command instructing to repeatedly write pattern C on seven pages.

When the command WriteSame A is received by the memory controller 210A or 210B, the processor 211A or 211B writes data pattern A into the 13 page buffer of the buffer memory 201 as shown in FIG. 10(a). Copy repeatedly. The processor 211A or 211B does not perform an operation to flush the buffer memory 201 after processing the command WriteSame A. That is, data pattern A is retained in the buffer memory 201 even after processing the command WriteSame A.

When the command WriteSame A is received by the memory controller 210A or 210B after processing the command WriteSame A, the processor 211A or 211B processes the data pattern A of the buffer memory 201 as shown in FIG. 10(b). The data pattern B is repeatedly copied to 12 page buffers allocated next to the page buffer where B is stored.

Next, when the command WriteSame C is received by the memory controller 210A or 210B after processing the commands WriteSame A and WriteSame B, the processor 211A or 211B processes the buffer memory (as shown in FIG. 10(c)). In step 201), data pattern C is repeatedly copied to 7 page buffers allocated next to the page buffers in which data pattern A and data pattern B are stored.

Referring to (c) of FIG. 10 , it can be seen that data patterns A, B, and C are preserved in the buffer memory 201 even after the commands WriteSame A, WriteSame B, and WriteSame C are sequentially processed.

FIG. 11 is a diagram illustrating a method of verifying unity of data in the buffer memory 201 of the memory controller 210A or 210B according to an embodiment of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

For example, the memory controller 210A or 210B manages the buffer memory 201 in the manner shown in FIG. 10 to preserve data of previously processed commands. Also, the buffer memory 201 may include a plurality of page buffers in a ring buffer format. 10 shows an example in which the buffer memory 201 includes 32 page buffers in a ring buffer format for convenience of description.

The processor 211A or 211B counts the number of times the same data pattern is continuously copied to the page buffers of the buffer memory 201 . As an example, in FIG. 11, the same buffer count value is indicated. A state in which no data is stored in the page buffer of the buffer memory 201 is indicated by 'E'.

As shown in FIG. 11(a), in a state in which all page buffers of the buffer memory 201 are empty, the same buffer count value becomes '0'. As shown in FIG. 11(b), when the data pattern A is copied to the 8 page buffers of the buffer memory 201, the same buffer count value becomes '8'.

As shown in FIG. 11(c), when data pattern A of the buffer memory 201 is copied to eight page buffers and then data B is copied to one page buffer, the same buffer count value is changed to '1'.

Next, as shown in FIG. 11(d), when data pattern B of the buffer memory 201 is copied to one page buffer and then data B is copied to five page buffers, the same buffer count value is changed to '6'.

Next, as shown in FIG. 11(e), when data pattern B of the buffer memory 201 is copied to five page buffers and then data C is copied to one page buffer, the same buffer count value is changed to '1'.

Next, as shown in FIG. 11(f), when data pattern C of the buffer memory 201 is copied to one page buffer and then data C is copied to 20 page buffers, the same buffer count value is changed to '21'. Referring to FIG. 11(f), since the buffer memory 201 is configured in the form of a ring buffer, data pattern C is updated in the page buffer in which the oldest data pattern A is stored after data is stored in all page buffers. That is, among the 20 pages of data pattern C, first copy to the empty 18-page buffer of the buffer memory 201, and then copy the remaining 2 pages of data C to the 2 page buffers where the data pattern A is stored. .

Next, as shown in FIG. 11(g), when data pattern C of the buffer memory 201 is copied to 20 page buffers and then data C is copied to 10 page buffers, the same buffer count value is changed to '31'. Referring to FIG. 11(g), since data is stored in all page buffers, data pattern C is updated in 10 page buffers in which the oldest data patterns A and B are stored.

Next, as shown in FIG. 11(h), when data pattern C of the buffer memory 201 is copied to 10 page buffers and then data C is copied to one page buffer, the same buffer count value is changed to '32'. Referring to FIG. 11(h), since data is stored in all page buffers, data pattern C is updated in one page buffer where the oldest data pattern B is stored. Accordingly, data pattern C is stored in all page buffers of the buffer memory 201 . Accordingly, when the same buffer count value indicates '32', it can be known that all page buffers of the buffer memory 201 are copied with the same data pattern.

That is, when the same buffer count value becomes equal to the total number of page buffers in the buffer memory 201, all page buffers in the buffer memory 201 are copied with the same data pattern.

12 is a diagram illustrating an example of a process of executing a write same command in the memory controller 210A or 210B according to an embodiment of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

In FIG. 12, a section marked with 'M' is a section in which data patterns are copied to the buffer memory 201, and a section marked with 'W' is a section in which the processor 211A or 211B processes a write operation using firmware. Assume that the data patterns of commands WriteSame 1 to WriteSame 9 are all the same.

As an example, FIG. 12 illustrates a process of executing a write same command in the memory controller 210A or 210B when the memory controller 210A or 210B manages the buffer memory 201 in the same manner as in FIG. 9 . 12 shows a process of executing a write same command when the processor 211A or 211B manages the buffer memory 201 by flushing the buffer memory 201 after processing one write same command. has been shown

Referring to FIG. 12 , whenever a write same command is received by the memory controller 210A or 210B, an operation section in which the data pattern of the write same command is copied to the buffer memory 201 and the processor 211A or 211B writes the same data to the firmware An action section that processes an action is required.

13 is a diagram showing another example of a process of executing a write same command in the memory controller 210A or 210B according to an embodiment of the present invention. The configuration of the memory controller 210A or 210B shown in FIG. 4A or 4B will be described.

In FIG. 13, a section marked with 'M' is a section in which data patterns are copied to the buffer memory 201, and a section marked with 'W' is a section in which the processor 211A or 211B processes a write operation using firmware. Assume that the data patterns of commands WriteSame 1 to WriteSame 9 are all the same.

As an example, FIG. 13 illustrates a process of executing a write same command in the memory controller 210A or 210B when the memory controller 210A or 210B manages the buffer memory 201 in the same manner as in FIG. 10 . That is, a process of executing a write same command when the processor 211A or 211B manages the buffer memory 201 in a manner of preserving data of a previously processed command without flushing is illustrated in FIG. 13 .

Referring to FIG. 13, an operation period in which the data pattern of the write same command is copied to the buffer memory 201 until all page buffers of the buffer memory 201 are copied with the same data pattern, and the firmware in the processor 211A or 211B Therefore, an operation period for processing a low light operation is required. For example, until the TI point at which all page buffers of the buffer memory 201 are copied with the same data pattern, the operation section of copying the data pattern of the write same command to the buffer memory 201 and the processor 211A or 211B to firmware An operation section processing a light operation is required.

However, after the TI point at which all page buffers of the buffer memory 201 are copied with the same data pattern, the copying operation to the buffer memory 201 is skipped for the write same command, and the processor 211A or 211B performs a write operation by firmware. can handle

For example, in Case 1, the operation of copying commands WriteSame 4 to WriteSame 9 after TI to the buffer memory 201 may be skipped, and the processor 211A or 211B may process the write operation with firmware. That is, memory copying in the buffer memory 201 does not occur after the TI time point.

As another example, case 2 shows a case in which the number of pages of a data pattern according to length information of one command WriteSame 1 exceeds the total number of page buffers of the buffer memory 201 . In this case, memory copying in the buffer memory 201 according to one command WriteSame 1 is performed until before time T1, and the operation of copying to the buffer memory 201 after time T1 is skipped. Accordingly, after the time point T1, the processor 211A or 211B may process a write operation with firmware using data previously copied to the buffer memory 201.

Therefore, referring to FIGS. 12 and 13 , managing the buffer memory 201 in the manner of FIG. 10 is advantageous in terms of performance compared to managing the buffer memory 201 in the manner of FIG. 9 .

14 is a diagram showing an example of a process of executing a write same command without using the direct memory access module 203 in the memory controller 210A according to an embodiment of the present invention.

Referring to FIG. 14 , an operation of copying data to the buffer memory 201 (MEMCPY) and an operation of processing a write command by firmware in the processor 211A (WRITE) are serially performed.

15 is a diagram showing an example of a process of executing a write same command using the direct memory access module 203 in the memory controller 210B according to an embodiment of the present invention.

Referring to FIG. 15 , an operation of copying data to the buffer memory 201 (MEMCPY) and an operation of processing a write command by firmware in the processor 211B (WRITE) are performed in parallel. That is, an operation of copying data to the buffer memory 201 (MEMCPY) and an operation of processing a write command by firmware in the processor 211B (WRITE) may be independently performed.

16 is a diagram illustrating an example of a process of executing a write same command when consistency of data in the memory buffer 201 is confirmed in the memory controller 210B according to an embodiment of the present invention.

Referring to FIG. 16, until time T1 when the same data pattern is copied to all page buffers of the buffer memory 201, an operation of copying data to the buffer memory 201 (MEMCPY) and writing by the processor 211B to firmware The operation of processing the command (WRITE) is performed in parallel. After the point in time T1 when the same data pattern is copied to all page buffers of the buffer memory 201, the operation of copying the data pattern of the write same command to the buffer memory 201 is skipped, and the processor 211B transfers the write command to the firmware. It performs the operation (WRITE) to process.

17 is a flowchart of a method for performing a write operation according to an embodiment of the present invention. As an example, the flowchart of FIG. 17 may be performed in a memory controller of a storage device in various forms including the storage devices included in FIGS. 1A, 1B, 2A, and 2B. For example, it may be performed in the memory controller 210A or 210B of the storage device shown in FIG. 4A or 4B.

The processor 211A or 211B determines whether a command instructing a write operation is received from the host (S110). For example, a command instructing a write operation may include a write same command.

When a command instructing a write operation is received from the host, the processor 211A or 211B compares a data pattern of previously received commands with a data pattern of a command instructing a write operation currently received (S120). For example, if a cyclical redundancy check (CRC) value included in a data pattern of a currently received command indicating a write operation is the same as a CRC value included in a data pattern of previously received commands, the processor 211A or 211B performs data processing. It can be determined that the patterns are the same.

The processor 211A or 211B determines whether a data pattern of previously received commands stored in all page buffers of the buffer memory 201 and a data pattern of a command indicating a currently received write operation are the same (S130). For example, the processor 211A or 211B determines that all page buffers of the buffer memory 201 are copied with the same data pattern, and the data pattern of the command instructing the currently received write operation is copied to the buffer memory 201. Determine whether the pattern is the same.

As a result of the determination in operation S130, when the data pattern of previously received commands stored in all page buffers of the buffer memory 201 and the data pattern of the command indicating the currently received write operation are not the same, the currently received write operation An operation of copying the data pattern of the command indicating to the buffer memory 201 is performed (S140). For example, when all page buffers of the buffer memory 201 are not copied with the same data pattern, or all page buffers of the buffer memory 201 are copied with the same data pattern, but a command indicating the currently received write operation If the data pattern of the buffer memory 201 is not the same as the data pattern copied to the page buffer of the buffer memory 201, an operation of copying the data pattern of the command instructing the currently received write operation to the buffer memory 201 is performed. .

If, as a result of operation S130, the data pattern of previously received commands stored in all page buffers of the buffer memory 201 and the data pattern of the command indicating the currently received write operation are the same, the currently received write operation The operation of copying the data pattern of the command indicating to the buffer memory 201 is skipped, and an operation of writing the data copied to the buffer memory 201 to the memory device 220 is performed (S150). Also, after operation S140 is performed, an operation of writing the data copied to the buffer memory 201 to the memory device 220 is performed.

18 is a flowchart of a buffer memory management method according to an embodiment of the present invention. As an example, the flowchart of FIG. 17 may be performed in a memory controller of a storage device in various forms including the storage devices included in FIGS. 1A, 1B, 2A, and 2B. For example, it may be performed in the memory controller 210A or 210B of the storage device shown in FIG. 4A or 4B.

The processor 211A or 211B sequentially copies data of commands received from the host to the buffer memory 201 (S210). For example, when write same commands are continuously received from the host, the processor 211A or 211B sequentially copies data patterns of the write same commands received from the host to the buffer memory 201 . For example, as shown in FIG. 10 , data patterns of write same commands are sequentially copied to the buffer memory 201 in a manner of preserving data patterns of previously processed commands.

Next, the processor 211A or 211B determines whether all page buffers of the buffer memory 201 are copied with the same data pattern (S220). For example, as shown in FIG. 11 , it may be determined whether all page buffers of the buffer memory 201 are copied with the same data pattern using the same buffer count value.

As a result of the determination in operation S220, when all page buffers of the buffer memory 201 have been copied with the same data pattern, the processor 211A or 211B processes the data pattern of the currently received write same command and the page buffer of the buffer memory 201. It is determined whether the data patterns copied to are the same (S230).

As a result of determination in operation S220, all page buffers of the buffer memory 201 are not copied with the same data pattern, or as a result of determination in operation S230, the data pattern of the currently received write same command and the page buffer of the buffer memory 201 are copied. If the existing data patterns are not the same, the processor 211A or 211B copies the data pattern of the currently received write same command to the buffer memory 201 (S240). For example, the data pattern of the currently received write same command may be copied to the buffer memory 201 in the manner shown in FIG. 10 or FIG. 11 .

When the data pattern of the currently received write same command and the data pattern copied to the page buffer of the buffer memory 201 are identical as a result of the determination in operation S230, the processor 211A or 211B returns the currently received data pattern of the write same command. The operation of copying to the buffer memory 201 is skipped (S250).

19 is a flowchart of a light operation method performed in a computing system according to an embodiment of the present invention. The flowchart of FIG. 17 may be performed in various types of computing systems including the computing systems included in FIGS. 1A, 1B, 2A, and 2B. For convenience of description, a method of processing a write same command performed in the computing system 1000A of FIG. 1 will be described.

The computing system 1000A may be classified into a host system, a host interface layer (HIL), and a flash translation layer (FTL) in terms of software. The host system is implemented in the firmware of the host 100, and the host interface layer (HIL) and flash translation layer (FTL) are implemented in the firmware of the storage device 200A.

In the host system, a write same command including one sector size data and sector length information is generated and transmitted to the host interface layer (HIL) (S310).

The host interface layer (HIL) determines whether the 1-sector size data pattern of the write same command and the data pattern of the previously received command are the same (S320). For example, if a CRC value included in a data pattern having a size of 1 sector and a CRC value included in data patterns of previously received commands are the same, it may be determined that the data pattern is the same. As another example, all bits of a data pattern of one sector size and data patterns of previously received commands may be compared.

Then, in the host interface layer (HIL), copy processing is performed from the data pattern of the size of 1 sector of the write same command to the data pattern of size of 1 page (S330).

Then, the copy-processed 1-page data pattern in the host interface layer (HIL), logical page number length (LPN length) information, and pattern detect result information are transmitted to the flash translation layer (FTL) ( S340). Here, the logical page number (LPN) length information corresponds to length information obtained by converting sector length information included in the write same command into page length information. And, the pattern detection result information corresponds to information as a result of determining whether the one-sector size data pattern of the write same command and the data pattern of the previously received command are the same.

In the flash translation layer (FTL), it is determined whether the pattern detection result information received from the host interface layer (HIL) indicates that the 1-sector size data pattern of the currently received write same command and the data pattern of the previously processed command are the same. (S350).

As a result of determination in operation S350, when the pattern detection result information received from the host interface layer (HIL) indicates that the 1-sector size data pattern of the currently received write same command and the data pattern of the previously processed command are the same, flash conversion In the layer (FTL), it is determined whether the data pattern of the currently received write same command is copied to all page buffers of the buffer memory 201 (S360).

When the pattern detection result information received from the host interface layer (HIL) as a result of determination in operation S350 indicates that the 1-sector size data pattern of the currently received write same command and the data pattern of the previously processed command are not identical, or As a result of operation S360, if all page buffers of the buffer memory 201 have not copied the data pattern of the currently received write same command, the 1-page size data pattern received from the host interface layer (HIL) is converted to a logical page. It is copied to the buffer memory 201 as many times as the number of times corresponding to the number (LPN) length information (S370).

If, as a result of operation S360, the data pattern of the currently received write same command is copied to all page buffers of the buffer memory 201 as a result of the determination, the data copied to the buffer memory 201 in the flash translation layer (FTL) A light operation process is performed using (S380). Accordingly, if the data pattern of the currently received write same command is copied to all page buffers of the buffer memory 201, the operation of copying the data pattern of the currently received write same command to the buffer memory 201 is skipped. You will be able to do it.

Meanwhile, the storage device applied to the present invention described above may be mounted using various types of packages. For example, the storage device according to the present invention includes PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic MetricQuad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( WSP), etc. can be mounted using packages such as

As described above, the optimum embodiment has been disclosed in the drawings and specifications. Although specific terms have been used herein, they are only used for the purpose of describing the present invention, and are not used to limit the scope of the present invention described in the meaning or claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1000A, 1000B, 2000A, 2000B: Computing Systems
100, 2100: host
200A, 200B, 2210-1, 2210-M, 2210'-1, 2210'-M: Storage Device
201, 201-1, 201-M: buffer memory
202, 202-1, 202-M: buffer management module
203, 203-1, 203-M: Direct memory access module
2110, 211A, 211B: Processor
2120: memory 2130: I/O controller
2140: I/O Bridge 2200A, 2200B: I/O Device Block
210A, 210B: memory controller 220: memory device
220-1: non-volatile memory
212A, 212B: RAM 213: Host interface
214: memory interface 215: ROM
216: bus 11: memory cell array
12: control logic 13: voltage generator
14: row decoder 15: page buffer

Claims (10)

comparing a data pattern of a command indicating a currently received write operation with a data pattern of previously received commands;
When the data pattern of the command instructing the write operation is the same as the data pattern of previously received commands, whether the number of page buffers in which the data pattern is stored matches the same buffer count set in the buffer memory determining; and
and performing a write operation by selectively using the data copied to the buffer memory based on the determination result. The method of claim 1 , wherein the command instructing the write operation includes a write same command, and the write same command is a command for performing an operation of writing one data pattern to two or more pages, respectively. A method for performing a light operation, characterized in that. 2 . The method of claim 1 , wherein the comparing of the data patterns includes a cyclical redundancy check (CRC) value included in the data pattern of the command instructing the write operation and a CRC value included in the data pattern of previously received commands. A method of performing a write operation, characterized in that it is determined that the data patterns are the same. The method of claim 1 , wherein the comparing of the data patterns is performed in a host interface layer of a memory controller, the host interface layer transmits information about a result of the pattern comparison to a flash conversion layer, and the flash conversion layer transmits information about a result of the pattern comparison. and determining whether or not to reuse data patterns of the previously received commands based on information about a pattern comparison result. The method of claim 1 , wherein all pages in a buffer memory to which data patterns of the previously received commands are sequentially copied are memory-copied with the same data pattern, and the data patterns copied to the buffer memory and the command instructing the write operation and skipping an operation of copying a data pattern of a command instructing the write operation to the buffer memory when the data patterns of the write operations are the same. 6. The method of claim 5, wherein the buffer memory includes a ring buffer memory, counts the number of page buffers to which the same data pattern is continuously copied to the ring buffer memory, and the counted number of page buffers is stored in the buffer memory. A method of performing a write operation comprising: determining that all pages in a buffer memory are memory copied with the same data pattern when the total number of included page buffers is the same. sequentially copying command data received from the host to a buffer memory; and
When a write same command of the same data pattern as the data pattern copied to the buffer memory is received while all the page buffers in the buffer memory are copied with the same data pattern, the write same command is received in the buffer memory. Skipping an operation of copying data of a light same command;
and performing a write operation according to the write same command using the data copied to the buffer memory. 8. The method of claim 7, wherein the buffer memory includes a ring buffer memory, and the number of page buffers to which the same data pattern is continuously copied to the ring buffer memory is equal to the total number of page buffers included in the buffer memory. A buffer memory management method characterized in that it is determined that all pages in the buffer memory are memory copied with the same data pattern. 8. The method of claim 7 , wherein if a CRC value included in the data patterns of the write same command and a cyclical redundancy check (CRC) value included in the data patterns of previously received commands are identical, it is determined that the data patterns are identical. buffer memory management method. 8 . The method of claim 7 , wherein the operation of copying the write command to the buffer memory and the operation of processing the write same command in firmware are performed in parallel.

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