TWI619078B - Host controller, method operational on a host controller for communicating with a target device and readable storage medium - Google Patents

Abstract

The present invention provides a host controller that unilaterally supports queue blocking functionality. The host controller may receive a first task labeled with one of a series of blocking indicators. Therefore, the host controller delays the transmission of the first task to a target device. In addition, the host controller also delays the transmission of any task appearing after the first task to the target device. Upon receiving an indication from the target device that all previously sent tasks have been processed, the host controller sends the first task only to the target device. Upon receiving an indication from the target device that the first task has been processed, the host controller sends to the target device only any tasks that occur after the first task.

Description

Host controller, method for operating on a host controller for communication with a target device, and readable storage medium Claim priority under 35 U.S.C. §119

This utility patent application claims that the application titled "Providing Queue Barriers When Unsupported By An I / O Protocol or Target Device" was filed on July 23, 2013. US Patent Provisional Patent Application No. 61 / 857,570, which has been assigned to the assignee and is hereby expressly incorporated herein by reference.

The following is generally about performing tasks within a queue, and more specifically, about providing or facilitating such queues when they are not supported by an in-use input / output (I / O) agreement Row blocking method and device.

Software operating in the I / O host controller in the host device can queue several tasks sent by the I / O host controller to the target I / O device for enqueuing and execution. In some cases, the execution order can be determined by the receiving target I / O device, which is beyond the control of the host device. Therefore, the receiving target I / O device can change the execution order of the tasks.

In some cases, the software on the host device will want to guarantee a certain execution order of tasks sent to the target I / O device. For example, some I / O communication protocols provide queue barriers to indicate whether tasks cannot be processed out of order. Target I / O in other situations The device and / or I / O communication protocol (used between the host device and the target I / O device) may not provide an interception to enforce this order of execution.

Therefore, there is a need to provide queue blocking functionality that allows the host device to control the execution order at the target I / O device if this functionality is not supported by the target I / O device or I / O communication protocol.

A host controller is provided, which includes: a communication interface that communicates with a target device; and a processing circuit that is coupled to the communication interface. The processing circuit may be adapted to: (a) obtain a first task marked with a series of blocking indicators; (b) delay the transmission of the first task to the target device; and / or (c) once from the The target device receives an indication that all previously sent tasks have been processed, and sends the first task to the target device.

In one example, the processing circuit may be further adapted to: (a) sequentially obtain multiple tasks from a task queue, wherein the first task is one of the multiple tasks; (b) identify each task Whether a queue blocking indicator is marked; and / or (c) determining that the queue blocking indicator is marked for the first task.

In addition, the processing circuit may be further adapted to delay the transmission of any task appearing after the first task to the target device until the target device receives the indication that all previously sent tasks have been processed. Upon receiving an indication from the target device that the first task has been processed, the processing circuit may then send any task that occurs after the first task to the target device.

In one implementation, the host controller and the target device may communicate using one of the protocol that the queue blocking indicator functionality is not supported. According to one aspect, a single queue blocking indicator functionality is not supported in the target device. According to another aspect, the queue blocking indicator may be different from a separate queue blocking functionality supported in the target device or in an input / output communication protocol between the host controller and the target device. .

In one implementation, the host controller may be a device separate from the target device. In another implementation, the host controller can be integrated with the target device in a single semiconductor device. In one example, the target device may be a storage device and the tasks include read and / or write operations.

The first task without the queue blocking indicator may be sent to the target device. The first task and other tasks may be obtained by the processing circuit from a task queue, and each of the first task and the other tasks is provided by the processing circuit with a queue of blocking indicators relative to each task marked with each other. Other tasks are placed in the order of the task queue for processing.

A method operable on a host controller for communication with a target device is also provided, comprising: (a) obtaining a first task labeled with a queue of blocking indicators; (b) delaying (e.g., (Suspend, temporarily stop) the transmission of the first task to the target device; (c) once receiving an indication from the target device that all previously sent tasks have been processed, send the first task to the target device .

The method may further include: (a) sequentially obtaining a plurality of tasks from a task queue, wherein the first task is one of the plurality of tasks; (b) determining whether each task is marked with a queue of blocking instructions (C) determine that the first task is marked with the queue blocking indicator; and / or (d) delay the transmission of any task that occurs after the first task to the target device until it is received from the target device Until all instructions for previously sent tasks have been processed. Upon receiving an indication from the target device that the first task has been processed, any task that occurs after the first task can be sent to the target device.

In one example, the host controller and the target device can communicate using one of the protocol that the queue blocking indicator functionality is not supported. In another example, the queue blocking indicator may be different from a separate queue blocking functionality supported in the target device or in an input / output communication protocol between the host controller and the target device. . In yet another example, the queue blocking indicator functionality is not supported in the target device.

Provide a non-transitory processor-readable storage medium having one or more instructions Order, when the one or more instructions are executed by the at least one processing circuit, the at least one processing circuit performs the following operations: (a) obtaining a first task marked with a queue of blocking indicators; (b) delaying the Transmission of a task to the target device; (c) once receiving an indication from the target device that all previously sent tasks have been processed, sending the first task to the target device; and / or (d) delayed Any task that occurs after the first task is transmitted to the target device until the target device receives the indication that all previously sent tasks have been processed.

The non-transitory processor-readable storage medium may further include one or more instructions that, when executed by the at least one processing circuit, cause the at least one processing circuit to perform the following operations: (a) queue from a task Obtain a plurality of tasks in sequence, wherein the first task is one of the plurality of tasks; (b) find out whether each task is marked with a series of blocking indicators; and / or (c) determine the first task The queue blocking indicator is marked. Upon receiving an indication from the target device that the first task has been processed, any task that occurs after the first task can be sent to the target device.

102‧‧‧Host device

104‧‧‧Target I / O device

106‧‧‧Bus

108‧‧‧ host software

109‧‧‧Task queue

110‧‧‧Host Controller

112‧‧‧Target Controller

114‧‧‧Task queue

116‧‧‧Storage device

302‧‧‧First task queue

304‧‧‧Second task queue

502‧‧‧Host device

504‧‧‧Processing Circuit

506‧‧‧Host Controller

508‧‧‧ processor-readable storage medium / device

510‧‧‧Bus

512‧‧‧Transceiver Circuit

514‧‧‧Task generator module / circuit

516‧‧‧Side barrier marking module / circuit

520‧‧‧Queue blocking indicator checker

522‧‧‧Task queue

524‧‧‧Task Generator Instructions

526‧‧‧Queue Block Marker Instructions

530‧‧‧Memory device

702‧‧‧Host Controller

704‧‧‧controller processing circuit

706‧‧‧Storage device

708‧‧‧Register

710‧‧‧ input / output communication interface or circuit

711‧‧‧Task Processing Module / Circuit

712‧‧‧ queue blocking indicator detection module / circuit

714‧‧‧Task suspension module / circuit

716‧‧‧Task Recovery Module / Circuit

719‧‧‧ task processing instruction

720‧‧‧ queue blocking indicator detection instruction

722‧‧‧Task suspension instruction

724‧‧‧Task resume instruction

726‧‧‧Task queue

FIG. 1 is a block diagram of a system including a host device coupled to a target I / O device via a bus and adapted to implement queue blocking functionality.

FIG. 2 is a flowchart illustrating how the queue blocking function can be implemented.

FIG. 3 (including FIGS. 3A, 3B, and 3C) graphically illustrates a process of an exemplary implementation of a queue blocking indicator on a host device.

FIG. 4 is a flowchart illustrating a method operable by the host controller to implement queue blocking for tasks.

FIG. 5 is a block diagram illustrating an illustrative example of a host device that implements host-controlled queue blocking functionality.

6 is a flowchart illustrating an exemplary method operable at a host device to implement queue blocking functionality.

FIG. 7 is a block diagram illustrating an exemplary host controller adapted to facilitate queue blocking functionality.

8 is a flowchart illustrating an exemplary method that can be operated by a host controller adapted to facilitate queue blocking functionality.

FIG. 9 is another flowchart illustrating an exemplary method that can be operated by a host controller adapted to facilitate queue blocking functionality.

The description set forth below with reference to the drawings is intended as a description of various configurations and is not intended to represent the only configurations that can implement the concepts and features described herein. The following description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known circuits, structures, technologies, and components are shown in block diagram form to avoid obscuring the concepts and features described.

Various concepts presented throughout the present invention can be implemented across a wide variety of telecommunication systems, network architectures, electronic devices, mobile devices, computing devices, and communication standards. Certain aspects of the invention are described below with reference to specific protocols, systems, and technologies. However, those of ordinary skill in the art will recognize that one or more aspects of the invention may be used in and include one or more other wireless communication protocols, systems, and technologies.

Overview

The various features and aspects of the present invention are related to ensuring that tasks are performed in a certain order, even when the receiving target device or interface protocol does not provide support for this queue ordering. Host software operating on the host device may mark a task with a queue blocking (QBR) indicator (eg, a label or tag). However, the target I / O device communicating with the host device and / or the I / O communication protocol used may not support this QBR indicator. Therefore, when the host I / O controller processes a task that is tagged / tagged with the QBR indicator, it will not send the task to the target I / O device until it is previously queued (at target I / O device Until all tasks are performed. The target I / O device can send an execution response to the host I / O controller when each task is executed or processed. The host I / O controller at the host device can also delay / maintain all tasks queued after the task marked with QBR and pass all these tasks to the task marked with QBR only after execution Target I / O device. Therefore, queue blocking can be implemented as part of the I / O interface in the host I / O controller of the host device. For example, where queue blocking is not natively supported by I / O communication protocols and / or target I / O devices, such queue blocking at the host I / O controller may be useful. In other cases, even if the I / O communication protocol supports queue blocking, this queue blocking at the host I / O controller can be useful. For example, there may be situations where even if the I / O protocol supports queue blocking, it may still be necessary to allow the host I / O controller to implement queue blocking as well, such as when the I / O protocol may not allow sending. While blocking commands while others are still in progress. This concept anticipates the use of one or more tasks labeled / tagged QBR in the queue at any one time (ie, simultaneously).

Exemplary Operating Environment

FIG. 1 is a block diagram of a system including a host device 102 coupled to a target I / O device 104 via a bus 106 and adapted to implement queue blocking functionality. The host device 102 may include host software 108, a task queue 109, and a host controller 110. The target I / O device 104 may include a controller 112, a task queue, and a storage device 116. The host task queue 109 may keep tasks sent to the target I / O device 104. For example, the host task queue 109 may be used by the host software 108 to provide tasks to the host controller 110 and may be used to maintain the tasks until the tasks are sent to the target I / O device 104.

In various implementations, the target I / O device 104 may be a component different from or separate from the host device, or the target I / O device 104 may be integrated with the host device 102 into a single semiconductor chip. For example, the target I / O device 104 may be a flash memory device that conforms to the Embedded Multimedia Controller (eMMC) standard of the Joint Electronic Device Engineering Association (JEDEC). Queue barriers are sometimes defined by agreement to allow defining pins relative to other tasks The order of execution of a task. However, this situation only works if the target I / O device recognizes and adheres to the execution order defined by this blocking tag / tag.

According to one approach, the host software 108 may generate tasks that should be performed in a certain order relative to other tasks. For example, the first task must be performed before all subsequent tasks are performed. Therefore, the host software 108 may mark a queued blocking (QBR) indicator (e.g., a tag, tag, or bit) for the first task to indicate that the first task (e.g., the first The task must be performed after all tasks issued before the first task, and / or the first task must be performed before all tasks issued after the first task, etc.). The host controller 110 may recognize that the first task is marked with a QBR indicator. Therefore, the host controller 110 may delay or maintain the first task instead of sending the first task to the target I / O device 104 until receiving a response or instruction that all previous tasks have been performed by the target I / O device 104. Likewise, the host controller 110 may delay or hold all subsequent tasks instead of sending all subsequent tasks to the target I / O device 104. Once the host controller 110 receives an indication that all previous tasks have been performed by the target I / O device 104, the host controller sends the first task to the target I / O device 104. Before sending subsequent tasks to the target I / O device 104, the host controller 110 then waits to receive an indication that the first task has been performed by the target I / O device 104. It should be noted that "tasks" disclosed herein may be data and / or non-data tasks (eg, commands, instructions, etc.). In one example, tasks may include read and / or write operations.

FIG. 2 is a flowchart illustrating how the queue blocking function can be implemented. The host software 108 may generate tasks 1... 204 and provide the tasks to the host controller 110. The host controller 110 then sends tasks 1 ... n to the target controller 112, which provides the tasks to a task queue 114 from which the tasks 208 can be executed or processed.

The host software 108 may also generate a task R 210 labeled with a queue blocking indicator 212 (eg, a tag or label). The task R is provided to the host controller 110. However, because task R is tagged / labeled as QBR, host controller 110 delays or maintains task R 216. The host controller 110 waits for a response that all previously sent tasks from the target I / O device 104 have been executed or processed. After receiving the response 217 that the tasks 1 ... n have been executed or processed by the target I / O device 104, the host controller 110 sends the task R to the target controller 112. It should be noted that in some implementations, a reply that tasks 1 ... n have been executed or processed may be sent while the last task (i.e. task n) is processed but this processing has not been completed. The task R is passed from the target controller 112 to the task queue 114, and the task 226 is processed or executed from the task queue.

During this period, the host controller 110 delays or holds 222 any task t ... w 218 generated after the task R until the host controller receives a response that the task R has been executed or processed by the target I / O device 104. After receiving the response 224 that the task R has been executed or processed by the target I / O device 104, the host controller 110 sends the task t ... w to the target controller 112, which transmits the task to the task 伫Column 114 may process or perform such tasks 228 from the task queue.

In this way, the host controller 110 can unilaterally implement queue blocking for tasks, even when the target I / O controller and / or I / O protocol does not support queue blocking. Therefore, task execution sequencing may be implemented by the host controller 110.

It should be noted that one or more tasks that are tagged / tagged with QBR may be used in the task queue at any one time (i.e., simultaneously). Therefore, multiple tasks tagged / labeled with QBR can be placed in the host device queue. Each task labeled / labeled with QBR is assigned to each labeled / labeled QBR. The tasks are placed in the order of the host device's task queue and sent to the target I / O device.

FIG. 3 (including FIGS. 3A, 3B, and 3C) graphically illustrates a process of an exemplary implementation of a queue blocking indicator on a host device. The host device 102 may implement a first task queue 302, and tasks are placed in the first task queue for processing by the host controller 110. The target device 104 may similarly implement the second task queue 304, and the tasks received by the target controller 112 are placed in the second task queue for processing by the target device 104.

The tasks in the first task queue 302 may be labeled or marked with a queue blocking indicator. For example, the queue barrier indicator = "0" indicates no queue barrier, and the queue barrier indicator = "1" indicates queue barrier. The host controller 110 may check the queue blocking indicator of each task before executing or processing each task. If the queue blocking indicator = "0" for a specific task, the host controller processes the task. Otherwise, if the queue blocking indicator = "1" for a specific task, the host controller delays or suspends processing of that task (and all possible subsequent tasks) until the host controller receives all previously sent tasks Until the instruction or response has been processed by the target device 104.

At time k, the host controller 110 may execute or process task n by sending task n to the target device 104. In the target device, task n is placed in the second task queue 304. When the target device 104 processes each task, the target device may send an execution response for each task to the host device 102.

At time k + i, the host controller 110 may execute or process task n + i by sending task n + i to the target device 104. In the target device, task n + i is placed in the second task queue. 304.

At time k + i + 1, the host controller 110 may be ready to perform or process task p. After checking the queue blocking indicator for task p, the host controller then detects that the indicator is enabled or set to "1", thereby indicating that queue blocking is confirmed for task p. Therefore, the host controller 110 suspends or delays the processing of task p (and all subsequent tasks) until the host controller receives a response or instruction that all previous tasks sent to the target device 104 have been processed.

By the time k + i + j, the host controller 110 may have received a response that all previous tasks including the task n + i have been executed or processed by the target device 104. Therefore, at time k + i + j + 1, the host controller 110 can process task p. The host controller 110 may delay all subsequent tasks until the task p (ie, the task with the queue blocking indicator) has been instructed or answered by the target device. At time k + i + j + 2, the host controller 110 may receive any The execution response of task p. Then, at time k + i + j + 3, the host controller 110 can process subsequent tasks p + 1, and so on.

It should be noted that in one example, the queue blocking indicator may be a bit attached to each task. In another example, the queue blocking indicators for each task may be maintained in separate memory segments.

FIG. 4 is a flowchart illustrating a method operable by the host controller to implement queue blocking for tasks. This method may be implemented, for example, by the host controller 110 illustrated in FIGS. 1, 2 and 3. The host controller may include a communication interface through which the host controller communicates with the target device. The processing circuit in the host controller can be adapted to perform the following operations: (a) obtaining a first task 402 marked with a queue blocking indicator; (b) delaying the transmission of the first task to the target device 404; (c) Delaying the transmission of any task to the target device after the first task 406; (d) sending the first task to the target device 410 upon receiving from the target device an indication 408 that all previously sent tasks have been processed; and / Or (e) Upon receiving from the target device an indication 414 that the first task has been processed, any task that occurs after the first task is sent to the target device 416. Otherwise, any task 412 that appears after the first task is delayed until this instruction is received. It should be noted that in some implementations, the queue blocking indicator is not sent to the target device.

In some implementations, the host controller and the target device may communicate using a protocol in which queue blocking indicator functionality is not supported. In addition, queue blocking indicator functionality may not be supported on the target device. The host controller can be integrated with the target device in a single semiconductor device. In one example, the target device may be a storage device (eg, non-volatile storage, volatile storage, flash storage, etc.).

Exemplary Host Device

FIG. 5 is a block diagram illustrating an illustrative example of a host device that implements host-controlled queue blocking functionality. The host device 502 may include a processing circuit 504, a host controller 506, a processor-readable storage medium / device 508, a memory device 530, a transceiver circuit 512, and a sink. Stream 510.

The processing circuit 504 may include a task generator module / circuit 514 that is adapted to generate one or more tasks and place the tasks in a task queue 522 within the shared memory device 530. The processing circuit 504 may also include a queue blocking marking module / circuit 516 adapted to mark one or more tasks, such as a queue blocking indicator instructed by an operating system, host software, or compiler. In one example, the processor-readable storage media device 508 may include a task generator instruction 524 and a queue blocking flag instruction 526 to allow host software operating on the processing circuit 504 to perform these functions.

The host controller 506 can obtain tasks from the task queue 522 in the memory device 530. The queue blocking indicator checker 520 may check each task before execution to find out whether a queue blocking indicator is set for that particular task. If no queue blocking indicator is set for the task, the host controller 506 can process the task, for example, send the task (eg, data and commands) to the target device via the transceiver circuit 512. If a queue blocking instruction is set for a task (for example, "1"), the host controller 506 may delay, temporarily suspend or suspend the execution or processing of the task and all subsequent tasks. In one example, the tasks may include read and / or write operations to be performed on the target device.

The host controller 506 can maintain status information for tasks in progress. The target device may send a response to the host controller 506 for each task that the target device has processed. After receiving an indication that all previous tasks have been processed, the host controller 506 can process (eg, send) tasks that were temporarily suspended or suspended and all subsequent tasks.

6 is a flowchart illustrating an exemplary method operable at a host device to implement queue blocking functionality. Host software operating on the host device may obtain or generate one or more tasks 602. For each task, the host software can ascertain whether the task should mark the queue blocking indicator 604 or not. If the queue blocking indicator is to be marked for the task, a blocking queue indicator 606 for the task is set or enabled. Each task is then stored in a task queue 608 shared with the host controller.

Example host controller

FIG. 7 is a block diagram illustrating an exemplary host controller adapted to facilitate queue blocking functionality. In this example, the host controller 702 may include a controller processing circuit 704 that is coupled to one or more registers 708 and / or an input / output communication interface or circuit 710. The controller processing circuit 704 may include a task processing module / circuit 711, a queue blocking indicator detection module / circuit 712, a task suspension module / circuit 714, and / or a task recovery module / circuit 716.

The task processing module / circuit 711 may retrieve a task from the task queue 726, process the captured task, and then process the next task in the task queue 726. Such tasks may include, for example, performing a read or write operation from / to an external target device. The queue blocking indicator detection module / circuit 712 can find out whether a task is marked or tagged with a queue blocking indicator before processing a specific task. If a queue blocking indicator is detected for a specific task, the task suspension module / circuit 714 may freeze, suspend, or temporarily suspend processing of the task and subsequent tasks (e.g., suspend the current task and be in the queue for an application Any subsequent tasks). The task recovery module / circuit 716 may monitor the completion of previous tasks at the target device and resume the processing of the tasks in the task queue after receiving the instructions that all previous tasks have been processed by the target device.

In one example, the host controller 702 may be coupled to the storage device 706 (eg, via the I / O interface circuit 710) in order to obtain one or more operation instructions. For example, the storage device 706 may include a task processing instruction 719 to process a task from the task queue 726, a queue blocking indicator detection instruction 720 to detect the presence or presence of a blocking indicator, A task pause instruction 722 that suspends processing of tasks from the task queue when a blocking indicator is detected, and / or a task resume instruction 724 that resumes processing of the task once the blocking indicator has been cleared.

In one example, the input / output communication interface or circuit 710 may be used to communicatively couple the controller processing circuit 704 to the bus, the input / output communication interface or circuit being via the The bus is coupled to / from the transceiver circuit of the target device. Alternatively, the input / output communication interface or circuit 710 may directly couple the controller processing circuit 704 to the target device.

8 is a flowchart illustrating an exemplary method that can be operated by a host controller adapted to facilitate queue blocking functionality. The host controller can obtain task 802 from the task queue. The host controller then determines if the task is marked with a queue blocking indicator 804. If the task is marked with a queue blocking indicator, the host controller delays the transmission of the task to the target device 806. Once the host controller receives an indication 808 that the target device has completed processing of all previously sent tasks, the host controller sends the task to the target device 810. This process can be repeated for each task in the task queue.

FIG. 9 is another flowchart illustrating an exemplary method that can be operated by a host controller adapted to facilitate queue blocking functionality. The host controller may sequentially obtain a plurality of tasks from the task queue, wherein the first task is one of the plurality of tasks 902. When each task is obtained or retrieved, the host controller can ascertain whether each task is marked with a queue blocking indicator 904. For example, it may be determined that the first task is marked with a queue blocking indicator 906. Therefore, the host controller delays the transmission 908 of the first task to the target device. Similarly, the host controller may delay the transmission of any task that occurs after the first task to the target device until the target device receives an indication that all previously sent tasks have been processed 910. Upon receiving an indication from the target device that all previously sent tasks have been processed, the first task is sent to the target device 912. Once an indication is received from the target device that the first task has been processed, any tasks that occur after the first task can be sent to the target device 914.

In one example, the host controller and the target device communicate using one of the protocol that the queue blocking indicator functionality is not supported. In another example, the queue blocking indicator functionality is not supported in the target device. In yet another example, the queue blocking indicator may differ from the separate queue blocking functionality supported in the target device or in an input / output communication protocol between the host controller and the target device.

In one implementation, the host controller may be a device separate from the target device. In another implementation, the host controller can be integrated with the target device in a single semiconductor device. In yet another implementation, the target device is a storage device and the tasks include read and / or write operations. According to one aspect, the first task without the queue blocking indicator is sent to the target device.

Although the aspects, configurations, and embodiments discussed above are discussed with specific details and particularities, in FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and / or FIG. One or more of the illustrated components, steps, features, and / or functions may be reconfigured and / or combined into a single component, step, feature, or function, or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may be added or not used without departing from the invention. The equipment, devices, and / or components illustrated in FIG. 1, FIG. 2, FIG. 3, FIG. 5, and / or FIG. 7 may be configured to perform or use FIG. 2, FIG. 3, FIG. 4, FIG. 6, and / or FIG. One or more of the methods, features, parameters and / or steps described in 8. The novel algorithms described herein can also be efficiently implemented in software and / or embedded in hardware.

Also, it should be noted that at least some implementations have been described as a processing program, which is depicted as a flowchart or flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential handler, many operations can be performed in parallel or concurrently. In addition, the order of operations can be reconfigured. When the operation of the processing program is completed, the processing program is terminated. The processing procedure may correspond to a method, a function, a procedure, a subroutine, a subroutine, and the like. When the handler corresponds to a function, the termination of the handler corresponds to the function returning to the calling function or the main function. The methods described herein may be implemented partially or completely by programming (e.g., instructions and / or data), which may be stored in a non-transitory machine-readable, computer-readable, and / or processor The readable storage medium is executed by one or more processors, machines, and / or devices.

Those skilled in the art should further understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as hard Software, firmware, firmware, middleware, microcode, or any combination thereof. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described generally above with regard to functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

Various features associated with the examples described herein and shown in the drawings may be implemented in different examples and implementations without departing from the scope of the invention. Therefore, although certain specific configurations and configurations have been described and shown in the accompanying drawings, these embodiments are merely illustrative and do not limit the scope of the present invention. Various other additions, modifications, and deletions to the described embodiments will be apparent. Therefore, the scope of the present invention is determined only by the written language and legal equivalents of the scope of the patent application that follows.

102‧‧‧Host device

104‧‧‧Target I / O device

302‧‧‧First task queue

304‧‧‧Second task queue

Claims (23)

A host controller includes: a communication interface that communicates with a target device external to the host controller; a processing circuit that is coupled to the communication interface; the processing circuit is adapted to: from the host controller One of the task queues sequentially obtains a plurality of tasks for execution on the target device, and a specific subset of the plurality of tasks containing less than the owner of the plurality of tasks is unilaterally obtained by the The host controller is marked with a queue of blocking indicators; one of the plurality of tasks is obtained by the host controller and marked with the queue of blocking indicators for performing a first task on the target device; After detecting a first queue blocking indicator, the transmission of the first task from the host controller to the target device is delayed; once an indication is received from the target device that all previously sent tasks have been processed, Send the first task to the target device. For example, the host controller of claim 1, wherein the processing circuit is further adapted to: find out whether each task is marked with a queue blocking indicator; and determine that the first task is marked with the queue blocking indicator. If the host controller of claim 1, wherein the processing circuit is further adapted to: delay the transmission of any task appearing after the first task to the target device, until the target device receives all previously sent tasks has been obtained Until the instructions are processed. If the host controller of item 3 is requested, wherein the processing circuit is further adapted to: upon receiving an indication from the target device that the first task has been processed, send any task that occurs after the first task to The target device. If the host controller of claim 1, wherein the host controller and the target device are used Queue blocking indicator functionality is not supported by one of the protocol communications. As in the host controller of item 1, one of the separate queue blocking indicator functionality is not supported in the target device. The host controller of claim 1, wherein the first queue blocking indicator is different from a separate one supported in the target device or in an input / output communication protocol between the host controller and the target device. Queue blocking functionality. The host controller of claim 1, wherein the host controller is a device separate from the target device. For example, the host controller of claim 1, wherein the host controller and the target device are integrated in a single semiconductor device. If the host controller of claim 1, wherein the target device is a storage device and the tasks include read and / or write operations. If the host controller of item 1 is requested, the first task without the queue blocking indicator is sent to the target device. For example, the host controller of claim 1, wherein the first task and other tasks are obtained from a task queue by the processing circuit, and each of the first task and other tasks is performed by the processing circuit according to each Tasks are processed relative to the order in which other tasks marked with a queue of blocking indicators are placed in the task queue. A method operable on a host controller for communicating with a target device external to the host controller, comprising: sequentially obtaining from a task queue in the host controller for use in the target device A plurality of tasks executed on the computer, the specific subset of which includes one of the plurality of tasks less than the owner of the plurality of tasks is unilaterally marked by the host controller with a series of blocking indicators; from the plurality of The task obtains a first task marked with the queue blocking indicator for performing on the target device; After detecting a first queue blocking indicator, the transmission of the first task to the target device in the host controller is delayed; once an indication is received from the target device that all previously sent tasks have been processed , The first task is sent to the target device. The method of claim 13, further comprising: determining whether each task is marked with a queue blocking indicator; and determining that the first task is marked with the queue blocking indicator. The method of claim 14, further comprising: delaying transmission of any task occurring after the first task to the target device until the target device receives the indication that all previously sent tasks have been processed. The method of claim 15, further comprising: upon receiving an indication from the target device that the first task has been processed, sending any task that occurs after the first task to the target device. The method of claim 13, wherein the host controller and the target device use one of the protocol communication functions whose queue blocking indicator functionality is not supported. The method of claim 13, wherein the first queue blocking indicator is different from a separate queue supported in the target device or in an input / output communication protocol between the host controller and the target device Barrier functionality. The method of claim 13, wherein the queue blocking indicator functionality is not supported in the target device. A non-transitory processor-readable storage medium having one or more instructions that, when executed by at least one processing circuit of a host controller, causes the at least one processing circuit to perform the following operations: A task queue in the host controller sequentially obtains a plurality of tasks for execution on a target device external to the host controller. A specific subset of the plurality of tasks of the owner of the plurality of tasks is marked with a series of blocking indicators by the host controller; obtained from the plurality of tasks is unilaterally marked by the host controller with The queue blocking indicator is used to perform a first task on the target device; after detecting a first queue blocking indicator, delaying the first task from the host controller to the target device And upon receiving from the target device an indication that all previously sent tasks have been processed, the first task is sent to the target device. If the non-transitory processor-readable storage medium of claim 20 further has one or more instructions, the one or more instructions, when executed by the at least one processing circuit, cause the at least one processing circuit to perform the following operations: Whether each task is marked with a queue blocking indicator; and determining whether the first task is marked with the queue blocking indicator. If the non-transitory processor-readable storage medium of claim 20 further has one or more instructions, the one or more instructions, when executed by the at least one processing circuit, cause the at least one processing circuit to perform the following operations: Any task appearing after the first task is transmitted to the target device until the target device receives the indication that all previously sent tasks have been processed. If the non-transitory processor-readable storage medium of claim 20 further has one or more instructions, the one or more instructions, when executed by the at least one processing circuit, cause the at least one processing circuit to perform the following operations: The target device receives an indication that the first task has been processed, and sends any tasks that occur after the first task to the target device.