TWI614764B - Memory apparatus and an operating method using the same - Google Patents

Abstract

A memory device includes a memory cell array, a temporary storage unit, and a command generator. The memory cell array includes a plurality of memory cells. The temporary storage unit is used to record multiple customized information. The instruction generator is coupled to the temporary storage unit and the memory cell array. The instruction generator receives the custom command and performs at least two memory operations on the memory cell array according to the received custom command and the customized information. Custom information is generated based on the at least two memory operations described. In addition, a method of operating a memory device has also been proposed.

Description

Memory device and method of operating same

The present invention relates to a memory device and a method of operating the same, and more particularly to a memory device capable of customizing memory commands and a method of operating the same.

Synchronous dynamic random-access memory (SDRAM) is a dynamic random access memory with a synchronous interface that synchronizes with the bus of the computer by means of a clock signal. With the advancement of memory technology, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) has also been developed. DDR SDRAM is a SDRAM with double transfer rate. It can transmit data on both the rising and falling edges of the system clock. Therefore, its transfer rate is twice that of the system clock and it has high efficiency.

In order to further improve work efficiency, second, third and fourth generation DDR SDRAM has been developed. However, due to the standards set by the JEDEC Solid State Technology Association for DRAM, the DRAM needs to receive multiple memory commands from the memory controller in succession, and perform corresponding operations on memory-by-memory commands. The memory operation can complete the action. For example, when a piece of data is to be written, the memory controller successively issues DRAM corresponding operations to the memory: Activate column address, Read row address, and Precharge. Three memory commands are executed, and the above three memory operations are successively completed by the DRAM. In another example, when multiple data pieces are to be continuously written, the memory controller not only needs to issue RD commands to the DRAM multiple times, but also must transfer multiple memory addresses to the DRAM. Therefore, if you can reduce the excessive transfer between the memory controller and the DRAM, including memory commands or address, etc., it will improve the efficiency of the system and reduce the power consumption of the system.

The invention provides a memory device and an operation method thereof, which can reduce the number of transmissions of memory commands, thereby improving the efficiency of the memory device and reducing power consumption.

The memory device of the present invention includes a memory cell array, a temporary storage unit, and a command generator. The memory cell array includes a plurality of memory cells. The temporary storage unit is used to record multiple customized information. The instruction generator is coupled to the temporary storage unit and the memory cell array. The instruction generator receives the custom command and performs at least two memory operations on the memory cell array according to the received custom command and the customized information. Custom information is generated based on the at least two memory operations described.

The memory device operating method of the present invention is applicable to a memory device including a memory cell array and a temporary storage unit. The method of operating the memory device includes the following steps. Write multiple custom messages to the scratchpad unit. Receive custom commands. Perform at least two memory operations on the memory cell array based on the received custom commands and custom information. Custom information is generated based on the at least two memory operations described.

Based on the above, in the embodiment of the present invention, a plurality of customized information is recorded in a temporary storage unit of the memory device, and the memory device operation method can be customized according to the memory device when receiving a custom command. Commands and custom information to perform at least two memory operations. According to this, the access efficiency of the memory device can be improved and the power consumption can be reduced.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic block diagram of a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1 , the memory device 100 of the embodiment includes a temporary storage unit 110 , an instruction generator 120 , and a memory cell array 130 . In this embodiment, the temporary storage unit 110 is, for example, a mode register (MR) in which a plurality of custom information UD_INFO are recorded. The command generator 120 is, for example, a state machine, driven by the clock of the system to access the memory cell array according to the received custom command UD_CMD and the custom information UD_INFO recorded in the temporary storage unit 110. 130 performs at least two memory operations.

For example, after the memory device 100 is powered on, for example, a state including initialization, idle, activation, or precharge may be experienced, wherein the idle state may enter. Mode Register Set (MRS) status. In an embodiment, the customized information UD_INFO may be written to the temporary storage unit 110 in this MRS state, for example. If the instruction generator 120 receives the custom command UD_CMD, at least two memory operations can be performed on the memory cell array 130 according to the custom information UD_INFO in the temporary storage unit 110. Hereinafter, the memory device 100 of the present invention will be exemplified by the memory device 100 of FIG.

2 is a schematic diagram of customized information according to an embodiment of the present invention. Referring to FIG. 2, the customized information UD_INFO of the embodiment is recorded in the temporary storage unit 110 by the user to define information for the memory device 100 to perform the memory operation. In this embodiment, the customized information UD_INFO includes command flow information 210, address increment information 220, start address information 230, and loop information 240. However, the invention is not limited thereto. In other embodiments, the information included in the custom information UD_INFO can be adjusted according to different requirements, so that when the memory device 100 receives the custom command UD_CMD, the memory device 100 can execute according to the customized information UD_INFO. At least two memory operations are required.

In the present embodiment, the command flow information 210 includes command information CMD1 to CMD3 and delay information DL1 to DL3 for providing operation information for performing operations on the memory array 130. For example, the command information CMD1 to CMD3 are 1, 3, and 4, respectively, corresponding to three memory operations of activation (ACT), reading (RD), and pre-charging (PRE). The delay information DL1 to DL3 correspond to 0 clock cycles (CK), which respectively represent the time required to delay the memory specification itself after the memory operation of the corresponding command information CMD1 to CMD3 is executed. Extra delay time. In detail, the command information CMD1 and CMD2 are, for example, memory operations corresponding to activation and reading, respectively. Usually, after the memory device 100 performs the activation operation, at least the column controller to row controller transmission delay (RAS# to CAS# Delay, T _RCD ) is required to continue receiving the read command to perform the read operation. The custom information UD_INFO of the embodiment further defines the delay information DL1, so that the memory device 100 continues to perform the corresponding read operation after the delay of the T _RCD and the customized DL1 after executing the command information CMD1 corresponding to the activation operation. Command information CMD2 to increase the stability of the memory device.

In this embodiment, the start address information 230 includes a start column address RA_INI, a start row address CA_INI, and a start block address BA_INI. The start address information 230 is used to point to one of a plurality of memory cells of the memory cell array 130. After the command generator 120 receives the custom command UD_CMD, the memory cell pointed to by the memory cell array 130 or the start address information 230 is started according to the custom command UD_CMD and the custom information UD_INFO recorded in the temporary storage unit 110. At least two memory operations corresponding to the command flow information 210 are executed. For convenience of explanation, the memory cell corresponding to the start address information 230 is hereinafter referred to as a first memory cell.

3 is a schematic diagram of a conventional method of operating a memory device. Please refer to Figure 3. Generally, when the memory device wants to write a data to the column address, the row address, and the block address of the first memory cell of RA_INI, CA_INI, and BA_INI, for example, the clock cycle T1, first from the memory The body controller receives the active (ACT) memory command and provides the block address BA_INI and the column address RA_INI. After receiving the activation memory command, at least the column controller to the row controller transmits the delay T _RCD , and then receives the read (READ) memory provided with the row address CA_INI from the memory controller at the clock cycle T6. command. After receiving the read memory command, at least the read delay (Read Latency, RL) is passed, so that the clock period T11 starts to read the data D1 to D8 from the first memory cell. On the other hand, after receiving the read memory command, at least the internal read to precharge command delay (Read to Precharge Time, T _RTP ), and then receive the precharge (PRE) from the memory controller at the clock cycle T10. Command to perform a precharge operation. As such, in the example of FIG. 3 above, the memory device includes at least three memory command transmissions.

4 is a schematic diagram of a method of operating a memory device according to an embodiment of the invention. Referring to FIG. 4, the embodiment of the present invention defines a custom information UD_INFO including command flow information 210 and start address information 230 in the temporary storage unit 110 of the memory device 100, wherein the customized information UD_INFO is activated and read. Take and precharge three memory operations to generate. Accordingly, in the present embodiment, after the command generator 120 receives the custom command UD_CMD from the external (for example, the memory controller) after the clock cycle T1, according to the command flow information 210, the corresponding command information CMD1 is first executed. Activate memory operation. Subsequently, after the column controller to row controller transmission delay T _RCD , the delay time corresponding to the delay information DL1, and the read delay RL, the instruction generator 120 starts performing a read operation on the first memory cell. On the other hand, after receiving the custom command UD_CMD, the delay time corresponding to the column controller to the row controller transmission delay T _RCD , the delay information DL1 (0 in this embodiment), and the internal read precharge After the delay time corresponding to the command delay T _RTP and the delay information DL2 (0 in this embodiment), the instruction generator 120 starts performing a precharge operation on the memory cell array 130.

Compared with the memory device operating method in FIG. 3, the memory device 100 in the embodiment of FIG. 4 includes only one custom command UD_CMD transmission, and the data of D1 to D8 can be read from the first memory cell. And all the memory operations in the example of Figure 3 are executed. In addition, in the embodiment, after the pre-charging operation is performed on the memory cell array 130, the instruction generator 120 can pass the column pre-charge time (T _RP ) and the delay time corresponding to the delay information DL3. Perform the next memory operation again.

By using the memory device operating method of the embodiment of the present invention, the command flow information 210 and the start address information 230 are defined in the custom information UD_INFO and recorded in the temporary storage unit 110, and the command generator 120 receives the After the custom command UD_CMD, it is possible to perform at least two memory operations on the memory cell array 130. It is worth mentioning that, in some cases, the user is more likely to repeatedly perform the memory operation corresponding to the command flow information 210. Therefore, in the embodiment, the address increment information 220 and the loop information 240 are further defined in the custom information UD_INFO.

Please refer to Figure 2 again. In this embodiment, the address increment information 220 includes a column increment information RS, a row increment information CS, and a block increment information BS, and the loop information 240 includes a loop number LP. The loop number LP is used to indicate the number of repetitions of the memory operation performed on the memory cell array 130 in accordance with the command flow information 210, and the address increment information 220 is used to determine the memory cell to be operated as the operation object when the memory operation is repeated. For example, the number of repetitions corresponding to the number of loops LP is, for example, two times, and the column increment information RS, the row increment information CS, and the block increment information BS all correspond to N=N+1. Accordingly, the instruction generator 120 performs at least two of the first memory cells of the RA_INI, CA_INI, and BA_INI for the column address, the row address, and the block address according to the start address information 230, according to the command flow information 210. After the memory operation, the memory cells of the column address, the row address, and the block address are RA_INI+1, CA_INI+1, and BA_INI+1, respectively, and at least two memory operations are performed according to the command flow information 210 again. .

In this embodiment, by further defining the address increment information 220 and the loop information 240 in the custom information UD_INFO, the command generator 120 may receive the custom command UD_CMD according to the start address information 230, the bit. The address increment information 220 and the loop information 240 are used to sequentially execute at least two memory operations corresponding to the command flow information 210 for at least one of the memory cells 130.

It is worth mentioning that the command comparison table, the delay comparison table, the address increment comparison table, and the loop comparison table in the customized information UD_INFO of the embodiment of FIG. 2 are used to facilitate the corresponding command flow information 210 and the address increment information 220. And the content represented by each digit in the loop information 240, but the present invention does not limit the representation of the custom information UD_INFO. In addition to using the above-mentioned comparison tables, in other embodiments, those having ordinary knowledge in the art can record the customized information UD_INFO in other manners according to different needs.

In the present embodiment, the memory operation includes, for example, activation, reading, and pre-charging, but the present invention is not limited thereto. In other embodiments, the memory operation may be, for example, a memory such as NO OPERATION, ACTIVATE, READ, WRITE, PRECHARGE, and POWER DOWN. One of the body operations.

On the other hand, in the present embodiment, the command information CMD1 to CMD3 correspond to, for example, different memory operations, respectively. However, the present invention is not limited thereto, and in another embodiment, the command information CMD1 to CMD3 may, for example, correspond to the same memory operation. Hereinafter, another embodiment of the present invention will be described, detailing a method of operating a memory device according to an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of a memory device according to an embodiment of the invention. FIG. 6 is a flow chart showing a method of operating a memory device according to an embodiment of the invention. Referring to FIG. 5 , the memory device 100 of the embodiment includes a temporary storage unit 110 , an instruction generator 120 , and a memory cell array 130 , and further includes a detecting unit 140 , a signal decoder 150 , and a plurality of multiplexers 161 and 163 . . It is worth mentioning that the instruction generator 120 of the present embodiment includes a custom command generator 121 and a custom address generator 123. The signal decoder 150 includes a command decoder 151 and an address decoder 153.

Please refer to FIG. 5 and FIG. 6 at the same time. In step S610, the memory device 100 writes a plurality of pieces of custom information UD_INFO in the temporary storage unit 110. In this embodiment, the step of writing the custom information UD_INFO to the temporary storage unit 110 further includes steps S611 to S615. In step S611, the memory device 100 can receive a signal, for example, from the outside. In step S613, the detecting unit 140 detects whether the received signal is a write signal corresponding to at least one of the custom information UD_INFO. If the received signal is a write signal corresponding to at least one of the custom information UD_INFO, in step S615, at least one custom information UD_INFO corresponding to the write signal is recorded in the temporary storage unit 110 according to the write signal. in. In this embodiment, the write signal corresponding to at least one of the custom information UD_INFO may be, for example, a write signal defined by the user. Therefore, steps S611 to S615 can be performed, for example, several times to record the custom information UD_INFO required by all users.

For example, the memory device 100 can receive a write signal corresponding to the command flow information 210, for example, from the outside, and the command flow information 210 includes at least two command information and at least one delay information. After the detecting unit 140 detects that the received write signal corresponds to the command flow information 210, the command flow information 210 can be written into the temporary storage unit 110 according to the write signal. In addition to this, the memory device 100 can receive another write signal corresponding to the loop information 240, for example, from the outside. After the detecting unit 140 detects that the received write signal corresponds to the loop information 240, the loop information 240 can be written into the temporary storage unit 110 according to the write signal. However, the present invention does not limit the content of the custom information UD_INFO corresponding to the write signal. That is to say, the write signal in this embodiment may be, for example, one or a combination of command flow information, start address information, address increment information, and loop information. In other embodiments, those skilled in the art can define a write signal corresponding to different customized information according to their needs.

After the custom information UD_INFO is recorded to the temporary storage unit 110, the instruction generator 120 receives the custom command UD_CMD in step S620. In the present embodiment, the custom command UD_CMD is generated by the user by at least one hot key and transmitted to the command generator 120 through the memory controller, but the present invention is not limited thereto. In other embodiments, the custom command UD_CMD may also be, for example, a trigger signal defined as any other type.

Once the instruction generator 120 receives the custom command UD_CMD, it proceeds to step S630. In step S630, the instruction generator 120 performs at least two memory operations on the memory cell array 130 according to the received custom command UD_CMD and the custom information UD_INFO in the temporary storage unit 110. In the embodiment, the multiplexer 161 is coupled to the custom command generator 121 and the command decoder 151, and the multiplexer 163 is coupled to the custom address generator 123 and the address decoder 153. When the instruction generator 120 receives the custom command UD_INFO, the multiplexer 161 switches to cause the custom command generator 121 to issue a command to the memory cell array 130 according to the command flow information 210, and the multiplexer 163 switches to enable The custom address generator 121 provides address information to the memory cell array 130 based on the address increment information 220, the start address information 230, and the loop information 240. In this embodiment, the manner in which the instruction generator 120 performs at least two memory operations on the memory cell array 130 according to the received custom command UD_CMD and the custom information UD_INFO in the temporary storage unit 110 is in the foregoing embodiment. Detailed description will not be repeated here.

Returning to step S613, if the received signal is not a write signal corresponding to at least one of the custom information UD_INFO, then step S640 is reached. In step S640, the signal decoder 150 decodes the received signal to obtain a decoding result. Then, in step S650, a single memory operation corresponding to the received signal is performed on the memory cell array 130 according to the decoding result. In this embodiment, the signal decoded by the signal decoder 150 may be, for example, an external signal including a single memory operation, and the decoding result includes a memory command and address information. The command decoder 151 decodes the external signal to obtain its corresponding memory command. The multiplexer 161 switches to cause the command decoder 151 to perform a corresponding single memory operation on the memory cell array 130 in accordance with the memory command. On the other hand, the address decoder 153 decodes the external signal to obtain the address information corresponding thereto. The multiplexer 163 switches to cause the address decoder 153 to provide the memory cell array 130 in accordance with the address information to cooperate with the single memory operation described above.

In other words, in the present embodiment, a plurality of custom information UD_INFOs are recorded in the temporary storage unit 110. If the memory device 100 receives the external signal corresponding to the operation of the single memory and does not receive the custom command UD_CMD as the trigger signal, the memory cell array 130 is executed according to the decoded result decoded by the external signal. Single memory operation. In particular, if the command generator 120 of the memory device 100 receives the custom command UD_CMD as the trigger signal, the memory cell array 130 is executed according to the custom command UD_CMD and the custom information UD_INFO recorded in the temporary storage unit 110. At least two memory operations.

It is worth mentioning that, in the third generation double data rate synchronous dynamic random access memory (DDR3 SDRAM), when receiving an external signal corresponding to a read operation from the memory controller, it is readable. The data length is 8 bits, that is, the Burst Length (BL) is 8. However, the three command information CMD1 to CMD3 included in the command flow information 210 in this embodiment correspond to the read operation RD. Therefore, when the user wants to read 24 bits of data from the memory device 100, only one custom command UD_CMD needs to be transferred to the command generator 120 of the memory device 100, so that three readings can be performed in sequence. Take the operation to read the data of 24 bits. In other words, the custom command UD_CMD of the embodiment of the present invention can perform two or more identical memory operations on the memory cell array 130 in sequence.

In addition, the custom command of the embodiment of the present invention corresponds to custom information, and the present invention does not limit the number of custom commands. In other embodiments, the temporary storage unit may also record, for example, a plurality of sets of customized information, wherein each group of customized information includes command flow information, address increment information, start address information, and loop information. And performing at least two memory operations on the memory cell array according to the received custom command type as a basis for selecting one of the customized information. For example, the temporary storage unit records, for example, the first customized information and the second customized information. When the user generates the first custom command by inputting the hotkey combination, and the command generator receives the first custom command, the memory cell array is determined according to the first custom information recorded in the temporary storage unit. Perform at least two memory operations corresponding to the first custom information. On the other hand, when the command generator receives the second custom command from the host system, performing at least the second custom information corresponding to the memory cell array according to the second custom information recorded in the temporary storage unit. Two memory operations.

In summary, the memory device and the memory device operating method provided by the embodiments of the present invention record the customized information in the temporary storage unit of the memory device, and trigger the memory device when receiving the custom command. At least two memory operations are performed on the memory cell array of the memory device based on the received custom command and the custom information recorded in the temporary storage unit. According to this, the number of instruction transmissions can be saved to reduce the power consumption of the system.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100: memory device 110: temporary storage unit 120: command generator 121: custom command generator 123: custom address generator 130: memory cell array 140: detection unit 150: signal decoder 151: command decoder 153: address decoder 161, 163: multiplexer 210: command flow information 220: address increment information 230: start address information 240: loop information ACT, WR, RD, PRE, PREA, PD, PRE: Memory command BA_INI: Block start information BS: Block increment information CA_INI: Line start information CK: Clock cycle CMD1, CMD2, CMD3: Command information CS: Line increment information D1, D2, D3, D4, D5, D6, D7, D8: Data DL1, DL2, DL3: Delay information LP: Number of loops RA, CA, BNK: Address information RA_INI: Column start information RL: Read delay RS: Column increment information S610, S611, S613 , S615, S620, S630, S640, S650: steps of the memory device operation method T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15: clock period t _RCD: to row controller column controller propagation delay t _RTP: internal read command to precharge delay UD_CMD: Custom Command UD_INFO: Custom Information

1 is a schematic block diagram of a memory device in accordance with an embodiment of the present invention. 2 is a schematic diagram of customized information according to an embodiment of the present invention. 3 is a schematic diagram of a conventional method of operating a memory device. 4 is a schematic diagram of a method of operating a memory device according to an embodiment of the invention. FIG. 5 is a schematic structural diagram of a memory device according to an embodiment of the invention. FIG. 6 is a flow chart showing a method of operating a memory device according to an embodiment of the invention.

S610, S611, S613, S615, S620, S630, S640, S650: steps of the method of operating the memory device.

Claims (20)

A memory device includes: a memory cell array including a plurality of memory cells; a temporary storage unit for recording a plurality of custom information; and an instruction generator coupled to the temporary storage unit and the memory cell array The instruction generator receives a custom command, and performs at least two memory operations on the memory cell array according to the custom command and the customized information, wherein each of the customized information is based on at least two Memory operations are produced. The memory device of claim 1, further comprising: a detecting unit configured to receive a write signal and detect whether the write signal corresponds to at least one of the customized information If the write signal corresponds to at least one of the customized information, the corresponding at least one custom information is recorded in the temporary storage unit according to the write signal. The memory device of claim 1, further comprising: a signal decoder for receiving and decoding an external signal, and performing the external signal on the memory cell array according to a decoding result of the signal decoder Corresponding single memory operation. The memory device of claim 1, wherein the temporary storage unit is a mode register, and at least one of the customized information is in a mode register setting state of the memory device. Write to this mode register. The memory device of claim 1, wherein the customized information comprises at least two command information and at least one delay information, wherein each of the command information corresponds to a memory operation. The memory device of claim 5, wherein the custom information further includes a loop information, wherein the command generator repeatedly performs the command information corresponding to the memory cell array according to the loop information. The memory operations. The memory device of claim 6, wherein the customized information further includes a start address information and an address increment information, wherein the command generator is based on the start address information, the address The incremental information and the loop information sequentially operate at least one of the memory cells in the memory cell array. The memory device of claim 1, wherein the at least two memory operations performed include a first memory operation and a second memory operation, and the first memory operation is the same as the The second memory operates. The memory device of claim 1, wherein the memory gymnastics is one of no operation, activation, reading, writing, pre-charging, and power saving. The memory device of claim 1, wherein the custom command is generated by at least one hot key. A memory device operating method is applicable to a memory device, wherein the memory device includes a memory cell array and a temporary storage unit, and the memory device operating method includes: Writing a plurality of customized information to the temporary storage unit; receiving a custom command; and performing at least two memory operations on the memory cell array according to the custom command and the customized information, wherein each of the customized information They are generated based on at least two memory operations, respectively. The method for operating a memory device according to claim 11, wherein the step of writing the customized information to the temporary storage unit comprises: receiving a write signal; detecting whether the write signal corresponds to the At least one of the custom information; and if the write signal corresponds to at least one of the custom information, the at least one custom information corresponding to the write signal record is recorded in the temporary storage unit. The method for operating a memory device according to claim 11, further comprising: receiving and decoding an external signal to obtain a decoding result; and performing a single memory corresponding to the external signal to the memory cell array according to the decoding result. Body operation. The method for operating a memory device according to claim 11, wherein the temporary storage unit is a mode register, and at least one of the customized information is in a mode register of the memory device. The setup status is written to this mode register. The method for operating a memory device according to claim 11, wherein the step of writing the customized information to the temporary storage unit comprises: writing at least two command information and at least one delay information to the temporary storage unit , wherein each of the command information corresponds to a memory operation. The method for operating a memory device according to claim 15, wherein the step of writing the customized information to the temporary storage unit further comprises: writing a loop information to the temporary storage unit, wherein Defining the command and the custom information to perform the at least two memory operations on the memory cell array, comprising: repeating, by the loop information, the at least two corresponding to the at least two command information of the memory cell array Memory operation. The method for operating a memory device according to claim 16, wherein the step of writing the customized information to the temporary storage unit further comprises: writing a start address information and an address increment information to the temporary And the storing unit, wherein the performing the at least two memory operations on the memory cell array according to the custom command and the customized information comprises: updating the information according to the start address information, the address, and the loop information The at least two memory operations are performed on the at least one memory cell in the memory cell array in sequence. The method for operating a memory device according to claim 11, wherein the step of performing the at least two memory operations on the memory cell array according to the custom command and the customized information comprises: according to the custom command And the custom information, sequentially the memory cell array The column performs a first memory operation and a second memory operation, wherein the first memory operation is the same as the second memory operation. The memory device operating method according to claim 11, wherein the memory gymnastics is one of no operation, activation, reading, writing, pre-charging, and power saving. The method of operating a memory device according to claim 11, wherein the custom command is generated by at least one hot key.