JP2014220025A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing unnecessary operation delays.SOLUTION: A semiconductor device comprises: a plurality of memory cells retaining data; and sense amplifiers amplifying the data read from the respective memory cells. The plurality of memory cells include: a memory section divided into blocks each including a plurality of memory cells sharing one sense amplifier; a command decoder receiving commands from a controller that transmits commands for instructing the memory cells to operate; and a timing adjustment unit receiving address information for identifying a memory cell instructed by the command from the controller to operate, determining whether a latest memory cell that is the memory cell identified by the latest received address information and a previous memory cell that is the memory cell identified by the previously received address information are included in the same block, and adjusting timing at which the controller transmits the commands based on the determination result.

Description

  The present invention relates to a semiconductor device.

  A semiconductor device typified by a DRAM (Dynamic Random Access Memory) operates in accordance with a command issued by a control device. For example, in a DRAM, commands include a precharge command for storing charge in a memory cell and setting the memory cell array in a predetermined precharge state, a read command for instructing reading of data stored in the memory cell, and a command to the memory cell. There is a write command for instructing data writing. The command includes an active command that activates each bank when a memory cell array including a plurality of memory cells is divided into a plurality of banks. These commands are normally issued in association with address information specifying a memory cell or bank to be operated.

  In such a semiconductor device, if the next command is received before the operation corresponding to the previous command is completed, the target memory cell cannot be accessed with the next command, and the semiconductor device is normally operated. May not work. For this reason, in the semiconductor device, the minimum interval for issuing a command is determined so that the next command is issued after the operation corresponding to each command is completed.

  For example, as a minimum interval for issuing a command, a minimum interval tWR from issuing a write command Wrt to issuing a precharge command Pre, a minimum interval from issuing a precharge command Pre to issuing an active command Act The minimum interval tRCD from the issuance of tRP, the active command Act to the issuance of the first write command Wrt or the read command Red is determined.

  Since the operation time required to complete the operation varies from operation to operation, the minimum interval for issuing a command is usually an interval equal to or longer than the operation time of the operation corresponding to the command, depending on the type of the previously issued command. Determined.

  The operation time is held in the mode register as mode information, for example. Patent Document 1 discloses a semiconductor device including a mode register that holds CAS (Column Address Strobe) latency indicating operation time from when a semiconductor device receives a read command until data is actually output as mode information. Has been. Although not disclosed in Patent Document 1, as other mode information, there is a CAS write latency indicating a time from when a write command is received until data is actually written into a memory cell.

JP 2009-181638 A

  However, the present inventor has clarified that an unnecessary operation delay may be caused when a minimum interval for issuing a command is determined according to an operation time. Hereinafter, the cause of unnecessary operation delay will be described.

  Usually, the minimum interval for issuing commands is set to a uniform value according to the type of command issued first. However, the problem that the semiconductor device does not operate normally does not always occur when the next command is received before the operation corresponding to the previous command is completed. Even while the operation corresponding to the previous command is not completed, the semiconductor device operates normally if the memory cell targeted by the next command can be accessed.

  A semiconductor device cannot simultaneously access a plurality of memory cells that share a sense amplifier that amplifies data read from the memory cell, but can simultaneously access a plurality of memory cells that do not share a sense amplifier. Can be accessed.

  Therefore, when the memory cell array is divided into blocks including a plurality of memory cells sharing a sense amplifier, the sense amplifier is shared for the plurality of memory cells included in the same block. Because of this possibility, the semiconductor device may not be able to access those memory cells simultaneously. On the other hand, since the sense amplifier is not shared for a plurality of memory cells included in different blocks, the semiconductor device can simultaneously access these memory cells.

  Therefore, when the memory cell whose operation is instructed by the previous command and the memory cell whose operation is instructed by the next command are included in different blocks, the operation according to the previous command is actually performed. Even if the next command is issued before it is completed, the semiconductor device operates normally, but later commands are issued after an interval equal to or longer than the operation time, causing an unnecessary operation delay.

The semiconductor device of the present invention is
A plurality of memory cells that hold data; and a sense amplifier that amplifies data read from each of the memory cells, wherein the plurality of memory cells are arranged in a block including a plurality of memory cells that share the sense amplifier. A divided memory section; and
A command decoder that receives the command from a control device that issues a command for instructing an operation on the memory cell;
The address information specifying the memory cell whose operation is instructed by the command is received from the control device, and the memory cell specified by the recently received address information and the address information received last time are specified. A timing adjustment unit that determines whether or not a previous memory cell that is a memory cell is included in the same block, and that adjusts a timing at which the control device issues the command based on the determination result; .

The semiconductor device of the present invention is
A plurality of memory cell blocks each including a plurality of memory cells, each accessed by different address information;
A detection circuit for holding first address information corresponding to the memory cell block selected in the second access received one before the first access;
In the detection circuit, the second address information corresponding to the memory cell block selected in the first access matches the first address information, and the first access is predetermined from the second access. The detection signal is set to the first value when the period has not elapsed.

  According to the present invention, in a semiconductor device having a memory unit divided into a plurality of blocks including a plurality of memory cells sharing a sense amplifier, a command for instructing an operation on the memory cell and a memory in which the operation is instructed by the command The latest memory cell, which is the memory cell specified by the recently received address information, and the previous memory cell, which is the memory cell specified by the previously received address information, are received in the same block. Whether or not it is included is determined, and the timing of issuing the command is adjusted based on the determination result.

  As a result, when the memory cell specified by the address information does not share the sense amplifier, the next command can be issued without waiting for the operation corresponding to the previous command to be completed, which is unnecessary. It becomes possible to reduce the operation delay.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows arrangement | positioning of the bank and array in the memory part of FIG. It is a figure which shows the structure in the array of FIG. It is a figure which shows the detailed structure in the block of FIG. FIG. 2 is a diagram illustrating a configuration of an address comparison circuit in the timing adjustment unit of FIG. 1. 6 is a flowchart for explaining the operation of the address comparison circuit of FIG. It is a figure which shows the structure of the timer circuit in the timing adjustment part of FIG. 8 is a flowchart for explaining the operation of the timer circuit of FIG. 2 is a timing chart for explaining operation timings in a first operation pattern of the semiconductor device of FIG. 1. 6 is a timing chart for explaining operation timings in a second operation pattern of the semiconductor device of FIG. 1. 6 is a timing chart for explaining operation timings in a third operation pattern of the semiconductor device of FIG. 1. It is a figure which shows the structure of the timer circuit of the semiconductor device concerning the modification of the 1st Embodiment of this invention. 13 is a flowchart for explaining the operation of the timer circuit of FIG. 13 is a timing chart for explaining an operation timing in a fourth operation pattern of the semiconductor device having the timer circuit of FIG. 13 is a timing chart for explaining operation timings in a fifth operation pattern of the semiconductor device having the timer circuit of FIG. 13 is a timing chart for explaining operation timings in a sixth operation pattern of the semiconductor device having the timer circuit of FIG. It is a figure which shows the structure of the semiconductor device concerning the 2nd Embodiment of this invention. It is a figure which shows the structure of the timer circuit in the timing adjustment part of FIG. 18 is a timing chart for explaining the operation timing of the semiconductor device of FIG. It is a figure which shows the structure of the timing adjustment part of the semiconductor device concerning the modification of the 2nd Embodiment of this invention. FIG. 21 is a timing chart for explaining operation timings of the semiconductor device having the timing adjustment unit of FIG. 20. FIG. It is a figure which shows the structure of the computer system concerning the 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in this specification and drawing, the description which overlaps may be abbreviate | omitted by attaching | subjecting the same code | symbol about the component which has the same function.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention. A semiconductor device 100 shown in FIG. 1 is a semiconductor memory device, and more specifically a DRAM.

  The semiconductor device 100 operates in response to a command issued by an external control device (not shown). Further, the semiconductor device 100 specifies a memory cell whose operation is instructed by the command based on address information issued in association with the command by the control device, and performs the operation indicated by the command on the specified memory cell.

  The timing at which the control device issues a command is adjusted based on information output from the semiconductor device 100 to the control device. Hereinafter, the overall configuration of the semiconductor device 100 will be described with reference to FIG. 1, and then the detailed configuration of the memory unit that stores data in the semiconductor device 100 will be described with reference to FIGS. A detailed configuration of the timing adjustment unit that adjusts the timing at which the apparatus issues a command will be described with reference to FIGS.

  A semiconductor device 100 illustrated in FIG. 1 includes a memory unit 101, a clock terminal group 102, a clock generation circuit 103, and a mode register 104. The semiconductor device 100 also includes a command terminal group 105, a command decoder 106, a chip control circuit 107, an RW amplifier 108, a latch circuit 109, a data input / output buffer 110, a bank BK and a row address buffer 111, a column An address buffer 112 and a timing adjustment unit 113 are included.

  The memory unit 101 includes a memory cell array 121 in which a plurality of memory cells holding stored data are arranged in an array, a column decoder 122 and a row decoder 123 that select memory cells based on address information, an array control circuit 124, Have A more detailed configuration of the memory unit 101 will be described later.

  Clock terminal group 102 receives external clock signals CK and / CK and clock enable signal CKE.

  In the present specification, a signal having “/” at the beginning of the reference sign means a complementary signal of the signal of the same name without having “/” added at the beginning of the reference sign. In other words, if a signal without “/” is a high active signal, a signal with “/” is an inverted signal of a signal without “/” or a low active signal. is there.

  Clock generation circuit 103 receives external clock signals CK and / CK and clock enable signal CKE from clock terminal group 102, and generates internal clock signal ICLK using external clock signals CK and / CK and clock enable signal CKE. To do. The clock generation circuit 103 outputs the generated internal clock signal ICLK to the mode register 104, the command decoder 106, the chip control circuit 107, the latch circuit 109, the data input / output buffer 110, and the timing adjustment unit 113. Each unit receiving the internal clock signal ICLK operates in synchronization with the internal clock signal ICLK.

  The mode register 104 is a circuit in which operation parameters of the semiconductor device 100 are set. The operation parameters set in the mode register 104 are, for example, a burst length and CAS latency. The mode register 104 outputs the set operation parameter to the chip control circuit 107.

  The command terminal group 105 receives a command from an external control device that issues a command for instructing the operation to the memory unit 101.

  The command decoder 106 receives a command from the command terminal group 105 and generates an internal command signal by holding, decoding, and counting the command. The command decoder 106 outputs the generated internal command signal to the chip control circuit 107 and the timing adjustment unit 113.

  The chip control circuit 107 is a circuit that controls operations on the memory unit 101. The chip control circuit 107 receives the internal command signal output from the command decoder 106 and the mode information held in the mode register, and instructs the operation of the memory unit 101 based on the received internal command signal and mode information. Specifically, the chip control circuit 107 instructs the RW amplifier 108, the latch circuit 109, the bank BK and row address buffer 111, the column address buffer 112, and the array control circuit 124 about the operation content and operation timing. The operation of the memory unit 101 is controlled.

  An RW (Read Write) amplifier 108 amplifies data to be written to the memory unit 101 and data read from the memory unit 101. The RW amplifier 108 amplifies data to be written in the memory unit 101 and outputs the amplified data to the memory unit 101, amplifies data read from the memory unit 101, and outputs the amplified data to the latch circuit 109.

  The latch circuit 109 temporarily stores data to be written to the memory unit 101 and data read from the memory unit 101.

  The data input / output buffer 110 receives data to be input to the memory unit 101 from the input / output terminal group DQ and outputs the data to the latch circuit 109. Output.

  Bank BK and row address buffer 111 temporarily store the bank address and row address included in the address information issued by the control device, and output the stored bank address and row address to array control circuit 124.

  The column address buffer 112 temporarily stores the column address included in the address information issued by the control device, and outputs the stored column address to the column decoder 122.

  The timing adjustment unit 113 receives address information issued by the control device and an internal command signal output by the command decoder 106. Further, the timing adjustment unit 113 compares the latest address information, which is address information recently received from the control device, with the previous address information, which is address information received last time. Based on this comparison, the timing adjustment unit 113 determines whether the latest memory cell that is the memory cell specified by the latest address information and the previous memory cell that is the memory cell specified by the previous address information are included in the same block. Judge whether or not. The timing adjustment unit 113 adjusts the timing at which the control device issues a command based on the determination result. Details of the timing adjustment unit 113 will be described later.

  Here, a detailed configuration of the memory unit 101 will be described.

  FIG. 2 is a diagram showing the arrangement of banks and arrays in the memory unit 101 of FIG.

  In the present embodiment, the memory unit 101 is divided into four banks BK. Each bank BK is selected by bank addresses BA1 and BA0. When the bank address value is (BA1, BA0 = 0, 0), the bank BK0 is selected. When the value of the bank address is (BA1, BA0 = 0, 1), the bank BK1 is selected. When the value of the bank address is (BA1, BA0 = 1, 0), the bank BK2 is selected. When the bank address value is (BA1, BA0 = 1, 1), the bank BK3 is selected.

  Each bank BK is divided into two areas. Two rows of row decoders are arranged at the center of each area, and column decoders are arranged at the center of each area in a direction perpendicular to the longitudinal direction of the row decoder. . An array is arranged in each of the four areas divided by the row decoder and the column decoder. Therefore, eight arrays are included in one bank BK.

  FIG. 3 is a diagram showing a configuration in the array 0 of FIG.

  One array is divided into four blocks. Since one bank BK includes eight arrays, one bank BK is divided into 32 blocks. Each block is selected by block addresses X14 to X10 composed of 5-bit row addresses. For example, block 0 is selected when the values of block addresses X14 to X10 are 0, 0, 0, 0, 0. Each block is provided with a row decoder for selecting a word line and a sense amplifier for amplifying a signal read from the memory cell selected by the word line to the bit line.

  FIG. 4 is a diagram showing a detailed configuration in the block of FIG.

  In one block, the word line WL and the bit line pair BLP are arranged in an orthogonal direction, and the memory cell MC is arranged at a predetermined intersection between the word line WL and the bit line BLP. The bit line pairs BLP are alternately connected to sense amplifiers SA arranged on both sides of the block. Each block is a memory cell block that includes a plurality of memory cells and is accessed by different address information.

  Returning to the description of FIG.

  The column decoder 122 receives the column addresses Y9 to Y0 included in the address information issued by the control device, and selects one of the 1024 column selection lines YS based on the column addresses Y9 to Y0. The column selection line YS is selectively connected to the sense amplifier SA and the I / O. When the column selection line YS is selected, the bit line pair BLP is selected via the sense amplifier SA connected to the column selection line YS.

  The array control circuit 124 receives row addresses X14 to X0 included in the address information issued by the control device. The row addresses X14 to X0 include block addresses X14 to X10 that specify blocks, and the array control circuit 124 selects one of a plurality of blocks using the block addresses X14 to X10, and the remaining addresses Row addresses X 9 to X 0 are output to the row decoder 123.

  The row decoder 123 selects one of the 1024 word lines WL based on the row address.

  When the word line WL and the bit line pair BLP are selected, the memory cell MC arranged at a predetermined intersection between the selected word line WL and the bit line pair BLP is selected.

  When reading the storage data held in the memory cell MC, the storage data held in the selected memory cell MC is read out to the bit line BL and input to the sense amplifier SA in response to the read command. The stored data input to the sense amplifier SA is amplified and output to the R / W amplifier 108 via the I / O line connected to the sense amplifier SA.

  When the storage data is written to the memory cell MC, the data input to the memory unit 101 via the R / W amplifier 108 and the I / O line is selected via the sense amplifier SA according to the write command. Data is written in the memory cell MC.

  A detailed configuration of the timing adjustment unit 113 will be described with reference to FIGS. The timing adjustment unit 113 includes an address comparison circuit 131 and a timer circuit 132. FIG. 5 is a diagram showing a configuration of the address comparison circuit 131 in the timing adjustment unit 113 of FIG.

  The timing adjustment unit 113 includes four address comparison circuits 131 corresponding to each bank BK.

  Each address comparison circuit 131 receives a bank active signal ACT that takes a high level value when receiving an active command Act for the corresponding bank BK and a precharge command Pre for the corresponding bank BK. The bank precharge signal PRE which sometimes takes a high level value and the block address included in the address information are received and controlled independently for each bank BK.

  Each address comparison circuit 131 has a block address register BLR for recording a block address. The block address register BLR is a block address at a timing when the take-in terminal S receiving the bank precharge signal PRE takes a high level value. Is recorded. Since the precharge command Pre is issued after the active command Act and address information are issued, the block address register BLR records the block address included in the address information issued in association with the active command Act. .

  FIG. 6 is a flowchart for explaining the operation of the address comparison circuit 131.

  The address comparison circuit 131 receives the bank active signal ACT and determines whether or not the value of the received bank active signal ACT is at a high level (step S100). If the value of the bank active signal ACT is at a low level, the address comparison circuit 131 repeats step S100 until the value of the bank active signal ACT becomes a high level.

  On the other hand, when the value of the bank active signal ACT is at a high level, the address comparison circuit 131 compares the block address stored in the block address register with the recently received block address (step S105).

  The address comparison circuit 131 determines whether or not the comparison result indicates that the block addresses match (step S110).

  If the comparison result indicates that the block addresses match, the address comparison circuit 131 sets the value of the match signal HIT to the high level (step S115).

  On the other hand, if the comparison result indicates that the block addresses do not match, the value of the match signal HIT is set to low level (step S120).

  When the value of the coincidence signal HIT is either high level or low level, the address comparison circuit 131 determines whether or not the value of the bank precharge signal PRE is high level (step S125). If the value of the bank precharge signal PRE is at a low level, the address comparison circuit 131 repeats step S125 until the value of the bank precharge signal PRE becomes a high level.

  On the other hand, when the value of the bank precharge signal PRE is at a high level, the block address register BLR of the address comparison circuit 131 records the recently received block address (step S130).

  Thus, when the control device issues the active command Act, the address comparison circuit 131 provided corresponding to the bank BK specified by the address information issued in association with the active command Act is included in the address information. The block address and the block address stored in the block address register BLR are compared, and a match signal HIT indicating the comparison result is output. In the address comparison circuit 131, when the block addresses match, the value of the match signal HIT becomes a high level, and when they do not match, the value of the match signal HIT becomes a low level. In response to the precharge command Pre, the block address register BLR records the recently received block address. As a result, the timing adjustment unit 113 compares, for each bank BK, the latest address information issued in association with the currently received active command Act and the previous address information issued in association with the previously received active command Act. Thus, the coincidence signal HIT indicating whether or not the previous memory cell and the latest memory cell are included in the same block is output.

  FIG. 7 is a diagram showing a configuration of the timer circuit 132. As shown in FIG.

  The timing adjustment unit 113 includes four timer circuits 132 corresponding to the banks BK.

  Each timer circuit 132 receives a bank active signal ACT, a bank write signal WRT that takes a high level value when the timer circuit 132 receives a write command Wrt for the corresponding bank BK, and an internal clock signal ICLK. receive.

  Each timer circuit 132 has a timer that starts counting when the bank write signal WRT takes a high level value. The timer has an initial value CNT set according to the bank write signal WRT, and decrements and outputs the count value cnt every time it receives the internal clock signal ICLK. Each timer circuit 132 validates the output of the count value cnt according to the bank active signal ACT. Therefore, each timer circuit 132 outputs the count value cnt while the value of the bank active signal ACT is at a high level.

  In addition, the timer circuit 132 measures an elapsed time from the start of the operation for the previous memory cell. In the present embodiment, the timer circuit 132 is a tWR timer that counts the time from when the semiconductor device 100 receives the write command Wrt until it receives the active command Act. Each timer circuit 132 sets the initial value CNT to a value obtained by converting the time required for the semiconductor device 100 to write the memory cell into the number of clocks.

  The count values cnt0 to cnt3 output from each timer circuit 132 are connected for each bit and input to the first NOR gate 133 having n inputs. These input signals may be connected to a level keeper for maintaining the state (not shown). The output of the first NOR gate 133 is input to the second NOR gate 134. The second NOR gate 134 also receives a signal obtained by inverting the match signal HIT output from the address comparison circuit 131.

  FIG. 8 is a flowchart for explaining the operation of each timer circuit 132.

  The timer circuit 132 receives the bank write signal WRT and determines whether or not the value of the received bank write signal WRT is at a high level (step S200). When the value of the bank write signal WRT is at the low level, the timer circuit 132 repeats the determination in step S200.

  On the other hand, when the value of the bank write signal WRT is at the high level, the timer circuit 132 sets the initial value CNT of the tWR timer (step S205).

  The timer circuit 132 determines whether or not the value of the bank active signal ACT is at a high level (step S210). When the value of the bank active signal ACT is at the high level, the timer circuit 132 outputs the count value cnt (step S215). On the other hand, when the value of the bank active signal ACT is at a low level, the timer circuit 132 omits the operation of step S215.

  The timer circuit 132 determines whether the count value cnt is 0 (step S220). When the count value cnt is 0, the timer circuit 132 repeats Step S210 and Step S215.

  On the other hand, when the count value cnt is not 0, the timer determines whether or not the internal clock signal ICLK has been received (step S225). If the internal clock signal ICLK is not received, the timer waits until the internal clock signal ICLK is received.

  On the other hand, when the internal clock signal ICLK is received, the timer decrements the count value (step S230).

  Thus, each timer circuit 132 outputs count values cnt0 to 3 when the bank active signal ACT becomes high level for each bank BK.

  Note that the timer circuit 132 continuously and repeatedly determines whether or not the value of the bank write signal WRT is at a high level. Therefore, when the timer circuit 132 determines that the value of the bank write signal WRT is at a high level even while the operation of FIG. 8 is being performed, the timer circuit 132 stops the operation being executed and the process of step S205 Start operation. Thereby, every time the value of the bank write signal WRT becomes high level, the timer circuit 132 resets the count operation so far and executes the processing of step S205 and subsequent steps.

  Returning to the description of FIG.

  The timing adjustment unit 113 controls information for adjusting the timing at which the control device issues a command based on the coincidence signal HIT output from the address comparison circuit 131 and the count values cnt0 to 3 output from the timer circuits 132. RCD is output.

  Specifically, the timing adjustment unit 113 outputs control information RCD that indicates a minimum interval from a predetermined reference time point until a command is issued. In the present embodiment, the reference time point is a time point when the control device issues an active command Act.

  The first NOR gate 133 receives the count values cnt0 to cnt3 output from each timer circuit 132. When all these count values are 0, the first NOR gate 133 is high level, and when at least one count value is not 0, it is low level. A signal is output as the first input of the second NOR gate. A signal obtained by inverting the coincidence signal HIT is input to the second NOR gate. Note that the value of the coincidence signal HIT is either high level or low level. As a result, when the value of the coincidence signal HIT is high, the second input of the second NOR gate is low, and when the value of the coincidence signal HIT is low, the second input of the second NOR gate is high. Become a level.

  Further, the value of the control signal RCD is high when both the first input and the second input of the second NOR gate are low, and is low otherwise.

  A combination of the count value cnt and the coincidence signal HIT, a first input generated according to the count value, a second input generated according to the coincidence signal HIT, generated according to the first input and the second input The value of the control signal RCD is as shown in Table 1 below. In Table 1, H indicates that the value is high level, and L indicates that the value is low level.

  As described above, the timing adjustment unit 113 of the semiconductor device 100 receives the command and address information, and sets the control information RCD for adjusting the timing at which the control device issues a command according to the command and address information. Output.

  Further, the timing adjustment unit 113 is based on a determination result indicating whether the latest memory cell and the previous memory cell are included in the same block, and an elapsed time from the start of the operation on the previous memory cell. The control information RCD, which is a detection signal for setting the minimum interval between commands in the control device, is output.

  The timing adjustment unit 113 sets the minimum interval to the first value when the latest memory cell and the previous memory cell are included in the same block (address information matches) and the elapsed time is less than or equal to a predetermined threshold value. To do. In addition, when the latest memory cell and the previous memory cell are included in different blocks (address information does not match), the timing adjustment unit 113 sets the minimum interval to a predetermined second value equal to or smaller than the first value. To do. The timing adjustment unit 113 can use a predetermined value larger than the second value as the first value. Thereby, the timing for issuing the command is adjusted.

  Hereinafter, the operation timing of the semiconductor device 100 will be described for three patterns of command and address information issued by the control device.

  FIG. 9 is a timing chart for explaining the operation timing of the semiconductor device 100 for the first operation pattern of the control device.

  In the first operation pattern, the control device issues an active command Act, a write command Wrt, and a precharge command Pre for the block 0 of the bank BK0, and then performs an active command Act and a read for the block 0 of the same bank BK0. Issue command Red.

  When the control device issues an active command Act and address information at time T0, the command decoder 106 generates a bank active signal ACT, which is an internal signal, according to the active command Act. In response to the bank active signal ACT, the chip control circuit 107 activates the word line SWL-0i in the block 0 of the bank BK0, and the data read from the memory cell MC to the bit line pair BLP is output by the sense amplifier SA. Amplified and retained. The chip control circuit 107 performs control so that the word line SWL-0i is selected only for the time required for writing to the memory cell MC.

  When the control device issues a write command Wrt at time T3, the command decoder 106 generates a bank write signal WRT which is an internal signal in response to the write command Wrt. The chip control circuit 107 writes data from the R / W amplifier 108 to the sense amplifier SA in response to the bank write signal WRT, and starts writing data from the sense amplifier SA to the memory cell MC via the bit line BL. Is done.

  The timing adjustment unit 113 sets the initial value CNT = 6 of the tWR timer according to the bank write signal WRT. The tWR timer decrements the count value cnt every time it receives the internal clock signal ICLK generated by the clock generation circuit 103 according to the clock signal CK.

  On the other hand, the control device waits for a minimum interval tWR = 2 clocks from the issuance of the write command Wrt to the issuance of the write command to issuance of the precharge command Pre set in the semiconductor device 100. The precharge command Pre is issued at time T5. The command decoder 106 generates a bank precharge signal PRE that is an internal command signal in response to the precharge command Pre. The block address register BLR records the block address included in the address information issued at time T0 according to the bank precharge signal PRE.

  In addition, the control device sets the minimum interval tRP = 2 clocks from issuing the precharge command Pre to issuing the active command Act set in the semiconductor device 100 after issuing the precharge command Pre. At time T7, an active command Act for block 0 of bank BK0 is issued. The command decoder 106 generates a bank active signal ACT that is an internal signal in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address and the latest block address match, the value of the match signal HIT becomes high level. Since the count value cnt at this time is 2, the timing adjustment unit 113 generates a control signal RCD having a high level value and outputs it to the control device.

  The chip control circuit 107 activates the target bank BK at a timing according to the value of the match signal HIT. Specifically, the chip control circuit 107 activates the target bank BK by activating the word line SWL in the target bank BK at a timing according to the value of the match signal HIT. More specifically, when the value of the coincidence signal HIT is at a high level, the chip control circuit 107 provides a waiting time until the word line SWL activated by the previous command is inactivated, The word line SWL in the bank BK is activated. On the other hand, when the value of the coincidence signal HIT is at a low level, the chip control circuit 107 does not provide a standby time regardless of the state of the word line SWL activated by the previous command, The word line SWL is activated.

  Here, since the value of the coincidence signal HIT is at a high level and the word line SWL-0i activated according to the previous command is activated at the time T7, the chip control circuit 107 is activated. The process waits until the writing to the memory cell MC started in response to the previous command is completed. When the writing to the memory cell MC is completed, the chip control circuit 107 deactivates the word line SWL-0i and waits for a predetermined time before activating the word line SWL-0j.

  On the other hand, when the control device receives the control signal RCD, based on the control signal RCD, the control device sets a minimum interval tRCD from the issuance of the active command Act to the issuance of the first column access command to a predetermined first value = 4 or the second value = 2. In the present embodiment, the control device sets tRCD = 4 when the value of the control signal RCD is high, and sets tRCD = 2 when the value of the control signal RCD is low. Here, since the value of the control signal RCD is at a high level, the control device sets tRCD = 4 and issues a read command Red at time T11.

  As described above, when the control device continuously issues active commands for the same block, and when the count value cnt of the tWR timer is not 0 when the subsequent active command is issued, the timing adjustment unit 113 Outputs a control signal RCD for delaying the timing of issuing the column access command after the subsequent active command. Therefore, it is possible to avoid a situation in which the semiconductor device 100 does not operate normally due to the subsequent column access command being issued before the operation corresponding to the previous command is completed.

  FIG. 10 is a timing chart for explaining the operation timing of the semiconductor device 100 for the second operation pattern of the control device.

  In the second operation pattern, the control device issues an active command Act, a write command Wrt, and a precharge command Pre for the block 0 of the bank BK0, and then an active command Act and a read command for the block 1 of the bank BK0. Issue Red.

  Note that the control device issues the active command Act at time T0, then issues the precharge command Pre at time T5, and the operation of the semiconductor device 100 in response to the precharge command Pre is the first operation pattern. Therefore, the description is omitted here.

  The control device sets the minimum interval tRP = 2 clocks from issuing the precharge command Pre at time T5 to issuing the active command Act, which is set in the semiconductor device 100 after issuing the precharge command Pre. At time T7, the address information indicating the block 1 of the bank BK0 and the active command Act are issued. The command decoder 106 generates a bank active signal in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address and the latest block address do not match, the value of the match signal HIT becomes low level. Therefore, the timing adjustment unit 113 generates a control signal RCD having a low level value and outputs the control signal RCD to the control device.

  In this case, the control device sets tRCD = 2.

  The chip control circuit 107 activates the target bank BK according to the value of the coincidence signal HIT. Here, since the value of the coincidence signal is low level, the chip control circuit 107 does not depend on the state of the word line SWL-0i in the block 0 activated in response to the active command Act issued at time T0. The target bank BK0 is activated by activating the word line SWL-ij in the block 1 without providing a waiting time. In this case, a period tp1 in which both the word line SWL-0i and the word line SWL-1j are activated occurs, but the block including each word line SWL is different and the sense amplifier SA is not shared, so the block 0 It is possible to activate the word line SWL-1j of the block 1 before the writing to the memory cell MC in the memory cell MC is completed.

  In this way, when the control device continuously issues active commands for different blocks, the column next to the active command after the active command is consecutively issued compared to the case where commands for the same block are successively issued. It becomes possible to advance the timing of issuing the access command. If the target block of the command is different, even if the operation corresponding to the previous command is not completed, the target block can be accessed by the subsequent command, so it is uniformly according to the operation time. Compared with the case where the timing of receiving a command is delayed, the timing of receiving a command can be advanced, and an unnecessary operation delay can be avoided while the semiconductor device 100 operates normally.

  FIG. 11 is a timing chart for explaining the operation timing of the semiconductor device 100 for the third operation pattern of the control device.

  In the third operation pattern, the control device issues an active command Act and a precharge command Pre for the block 0 of the bank BK0, and then issues an active command Act and a read command for the block 0 of the same bank BK0. Issue Red. Compared to the first operation pattern, the third operation pattern is different in that the write command Wrt is not issued after the previous active command Act.

  When the control device issues an active command Act and address information at time T0, the command decoder 106 generates a bank active signal ACT, which is an internal signal, according to the active command Act. In response to the bank active signal ACT, the chip control circuit 107 activates the word line SWL-0i in the block 0 of the bank BK0, and the data read from the memory cell MC to the bit line pair BLP is output by the sense amplifier SA. Amplified and retained.

  The control device issues a precharge command Pre at time T5. The command decoder 106 generates a bank precharge signal PRE in response to the precharge command Pre. The block address register BLR records the block address included in the address information issued at time T0 according to the bank precharge signal PRE.

  In addition, the control device sets the minimum interval tRP = 2 clocks from issuing the precharge command Pre to issuing the active command Act set in the semiconductor device 100 after issuing the precharge command Pre. The active command Act for the block 0 of the bank BK0 is issued. The command decoder 106 generates a bank active signal ACT in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address and the latest block address match, the value of the match signal HIT becomes high level. Since the count value cnt = 0 at this time, the timing adjustment unit 113 generates a control signal RCD having a low level value and outputs it to the control device.

  In this case, the control device sets tRCD = 2.

  The chip control circuit 107 receives the bank active signal ACT generated according to the active command Act issued at time T7, and activates the target bank BK. At this time, the value of the coincidence signal HIT is at a high level, but since the word line SWL-0i activated in response to the active command Act issued at time T0 has already been deactivated, the chip control circuit 107 Activates the word line SWL-0j without providing a waiting time.

  Thus, when the write command Wrt is not issued, the value of the tWR timer is 0 even when the same block is targeted. The timing for issuing the command is adjusted according to the elapsed time since the write command Wrt is issued in addition to the coincidence signal HIT. Therefore, if the write command Wrt is not issued, the subsequent command is issued. The timing to do is advanced. When the write command Wrt is not issued, it is not necessary to wait for the time required for writing to the memory cell, so that unnecessary operation delay can be avoided.

  As described above, the semiconductor device 100 according to the first embodiment of the present invention has the memory unit 101 divided into a plurality of blocks including the plurality of memory cells MC sharing the sense amplifier SA. The semiconductor device 100 receives a command for instructing an operation on a memory cell and address information for specifying a memory cell to be instructed by the command, and the latest memory cell and the previous memory cell are included in the same block. Determine whether or not. Then, based on the determination result, the timing for issuing the command is adjusted. As a result, when the memory cell specified by the address information does not share the sense amplifier, the next command can be issued without waiting for the operation corresponding to the previous command to be completed, which is unnecessary. It becomes possible to reduce the operation delay.

(Modification)
FIG. 12 is a diagram showing a timer circuit in a modification of the semiconductor device according to the first embodiment of the present invention.

  In the above description, the memory unit 101 writes data to the memory cell MC at a timing corresponding to the write command Wrt. However, in the field of the semiconductor memory device, the data is sent to the sense amplifier SA at the timing when the write command Wrt is issued. There is a system that writes data to the memory cell MC after the pre-charge command Pre is issued. In this case, data writing to the memory cell is actually started in response to the precharge command Pre. For this reason, it is possible to maintain normal operation by adjusting the timing at which the command is issued according to the elapsed time since the precharge command Pre is issued.

  The timer circuit 132A in this modification uses a tRP timer that receives a bank precharge signal PRE instead of the bank write signal WRT and starts counting in accordance with the bank precharge signal PRE.

  FIG. 13 is a flowchart for explaining the operation of the timer circuit 132A according to this modification. The operation of the timer circuit 132A according to the present modified example is that the value of the bank precharge signal PRE is high when the value of the bank write signal WRT is high instead of executing step S200 for determining whether or not the value of the bank write signal WRT is high. Since step S201 for determining whether or not there is performed is the same as FIG. 8, the description thereof is omitted.

  Hereinafter, the operation timing of the semiconductor device 100 according to the present modification will be described for three patterns of command and address information issued by the control device.

  FIG. 14 is a timing chart for explaining the operation timing of the semiconductor device 100 according to the present modification with respect to the fourth operation pattern of the control device.

  In the fourth operation pattern, the control device issues the active command Act and the precharge command Pre for the block 0 of the bank BK0, and then issues the active command Act and the read command Red for the block 0 of the same bank BK0. To do.

  When the control device issues an active command Act and address information at time T0, the command decoder 106 generates a bank active signal ACT in response to the active command Act. The chip control circuit 107 activates the word line SWL-0i in the block 0 of the bank BK0 in response to the bank active signal ACT, and the data read from the memory cell MC to the bit line pair BLP is amplified by the sense amplifier SA. And retained.

  The control device issues a precharge command Pre at time T3. The command decoder 106 generates a bank precharge signal PRE in response to the precharge command Pre. The block address register BLR records the block address included in the address information issued at time T0 according to the bank precharge signal PRE.

  In addition, the timer circuit 132A of the timing adjustment unit 113 sets the initial value CNT = 6 of the tRP timer according to the bank precharge signal PRE. The tRP timer decrements the count value cnt every time it receives the internal clock signal ICLK.

  In addition, the control device sets the minimum interval tRP = 2 clocks from issuing the precharge command Pre to issuing the active command Act set in the semiconductor device 100 from issuing the precharge command Pre. At time T5, an active command Act for block 0 of bank BK0 is issued. The command decoder 106 generates a bank active signal ACT in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address and the latest block address match, the value of the match signal HIT becomes high level. Since the count value cnt at this time is 4, the timing adjustment unit 113 generates a control signal RCD having a high level value and outputs it to the control device.

  The chip control circuit 107 activates the target bank BK according to the value of the coincidence signal HIT. Here, since the value of the coincidence signal HIT is at a high level and the word line SWL0i activated according to the previous command is activated at time T5, the chip control circuit 107 includes the bank control circuit 107. The word line SWL-0j in the block 0 of BK0 is not activated and is set in a standby state. When writing to the memory cell MC is completed, the chip control circuit 107 deactivates the word line SWL-0i, waits for a predetermined time, and activates the word line SWL-0j.

  On the other hand, when the control device receives the control signal RCD, based on the control signal RCD, the control device sets a minimum interval tRCD from the issuance of the active command Act to the issuance of the first column access command to a predetermined first value = 6 or the second value = 2. Here, the control device sets tRCD = 6 and issues a read command Red at time T11.

  FIG. 15 is a timing chart for explaining the operation timing of the semiconductor device 100 according to the present modification with respect to the fifth operation pattern of the control device.

  In the fifth operation pattern, the control device issues an active command Act and a read command Red for the block 1 of the bank BK0 after issuing an active command Act and a precharge command Pre for the block 0 of the bank BK0. Issue.

  When the control device issues an active command Act and address information at time T0, the command decoder 106 generates a bank active signal ACT in accordance with the active command Act. In response to the bank active signal ACT, the chip control circuit 107 activates the word line SWL-0i in the block 0 of the bank BK0, and the data read from the memory cell MC to the bit line pair BLP is sense amplifier SA. Amplified and retained at.

  When the control device issues a precharge command Pre at time T3, the command decoder 106 generates a bank precharge signal PRE in response to the precharge command Pre. The block address register BLR records the block address included in the address information issued at time T0 according to the bank precharge signal PRE.

  In addition, the timer circuit 132A of the timing adjustment unit 113 sets the initial value CNT = 6 of the tRP timer according to the bank precharge signal PRE. The tRP timer decrements the count value cnt every time it receives the internal clock signal ICLK.

  In addition, the control device sets the minimum interval tRP = 2 clocks from issuing the precharge command Pre to issuing the active command Act set in the semiconductor device 100 from issuing the precharge command Pre. At time T5, an active command Act for block 1 of bank BK0 is issued. The command decoder 106 generates a bank active signal ACT in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address and the latest block address do not match, the value of the match signal HIT becomes low level. Therefore, the timing adjustment unit 113 generates a control signal RCD having a low level value and outputs the control signal RCD to the control device.

  The chip control circuit 107 activates the target bank BK according to the value of the coincidence signal HIT. Here, since the value of the coincidence signal HIT is at a low level, the chip control circuit 107 activates the word line SWL-1j in the block 1 without providing a standby time according to the bank active signal ACT.

  In this case, a period tp2 occurs in which both the word line SWL-0i and the word line SWL-0j are activated. However, since the blocks are different and the sense amplifier is not shared, the block before the operation of the block 0 is completed. One word line SWL-0j can be activated.

  On the other hand, when the control device receives the control signal RCD, based on the control signal RCD, the control device sets a minimum interval tRCD from the issuance of the active command Act to the issuance of the first column access command to a predetermined first value = 6 or the second value = 2. Here, the control device sets tRCD = 2 and issues a read command Red at time T7.

  FIG. 16 is a timing chart for explaining the operation timing of the semiconductor device 100 according to the present modification example with respect to the sixth operation pattern of the control device.

  In the sixth operation pattern, the command and address information issued by the control device are the same as in the fourth operation pattern. In the sixth operation pattern, the timing for issuing each command is different from that in the fourth operation pattern. Specifically, in the sixth operation pattern, the period from when the precharge command Pre is issued until the next active command Act is issued is longer than that in the fourth operation pattern. For this reason, in the sixth operation pattern, the count value cnt of the tRP timer is 0 when the next active command Act is issued.

  The control device issues an active command Act and address information at time T0. The command decoder 106 generates a bank active signal ACT in response to the active command Act. The chip control circuit 107 activates the word line SWL-0i in the block 0 of the bank BK0 in response to the bank active signal ACT.

  The control device issues a precharge command Pre at time T3. The command decoder 106 generates a bank precharge signal PRE in response to the precharge command Pre. The block address register BLR records the block address included in the address information issued at time T0 according to the bank precharge signal PRE.

  In addition, the timer circuit 132A of the timing adjustment unit 113 sets the initial value CNT = 6 of the tRP timer according to the bank precharge signal PRE. The tRP timer decrements the count value cnt every time it receives the internal clock signal ICLK.

  In addition, the control device issues an active command Act for block 0 of bank BK0 at time T9. The command decoder 106 generates a bank active signal ACT in response to the active command Act.

  The timing adjustment unit 113 receives the bank active signal ACT and compares the block addresses. In this case, since the previous block address matches the latest block address, the value of the match signal HIT becomes high level. Since the count value cnt = 0 at this time, the timing adjustment unit 113 generates a control signal RCD having a low level value and outputs it to the control device.

  The chip control circuit 107 activates the target bank BK according to the value of the coincidence signal HIT. Here, although the value of the coincidence signal HIT is at a high level, since the word line SWL-0i has already been deactivated at the time T9, the chip control circuit 107 does not provide a standby time and the word line SWL-0j Activate.

  On the other hand, when the control device receives the control signal RCD, based on the control signal RCD, the control device sets a minimum interval tRCD from the issuance of the active command Act to the issuance of the first column access command to a predetermined first value = 6 or the second value = 2. Here, the control device sets tRCD = 2 and issues a read command Red at time T11.

  As described above, even in the semiconductor device according to the present modification, unnecessary operation delay can be reduced by adjusting the timing of issuing a command based on the comparison result.

  Further, in the semiconductor device according to the present modification, the command issuance timing is adjusted according to the elapsed time after receiving the precharge command Pre. Even in a semiconductor device in which data writing to the memory cell MC is executed in accordance with the precharge command Pre by adjusting the timing of issuing the command according to the elapsed time after receiving the precharge command Pre, A state in which the subsequent command is issued before the operation corresponding to the previous command is completed and the memory cell MC targeted by the subsequent command cannot be accessed and the semiconductor device 100 does not operate normally is avoided. It becomes possible.

  As described above, the semiconductor device (100) according to the present embodiment includes a plurality of memory cells (MC) that hold data, and a sense amplifier (SA) that amplifies data read from each of the memory cells. The memory cell includes a memory unit (101) divided into blocks including a plurality of memory cells sharing a sense amplifier, and a command decoder (command decoder) that receives a command from a control device that issues a command instructing an operation on the memory cell. 106), the address information specifying the memory cell whose operation is instructed by the command from the control device is received, and the memory cell specified by the recently received address information and the address information received last time are specified. Whether or not the previous memory cell that is a memory cell is included in the same block, Based on the determination result, control device and a timing adjustment unit for adjusting the timing of issuing a command (113).

  Further, in the semiconductor device (100) according to the present embodiment, the timing adjustment unit (113) sets a minimum interval until a command is issued from a predetermined reference time point in the control device based on the determination result. Adjust timing.

  Further, in the semiconductor device (100) according to the present embodiment, the timing adjustment unit (113) sets the minimum interval to the first value when the latest memory cell and the previous memory cell are included in the same block, When the memory cell and the previous memory cell are included in different blocks, the minimum interval is set to a predetermined second value equal to or smaller than the first value.

  In the semiconductor device (100) according to the present embodiment, the timing adjustment unit (113) uses a predetermined value larger than the second value as the first value.

  In the semiconductor device (100) according to the present embodiment, the plurality of blocks are divided into the plurality of banks BK, and the timing adjustment unit (113) issues an active command (Act) that activates the banks BK. Time is set as the reference time.

  Further, in the semiconductor device (100) according to the present embodiment, each of the plurality of memory cells (MC) includes a plurality of memory cells (MC), which are respectively accessed by different address information. And a detection circuit (113) for holding first address information corresponding to the memory cell block selected in the second access (ACT to PRE) received immediately before, the detection circuit including the first access The detection signal when the second address information corresponding to the memory cell block selected in (ACT to PRE) matches the first address information and the first access has not elapsed for a predetermined period from the second access. Is a first value.

  Further, in the semiconductor device (100) according to the present embodiment, the detection circuit (113) has the second address information corresponding to the memory cell block selected in the first access coincide with the first address information and The detection signal is set to the second value when the first access has passed a predetermined period from the second access.

  Further, in the semiconductor device (100) according to the present embodiment, the detection circuit (113) causes the second address information corresponding to the memory cell block selected in the first access to not match the first address information. Let the detection signal be the second value.

  Here, in the present embodiment, a DRAM is taken as an example, and it is known that a DRAM performs access (command input) to rows and columns in a time division manner. ACT is an access to a row, and WRT and RED are access to a column. On the other hand, the flash memory does not take such an access form, and access (command input) to a row and a column is not performed in a time division manner. The technical idea of the present invention is not limited to the time-sharing control in the DRAM, but can be applied to a case where access to a row and a column is performed at once (that is, ACT + (WRToRRED) + PRE).

(Second Embodiment)
FIG. 17 is a diagram showing a configuration of a semiconductor device 200 according to the second embodiment of the present invention.

  Compared with the semiconductor device 100, the semiconductor device 200 outputs a control information RCD indicating one of two predetermined high-level or low-level values as control information for controlling the timing. Instead of 113, a timing control device 213 that outputs control information ΔRCD that is n-bit binary data is provided.

  FIG. 18 is a diagram illustrating a timer circuit 232 portion of the timing adjustment unit 213.

  Although not shown in FIG. 18, the timing adjustment unit 213 includes four address comparison circuits 131 provided corresponding to each bank BK. The timing adjustment unit 213 includes four timer circuits 132 provided corresponding to the banks BK.

  Since the internal configurations of the address comparison circuit 131 and the timer circuit 132 are the same as those in the first embodiment, description thereof is omitted here.

  The timing adjustment unit 213 receives the coincidence signal HIT output from the address comparison circuit 131 and the count values cnt0 to cnt3 output from each timer circuit 132 for each bit, and outputs of the NAND gates 233. And n inverters 234 that invert and output.

  The count values cnt output from the four timer circuits 132 corresponding to the four banks BK are connected for each bit and input to the 2-input NAND gate 233 together with the match signal HIT for each bit. The output of the NAND gate 233 is input to the inverter 234, and the input n-bit data is inverted by the inverter 234 and n-bit control information ΔRCD is output from the inverter 234.

  Thereby, when the coincidence signal HIT takes a low level value, the value of ΔRCD becomes 0 regardless of the count value cnt, and when the coincidence signal HIT takes a high level value, the value of the control signal ΔRCD. Is a value based on the count value cnt. The timing adjustment unit 213 outputs the control signal ΔRCD to the control device.

  The control device sets the value indicated by the control signal ΔRCD to a value obtained by delaying the minimum interval by adding it to the initial value of the minimum interval at which the command is issued. Thereby, the timing for issuing the command is adjusted.

  Accordingly, when the latest memory cell and the previous memory cell are included in different blocks, the timing adjustment unit 213 has a predetermined minimum interval regardless of the elapsed time from the start of the operation on the previous memory cell. The value of In addition, when the latest memory cell and the previous memory cell are included in the same block, the timing adjustment unit 213 sets the minimum interval to the first value equal to or greater than the second value. In the present embodiment, the first value is a value corresponding to the elapsed time since the operation on the previous memory cell started. More specifically, the timing adjustment unit 213 calculates the first value by adding the count value cnt output from the timer circuit 132 to the second value.

  Thereby, the timing adjustment unit 213 uses the same value as the second value as the first value and the elapsed time is less than the threshold when the elapsed time from the start of the operation on the previous memory cell is equal to or greater than the predetermined threshold. In this case, a value larger than the second value is used as the first value. In addition, the timing adjustment unit 213 decreases the first value as the elapsed time is longer.

  FIG. 19 is a timing chart for explaining the operation timing of the semiconductor device 200 according to the second embodiment of the present invention.

  The control device issues an active command Act, a write command Wrt, and a precharge command Pre for the block 0 of the bank BK0, and then issues an active command Act and a read command Red for the block 0 of the same bank BK0.

  This operation timing has been described with reference to FIG. 9 except that the timing adjustment unit 213 outputs a control signal ΔRCD indicating an n-bit value instead of the control signal RCD having a high level or low level value. Since it is the same as the 1st operation pattern of a 1st embodiment, explanation is omitted here. Since the count value cnt of the tWR timer is 2 at this time when the active command Act is received, the timing adjustment unit 213 outputs a control signal ΔRCD indicating a value of 2.

  The control device receives the control signal ΔRCD, adds the value of the control signal ΔRCD to the minimum interval tRCD, and issues a read command Red after a time equal to or longer than the minimum interval tRCD has elapsed.

(Modification)
FIG. 20 is a diagram illustrating a timer circuit in a modification of the semiconductor device according to the second embodiment of the present invention.

  In the semiconductor device 200, the memory unit 101 writes data into the memory cell MC at a timing corresponding to the write command Wrt. However, in the semiconductor memory field, the data is sensed at the timing when the write command Wrt is issued. There is a system in which data is written up to SA and data is collectively written into the memory cell MC after the precharge command Pre is issued. In this case, since data writing to the memory cell MC is actually started in response to the precharge command Pre, the actual operation time can be counted by counting from the precharge command Pre.

  Therefore, the timer circuit 132A in the present modification uses a tRP timer that receives the bank precharge signal PRE instead of the bank write signal WRT and starts counting in accordance with the bank precharge signal PRE.

  FIG. 21 is a timing chart for explaining the operation timing of the semiconductor device 200 according to the present modification. The operation timing of this modification is the same as that of the semiconductor device 100 according to the modification of the first embodiment described with reference to FIG. 14, except that the control information output from the timing adjustment unit 113 indicates an n-bit value. . In this case, since the count value cnt output in response to the active command Act is 4, the timing adjustment unit 213 generates control information ΔRCD having a value of 4 and outputs it to the control device. The control device receives this control information ΔRCD and adds the value indicated by the control information ΔRCD to the minimum interval tRCD for issuing a command.

  Also in the semiconductor device 200 according to the second embodiment, as described in the modification of the semiconductor device 100 according to the first embodiment, the semiconductor device of a method of writing data to the memory cell MC according to the precharge command Pre. It is possible to apply to.

  As described above, even in the semiconductor device 200 according to the second embodiment of the present invention, the timing of issuing a command depends on whether the latest memory cell and the previous memory cell are included in the same block. Adjusted. Therefore, unnecessary operation delay can be reduced.

  In the present embodiment, the timing for issuing a command is adjusted according to the count value cnt. In the first embodiment, the minimum interval tRCD is determined to be either the first value or the second value determined in advance. For this reason, when the latest memory cell and the previous memory cell are included in the same block, the interval at which the command is issued needs to be the maximum value that can be taken. On the other hand, in the present embodiment, by giving the count value cnt itself to the control device, the control device can finely adjust the tRCD according to the elapsed time since the operation corresponding to the previous command is started. Thus, unnecessary operation delay can be further reduced.

  As described above, in the semiconductor device (200) according to the present embodiment, the timing adjustment unit (213) uses, as the first value, a value corresponding to the elapsed time from the start of the operation on the previous memory cell.

  Further, in the semiconductor device (200), the timing adjustment unit (213) uses the same value as the second value as the first value when the elapsed time is equal to or greater than the threshold, and the first when the elapsed time is less than the threshold. A value larger than the second value is used as the value of.

  In the semiconductor device (200), the timing adjustment unit (213) decreases the first value as the elapsed time is longer when the elapsed time is less than the threshold.

(Third embodiment)
FIG. 22 is a diagram showing a computer system including the semiconductor device 100 according to the first embodiment of the present invention or the semiconductor device 200 according to the second embodiment.

  This computer system includes the semiconductor device 100 according to the first embodiment of the present invention or the semiconductor device 200 according to the second embodiment, and the multi-core processor 300.

  The multi-core processor 300 includes four core processors 301, an input / output interface I / O 302, an external storage device control device 303, and an on-chip memory 304.

  The four core processors 301 correspond to the banks BK of the semiconductor device 100 or 200, respectively.

  The external storage device control device 303 is a memory controller that controls the semiconductor device 100 or 200. The external storage device controller 303 receives the control information RCD or ΔRCD output from the semiconductor device 100 or 200, and issues command and address information to the semiconductor device 100 or 200 at a timing based on the control signal RCD or ΔRCD.

  As described above, in the present embodiment, the semiconductor device 100 according to the first embodiment or the semiconductor device 200 according to the second embodiment can be used in combination with a multi-core processor.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  For example, in the above embodiment, the semiconductor device is a DRAM which is a dynamic memory, but the present invention is not limited to such an example. For example, the semiconductor device is a volatile static memory such as SRAM (Static RAM), a non-volatile memory such as flash memory, PRAM (Phase change RAM), STTRAM (Spin Torque Transfer RAM), and ReRAM (Resistivity RAM). May be.

  In the above embodiment, the case where the next command for the previous command is the read command Red has been described as an example, but the present invention is not limited to such an example. The next command may be a write command Wrt.

100, 200 Semiconductor device 101 Memory unit 102 Clock terminal group 103 Clock generation circuit 104 Mode register 105 Command terminal group 106 Command decoder 107 Chip control circuit 108 RW amplifier 109 Latch circuit 110 Data input / output buffer 111 Bank and row address buffer 112 Column address Buffers 113 and 213 Timing adjustment unit 121 Memory cell array 122 Column decoder 123 Row decoder 124 Array control circuit 131 Address comparison circuit 132 and 132A Timer circuit 300 Multicore processor 303 External storage device control unit (control device)

Claims (11)

A plurality of memory cells that hold data; and a sense amplifier that amplifies data read from each of the memory cells, wherein the plurality of memory cells are arranged in a block including a plurality of memory cells that share the sense amplifier. A divided memory section; and
A command decoder that receives the command from a control device that issues a command for instructing an operation on the memory cell;
The address information specifying the memory cell whose operation is instructed by the command is received from the control device, and the memory cell specified by the recently received address information and the address information received last time are specified. A timing adjustment unit that determines whether or not a previous memory cell that is a memory cell is included in the same block, and that adjusts a timing at which the control device issues the command based on the determination result; Semiconductor device.   2. The semiconductor according to claim 1, wherein the timing adjustment unit adjusts the timing by setting, in the control device, a minimum interval from a predetermined reference time point until the command is issued based on the determination result. apparatus.   When the latest memory cell and the previous memory cell are included in the same block, the timing adjustment unit sets the minimum interval to a first value, and the recent memory cell and the previous memory cell are included in different blocks. 3. The semiconductor device according to claim 2, wherein the minimum interval is a predetermined second value equal to or smaller than the first value.   The semiconductor device according to claim 3, wherein the timing adjustment unit uses a predetermined value larger than the second value as the first value.   4. The semiconductor device according to claim 3, wherein the timing adjustment unit uses a value corresponding to an elapsed time from the start of an operation on the previous memory cell as the first value.   The timing adjustment unit uses the same value as the second value as the first value when the elapsed time is equal to or greater than a threshold value, and sets the first value as the first value when the elapsed time is less than the threshold value. The semiconductor device according to claim 5, wherein a value larger than 2 is used.   The semiconductor device according to claim 6, wherein when the elapsed time is less than a threshold, the timing adjustment unit decreases the first value as the elapsed time is longer. The plurality of blocks are divided into a plurality of banks,
The semiconductor device according to claim 2, wherein the timing adjustment unit sets a time point when an active command for activating the bank is issued as the reference time point. A plurality of memory cell blocks each including a plurality of memory cells, each accessed by different address information;
A detection circuit for holding first address information corresponding to the memory cell block selected in the second access received one before the first access;
In the detection circuit, the second address information corresponding to the memory cell block selected in the first access matches the first address information, and the first access is predetermined from the second access. A semiconductor device, wherein a detection signal is a first value when a period has not elapsed.   In the detection circuit, the second address information corresponding to the memory cell block selected in the first access matches the first address information, and the first access is changed from the second access. The semiconductor device according to claim 9, wherein the detection signal is set to a second value when the predetermined time has elapsed.   The detection circuit sets the detection signal to the second value when the second address information corresponding to the memory cell block selected in the first access does not match the first address information. The semiconductor device according to claim 10.

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