TWI611285B - System and method for realizing gate drive circuit - Google Patents

Abstract

The invention relates to a system and method for implementing a gate driving circuit. A system for implementing a gate driving circuit is provided. The system includes a driving chip. The driving chip includes a pre-driver, a first high-side transistor, and a second high-side transistor. The driving capability of the first high-side transistor is greater than that of the second high-side transistor. Driving capability of high-side transistor, high-side delay element, high-side delay element is connected to the first high-side transistor; first low-side transistor and second low-side transistor, of which the driving capability of the first low-side transistor Greater driving capability than the second low-side transistor, and a low-side delay element, the low-side delay element is connected to the first low-side transistor; and a MOS power stage, which includes a power transistor.

Description

System and method for implementing gate driving circuit

The present invention relates to the field of circuits, and more particularly, to a system and method for implementing a gate driving circuit.

In switching power supply applications, the design of a chip-level drive circuit that controls external power MOS (Metal Oxide Semiconductor) switches needs to meet EMI (Electro-Magnetic Interference, electromagnetic interference) while ensuring high system efficiency. Claim.

In the traditional drive circuit design, the above two requirements are difficult to meet at the same time. When the drive is strong, the switching loss can be reduced to obtain a relatively high transmission efficiency. However, at this time, EMI often cannot meet the requirements, especially for the current new-type This contradiction is particularly prominent in super-junction power MOS.

FIG. 1 is a simplified diagram showing a conventional system for implementing a gate driving circuit. A traditional method is to connect a resistor with a certain resistance value in series to the gate of the output of the driving circuit to the power MOS to solve EMI. As shown in FIG. 1, the first figure includes the driving chip and the external power MOS. Doing so will inevitably increase switching losses and reduce efficiency.

Fig. 2 is a Vg waveform diagram showing a system as shown in Fig. 1. The Vg waveform of the gate drive in series (dashed line) and non-series resistance (solid line) is shown in Figure 2. As shown by the solid line in Figure 2, when there is no series resistor, the rising and falling edges of the gate drive waveform are faster, and the waveform will show obvious oscillations, which will affect the EMI characteristics. On the other hand, as shown by the dotted line, when the resistor is connected in series, the rising and falling edges of the gate drive waveform become slower and oscillations are suppressed, but the drive loss increases.

As shown in Figure 2, when a voltage is applied, an input current Igate = I1 + I2; when the gate-source voltage Vgs is applied, the drain-source voltage Vds decreases. During turn-on or turn-off, the total equivalent capacitance Ceq of the gate-source is: Igate = I1 + I2 = (Cgd × (1 + Av) + Cgs) × dVgs / dt = Ceq × dVgs / dt

Among them, Igate is the gate current, I1 is the current flowing through the gate leakage capacitor Cgd, I2 is the current flowing through the gate source capacitor Cgs, and (1 + Av) is called the Miller effect parameter, which describes the output and input Capacitor feedback. When the gate-drain voltage approaches zero, the Miller effect will occur. Before the MOS is turned on, the D-pole voltage is greater than the G-pole voltage, and the amount of electricity stored in the MOS parasitic capacitor Cgd needs to be injected into the G-pole to neutralize the charge when it is on. The Miller effect will seriously increase the turn-on loss of the MOS, resulting in a Miller platform, so that the MOS transistor cannot quickly enter the on or off state.

FIG. 3 is a diagram showing the operating waveforms of the system as shown in FIG. 1. Among them, drv_h is the driving signal of the power-on transistor MN_hs, drv_l is the driving signal of the power-down transistor MN_ls, td is the dead time between the upper and lower transistors, the gate electrode drives the waveform on the pin of the chip, and Vg is the external power MOS gate There is a Miller plateau on the pole voltage waveform, rising and falling edges, tr and tf are rising and falling times, which increase with the increase of Rg, and the loss also increases. As a result, the drive architecture in Figure 1 makes it difficult to make a good balance between loss and EMI.

FIG. 4 is a simplified diagram showing another conventional system for implementing a gate driving circuit. The architecture of Figure 1 is a way to improve EMI, but this method can only adjust the driving rising and falling edges by the same amount. It cannot adjust the rising and falling edges separately, and the flexibility is poor. If you want to adjust the rising and falling edges separately, you can introduce different resistors for the rising and falling edges. The difference between the methods in Figure 4 and Figure 1 is that the diodes are used to separate the rising and falling edges. The resistance of Rgh and Rgl, the speed of the rising and falling edges can be achieved by using different Rgh and Rgl, and the adjustment is more flexible.

FIG. 5 is a diagram showing the operating waveforms of the system as shown in FIG. 4. It can be seen from the waveform in Figure 5 that assuming Rgh> Rgl, the rising edge of the power MOS gate will be slower than the falling edge. If you need to make the rising edge different from the falling edge when solving EMI, you can use the method in Figure 4. However, the drive architecture of Figure 4 is also difficult to A good compromise between EMI.

The system to solve EMI is essentially to weaken the driving ability before the rising or falling edge of the Miller platform, and reduce the on and off oscillations as shown in Figure 2 to reduce the impact on EMI. However, after the Miller platform is completed, it is hoped that the driving capability will be strengthened and the power MOS transistor will be quickly turned on or off to minimize the driving loss and improve the efficiency. Obviously, the above two driving architectures cannot take both points into consideration. In view of the shortcomings of the traditional method, the present invention will provide a driving architecture that can make a good compromise between efficiency and EMI requirements.

In view of the problems described above, the present invention provides a system and method for implementing a gate driving circuit. By way of example only, some embodiments of the invention are applied to a gate drive system. However, it should be understood that the present invention has a wider scope of application.

According to an aspect of the present disclosure, a system for implementing a gate driving circuit is provided, including: a driving chip, the driving chip including a pre-driver, a first high-side transistor, and a second high-side transistor, wherein the first high-side transistor The crystal driving capability is greater than that of the second high-side transistor. The high-side delay element and the high-side delay element are connected to the first high-side transistor; the first low-side transistor and the second low-side transistor, where the first low The driving capability of the edge transistor is greater than that of the second low-side transistor, and the low-side delay element, the low-side delay element is connected to the first low-side transistor; and the MOS power stage, which includes the power transistor MN0; In the process of controlling the turning on of the power transistor MN0, the second high-side transistor is configured to generate a first driving signal near the end of the first Miller platform to turn on the first high-side transistor, so that the second high-side transistor is turned on. The transistor is first turned on to drive the power transistor MN0 with the first current, and the first high-side transistor is not turned on until the first Miller platform ends, and the power transistor MN0 is turned on with the second current. The magnitude of the first current is smaller than the magnitude of the second current; and wherein during the control power transistor MN0 is turned off, the second low-side transistor is configured to generate a second driving signal near the end of the second Miller platform to The first low-side transistor is turned on, so that the second low-side transistor is turned on first, and the power transistor MN0 is driven with the third current until the end of the second Miller platform, the first low-side transistor is turned on and driven with the fourth current The power transistor MN0 is turned off, and the amplitude of the third current is less than The magnitude of the fourth current.

According to another aspect of the present disclosure, a system for implementing a gate driving circuit is provided, including: a driving chip, the driving chip including a pre-driver, and a delay component; and a MOS power stage including a power transistor MN0; The pre-driver includes a first current source and a second current source, wherein the first current source is larger than the second current source, the first transistor MP1 and the second transistor MP2 of the PMOS switch, the lower driving transistor MN1, and the NMOS switch circuit. Crystal VMN2, the first Zener secondary body, the second Zener secondary body, and the capacitor that are initially cut off; in the process of controlling the power transistor MN0 to turn on, the pre-driver is configured to generate a first driving signal MN1 is turned off and MP1 is turned on. When the breakdown voltage of the second Zener diode is reached, the second current source starts to charge the capacitor until the delay period defined by the delay element expires. At this time, the pre-driver is also configured to generate The second driving signal turns on MP2 and keeps MP1 on. The first current source and the second current source charge the capacitor at the same time to achieve the first Zener secondary body and the second Qi The breakdown voltage of two bodies.

According to yet another aspect of the present disclosure, a method for implementing a gate driving circuit is provided, which includes: in the process of controlling the power transistor MN0 to turn on, generating a first driving signal near the end of the first Miller platform to make the first driving signal A high-side transistor is turned on, so that the second high-side transistor is turned on first to drive the power transistor MN0 with the first current, and the first high-side transistor is turned on until the first Miller platform ends, driving the power transistor with the second current. The crystal MN0 is turned on, wherein the amplitude of the first current is smaller than that of the second current; and in the process of controlling the power transistor MN0 to be turned off, a second driving signal is generated near the end of the second Miller platform to make the first low side The transistor is turned on, so that the second low-side transistor is turned on first, and the power transistor MN0 is driven by the third current until the end of the second Miller platform. The first low-side transistor is turned on, and the power transistor MN0 is turned off by the fourth current. Off, wherein the amplitude of the third current is smaller than the amplitude of the fourth current.

As described above, the novel gate drive circuit is implemented based on the traditional drive architecture, and adds independent control mechanisms and segmented control mechanisms for the rising and falling edges of the drive, which can achieve a good balance between switching losses and system EMI. Compromise, get higher efficiency.

In summary, the present invention includes at least the following beneficial effects: It is necessary to increase the cost of the original components to eliminate EMI around the system; it can independently control the rising and falling edges of the external power MOS gate voltage; it can control the rising or falling edge of the external power MOS gate voltage itself. ; In practical applications, the drive architecture can be selected according to the needs, and the circuit parameters can be flexibly adjusted based on the characteristics of the external power MOS, such as the delay times tdh and tdl, the sensing thresholds vh and vl, the size of the MN_hs and MN_ls transistors, and the current source Is And Im size to make a good compromise between efficiency and EMI.

The system and method for implementing a gate driving circuit according to the embodiments of the present application provide a new driving architecture, which can not only adjust the driving rising and falling edges separately, but also can perform stepwise adjustment on the rising or falling edge itself. A good compromise can be made between efficiency and EMI requirements. Depending on the embodiment, one or more benefits may also be obtained. These benefits, as well as various additional objects, features, and advantages of the present invention can be fully understood with reference to the following detailed description and accompanying drawings.

Vgs‧‧‧Gate-source voltage

Vds‧‧‧drain-source voltage

Ceq‧‧‧Total equivalent capacitance

Cgd‧‧‧Gate Leakage Capacitor

Cgs‧‧‧ Gate source capacitor

PIN‧‧‧Driver

td‧‧‧ dead time

tr‧‧‧ rise time

tf‧‧‧fall time

Tdh, tdl‧‧‧ delay time

vh, vl‧‧‧sensing threshold

C0‧‧‧capacitor

drv_h, drv_l‧‧‧ drive signal

Rg, Rgh, Rgl‧‧‧ resistance

PMOS, NMOS‧‧‧Switch

MN_hs_m, MN_hs_s‧‧‧High-side transistor

MN_ls_m, MN_ls_s‧‧‧Low-side transistor

delay_cell_h‧‧‧High-side delay component

delay_cell_l‧‧‧Low-side delay component

Lm‧‧‧ primary winding

Rcs‧‧‧Induction Resistor

Igate‧‧‧Gate current

Is, Im‧‧‧ current source

Zd1, Zd2 ‧‧‧Zina secondary body

Gate_h‧‧‧node

comp_hs, comp_ls‧‧‧ Gate Threshold Sensing Comparator

MN0, MN1, MN2, MN_hs, MN_ls‧‧‧Transistors

drv_h_d, drv_l_d, Gate_sense_h, Gate_sense_l‧‧‧ signal

Vg‧‧‧ Off-chip power MOS transistor MN0 gate voltage

Supply voltage of VCC‧‧‧ driver chip

Vbulk‧‧‧ input AC input voltage after bridge rectification filtering

pwm‧‧‧Logical control signal of driving part

Hereinafter, the features, advantages, and technical effects of the exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Similar reference numerals in the drawings represent similar elements, wherein: FIG. 1 shows a conventional implementation gate Simplified diagram of a system of pole drive circuits.

Fig. 2 is a waveform diagram showing Vg of the system as shown in Fig. 1.

FIG. 3 is a diagram showing the operating waveforms of the system as shown in FIG. 1.

FIG. 4 is a simplified diagram showing another conventional system for implementing a gate driving circuit.

FIG. 5 is a diagram showing the operating waveforms of the system as shown in FIG. 4.

FIG. 6 is a simplified diagram illustrating a system for implementing a gate driving circuit according to an embodiment of the present disclosure.

FIG. 7 is a diagram showing the operating waveforms of the system as shown in FIG. 6.

FIG. 8 is a simplified diagram illustrating another system for implementing a gate driving circuit according to an embodiment of the present disclosure.

FIG. 9 is a diagram showing the operating waveforms of the system as shown in FIG. 8.

FIG. 10 is a simplified diagram illustrating a system implementing a gate driving circuit according to another embodiment of the present disclosure.

FIG. 11 is a diagram showing the operating waveforms of the system as shown in FIG. 10.

FIG. 12 is a simplified diagram illustrating another system for implementing a gate driving circuit according to another embodiment of the present disclosure.

FIG. 13 is a diagram showing the operating waveforms of the system as shown in FIG. 12.

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely for providing a better understanding of the present invention by showing examples of the present invention. The invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

FIG. 6 is a simplified diagram illustrating a system for implementing a gate driving circuit according to an embodiment of the present disclosure. This figure is only an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art should understand many variations, substitutions, and modifications.

As shown in Figure 6, before the external power MOS is turned on or off of the Miller platform, a relatively weak driving capability is used to make the rising and falling edges slow enough to reduce the impact of the oscillation on the Miller platform on EMI ; After the Miller platform of external power MOS is completed, increase the driving capacity so that the rising and falling edges can be completed quickly.

Figure 6 shows the driver chip and the external power MOS power stage. The driver chip includes a pre-driver driver stage, high-side transistors MN_hs_m and MN_hs_s, high-side delay components delay_cell_h, low-side transistors MN_ls_m and MN_ls_s, and low-side delay components delay_cell_l. Power MOS power stage including power transistor MN0, the primary winding Lm, and the sense resistor Rcs.

Among them, the driving capability of the high-side transistor MN_hs_m is greater than MN_hs_s. The control signal of MN_hs_s is the driving signal drv_h. Drv_h generates a drv_h_d signal for controlling MN_hs_m after being delayed by the high-side delay component delay_cell_h. Similarly, the driving capability of the low-side transistor MN_ls_m is greater than MN_ls_s. The control signal of MN_ls_s is the driving signal drv_l. Drv_l generates a drv_l_d signal for controlling MN_ls_m after being delayed by the low-side delay component delay_cell_l. The delay time of the high-side delay element delay_cell_h may be different from the delay time of the low-side delay element delay_cell_l.

In the process of controlling the power transistor MN0 to turn on, MN_hs_s is first turned on, and the power transistor MN0 is driven with a weak current. The MN_hs_m is turned on until the Miller platform ends, and the power transistor MN0 is driven with a strong current to complete the entire turn-on process. Therefore, the delay time of the delay element delay_cell_h should be set to ensure that the drv_h_d signal is generated to make MN_hs_m turn on near the end of the Miller platform.

In the process of controlling the power transistor MN0 to turn off, MN_ls_s is first turned on, and the power transistor MN0 is driven with a weak current. Until the Miller platform ends, MN_ls_m is turned on, and the power transistor MN0 is driven with a strong current to complete the entire shutdown. Off process. Therefore, the delay time of the delay element delay_cell_l should be set to ensure that the drv_l_d signal is generated to make MN_ls_m turn on near the end of the Miller platform.

FIG. 7 is a diagram showing the operating waveforms of the system as shown in FIG. 6. In Figure 7, drv_h is the driving signal of the power-on crystal MN_hs_s, drv_h_d is the driving signal of the power-on crystal MN_hs_m, drv_l is the driving signal of the power-down crystal MN_ls_s, drv_l_d is the driving signal of the power-down crystal MN_ls_m, and td is power-on and power-off Dead time between crystals, tdh is the delay from MN_hs_s to MN_hs_m on, tdl is the delay from MN_ls_s to MN_ls_m. The gate drives the waveform on the PIN pin of the chip. There is a Miller platform on the rising and falling edges, tr Is the rise time, and tf is the fall time. From the perspective of the gate waveform, both its rising and falling edges can be controlled independently, and its rising or falling edges themselves are segmented. In this way, you can adjust MN_hs_m, MN_hs_s, MN_ls_m, MN_ls_s The size of the transistor is used to adjust the driving capability, and the segmentation time can be controlled by adjusting tdh and tdl, which increases the flexibility of the system.

FIG. 8 is a simplified diagram illustrating another system for implementing a gate driving circuit according to an embodiment of the present disclosure. The main difference between Figure 8 and Figure 6 is that two high-side independent MN_hs_m and MN_hs_s are combined into one MN_hs, and the gate voltage of MN_hs is controlled through pre-drive to achieve high-side two-stage turn-on control. Specifically, MN_hs adds a front control circuit, including current sources Im and Is (Im> Is), the first transistor MP1 and the second transistor MP2 of the PMOS switch, and the transistor MN1 and the transistor of the NMOS switch. MN2, Zener secondary bodies Zd1, Zd2, and capacitor C0.

The Drv_h signal in FIG. 8 is inverted from the drv_h in FIG. 7, so the drv_h signal needs to be inverted for subsequent processing. For example, the delay_cell_h delay and subsequent inversion are used to generate the drv_h_d signal for controlling MP2.

In the process of controlling the opening of MN_hs, the drv_h signal changes from high to low to make MN1 turn off, and MP1 is turned on, and the Gate_h node is charged with a small current Is. At the beginning, Zd2 is turned off, and there is no path between Gate_h and capacitor C0. Thus Gate_h will quickly rise to the breakdown voltage point of Zd2. After that, Is starts to charge capacitor C0, and the rising slope of Gate_h is slowed to ensure that the gate voltage slowly rises near the Miller platform of power transistor MN0. After that, drv_h is delayed by delay_cell_h (at this time, the power transistor can be considered The Miller platform of MN0 has ended), generate the drv_h_d signal, turn on MP2 (MP1 is still on at this time), and fast charge the nodes Gate_h and C0 with the current of Is + Im. The rising slope of Gate_h becomes faster and rises rapidly to Zd1 plus Zd2 At the same time, the breakdown voltage of the clamp element also rises rapidly to the target value, completing the entire turn-on process.

In the control of the MN_hs shutdown process, the turn-on process of the power-down transistor is similar to that shown in Figure 6 for the falling edge, and is not repeated here. The difference is that when the transistor is turned on, the transistor MN2 needs to be turned on through the drv_l signal to discharge the capacitor C0.

FIG. 9 is a diagram showing the operating waveforms of the system as shown in FIG. 8. The drv_h and drv_h_d signals in Figure 9 are inverted from those in Figure 7 and increased Gate_h waveform. As shown in Figure 9, Gate_h guarantees that the gate voltage slowly rises near the Miller platform of the power transistor MN0

Compared with the traditional method, the first implementation manner described above can well compromise between efficiency and EMI. However, due to the different characteristics of the power MOS power transistor MN0, the delay times tdh and tdl are not so easy to control. We hope to be able to determine the starting time of the Miller platform first, and then delay tdh and tdl according to the length of the Miller platform of the power transistor MN0 to achieve better segmentation control.

FIG. 10 is a simplified diagram illustrating a system implementing a gate driving circuit according to another embodiment of the present disclosure. The difference between FIG. 10 and FIG. 6 is that the driving chip further includes two gate threshold sensing comparators comp_hs and comp_ls, which are respectively used to sense the low threshold vl and the high threshold vh of the Miller platform. For example, the Miller platform of the actual device power transistor MN0 is around 5V, the low threshold vl can be set to 4V, and the high threshold vh can be set to 6V.

The high-side threshold sensing is implemented by comp_hs, which generates the Gate_sense_h signal. After the delay of the high-side delay component delay_cell_h, and the drv_h are generated, the drv_h_d signal is generated to control the opening of MN_hs_m. Similarly, the low-side threshold sensing is implemented by comp_ls, which generates The Gate_sense_l signal is delayed by the low-side delay component delay_cell_l and ANDed with drv_l to generate a drv_l_d signal to control the opening of MN_ls_m to achieve segmented control in this way.

FIG. 11 is a diagram showing the operating waveforms of the system as shown in FIG. 10. The signals in FIG. 11 are similar to those in FIG. 7 and will not be repeated here. The difference is that the gate PIN sensing signal Gate_sense_h and Gate_sense_l waveforms are added, and the starting point of the tdh delay time is the rising edge of Gate_sense_h (instead of the rising edge of drv_h), and the starting point of the tdl delay time is the rising edge of Gate_sense_l (Not the rising edge of drv_l).

In the preferred embodiment shown in FIG. 10, a more accurate two-stage turn-on and turn-off control can be achieved, so that a better compromise between efficiency and EMI can be achieved.

FIG. 12 is a simplified diagram illustrating another system for implementing a gate driving circuit according to another embodiment of the present disclosure. The main difference between Figure 12 and Figure 10 is that The two high-side independent MN_hs_m and MN_hs_s are combined into one transistor MN_hs, and the gate voltage of MN_hs is controlled by pre-drive to achieve the high-side two-stage turn-on control. Specifically, MN_hs adds a front control circuit, including current sources Im and Is (Im> Is), the first transistor MP1 and the second transistor MP2 of the PMOS switch, the lower driving transistor MN1, and the NMOS switching transistor MN2. , Zener secondary bodies Zd1, Zd2, and capacitor C0. The Drv_h signal is inverted from drv_h in FIG. 11, so the Gate_sense_h signal here is delayed by delay_cell_h and subsequent inversion, and then ORed with the drv_h signal to generate the drv_h_d signal, which is used to control MP2.

In the process of controlling the opening of MN_hs, the drv_h signal changes from high to low to make MN1 turn off, and MP1 is turned on, and the Gate_h node is charged with a small current Is. At the beginning, Zd2 is turned off, and there is no path between Gate_H and capacitor C0. Therefore, Gate_h will quickly rise to the breakdown voltage point of Zd2. After that, Is starts to charge capacitor C0, and the rising slope of Gate_h becomes slower, ensuring that the gate voltage slowly rises near the Miller platform of power transistor MN0. After sensing that the Gate_sense_h signal changes from low to high, and after the delay_cell_h delay (at this time, the Miller platform of the power transistor MN0 can be considered to have ended), a drv_h_d signal is generated, and MP2 is turned on (at this time MP1 is still on), and Is + The current Im charges the node Gate_h and capacitor C0 quickly. The rising slope of Gate_h becomes faster and rises to the breakdown clamp voltage of Zd1 plus Zd2. At the same time, the gate voltage also rises rapidly to the target value, completing the entire turn-on process.

At the falling edge, the turn-on process of the power-down transistor is similar to that in Figure 10, and is not repeated here. The difference is that during the turn-on process of the power-down transistor, the transistor MN2 needs to be turned on through drv_l to discharge the capacitor C0.

FIG. 13 is a diagram showing the operating waveforms of the system as shown in FIG. 12. The drv_h and drv_h_d signals in FIG. 13 are inverted from those in FIG. 11 and a Gate_h waveform is added.

The present invention may be implemented in other specific forms without departing from the spirit and essential characteristics thereof. For example, the algorithm described in a particular embodiment can be modified and the system architecture The structure does not depart from the basic spirit of the present invention. Therefore, the current embodiment is considered in all aspects as exemplary rather than limiting, and the scope of the present invention is defined by the scope of the attached patent application rather than the above description, and the meaning and scope of falling within the scope of patent application and All changes within the scope of equivalents are thus included in the scope of the invention.

Some or all of the elements of the various embodiments of the invention, alone and / or in combination with at least another element, are one of one or more software elements, one or more hardware elements, and / or software and hardware elements Or multiple combinations to achieve. In another example, some or all of the elements of various embodiments of the present invention are implemented in one or more circuits alone and / or in combination with at least another element, such as in one or more analog circuits and / or Implemented in one or more digital circuits. In yet another example, various embodiments and / or examples of the present invention may be combined.

Although specific embodiments of the present invention have been described, those skilled in the art will appreciate that there are other embodiments equivalent to the described embodiments. Therefore, it will be understood that the present invention is not limited by the specific embodiments shown, but is limited only by the scope of patent application.

MN0‧‧‧Power Transistor

Lm‧‧‧ primary winding

Rcs‧‧‧Induction Resistor

drv_h, drv_l‧‧‧ drive signal

drv_h_d, drv_l_d‧‧‧ signal

pwm‧‧‧Logical control signal of driving part

Vbulk‧‧‧ input AC input voltage after bridge rectification filtering

MN_hs_m, MN_hs_s‧‧‧High-side transistor

MN_ls_m, MN_ls_s‧‧‧Low-side transistor

delay_cell_h‧‧‧High-side delay component

delay_cell_l‧‧‧Low-side delay component

Supply voltage of VCC‧‧‧ driver chip

Claims (9)

A system for implementing a gate driving circuit includes a driving chip including a pre-driver, a first high-side transistor and a second high-side transistor, wherein the driving capability of the first high-side transistor is greater than that of the first high-side transistor. Said driving capability of a second high-side transistor, a high-side delay element, said high-side delay element is connected to said first high-side transistor; a first low-side transistor and a second low-side transistor, wherein said A driving capability of a first low-side transistor is greater than a driving capability of the second low-side transistor, and a low-side delay element connected to the first low-side transistor; and a MOS power stage, Connected to the driving chip, the MOS power stage includes a power transistor, and the power transistor is connected to the high-side delay element and the low-side delay element, respectively; wherein the process of controlling the power transistor to turn on is controlled. Wherein the second high-side transistor is configured to generate a first driving signal at the end of the first Miller platform near the power transistor to turn on the first high-side transistor, so that the second high The transistor is first turned on to drive the power transistor with a first current, and the first high-side transistor is not turned on until the first Miller platform ends, and the power transistor is turned on with a second current. The amplitude of the first current is smaller than the amplitude of the second current; and wherein in the process of controlling the power transistor to be turned off, the second low-side transistor is configured to be close to the first At the end of the two Miller platform, a second driving signal is generated to turn on the first low-side transistor, so that the second low-side transistor is turned on first, and the power transistor is driven with a third current until the second After the Miller platform ends, the first low-side transistor is turned on, and the power transistor is turned off with a fourth current, wherein the magnitude of the third current is smaller than the magnitude of the fourth current. The system of claim 1, wherein the size of the first high-side transistor, the second high-side transistor, the first low-side transistor, and the second low-side transistor are Is adjustable. The system of claim 1, wherein the first Miller platform and the The second Miller platform is the same. The system of claim 1, wherein the first Miller platform and the second Miller platform are different. The system according to item 3 of the scope of patent application, wherein the driving chip further comprises: a first gate threshold sensing comparator connected to the high-side delay element and the power transistor, respectively, and configured to sense High thresholds of the first Miller platform and the second Miller platform and generate a first sensing signal, wherein the first sensing signal is delayed by the high-side delay element and inversely processed to generate the The first driving signal; and a second gate threshold sensing comparator connected to the low-side delay element and the power transistor, respectively, configured to sense the first Miller platform and the second meter The low threshold of the platform is generated and a second sensing signal is generated, wherein the second sensing signal is delayed by the low-side delay element and subjected to inversion processing to generate the second driving signal. A system for implementing a gate driving circuit includes a driving chip including a pre-driver and a time delay component; and a MOS power stage connected to the driving chip, the MOS power stage including a power transistor; wherein The pre-driver includes a first current source and a second current source, wherein the first current source is larger than the second current source, a first transistor and a second transistor of a PMOS switch, and a lower driving transistor, The NMOS switching transistor is initially a first Zener diode, a second Zener diode, and a capacitor that are turned off. The first Zener diode is connected to the first transistor of the PMOS switch and Between the capacitors, the second Zener diode is connected between the NMOS switching transistor and the capacitor, and the time delay component is connected to the first transistor and the second transistor of the PMOS switch, respectively. Connection; wherein in the process of controlling the power transistor to be turned on, the pre-driver is configured to generate a first driving signal to turn off the lower driving transistor while the first transistor of the PMOS switch is conducting After reaching the breakdown voltage of the second Zener diode body second current source begins to charge the delay defined by the delay expires until the capacitor assembly, the front case The driver is further configured to generate a second driving signal to turn on the second transistor of the PMOS switch and keep the first transistor of the PMOS switch on, and the first current source and the second current source are simultaneously The capacitor is charged so as to reach a breakdown voltage of the first Zener secondary body and the second Zener secondary body. The system according to item 6 of the patent application scope, wherein in controlling the power transistor to be turned off, the pre-driver is configured to generate a third driving signal to turn on the NMOS switching transistor and to The capacitor C0 is discharged. The system of claim 6, wherein the delay component defines the delay based at least on an expected duration of a Miller platform of the power transistor. The system according to item 8 of the scope of patent application, further comprising: a first gate threshold sensing comparator, which is respectively connected to the delay component and the power transistor, and is configured to sense the meter of the power transistor. A high threshold of the Ler platform and generate a first sensing signal, wherein the first sensing signal is delayed by the delay element and inversely processed to generate the first driving signal; and a second gate threshold sensing comparison Connected to the delay component and the power transistor, respectively, configured to sense a low threshold value of the Miller platform of the power transistor and generate a second sensing signal, wherein the second sensing signal passes through the The delay element delays and performs inversion processing to generate the third driving signal.