TWI610318B - Resistor device with zero temperature coefficient and method of manufacturing the same, method of manufacturing a resistive material with negative temperature coefficient - Google Patents

Abstract

The present disclosure provides a zero temperature coefficient resistive element including: a semiconductor substrate; a first dielectric layer on the semiconductor substrate; a first titanium nitride layer having a negative temperature coefficient on the first dielectric layer; A second dielectric layer on the first titanium nitride layer; a conductive structure embedded in the second dielectric layer; and a second titanium nitride layer having a positive temperature coefficient and located on the second dielectric layer , Wherein the second titanium nitride layer is connected to the first titanium nitride layer. The present disclosure also provides a method for manufacturing a zero temperature coefficient resistive element and a method for manufacturing a negative temperature coefficient resistive material.

Description

Zero temperature coefficient resistance element and manufacturing method thereof, and manufacturing method of negative temperature coefficient resistance material

The disclosure relates to a resistive element, and more particularly to a zero temperature coefficient resistive element and a manufacturing method thereof.

In semiconductor integrated circuits, in order to provide a stable voltage that does not change with temperature, a resistor with a low temperature coefficient and a band-gap reference circuit are a design method that can save area. For materials used in semiconductor manufacturing processes, it is not yet possible to achieve zero temperature coefficients with a single material.

Among the materials used in the silicon process, metal-like materials can provide lower temperature coefficients for making thin film resistors. Common metal-like materials include tantalum nitride (TaN) and titanium nitride (TiN), where tantalum nitride (TaN) has a negative temperature coefficient (NTC), and titanium nitride (TiN) has a positive temperature coefficient (positive temperature coefficient; PTC). Although previous studies have combined positive temperature coefficient resistance materials and negative temperature coefficient resistance materials to produce the effect of zero temperature resistance, not all semiconductor factories have deposition equipment suitable for two different resistance materials.

Therefore, there is an urgent need for a method capable of manufacturing a resistive material having both positive and negative temperature coefficients in one process technology.

According to an embodiment, the present disclosure provides a zero temperature coefficient resistive element including: a semiconductor substrate; a first dielectric layer on the semiconductor substrate; and a first titanium nitride layer having a negative temperature coefficient on the first dielectric. On the electrical layer; a second dielectric layer on the first titanium nitride layer; a conductive structure embedded in the second dielectric layer; and a second titanium nitride layer having a positive temperature coefficient and located on the first On the two dielectric layers, the second titanium nitride layer is connected to the first titanium nitride layer.

According to another embodiment, the present disclosure provides a method for manufacturing a zero temperature coefficient resistive element, including: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a first titanium nitride layer on the first dielectric Forming a second dielectric layer on the first titanium nitride layer; performing a heat treatment on the second dielectric layer; forming a conductive structure in the second dielectric layer; and forming a second titanium nitride layer On the second dielectric layer, the second titanium nitride layer is connected to the first titanium nitride layer.

According to yet another embodiment, the present disclosure provides a zero temperature coefficient resistive element including: a semiconductor substrate; a gate structure having a positive temperature coefficient on the semiconductor substrate; and a resistance layer having a negative temperature coefficient on the gate Structurally; where the resistive layer is in direct contact with the gate structure.

According to yet another embodiment, the present disclosure provides a method for manufacturing a zero temperature coefficient resistive element, including: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a resistive layer on the gate structure; forming a dielectric Layer on the resistive layer; and performing a heat treatment on the dielectric layer.

According to yet another embodiment, the present disclosure provides a negative temperature coefficient A method for manufacturing a resistive material includes: providing a resistive material having a positive temperature coefficient; and performing a heat treatment on the resistive material so that the resistive material has a negative temperature coefficient; wherein the resistive material is titanium nitride.

In order to make the above and other objects, features, and advantages of the present disclosure more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings, as follows:

100, 300‧‧‧ zero temperature coefficient resistance element

102, 302‧‧‧ semiconductor substrate

104‧‧‧First dielectric layer

106‧‧‧ first titanium nitride layer

108‧‧‧Second dielectric layer

110‧‧‧ conductive structure

112‧‧‧metal layer

114‧‧‧second titanium nitride layer

200, 400, 500‧‧‧ method flow chart

202-214, 402-410, 502-504‧‧‧ steps

304‧‧‧polycrystalline silicon layer

306‧‧‧metal silicide layer

308‧‧‧Gate structure

310‧‧‧resistance layer

This disclosure is best read in conjunction with the drawings and detailed description for easy understanding. It is emphasized that, in accordance with standard industry practice, individual features are not necessarily drawn to scale. In fact, for the sake of clarity, the size of each feature may be arbitrarily enlarged or reduced.

FIG. 1 is a cross-sectional view showing a zero temperature coefficient resistive element in an intermediate stage of a process according to an embodiment of the present disclosure; FIG. 2 is a flowchart showing a method for manufacturing a zero temperature coefficient resistive element according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view showing a zero temperature coefficient resistive element in an intermediate stage of a process according to another embodiment of the present disclosure; FIG. 4 is a flowchart showing a method for manufacturing a zero temperature coefficient resistive element according to another embodiment of the present disclosure; According to yet another embodiment of the present disclosure, a flowchart of a method for manufacturing a negative temperature coefficient resistive material is shown. Figures 6A and 7A show temperature coefficients of resistive materials manufactured in different processes according to some embodiments of the present disclosure. This disclosure shows some examples showing different manufacturing processes And FIG. 8 is a diagram showing temperature coefficients of two kinds of resistance materials in a zero temperature coefficient resistance element according to an embodiment of the present disclosure.

Several different embodiments are listed below according to the different features of this disclosure. The specific elements and arrangements in this disclosure are for simplicity, but this disclosure is not limited to these embodiments. For example, the description of forming the first element on the second element may include an embodiment in which the first element is in direct contact with the second element, and also includes an additional element formed between the first element and the second element such that the first element An embodiment in which an element is not in direct contact with a second element. In addition, for the sake of brevity, the disclosure is represented by repeated element symbols and / or letters in different examples, but it does not mean that there is a specific relationship between the embodiments and / or structures.

In addition, embodiments may use terms related to space, such as "above," "below," "higher," "lower," and similar terms. These relational words are for the convenience of describing the figure. The relationship between one element (s) or feature and another element (s) or feature in the formula. These spatial relations include different positions of the device in use or operation, as well as the positions described in the drawings. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted the same way.

It must be understood that when a layer is "on" another layer or substrate, it may mean directly on the other layer or substrate, or another layer sandwiched between other layers or substrates.

Some embodiments of the present disclosure provide a zero temperature coefficient resistive element and a method for manufacturing the same, using a common metal-like material, titanium nitride (TiN), through The arrangement of the process steps enables the titanium nitride (TiN) to undergo different heat treatments in different process steps, so that the titanium nitride (TiN) formed in the different process steps has a positive temperature coefficient or a negative temperature coefficient. In this way, the effect of zero temperature coefficient can be obtained by combining titanium nitride with positive temperature coefficient and negative temperature coefficient with appropriate proportions.

Some embodiments of the present disclosure also provide another aspect of a zero temperature coefficient resistive element and a method for manufacturing the same. The polycrystalline silicon gate structure is connected to a commonly used metal-like material, titanium nitride (TiN). A polycrystalline silicon gate structure with a positive temperature coefficient and a resistive material with a negative temperature coefficient can obtain the effect of a zero temperature coefficient.

In the method for manufacturing a zero temperature coefficient resistance element provided in the embodiments of the present disclosure described above, a metal-like material having a positive temperature coefficient (for example, titanium nitride) is converted into a resistance material having a negative temperature coefficient by using heat treatment.

Some embodiments of the disclosure are described below. Figures 1 and 3 are cross-sectional views showing the middle stage of forming a zero temperature coefficient resistive element according to some embodiments. FIG. 2 and FIG. 4 are flowcharts of a method for manufacturing a zero temperature coefficient resistive element according to some embodiments. Additional operations may be provided before, during, and / or after the phases described in Figures 1 to 4, such as some conventional semiconductor process steps. In different embodiments, some of the aforementioned stages may be replaced or removed. Additional features can be added to the semiconductor element structure. In various embodiments, some of the elements described below may be replaced or removed. For the purpose of clear description, some elements are omitted in the sectional views of FIGS. 1 and 3.

FIG. 1 is a cross-sectional view showing a zero temperature coefficient resistive element 100 at an intermediate stage of a process according to an embodiment of the disclosure.

As shown in FIG. 1, the zero temperature coefficient resistive element 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may be formed of a suitable semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, the compound material is like silicon germanium, silicon carbide, arsenic gallium, indium gallium, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, Gallium indium phosphide, a combination of the foregoing materials, and similar materials may use other crystal orientations.

In addition, the semiconductor substrate 102 may include a silicon-on-insulator (SOI) substrate. Generally, a silicon-on-insulator (SOI) substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, silicon-on-insulator (SOI), and silicon-germanium on insulator (SGOI). , Or a combination of the foregoing. The semiconductor substrate 102 may be doped with a p-type dopant, such as boron, aluminum, gallium, or a similar material, although the semiconductor substrate 102 may be doped with a n-type dopant as is conventionally known.

The first dielectric layer 104 is located on the semiconductor substrate 102. The material of the first dielectric layer 104 may include Tetra Ethyl Ortho Silicate (TEOS), or other similar materials. In some embodiments, the first dielectric layer 104 can be used as an etch stop layer (ESL).

The first titanium nitride layer 106 is located on the first dielectric layer 104. The first titanium nitride layer 106 has a negative temperature coefficient of approximately -300 to -600 ppm / ° C. In some embodiments, the thickness of the first titanium nitride layer 106 may be between 100 and 1000 angstroms, for example: 400 angstroms, 600 angstroms, or 800 angstroms. Here, the first titanium nitride layer 106 may also be referred to as a first thin film resistance layer.

The second dielectric layer 108 is located on the first titanium nitride layer 106. The material of the second dielectric layer 108 may include Boron-Doped Phospho-Silicate Glass (BPSG), Phospho-Silicate Glass (PSD), Boro-Silicate Glass; BSG), or other similar materials. The second dielectric layer 108 may include a conductive structure 110 therein. The material of the conductive structure 110 may include a suitable conductive material such as a copper alloy, aluminum, tungsten, silver, any combination of the foregoing materials, and / or the like. In some embodiments, the conductive structure 110 may be, for example, a contact.

The metal layer 112 is on the second dielectric layer 108. The distance between the metal layers 112 may be determined according to design. The thickness of the metal layer 112 may be greater than about 0.4 μm, but the present invention is not limited thereto, and may be determined by the technical specifications of the semiconductor at the time.

The second titanium nitride layer 114 is located on the second dielectric layer 108. More specifically, the second titanium nitride layer 114 covers the upper surface of the second dielectric layer 108, and extends to one side wall and a part of the upper surface of the metal layer 112, as shown in FIG. 1. The second titanium nitride layer 114 is in contact with the second dielectric layer 108 and the metal layer 112 via its back surface. The second titanium nitride layer 114 has a positive temperature coefficient of about 300 to 600 ppm / ° C. The second titanium nitride layer 114 is connected to the first titanium nitride layer 106 through the metal layer 112 and the conductive structure 110. In some embodiments, the thickness of the second titanium nitride layer 114 may be between 100 and 1000 angstroms, for example: 400 angstroms, 600 angstroms, or 800 angstroms. Here, the second titanium nitride layer 114 may also be referred to as a second thin film resistance layer.

As shown in Fig. 1, a first thin-film resistor layer having a negative temperature coefficient (that is, the first titanium nitride layer 106) and a second thin-film resistor layer having a positive temperature coefficient (that is, a second titanium nitride layer) 114) Connected / connected in series to produce a zero temperature coefficient effect, thereby forming a zero temperature coefficient resistance element 100.

It is worth mentioning that, compared to previous studies, the combination of two different resistance materials using a positive temperature coefficient and a negative temperature coefficient, for example: tantalum nitride (TaN) with a negative temperature coefficient and titanium nitride with a positive temperature coefficient (TiN) to generate the effect of zero temperature resistance. According to the zero temperature resistance element provided by some embodiments of the present disclosure, the same resistance material (titanium nitride) has a positive temperature coefficient and a negative temperature coefficient through the arrangement of process steps. Then, titanium nitride with a positive temperature coefficient and a negative temperature coefficient is combined according to an appropriate ratio to produce the effect of a zero temperature coefficient. Here, the bonding of the titanium nitride can be achieved through series or parallel. That is to say, compared with the previous research that requires deposition equipment suitable for two different resistance materials, in some embodiments of the disclosure, only one deposition equipment suitable for titanium nitride is needed to achieve the purpose of manufacturing a zero temperature coefficient device .

FIG. 2 is a flowchart 200 of a method for manufacturing a zero temperature coefficient resistive element according to an embodiment of the disclosure. For the purpose of explanation, the following description will be described with reference to FIGS. 1 and 2.

First, step 202 is performed to provide a semiconductor substrate 102. The semiconductor substrate 102 may be formed of a suitable semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, the compound material is like silicon germanium, silicon carbide, arsenic gallium, indium gallium, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, Gallium indium phosphide, a combination of the foregoing materials, and similar materials may use other crystal orientations.

In addition, the semiconductor substrate 102 may include a silicon-on-insulator (SOI) substrate. Generally, silicon-on-insulator (SOI) The substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI), silicon germanium on insulator (SGOI), or a combination of the foregoing materials. The semiconductor substrate 102 may be doped with a p-type dopant, such as boron, aluminum, gallium, or a similar material, although the semiconductor substrate 102 may be doped with a n-type dopant as is conventionally known.

Next, step 204 is performed to form a first dielectric layer 104 on the semiconductor substrate 102. The material of the first dielectric layer 104 may include Tetra Ethyl Ortho Silicate (TEOS), or other similar materials. The first dielectric layer 104 can be deposited by a suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), A spin-on process, a sputtering process, or a combination of the foregoing processes.

Next, step 206 is performed to form a first titanium nitride layer 106 on the first dielectric layer 104. The first titanium nitride layer 106 can be formed by a suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of the foregoing processes to a thickness of 100 to 600 angstroms, for example, 400 angstroms.

Next, step 208 is performed to form a second dielectric layer 108 on the first titanium nitride layer 106. The material of the second dielectric layer 108 may include Boron-Doped Phospho-Silicate Glass (BPSG), Phospho-Silicate Glass (PSD), Boro-Silicate Glass; BSG), or other similar materials. The second dielectric layer 108 may be deposited by a suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), A spin-on process, a sputtering process, or a combination of the foregoing processes.

Next, step 210 is performed to perform a heat treatment on the second dielectric layer 108. In one embodiment, the heat treatment is a boron-doped phosphorus-silica glass heat treatment (BPSG flow), and the process temperature is between 800 ° C and 900 ° C. In other embodiments, the temperature range of the heat treatment may be between 460 ° C and 900 ° C.

It should be noted that, in general silicon processes, titanium nitride (TiN) is usually used as a metal energy barrier layer after being used in a contact layer to avoid diffusion and / or provide metal adhesion. The subsequent process temperatures are lower than 450 ° C. However, step 206 is to form the first titanium nitride layer 106 before the contact layer is formed. Therefore, the first titanium nitride layer 106 will undergo the heat treatment of the subsequent step 210, such as boron-doped phosphorus -Silicon glass heat treatment (BPSG flow). It has been found through experiments that after the first titanium nitride layer 106 is subjected to a boron-doped phosphorus-silica glass heat treatment (BPSG flow) (process temperature ranging from 800 ° C to 900 ° C), the temperature coefficient of the heat-treated titanium nitride is changed from the original The positive temperature coefficient becomes a negative temperature coefficient. Because in the process of boron-doped phosphorus-silica glass heat treatment (BPSG flow), titanium nitride reacts with the upper oxide to produce a new structure, or titanium nitride itself is caused by boron-doped phosphorus-silica glass heat treatment ( BPSG flow), which causes a phase change, so that the temperature sensitivity and characteristics of the first titanium nitride layer 106 are changed. Therefore, after the heat treatment is performed in step 210, the first titanium nitride layer 106 is transformed into a resistive material layer having a negative temperature coefficient.

Next, step 212 is performed to form a conductive structure 110 in the second dielectric layer 108. The second dielectric layer 108 can be patterned using, for example, photolithographic masking and etching processes. According to this, the photolithographic mask is formed on the second dielectric layer 108 and then exposed to a patterned light. After exposure, remove a predetermined portion of the lithographic mask to expose the second dielectric layer underneath 108, followed by etching to remove the exposed portion, and patterning the second dielectric layer 108 to form an opening. It should be noted that the opening may be formed by any other suitable semiconductor patterning technology, such as an etching process, a laser ablation process, any combination of the foregoing processes, and / or a similar process.

In some embodiments, a barrier layer and a seed layer may be deposited on the surface of the opening. Next, a conductive material may be filled into the opening to form a conductive structure 110 in contact with the first titanium nitride layer 106. The conductive material filled in the opening may be any suitable conductive material, such as copper alloy, aluminum, tungsten, silver, any combination of the foregoing materials, and / or the like. The conductive material may be formed using a suitable technique, such as an electro-less plating process, chemical vapor deposition (CVD), electroplating, and / or the like.

According to some embodiments, a planarization process is performed to remove excess conductive material. The planarization process may be performed using a suitable technique, such as a combination of grinding, polishing, and / or chemical etching, etching, and polishing techniques. According to some embodiments, the planarization process may be performed using a chemical mechanical polishing (CMP) process.

Before step 214 is performed, a metal layer 112 may be formed on the second dielectric layer 108 and the conductive structure 110. The metal layer 112 may be deposited by any suitable process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the thickness of the metal layer 112 may be greater than about 0.4 μm, for example, it may be between 0.4 μm and 0.5 μm. However, the present invention is not limited to this, and may be determined by the current technical specifications of the conductor technology.

Next, step 214 is performed to form a second titanium nitride layer 114 on the second dielectric layer 108. The first titanium nitride layer 106 can be formed by a suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of the foregoing processes to a thickness of 100 to 600 angstroms, for example, 400 angstroms. In some embodiments, the second titanium nitride layer 114 covers the upper surface of the second dielectric layer 108 and extends to a side wall and a part of the upper surface of the metal layer 112. As shown in FIG. 1, the second titanium nitride layer 114 is connected / connected to each other through the metal layer 112, the conductive structure 110, and the first titanium nitride layer 106. It should be noted that after step 214, the process temperature experienced by the second titanium nitride layer 114 is less than about 450 ° C. It is found through experiments that the titanium nitride formed at such a process temperature has a positive temperature coefficient.

The manufacturing method provided in this embodiment arranges titanium nitride in different process steps. The first titanium nitride layer formed before the contact layer undergoes heat treatment at a process temperature between 460 ° C and 900 ° C. Boron-doped phosphorus-silica glass heat treatment (BPSG flow), so it is transformed into a resistance material with a negative temperature coefficient; and the second titanium nitride layer formed after the contact layer is less than about 450 ° C because of the process temperature experienced, so It is a resistive material with a positive temperature coefficient. Therefore, the manufacturing method provided in this embodiment forms titanium nitride with a positive temperature coefficient and a negative temperature coefficient in different steps of the manufacturing process, and combines the two to generate a zero temperature coefficient resistance element.

FIG. 3 is a cross-sectional view showing a thin film resistor element 300 at an intermediate stage of a process according to another embodiment of the disclosure. The zero temperature coefficient resistive element 300 includes a semiconductor substrate 302. For the material of the semiconductor substrate 302, reference may be made to the content described in FIG.

The gate structure 308 is located on the semiconductor substrate 302. Gate structure 308 Has a positive temperature coefficient, about 500 ~ 800ppm / ℃. In some embodiments, the gate structure 308 may include a polycrystalline silicon layer 304 and a metal silicide layer 306. The polycrystalline silicon layer 304 is located on the semiconductor substrate 302. In some embodiments, the polycrystalline silicon layer 304 may be formed of doped or undoped polycrystalline silicon. The metal silicide layer 306 is located on the polycrystalline silicon layer 304. In some embodiments, the metal silicide layer 306 may be formed of a suitable material, such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, or a combination of the foregoing materials.

The resistance layer 310 is located on the gate structure 308, and the resistance layer 310 is in direct contact with the gate structure 308. More specifically, the resistance layer 310 covers the upper surface of the semiconductor substrate 302 and extends to one side wall and a part of the upper surface of the gate structure 308. The resistance layer 310 has a negative temperature coefficient of approximately -300 to -600 ppm / ° C. The material of the resistance layer 310 is selected from the group consisting of titanium nitride (TiN). In some embodiments, the thickness of the resistance layer 310 may be between 100 and 1000 angstroms, for example: 400 angstroms, 600 angstroms, or 800 angstroms. Here, the resistance layer 310 can also be regarded as a thin film resistance layer.

As shown in FIG. 3, the thin film resistance layer 310 having a negative temperature coefficient and the gate structure 308 having a positive temperature coefficient are connected / connected in series, and a zero temperature coefficient effect is generated, thereby forming a zero temperature coefficient resistance element 300.

It is worth mentioning that although previous studies have used a combination of two different resistance materials with a positive temperature coefficient and a negative temperature coefficient, for example: tantalum nitride (TaN) with a negative temperature coefficient and titanium nitride (TaN) with a positive temperature coefficient ( TiN) to produce the effect of zero temperature resistance. However, such a process method requires two depositions of the resistance material, and needs to have deposition equipment suitable for two different resistance materials. In contrast, the zero-temperature resistance element provided by some embodiments according to the present disclosure The component is directly formed with a resistive material (for example: titanium nitride) on the gate structure. After a subsequent heat treatment, the resistive material (for example: titanium nitride) has a negative temperature coefficient, and the gate structure is originally formed after the heat treatment. Will have a positive temperature coefficient, thereby generating the effect of a zero temperature coefficient, forming a zero temperature coefficient resistance element. That is, compared with the previous research that required two depositions of the resistive material and the use of two different deposition devices, in some embodiments of the present disclosure, only one deposition of the resistive material is needed and only one suitable for the resistive material is needed. The deposition equipment (such as titanium nitride) can achieve the purpose of manufacturing a zero temperature coefficient resistance element.

FIG. 4 is a flowchart 400 of a method for manufacturing a zero temperature coefficient resistive element according to another embodiment of the disclosure. For the purpose of explanation, the following description will be described with reference to FIGS. 3 and 4.

First, step 402 is performed to provide a semiconductor substrate 302. For the material of the semiconductor substrate 302, reference may be made to the content described in FIG.

Next, step 404 is performed to form a gate structure 308 on the semiconductor substrate 302. The gate structure 308 has a positive temperature coefficient of approximately 300-600 ppm / ° C. In some embodiments, the gate structure 308 may include a polycrystalline silicon layer 304 and a metal silicide layer 306. A polycrystalline silicon layer 304 is formed on the semiconductor substrate 302. In some embodiments, the polycrystalline silicon layer 304 may be formed of doped or undoped polycrystalline silicon. The polycrystalline silicon layer 304 may be formed by a suitable process, such as low-pressure chemical vapor deposition (LPCVD), and / or a similar process. A metal silicide layer 306 is formed on the polycrystalline silicon layer 304. In some embodiments, the metal silicide layer 306 may be formed of a suitable material, such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, or a combination of the foregoing materials. The metal silicide layer 306 may be formed by a suitable process, such as chemical vapor deposition (CVD), and / or the like. Process.

Next, step 406 is performed to form a resistance layer 310 on the gate structure 308. The material of the resistance layer 310 is selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN). The resistive layer 310 may be formed by a suitable process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination of the foregoing processes to a thickness of 100 to 600 angstroms, for example, 400 angstroms.

Next, step 408 is performed to form a dielectric layer (not shown) on the first resistive layer 310. The material of the dielectric layer may include Boron-Doped Phospho-Silicate Glass (BPSG), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG) ), Tetra Ethyl Ortho Silicate (TEOS), Spin-On-Glass (SOG), atmospheric pressure chemical vapor deposition (APCVD) oxide, or other similar materials. The dielectric layer can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), spin coating A spin-on process, a sputtering process, or a combination of the foregoing processes.

Next, step 410 is performed to perform a heat treatment on the dielectric layer. In one embodiment, the heat treatment is a boron-doped phosphorus-silica glass heat treatment (BPSG flow), and the process temperature is between 800 ° C and 900 ° C. In other embodiments, the temperature range of the heat treatment may be between 460 ° C and 900 ° C.

It should be noted that, in step 406, the resistive layer 310 is formed before the contact layer is formed. Therefore, the resistive layer 310 will undergo a subsequent heat treatment in step 410, such as a boron-doped phosphorus-silica glass heat treatment ( BPSG flow). It was found through experiments that when the resistance layer 310 was heat-treated by boron-doped phosphor-silica glass (BPSG flow) (the process temperature is between 800 ° C. and 900 ° C.), the temperature coefficient of the resistance layer 310 is changed from an original positive temperature coefficient to a negative temperature coefficient. Taking titanium nitride as an example, its temperature coefficient has changed from about 300 to 600 ppm / ° C to about -300 to -600 ppm / ° C, because during the process of boron-doped phosphorus-silica glass heat treatment (BPSG flow), titanium nitride and The upper oxide reacts to produce a new structure, or the titanium nitride itself undergoes a phase change due to boron-doped phosphorus-silica glass heat treatment (BPSG flow), which changes the sensitivity and characteristics of titanium nitride to temperature. Therefore, after the heat treatment is performed in step 410, the resistance layer 310 is transformed into a resistance layer having a negative temperature coefficient. At the same time, since the gate structure 308 after heat treatment originally has a positive temperature coefficient, this embodiment combines the gate structure 308 with a positive temperature coefficient and the resistance layer 310 with a negative temperature coefficient in the same layer, resulting in Effect of zero temperature coefficient.

In the manufacturing method provided in this embodiment, a resistance layer (for example: titanium nitride) is directly formed on the gate structure, and a resistance layer (for example: titanium nitride) formed before the contact layer is subjected to a process temperature between Heat treatment at 460 ℃ ~ 900 ℃, such as boron-doped phosphorus-silica glass heat treatment (BPSG flow), is transformed into a resistive material with a negative temperature coefficient; and the gate structure after the heat treatment originally has a positive temperature coefficient. Therefore, the manufacturing method provided in this embodiment replaces the positive temperature coefficient resistor with a gate structure having a positive temperature coefficient in a process technology, and combines a resistance material (eg, titanium nitride) with a negative temperature coefficient after heat treatment to Generates a zero temperature coefficient resistive element.

FIG. 5 is a flowchart 500 of a method for manufacturing a negative temperature coefficient resistance material according to an embodiment of the disclosure.

First, step 502 is performed to provide a voltage having a positive temperature coefficient. 阻 材料。 Resistance material. Next, step 504 is performed to perform a heat treatment on the resistive material so that the resistive material has a negative temperature coefficient. In one embodiment, the resistive material is titanium nitride (TiN), and its temperature coefficient is changed from about 300 to 600 ppm / ° C to about -300 to -600 ppm / ° C before and after the heat treatment. In some embodiments, the temperature range of the heat treatment may be between 460 ° C and 900 ° C. In one embodiment, the heat treatment is boron-doped phosphorus-silica glass heat treatment (BPSG flow), and the temperature range is about 800 ° C to 900 ° C.

It should be noted that the above-mentioned embodiments are for illustrative purposes only, and the scope of this disclosure is not limited thereto. In the following, the temperature coefficient of resistivity (TCR) is measured for the resistive materials formed in different processes, and the TEM images of the resistive materials are observed.

Resistivity temperature coefficient detection

The temperature coefficient of resistivity (TCR) of the heat-treated titanium nitride is measured. First, at temperature T0, use 4156 Sweep V, Sense I, and find R0 from V / I. Next, change the test temperature to T1, obtain R1 in the same way, and obtain the resistance change rate at temperature T1 from (R1-R0) / R0. For other temperatures, the measured results are shown in Figure 6A. The "with dummy bars" and "no dummy bars" shown in Figure 6A represent different component layout graphics. W stands for component width and L stands for component length. The Y-axis (R-R0) represents the change rate of the specific temperature resistance from the reference temperature resistance. The resistance is measured by a general electrical parameter analyzer (Agilent 4156).

It can be seen from FIG. 6A that the heat-treated titanium nitride has a negative temperature coefficient.

In addition, the transmission electron microscope The treated titanium nitride layer was analyzed. Figure 6B shows a TEM image of the heat-treated titanium nitride layer. As shown in Figure 6B, two different structures can be seen, the lower layer is the originally deposited titanium nitride, and the upper layer is an additional structure after heat treatment. The results show that after heat treatment of the titanium nitride layer, it may react with the oxide above to produce a new structure.

On the other hand, the temperature coefficient of resistivity (TCR) of titanium nitride that has not been heat-treated is measured. Similarly, at temperature T0, use 4156 Sweep V, Sense I to find R0 from V / I. Next, change the test temperature to T1, obtain R1 in the same way, and obtain the resistance change rate at temperature T1 from (R1-R0) / R0. Other temperature analogies, the measured results are shown in Figure 7A. The "with dummy bars" and "no dummy bars" shown in Figure 7A represent different component layout graphics. W stands for component width and L stands for component length. The Y-axis (R-R0) represents the change rate of the specific temperature resistance from the reference temperature resistance. The resistance is measured by a general electrical parameter analyzer (Agilent 4156). It can be seen from FIG. 7A that titanium nitride which has not been heat-treated has a positive temperature coefficient.

In addition, the titanium nitride layer that was not heat-treated in the process was analyzed by a transmission electron microscope. Figure 7B shows a TEM image of the titanium nitride layer without heat treatment. As shown in FIG. 7B, the titanium nitride layer without heat treatment still has only one structure.

FIG. 8 shows the temperature coefficients of two kinds of resistance materials in the zero temperature coefficient resistance element provided by an embodiment of the disclosure. Here, the zero temperature coefficient resistive element is obtained by combining a polycrystalline silicon gate structure with a titanium nitride layer and subjecting it to heat treatment. As shown in FIG. 8, in this zero temperature coefficient resistive element, the polycrystalline silicon gate structure) has a positive temperature coefficient, and the titanium nitride layer has a negative temperature coefficient.

In summary, the present disclosure provides a zero temperature coefficient resistive element and a method for manufacturing the same. Through the arrangement of process steps, a titanium nitride layer is formed before a contact layer, and the titanium nitride layer undergoes subsequent process temperatures. After the boron-doped phosphor-silica glass heat treatment (BPSG flow) between 800 ° C and 900 ° C, it is transformed into a resistive material with a negative temperature coefficient. This titanium nitride layer with a negative temperature coefficient is combined with a resistor element with a positive temperature coefficient, such as a titanium nitride layer or a gate structure, to obtain a zero temperature coefficient resistor element. The manufacturing methods of the zero temperature coefficient resistance elements provided in this disclosure all use heat treatment to transform a metal-like material (for example, titanium nitride) with a positive temperature coefficient into a resistance material with a negative temperature coefficient.

Although the present disclosure has been disclosed as above with several preferred embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field may make arbitrary changes without departing from the spirit and scope of the present disclosure. And retouching, so the scope of protection of this disclosure shall be determined by the scope of the attached patent application.

200‧‧‧Method flow chart

202-214‧‧‧step

Claims (17)

A zero temperature coefficient resistive element includes: a semiconductor substrate; a first dielectric layer on the semiconductor substrate; a first titanium nitride layer having a negative temperature coefficient on the first dielectric layer, wherein the The first titanium nitride layer undergoes a heat treatment and includes an oxide layer and has the negative temperature coefficient; a second dielectric layer is located on the first titanium nitride layer; a conductive structure is embedded in the second dielectric layer. An electrical layer; a metal layer on the second dielectric layer and the conductive structure; and a second titanium nitride layer with a positive temperature coefficient on the second dielectric layer, wherein the second nitride A titanium layer is connected to the first titanium nitride layer through the conductive structure and the metal layer. The zero temperature coefficient resistive element according to item 1 of the scope of the patent application, wherein the material of the first dielectric layer includes Tetra Ethyl Ortho Silicate (TEOS). The zero temperature coefficient resistive element according to item 1 of the application, wherein the material of the second dielectric layer comprises a boron-doped phosphor-silicon glass (BPSG). A method for manufacturing a zero temperature coefficient resistive element includes: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a first titanium nitride layer on the first dielectric layer; forming a first Two dielectric layers on the first titanium nitride layer; Performing a heat treatment on the second dielectric layer; forming a conductive structure in the second dielectric layer; forming a metal layer on the second dielectric layer and the conductive structure; and forming a second titanium nitride layer On the second dielectric layer, the second titanium nitride layer is connected to the first titanium nitride layer through the conductive structure and the metal layer; and the first titanium nitride layer includes an oxide after the heat treatment. Floor. According to the method for manufacturing a zero temperature coefficient resistive element described in item 4 of the scope of patent application, wherein the material of the first dielectric layer includes Tetra Ethyl Ortho Silicate (TEOS). According to the method for manufacturing a zero temperature coefficient resistive element according to item 4 of the scope of the patent application, wherein the material of the second dielectric layer includes a boron-doped phosphor-silicon glass (BPSG). According to the method for manufacturing a zero temperature coefficient resistive element described in item 4 of the scope of patent application, the temperature range of the heat treatment is between 460 and 900 ° C. A zero temperature coefficient resistance element includes: a semiconductor substrate; a gate structure, after a heat treatment, has a positive temperature coefficient and is located on the semiconductor substrate; and a resistance layer having a negative temperature coefficient and is located on the gate structure, The resistive layer includes an oxide layer and has the negative temperature coefficient after the heat treatment; wherein the resistive layer is in direct contact with the gate structure. The zero temperature coefficient resistive element according to item 8 of the patent application scope, wherein the gate structure includes a polycrystalline silicon layer and a metal silicide layer, and the resistive layer Connected to this metal silicide layer. The zero temperature coefficient resistive element according to item 8 of the scope of the patent application, wherein the material of the resistive layer is titanium nitride (TiN). A method for manufacturing a zero temperature coefficient resistance element includes: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a resistance layer on the gate structure; forming a dielectric layer on the resistance layer; And performing a heat treatment on the dielectric layer; wherein the resistance layer includes an oxide layer after the heat treatment. According to the method for manufacturing a zero temperature coefficient resistive element according to item 11 of the scope of patent application, the gate structure includes a polycrystalline silicon layer and a metal silicide layer, and the resistance layer is connected to the metal silicide layer. According to the method for manufacturing a zero-temperature-coefficient resistor element according to item 11 of the scope of patent application, the material of the resistance layer is titanium nitride (TiN). The manufacturing method of the zero temperature coefficient resistive element according to item 11 of the scope of the patent application, wherein the material of the dielectric layer includes a boron-doped phosphor-silicon glass (BPSG), phosphor-silicon glass (Phosphosilicate Glass (PSG)), Boro-Silicate Glass (BSG), Tetra Ethyl Ortho Silicate (TEOS), Spin-On-Glass (SOG), atmospheric pressure Chemical vapor deposition (APCVD) oxide, or a combination of the foregoing materials. According to the method for manufacturing a zero-temperature-coefficient resistor element according to item 11 of the scope of patent application, the temperature range of the heat treatment is between 460 and 900 ° C. A method for manufacturing a negative temperature coefficient resistance material includes: providing a resistance material having a positive temperature coefficient; and performing a heat treatment on the resistance material so that the resistance material includes an oxide layer and having a negative temperature coefficient; wherein the resistance material For titanium nitride. The method for manufacturing a negative temperature coefficient resistive material as described in item 16 of the scope of patent application, wherein the temperature range of the heat treatment is between 460 ~ 900 ° C.