TWI606492B - Plasma doping a non-planar semiconductor device - Google Patents

Description

Plasma doping of non-planar semiconductor devices

The present invention relates to the fabrication of semiconductor devices, and more particularly to plasma doping methods for non-planar semiconductor devices.

As semiconductor device manufacturers continue to shrink the size of the transistor device to achieve better circuit density and higher performance, short channel effects, such as parasitic capacitance and off-state leakage, can hinder the characteristics of the transistor device. Recently, in the semiconductor process, fin field effect transistors (FinFETs), such as double gate transistors, three gate transistors, and wraparound gate transistors, have been developed to control short channel effects. The FinFET has a fin portion that protrudes from the surface of the substrate. The fin portion produces a longer equivalent channel length, thus reducing the short channel effect.

The fin portion defines the channel, source/drain region, and source/drain extension region of the FinFET. Similar to conventional planar metal oxide semiconductor devices (MOSFETs), the channel, source/drain regions, and source/drain extension regions of the FinFET device are doped with impurities (ie, doped) to produce the desired electronic properties. Ideally, the doping of each of these regions along the height of the fin To. Poor doping uniformity can cause undesirable changes in the threshold voltage across the gate height and source/drain breakdown.

Plasma doping (also known as plasma infiltration ion implantation) is a method of doping the FinFET device's channel, source/drain regions, and source/drain extension regions. However, the use of plasma doping to achieve highly uniform doping characteristics across the fin portion can be challenging. The plasma sheath formed during plasma doping will be very dependent on the size of the fin portion, so the plasma sheath will be inconsistent with the fin portion. Therefore, the plasma doping will mainly occur in the vertical direction, and the upper portion of the fin portion will be heavierly doped than the lower portion of the fin portion.

In an exemplary embodiment, a substrate is provided having a non-planar semiconductor body formed thereon. A substrate having a non-planar semiconductor body can be placed into the chamber. A plasma that can contain dopant ions can be formed in the chamber. A first bias voltage can be generated to implant a region of dopant ions in the non-planar semiconductor body. A second bias voltage can be generated to implant dopant ions in the same region. In one example, the first bias voltage and the second bias voltage can be different.

100‧‧‧Doping system

102‧‧‧ chamber

104‧‧‧Substrate

106‧‧‧ support

108‧‧‧ gas plate

110‧‧‧ sprinkler

114‧‧‧With network

116‧‧‧RF offset power

118‧‧‧With network

120‧‧‧ Plasma

122‧‧‧Electrochemical sheath

124‧‧‧vacuum pump

126‧‧‧Electrode screen

128‧‧‧ throttle valve

130‧‧‧ Controller

132‧‧‧ processor

134‧‧‧ main memory

136‧‧‧Storage medium

138‧‧‧Support device

300‧‧‧FinFET device

302‧‧‧Substrate

304‧‧‧Fin section

312‧‧‧Channel area

313‧‧‧Source extension area

314‧‧‧ source area

315‧‧‧Bungee extension area

316‧‧‧Bungee area

318‧‧‧ Plasma

319‧‧‧depth

320‧‧‧Electrochemical sheath

321‧‧‧First bias

323‧‧‧second bias

324‧‧‧ lower part

325‧‧ depth

Section 326‧‧‧

502‧‧‧Substrate

504‧‧‧Fin section

506‧‧‧ Adjacent structure

508‧‧‧ Height

510‧‧‧ critical size

511‧‧‧ liner

512‧‧‧ thickness

514‧‧‧PTS layer

515‧‧‧ discontinuous interface

516‧‧‧depth

518‧‧‧Electrochemical sheath

520‧‧ depth

521‧‧‧First bias

522‧‧‧ Plasma

523‧‧‧second bias

524‧‧‧ arrow

600‧‧‧FinFET device

602‧‧‧Substrate

604‧‧‧Fin section

606‧‧‧ source area

608‧‧‧Bungee area

610‧‧‧Source extension area

612‧‧‧Bungee extension area

614‧‧‧Channel area

616‧‧‧PTS layer

620‧‧‧ gate dielectric layer

622‧‧ depth

628‧‧" interface

Figure 1 is a schematic block diagram of an exemplary plasma doping system that can be used in a plasma doped FinFET device.

Figure 2 shows an example process for a plasma doped FinFET device

3A to 3D are shown in the plasma doped FinFET package Sectional view of an example FinFET at different stages in the sample process

Figure 4 shows another example process for a plasma doped FinFET device.

5A through 5G are cross-sectional views of exemplary FinFETs showing different stages in an exemplary process of a plasma doped FinFET device

6A-6C are cross-sectional views showing an exemplary FinFET device formed by an exemplary process of a doped FinFET device

A method of plasma doping to a non-planar semiconductor device is described. The following description is made to enable a person of ordinary skill in the art to make and use the various embodiments. The specific devices, methods, and applications are described by way of example only. Various modifications to the examples described herein are readily and obvious to those of ordinary skill in the art, and the general principles defined herein can be applied to other examples and applications without departing from the spirit and scope of the different embodiments. . Therefore, the various embodiments are not intended to limit the examples described and disclosed herein, but the scope of the claims can be supported. For example, an exemplary process for a plasma doped FinFET device can be described. Ideally, these exemplary processes may be additionally applied to non-planar semiconductor devices other than FinFET devices, such as non-planar multi-gate transistor devices and non-planar nanowire transistor devices.

(1) Plasma doping system

Figure 1 shows that it can be used for plasma doping of non-planar semiconductor devices. An exemplary plasma doping system 100, such as a FinFET device. The example plasma doping system 100 can have a chamber 102 surrounded by a cylindrical sidewall, a substrate, and an upper cover. The substrate 104 having a fin portion formed thereon is placed in the chamber 102 and supported on the support base 106. The temperature of the support 106 can be adjusted by heating and cooling mechanisms to control the temperature of the substrate 104.

Process gas can be supplied from the gas plate 108 to the chamber 102 via the showerhead 110. The process gas may be a mixed gas containing at least one doping gas (for example, boron trifluoride, diborane, phosphine, phosphorus pentafluoride, arsine, etc.) and an inert gas (for example, helium, argon, or neon). Etc.) Dilution. The vacuum pump 124 can extract the chamber 102 and control the chamber pressure to a desired range (eg, 2 to 150 mT) via the throttle valve 128.

By providing one or more power sources to the showerhead 110, the plasma 120 can be formed in the chamber 102 by process gases. For example, a radio frequency (RF) power source 112 can be provided to the showerhead 110 via the mating network 114. The RF power source 112 can have a power of 200W to 10 kW and a frequency of 5 to 30 MHz. The plasma 120 may contain dopant ions formed from at least one of the mixed gases. The plasma 120 may be formed between the showerhead 110 and the substrate 104 and the plasma sheath 122 may be formed between the plasma 120 and the substrate 104.

The RF offset power 116 can be provided to the support base 106 via the mating network 118. The RF offset power 116 can have a power of 50 to 500 W and a frequency of 0.5 to 5 MHz. The RF offset power 116 can create a bias across the plasma sheath 122 between the plasma 120 and the substrate 104. This bias can extract dopant ions from the plasma 120 and can accelerate the doping ions across the plasma sheath 122 to implant the fin portions on the substrate 104. The higher the bias generated, the implantable blend The deeper the impurity ions are in the fins. The RF offset power 116 can produce a bias voltage of 100V to 15kV. The bias can direct the implantation of dopant ions into the fin portion at an implantation angle that is substantially perpendicular to the surface of the substrate 104. For example, the implantation angle can be about 0 to 10 degrees with respect to an axis perpendicular to the surface of the substrate 104. An optional electrode screen 126 can be disposed between the plasma 120 and the substrate 104. A power source (not shown) can provide a potential to the electrode screen 126 to accelerate the doping ions across the plasma sheath 122 to the fin portion. The electrode screen 126 can be tilted to direct the dopant ions into the fin portion at the desired implantation angle.

Controller 130 can be coupled to many components of plasma doping system 100 and control plasma doping system 100 to perform the non-planar semiconductor device plasma doping process described herein. The function and characteristics of the controller 130 will be described in detail later.

The exemplary plasma doping system 100 described herein forms a plasma 120 by capacitive coupling. Preferably, the plasma implantation method of the non-planar semiconductor device can be performed using any suitable plasma doping system. For example, the plasma 120 can also be produced using inductive coupling. Plasma can also be provided from many other plasma source configurations, such as a toroidal plasma source, a spiral plasma source, a direct current plasma source, or a remote plasma source. It is to be understood that the provided parameter values, such as RF power and RF frequency, are merely exemplary and other values may be used within the scope of the present invention.

(2) Plasma doping of non-planar semiconductor devices

Referring to Figure 2, an exemplary process 200 for a plasma doped FinFET device is described. In step 202 of process 200, the substrate can be provided with fins A shaped portion is formed thereon. The fin portion may include a channel region, a source region, a drain region, a source extension region, and a drain extension region. At step 204, a substrate having a fin portion can be placed into the chamber. At step 206, a plasma can be formed in the chamber. The plasma may contain dopant ions. At step 208, a first bias voltage can be generated in the chamber to implant dopant ions into the region of the fin portion. The region may include any of a channel region, a source region, a drain region, a source extension region, and a drain extension region. At step 210, a second bias voltage can be generated in the chamber to implant dopant ions into the same region of the fin portion. The bias voltage can at least partially determine the depth at which the dopant ions are implanted into the fin portion. In one example, the first bias voltage can be different than the second bias voltage to implant different depths of dopant ions in the fin portion. In such an example, the first bias voltage can be greater than the second bias voltage.

A more detailed description of the exemplary process 200 is now provided, with reference to Figures 2 and 3A through 3D. 3A through 3D are cross-sectional views showing different stages of the FinFET device 300 in the process 200. In step 202 of process 200, as shown in FIG. 3A, substrate 302 can be provided with fin portions 304 formed thereon. Substrate 302 can comprise any known substrate suitable for use in the formation of FinFET device 300. For example, substrate 302 can comprise a single crystal semiconductor wafer (eg, germanium, germanium, gallium arsenide, etc.). In another example, the substrate 302 may include one or more epitaxial single crystal semiconductor layers (eg, germanium, germanium, antimony, gallium arsenide, indium phosphide, indium gallium arsenide, etc.) grown on different wafers (矽, 锗, gallium arsenide, etc.). One or more epitaxially grown semiconductor layers can serve as a buffer layer to gradient different lattice constants from the wafer to the upper surface of the substrate 302. In another example, the substrate 302 can include an insulating layer (for example, cerium oxide, cerium oxynitride, high dielectric constant layer, or the like) is interposed between the single crystal semiconductor substrate and the formed epitaxial layer, for example, an insulating layer covering the substrate. It is to be appreciated that the substrate 302 can include other substrates and layers, such as shallow trench isolation structures.

The fin portion 304 on the substrate 302 can be formed by conventional semiconductor fabrication methods such as, but not limited to, photolithography, etching, and chemical vapor deposition. The fin portion 304 can have a channel region 312 disposed between the source region 314 and the drain region 316. The source extension region 313 may be disposed between the channel region 312 and the source region 314 and the drain extension region 315 may be disposed between the channel region 312 and the drain region 316. The fin portion 304 may comprise a single crystal semiconductor material (eg, germanium, antimony, gallium arsenide, etc.). Alternatively, fin portion 304 can comprise a plurality of epitaxially grown semiconductor materials. In such an example, the multilayer epitaxially grown semiconductor material can form a vertical array of multiple nanowires in the channel region. As shown in FIG. 3A, the fin portion 304 can have a critical dimension 306, a height 308, and a length 310. In one example, the critical dimension 306 can be 5 to 50 nm, the height 308 can be 15 to 150 nm, and the length can be 20 to 1200 nm.

In step 204 of process 200, substrate 302 having fin portion 304 can be placed in the chamber. The chamber can be any chamber suitable for plasma implanting a non-planar semiconductor device, such as chamber 102 in FIG. At step 206 and as shown in FIG. 3B, a plasma 318 is formed in the chamber and a plasma sheath 320 is formed between the plasma 318 and the substrate 302. As previously mentioned, in FIG. 1, the plasma 318 may be formed by providing a process gas to the chamber and providing at least one power source (eg, an RF power source). Process gas At least one dopant gas that subsequently forms dopant ions in the plasma 318 is included. The type of dopant gas provided in the chamber can determine the type of dopant ion formed in the plasma 318. For example, a p-type dopant gas, such as diborane and boron trifluoride, forms p-type dopant ions, such as B+, BF+, BF2+, and BF3+, in the plasma 318. In contrast, n-type dopant gases, such as arsine and phosphine, form n-type dopant ions, such as P+ and As+, in the plasma 318. Thus, a suitable dopant species can be selected to electrically dope the region of the fin portion 304 with the desired dopant species. Typically, channel region 312 is implanted with p-type dopant ions when forming an NMOS transistor device, and is implanted with n-type dopant ions when forming a PMOS transistor device. In contrast, typical, source/drain regions 314/316 and source/drain extension regions 313/315, when forming a PMOS transistor device, are implanted with p-type dopant ions, and when forming an NMOS transistor The device is implanted with n-type dopant ions.

In step 208 of process 200 and referring to FIG. 3C, a first bias 321 can be generated in the chamber. As in the first FIG. 1 described above, the first bias 321 can be generated by providing RF bias power to the support base of the support substrate 302. A first bias 321 can be generated across the plasma sheath 320 to implant dopant ions from the plasma 318 into one or more regions of the fin portion 304, eg, source/drain regions 314/316, source/汲Polar extension region 313/315 or channel region 312. The magnitude of the bias determines, at least in part, the depth at which the dopant ions can be implanted into the fin portion 304. The higher the resulting bias voltage, the deeper the doping ions can be implanted into the fin portion 304. A first bias 321 can be created to implant dopant ions primarily at any desired depth in the fin portion 304. Such as the first As shown in FIG. 3C, a first bias 321 can be generated to implant dopant ions primarily into the depth 319 in the lower portion 324 of the fin portion 304. For example, the depth 319 can be 2 to 50 nm. In an example, the first bias voltage 321 can be 0.5 kV to 15 kV. In another example, the first bias voltage 321 can be 2 kV to 10 kV. In still another example, the first bias voltage 321 can be 2 kV to 6 kV.

The size of the plasma sheath 320 may be larger relative to the size of the fin portion 304, wherein the plasma sheath 320 formed on the fin portion 304 does not coincide with the fin portion 304. Thus, the dopant ions can be implanted only in the upper portion of the fin portion 304 at an implantation angle that is substantially perpendicular to the substrate 302. For example, the first bias 321 can be implanted with dopant ions implanted at an implant angle of about 0 degrees with respect to the axis perpendicular to the substrate 302. As previously mentioned, the implantation angle can be controlled at an angle by an electrode screen that is obliquely disposed on the substrate 302. For example, the electrode screen can be tilted to implant dopant ions into the fin portion 304 at a first implantation angle of the first bias 321 at an axis that is perpendicular to the substrate 302. In one example, the first implantation angle can be from 0 to 10 degrees. In another example, the first implantation angle can be 0 to 5 degrees.

In step 210 of process 200 and as shown in FIG. 3D, a second bias voltage 323 can be generated in the chamber. A second bias 323 can be generated across the plasma sheath 320 to implant dopant ions from the plasma 318 to the same region of the one or more fin portions 304 (ie, source/drain regions, source/drain Extended area or channel area). The second bias voltage 323 can be defined as the implantation of dopant ions into the fin portion 304 to a depth of 2 to 33 nm. The second bias 323 can be different from the first bias 321 in which the dopant ions can be implanted into the fin Divided into different depths in 304. For example, as shown in FIG. 3D, a second bias 323 that is lower than the first bias 321 can be generated, wherein the second bias 323 implants dopant ions into the portion 326 that is shallower than the depth 319 in the portion 324. The depth is 325. Portion 326 can partially overlap portion 324 or with portion 324. In an example, the second bias voltage 323 can be 0.5 kV to 10 kV. In another example, the second bias voltage 323 can be 0.5 kV to 6 kV. In still another example, the second bias voltage 323 can be 0.5 kV to 2 kV.

The second bias 323 can implant dopant ions into the fin portion 304 at an implantation angle that is substantially perpendicular to the substrate 302. Alternatively, the electrode screen can be tilted to implant dopant ions into the fin portion 304 at a second implantation angle of the second bias 323 to an axis that is perpendicular to the substrate 302. In an example, the second implantation angle can be from 1 to 10 degrees. In another example, the second implantation angle can be 2 to 6 degrees.

The bias voltage can affect the dispersion of dopant ions implanted in the fin portion 304. The doped ions in the dispersion fin portion 304 are dispersed. The dispersion occurs in a horizontal direction (eg, along the length direction 310 of the fin portion 304) and a vertical direction (eg, along the height direction 308 of the fin portion 304) and increases with bias. Implantation of dopant ions at different biases may result in greater overall dispersion, which may result in poor doping uniformity across the length 310 and height 308 of the fin portion 304. In this embodiment, the first implant angle and the second implant angle may be defined as reducing overall horizontal dispersion due to different bias implants. For example, if the first bias 321 is greater than the second bias 323, the first implant angle can be defined to be less than the second implant angle. In one such example, the first bias 321 can be 2 to 10 kV and the first implant angle can be 0 to 2 degrees, while the second bias 323 may be 0.5 to 2 kV and the second implantation angle may be 2 to 10 degrees.

It is also possible to reduce the overall dispersion by implanting different kinds of dopant ions due to different bias voltages. Different types of dopant ions can be implanted by providing different dopant gases into the chamber to form different kinds of dopant ions in the plasma 318. Doped ion species having a larger molecular weight tend to have a smaller penetration depth and dispersion. To reduce overall dispersion, dopant species with larger molecular weights can be implanted with higher biases, while dopant species with smaller molecular weights can be implanted with lower bias. For example, a doped ion species having a larger molecular weight of 74.9 can be implanted at a higher first bias voltage of 2 to 10 kV, and a doped ion species having a smaller molecular weight of 31.0 can be implanted at a lower second bias voltage of 0.5. Up to 2kV.

Preferably, deeper ion implantation is implanted prior to shallower ion implantation. As such, the shallower doped ion implantation will not be moved (knocked in) by subsequent deeper implants. For example, in process 200, the first bias voltage can be greater than the second bias voltage and the first bias voltage can be generated prior to the second bias voltage.

As described, step 210 can be performed in the same chamber as step 208. Or, preferably, steps 208 and 210 can be performed in different chambers. For example, in step 210, the substrate 302 having the fin portion 304 can be placed in a different chamber than in step 208. A plasma having dopant ions can be formed in different chambers and a plasma sheath can be formed between the plasma and the substrate 302. A second bias voltage can then be generated across the plasma sheath to implant dopant ions into the fin portion 304.

Preferably, process 200 is applicable to other non-planar semiconductor devices such as, but not limited to, non-planar multi-gate transistor devices, non-planar wraparound gate transistor devices, and non-planar nanowire transistor devices. For example, the fin portion 304 can be replaced by other non-planar semiconductor bodies, such as a nanowire or vertical nanowire array.

Referring to Figure 4, another exemplary process 400 for a plasma doped FinFET device is shown. 5A-5F show cross-sectional views of FinFET device 500 representing different stages in process 400. Process 400 includes steps 402 through 416. Optional steps 404 and 406 are indicated by dashed outlines.

In step 402 of process 400, as shown in FIG. 5A, a substrate may be provided having a fin portion 504 formed thereon. Substrate 502 can comprise a single crystal semiconductor substrate, one or more epitaxially grown layers on different germanium wafers, an insulating blanket substrate, or any other substrate on which known FinFET devices can be formed. The fin portion 504 can include a source/drain region, a source/drain extension region, and a channel region. The fin portion 504 can have a critical dimension 510, a height 508, and a length (not shown). Adjacent structures 506, such as masks, fictitious features, or adjoining fins, may be formed adjacent to fin portions 504.

In an optional step 404 of process 400 and as shown in FIG. 5B, a liner layer 511 can be formed over the fin portion 504 and surrounding the fin portion 504 and fill the region between the fin portion 504 and the abutment structure 506. During the plasma doping process, the liner layer 511 blocks dopant ions from reaching the substrate 502 and prevents the dopant ions from being repeatedly sputtered onto the sidewalls of the fin portion 504. In addition, the pad layer 511 increases the doping retention in the fin portion 504. to The thickness 512 of the liner layer 511 on the upper surface of the fin portion 504 can be sufficiently thin to not hinder dopant ions from entering the fin portion 504 during implantation. For example, the thickness 512 of the pad layer 511 may be formed on the upper surface of the fin portion 504 from 0 to 10 nm. Additionally, the liner layer 511 can have an approximately planar surface on the fin portion 504 and the abutment structure 506.

The liner layer 511 can comprise any material that captures implanted dopant ions. For example, the liner layer 511 can be a dielectric material or an internal dopant material such as, but not limited to, undoped yttrium oxide, doped yttrium oxide, tantalum nitride, an organic material, and yttrium oxynitride. The liner layer 511 can be formed by conventional semiconductor processes such as chemical vapor deposition, spin coating deposition, solution gel deposition processes, selective deposition processes, and selective etch back processes. The liner layer 511 can be formed prior to steps 408 and 410 in the process 400 and can be removed before or after the fin portion 504 of step 412 is annealed.

In a selectable step 406 of process 400 and as shown in FIG. 5C, a puncture stop (PTS) layer 514 can be formed in fin portion 504. PTS layer 514 can be formed in the source/drain regions, channel regions, and/or source/drain extension regions of fin portion 504 to prevent electron breakdown. The source/drain regions, the channel regions, and/or the source/drain extension regions may partially overlap the PTS layer 514. In addition, the PTS layer 514 can act as a barrier layer that blocks or significantly prevents doping migration during plasma doping and in the annealing process, thereby minimizing the vertical dispersion of doping in the fin portion 504. The PTS layer 514 can generate a discontinuous interface 515 between the source/drain regions of the PTS layer 514 and the fin portion 504, the channel region, and/or the source/drain extension region, wherein the doping concentration in each region Disappears discontinuously. For example, a PTS layer can be formed 514 such that the surface resistance (Rs) in the source/drain region, the channel region, and/or the source/drain extension region is in the PTS layer 514 and the source/drain region, the channel region, and/or the source/汲The 3 nm thickness of the interface 515 between the pole extension regions is increased by three orders of magnitude.

The PTS layer 514 can be formed by any species (such as, but not limited to, carbon, oxygen, fluorine, nitrogen, or any combination thereof) that is doped into the fin portion 504 to block doping movement. Alternatively, the PTS layer 514 can be formed by doping ion species doped opposite the dopant species implanted above the PTS layer 514. For example, if a p-type dopant ion is implanted in a region above the PTS layer 514, the PTS layer 514 can be formed by implanting n-type dopant ions. The implantable implant can be performed by any suitable implantation process, such as ion beam implantation or plasma doping. In one example, PTS layer 514 can be formed in the same plasma doping chamber as steps 412 and 414 in process 400.

The depth 516 formed by the PTS layer 514 can be formed to be approximately equal to the equivalent height 516 of the FinFET device 500. In the known technique, the equivalent channel width of the FinFET device 500 is approximately equal to twice the sum of the equivalent height of the FinFET and the critical dimension of the fin portion. Because the depth 516 can be controlled by the implant process, the equivalent channel width of the FinFET device 500 can be controlled by the implant process (eg, ion beam implant and plasma doping), independent of the actual height 508 of the fin portion 504. In an example, the PTS layer 514 can be formed in the substrate 502 below the fin portion 504. In such an example, the PTS layer 514 can overlap the lower portion of the fin portion 504. In another example, the PTS layer 514 can be formed at any depth 516 in the fin portion 504. Preferably, the PTS layer 514 can be formed larger than the fin portion 504. The depth 510 of the critical dimension 510. For example, the PTS layer 514 can be formed in the fin portion 504 at a depth 516 that is greater than the critical dimension 510 and less than the height 508 of the fin portion 504. The depth 516 of the formed PTS layer 514 may have a uniformity percentage of 5% or less across the length of the fin portion 504.

At step 408 of process 400, substrate 502 having fin portion 504 is placed into the chamber. The chamber can be any chamber suitable for plasma doping, such as chamber 102 in Figure 1. In step 410 and as shown in FIG. 5D, a plasma 522 is formed in the chamber and a plasma sheath 518 is formed between the plasma 522 and the substrate 502. The plasma 522 can contain dopant ions.

In step 412 of process 400 and as shown in FIG. 5E, a first bias voltage 521 can be generated in the chamber. A first bias voltage 521 can be generated to implant dopant ions into one or more regions of the fin portion 504, such as a source/drain region, a source/drain extension region, or a channel region. The first bias 521 can implant a doping ion primarily to a depth 520 in the fin portion 504. In an example, the depth 520 in the fin portion 504 can be 2 to 50 nm. In an example, the first bias voltage 521 can be 0.5 kV to 15 kV. In another example, the first bias voltage 521 can be 2 kV to 10 kV. In still another example, the first bias voltage 521 can be 2 kV to 6 kV. The first bias 521 can implant dopant ions into the fin portion 504 at an implantation angle that is substantially perpendicular to the substrate 502. For example, the implantation angle can be about 0 degrees. Alternatively, an electrode screen in a plasma doping system, such as electrode screen 126 shown in FIG. 1, can be tilted to cause first bias 521 to implant dopant ions into fin portion 504 at a first implantation angle. . In an example, the first implantation angle can be 0 to 10 degree. In another example, the first implantation angle can be 0 to 5 degrees.

In step 414 of process 400 and as shown in FIG. 5F, a second bias 523 can be generated in the chamber. A second bias 523 can be generated to implant dopant species of the same species (ie, p-type or n-type) as the first bias 521 to one or more regions of the same first bias 521 (ie, source/ The drain region, the source/drain extension region, or the channel region 312). The second bias 523 can be defined to implant dopant ions primarily to a depth of 2 to 33 nm in the fin portion 504. The second bias 523 can be different than the first bias 521, wherein the dopant ions can be implanted at different depths in the fin portion 504. For example, the second bias 523 can be lower than the first bias 521, wherein the second bias 523 can implant dopant ions to a depth that is shallower than the first bias 521 implanted with dopant ions. In such an example, the dopant ions implanted by the second bias voltage 523 may partially overlap the dopant ions implanted by the first bias voltage 521 in the fin portion 504. In an example, the second bias voltage 523 can be 0.5 kV to 10 kV. In another example, the second bias voltage 523 can be 0.5 kV to 6 kV. In still another example, the second bias voltage 523 can be 0.5 kV to 2 kV. The second bias 523 can implant dopant ions into the fin portion 504 at an implantation angle that is substantially perpendicular to the substrate 502. For example, the implantation angle can be about 0 degrees. Alternatively, the electrode screen can be tilted to cause the second bias 523 to implant dopant ions into the fin portion 504 at the second implantation angle. The second implantation angle can be approximately equal to the first implantation angle. Or the second implantation angle may be different from the first implantation angle. In one example, the second implantation angle can be from 0 to 10 degrees. In another example, the second implantation angle can be 0 to 5 degrees.

Ideally, an additional bias voltage can be generated to implant additional Doped ions into the fin portion 504. For example, a third bias voltage (not shown) can be generated. In one example, the total number of biases generated (including the first bias and the second bias) can be from 2 to 20. In another example, the total number of biases generated can be 2 to 6.

Each additional bias voltage can implant the same type (ie, p-type or n-type) dopant ions as the first and second biases to one or more regions of the same first and second bias voltages (ie, Source/drain region, source/drain extension region, and channel region). Each additional bias can also be implanted with dopant ions from the plasma screen in the tilted plasma doping system at any implantation angle in the fin portion 504. In addition, each of the generated bias voltages may be different. In one example, a gradually decreasing bias voltage can be generated to prevent implanted ion displacement (knock-in) during implantation.

The implantable ions can be implanted at an implantation angle that is inversely proportional to the bias voltage. For example, the highest bias can implant dopant ions at a minimum implantation angle, while the lowest bias can implant dopant ions at a maximum implantation angle. In such an example, the bias voltage and corresponding implant angle can be defined to minimize overall horizontal dopant ion dispersion in the fin portion 504. For example, the bias and implant angle can be defined as the height across the implanted region in the fin portion 504, achieving a doping concentration uniformity of 5% or less. In an exemplary process in which the PTS layer 514 is formed, the bias and implant angle can be defined as the depth 516 formed across the PTS layer 514 to achieve a doping concentration uniformity of 5% or less.

To reduce overall dispersion, one or more biases can be implanted with dopant species of a different molecular weight than the other biases. For example, one or more High bias voltages can implant dopant species with higher molecular weight relative to other bias voltages.

At step 416 of process 400 and as shown in FIG. 5G, fin portion 504 may be annealed. Annealing is indicated by arrow 524. During annealing, the implant doping in the fin portion 504 is activated. In addition, implant damage (eg, amorphization and crystallization damage) of the fin portion 504 can be repaired by means of crystallization re-growth. In annealing, it is preferred that the doping diffusion be minimized to maintain good doping uniformity in the fin portion 504. Annealing may be performed in the same process chamber as step 408, 410, 412 or 414 of process 400. Alternatively, the annealing can be performed on a separate annealing chamber. The fin portion 504 can be annealed by an annealing process that minimizes doping diffusion. For example, the fin portion 504 can be annealed by a laser annealing process or a pulsed laser annealing process. In another example, the fin portion 504 can be annealed with a dopant diffusion of no more than 5 nm.

As previously mentioned, the equivalent channel width of the FinFET device 500 can be controlled by the implant process, independent of the actual height 508 of the fin portion 504. Thus, the methods and processes of plasma doped non-planar semiconductor devices herein can be used in the fabrication of FinFET devices having different equivalent channel widths on a single substrate without the need to form fin portions having different actual heights. In this way, expensive lithography and pattern etching steps can be avoided. For example, substrate 502 can be provided having a first fin portion and a second fin portion (not shown) formed thereon. The first fin portion and the second fin portion may have approximately equal fin portion heights. The first fin portion may form a first FinFET device and the second fin portion may form a second FinFET device. Forming a first depth of the first PTS layer in the first fin portion and forming a second PTS layer a second depth in the second fin portion. The first depth and the second depth may be less than or equal to the heights of the first fin portion and the second fin portion. Additionally, the first depth can be different than the second depth, such that the first FinFET device can have a different channel width than the second FinFET device. For example, the first FinFET device can have a first channel width that is about equal to twice the sum of the first depth and the critical dimension of the first fin portion, and the second FinFET device can have twice the second depth and The sum of the critical dimensions of the second fin portion is about equal to the width of the second channel. Additionally, the first fin portion and the second fin portion may be doped, according to the plasma doping method and process of the non-planar semiconductor device described herein. For example, a first bias voltage can be generated to implant dopant ions into the region of the first fin portion and a second bias voltage can be generated to implant dopant ions into the region of the first fin portion. A third bias voltage can then be generated to implant dopant ions into the region of the second fin portion and a fourth bias voltage can be generated to implant dopant ions into the region of the second fin portion. In such an example, the first bias voltage and the second bias voltage may be different, and the third bias voltage and the fourth bias voltage may be different.

Preferably, additional semiconductor processes not shown in process 400 may be performed in the fabrication of FinFET device 500. For example, a conformal gate dielectric layer can be formed over the channel region of the FinFET device 500, a gate electrode can be formed over the conformal gate dielectric layer, and a pair of sidewall spacer layers can be formed on each side of the gate electrode. The completed FinFET device 500 can be a dual gate FinFET, a triple gate FinFET, or a wraparound gate FinFET.

Additionally, as previously mentioned, it is desirable that the example process 400 be applicable to other non-planar semiconductor devices such as, but not limited to, non-planar Multi-gate transistor device, non-planar wrap gate transistor device and non-planar nanowire transistor device. For example, the fin portion 504 can be replaced by other non-planar semiconductor bodies (eg, nanowires or vertical array nanowires), wherein the non-planar semiconductor body can be plasma doped by the exemplary process 400.

Referring to Figures 6A through 6C, an exemplary FinFET device 600 formed herein by an exemplary process is disclosed. FIG. 6A depicts a three-dimensional cross-sectional view of an exemplary FinFET device 600. FIG. 6B depicts a two-dimensional cross-sectional view of the length of the example FinFET device 600 along the fin portion 604. FIG. 6C depicts a two-dimensional cross-sectional view of the length of the example FinFET device 600 along the gate electrode 618. In the present embodiment, the FinFET device 600 can have a fin portion 604 disposed on the substrate 602. The fin portion 604 can include a source region 606, a drain region 608, a source extension region 610, a drain extension region 612, and a channel region 614. The depth 622 of the PTS layer 616 in the fin portion 604 can be set to be greater than the critical dimension 626 and less than the height 624. The channel width of the FinFET device 600 can be approximately equal to twice the sum of the depth 622 and the critical dimension 626. The depth 622 of the PTS layer 616 may have a uniformity percentage of 5% or less across the length of the fin portion 604. As shown in FIG. 6B, source/drain regions 606/608, source/drain extension regions 610/612, and channel regions 614 may be disposed on PTS layer 616. Any region may partially overlap the PTS layer 616. Each region can be doped to a percentage consistency of 5% or less across the depth 622. The doping concentration of either region may discontinuously disappear from the interface 628 between the PTS layer 616 and the source/drain regions 606/608, the source/drain extension regions 610/612, and the channel region 614. In one example, the planar resistance (Rs) of any region is at the thickness of interface 628 Increased by 3 orders of magnitude at 3 nm. The gate dielectric layer 620 can be disposed on the channel region 614 of the fin portion 604. Gate dielectric layer 620 can comprise any suitable electrically insulating material such as, but not limited to, hafnium oxide, high dielectric constant dielectric, hafnium oxide, and titanium oxide. The gate electrode 618 can be disposed on the gate dielectric layer 620. Gate electrode 618 can comprise any suitable electrically conductive material such as, but not limited to, doped polysilicon, metal, metal nitride, metal telluride, titanium, tantalum, and tungsten.

(3) Computer application

Referring to the first FIG. 1 described above, the plasma doping system 100 can have a controller 130. As previously mentioned, the controller 130 can be coupled to different components of the plasma doping system 100 and control the plasma doping system 100 to perform plasma implantation of the non-planar semiconductor devices described herein. For example, controller 130 is controlled by a mass airflow controller (not shown) that controls gas panel 108 to adjust the flow rate of the process gas and the ratio of process gases provided to chamber 102. The controller 130 also controls the RF power source 112 and the RF bias power 116 to set the magnitude and frequency of the RF power source and RF bias power provided to the chamber 102. Additionally, controller 130 can adjust the potential supplied to electrode screen 126 by a control power source (not shown). The controller 130 controls the implantation angle of the fin portion on the doped ion implantation substrate 104 by the inclination of the control electrode screen 126. In addition, the controller 130 controls the vacuum pump 124 and the throttle valve 128 to control the chamber pressure in the chamber 102.

Controller 130 can be one of any general purpose data processing systems that can be used to control different components of plasma doping system 100. Generally speaking The controller 130 can include communicating with the main memory 134, the storage medium 136, and the processor 132 of the support device 138 via the bus bar 140. Processor 132 can be one or more general purpose data processing devices such as a microprocessor, central processing unit (CPU), and the like. The primary memory 134 can be random access memory (RAM) or any other dynamic memory used to temporarily store information and instructions executed by the processor 132. The storage medium 136 can include any non-transitory computer readable storage medium capable of storing computer software, instructions or materials such as, but not limited to, hard disks, floppy disks, magnetic tapes, optical disks, read only memory (ROM) or other removable media. In addition to or fixed media. The support device 138 can include an input/output interface or a communication interface, such as a USB slot, a network interface, an Ethernet network, a PCMCIA slot, and the like. Support device 138 may allow computer programs, software, materials, or other instructions to be loaded into controller 130 for execution to processor 132 for execution.

Non-transitory computer readable storage medium, such as storage medium 136 or other suitable medium internal or external controller 130 may include computer executable instructions (generally referred to as computer code, groupable in the form of computer programs or other groups) ) to perform any one or more of the features or functions of the plasma doping process of the non-planar semiconductor device described herein. One or more such computer executable instructions, when provided to processor 132 for execution, may cause controller 130 to control plasma doping system 100 to perform the plasma doping process of the non-planar semiconductor device described herein. Any one or more features or functions.

The specific components, configurations, features, and functions are provided as described above, but it is desirable that those skilled in the art can use other variations. In addition, although the features may indicate that the description is linked to a particular embodiment, Those of ordinary skill in the art will appreciate that various technical features can be combined with the described embodiments. Further, the above-described viewpoints associated with a specific embodiment may be separately provided.

Although the embodiments have been described in detail with reference to the drawings, it should be noted that various changes and modifications may be apparent to those of ordinary skill in the art. Such changes and modifications are considered to be included in the various embodiments as defined in the appended claims.

Claims (23)

A method of plasma doping a non-planar semiconductor device, comprising: providing a substrate having a first non-planar semiconductor body formed on the substrate; placing the substrate into a chamber; forming a plasma in the chamber, the plasma Having a dopant ion; generating a first bias to implant dopant ions into a region of the first non-planar semiconductor body, wherein: the first bias accelerates dopant ions to the substrate; and is accelerated by the first bias The dopant ions are directed to the substrate at a first implantation angle for an axis orthogonal to the substrate; and a second bias is generated to implant dopant ions into the region, wherein: the second bias is accelerated Doping ions toward the substrate; and the dopant ions accelerated by the second bias are directed to the substrate at a second implantation angle for the axis; the first bias voltage is greater than the second bias voltage; The first implantation angle is less than the second implantation angle. The method of claim 1, wherein the region is at least one of a channel region, a source region, a drain region, a source extension region, and a drain extension region. The method of claim 1, wherein the first bias voltage is generated prior to generating the second bias voltage. The method of claim 1, wherein the first bias is generated to implant a first dopant ion species into the region, wherein the second bias implant is generated a second dopant ion species to the region, and wherein the first dopant ion species has a molecular weight greater than the second dopant ion species. The method of claim 1, wherein the first bias is implanted into the first dopant ion species to the region, wherein the second bias is implanted into the second dopant ion species to the region, and wherein The first dopant ion species has a different molecular weight than the second dopant ion species. The method of claim 1, further comprising: generating a third bias to implant dopant ions into the region, wherein the third bias is different from the first bias and the second bias. The method of claim 1, wherein the first non-planar semiconductor body has a height, and wherein the first bias, the first implant angle, the second bias, and the second implant angle are defined to achieve The doping concentration uniformity across this height in this region is a percentage of 5% or less. The method of claim 1, further comprising: forming a liner layer on the first non-planar semiconductor body and surrounding the first non-planar semiconductor body before the substrate is placed in the chamber. The method of claim 8, wherein the first non-planar semiconductor body has an upper surface, and wherein the liner layer is formed to have a thickness of 0 to 10 nm on the upper surface of the first non-planar semiconductor body. The method of claim 1, further comprising: forming a breakdown stop layer. The method of claim 10, wherein the breakdown stop layer is formed in the substrate and directly below the first non-planar semiconductor body. The method of claim 10, wherein the first non-planar semiconductor The body body has a critical dimension and height, and wherein the breakdown stop layer is formed in the first non-planar semiconductor body and is larger than the critical dimension of the first non-planar semiconductor body and larger than the first non-planar semiconductor body The height is small and deep. The method of claim 12, wherein the first non-planar semiconductor device has a channel width, and wherein the channel width is about twice the depth of the breakdown stop layer plus the critical dimension. The method of claim 12, wherein the first bias, the first implant angle, the second bias, and the second implant angle are defined such that the crossing of the breakdown stop layer is achieved in the region The depth doping concentration uniformity is a percentage of 5% or less. The method of claim 12, wherein the first non-planar semiconductor body has a length, and wherein the depth of the breakdown stop layer has a consistency of 5% or more across the length of the first non-planar semiconductor body. a small percentage. The method of claim 1, wherein the substrate is provided with a second non-planar semiconductor body formed on the substrate, wherein the first non-planar semiconductor body and the second non-planar semiconductor body each have a height, wherein The height of the first non-planar semiconductor body is approximately equal to the height of the second non-planar semiconductor body, and further comprising: forming a first breakdown stop layer in the first non-planar semiconductor body and at a first depth; forming a a second breakdown stop layer in the second non-planar semiconductor body and At a second depth, wherein the first depth is different from the second depth, and wherein the first depth and the second depth are less than or equal to the height of the first non-planar semiconductor body and the second non-planar The height of the semiconductor body; generating a third bias to implant dopant ions into the region of the second non-planar semiconductor body; and generating a fourth bias to implant dopant ions into the second non-planar semiconductor body a region, wherein the third bias voltage and the fourth bias voltage are different. The method of claim 16, wherein the first non-planar semiconductor body and the second non-planar semiconductor body each have a critical dimension, wherein the first non-planar semiconductor body forms a first non-planar semiconductor device having a first channel width and The second non-planar semiconductor body forms a second non-planar semiconductor device having a second channel width, and wherein the first channel width is about twice the first depth plus the criticality of the first non-planar semiconductor body The second depth, which is approximately twice the size and width of the second channel, plus the critical dimension of the second non-planar semiconductor body. The method of claim 1, further comprising: annealing the first non-planar semiconductor body. The method of claim 1, wherein the first non-planar semiconductor system is one of a fin portion, a nanowire, and a vertical nanowire array. The method of claim 1, wherein the non-planar semiconductor device is one of a FinFET device, a non-planar multi-gate transistor device, or a non-planar nanowire transistor device. A method of plasma doping a non-planar semiconductor device, comprising: Providing a substrate having a non-planar semiconductor body formed on the substrate; placing the substrate into a chamber; forming a plasma in the chamber, the plasma containing dopant ions; generating a first bias to accelerate dopant ions to An area of the non-planar semiconductor body; the electrode screen is disposed in the chamber at a first tilt angle such that the dopant ions accelerated by the first bias are first implanted on an axis orthogonal to the substrate An angle is implanted in the region; a second bias is generated to accelerate dopant ions to the region, wherein the second bias is less than the first bias; and the electrode screen is disposed in the chamber at a second tilt angle The dopant ions accelerated by the second bias are implanted into the substrate at a second implantation angle for the axis, wherein the second implantation angle is greater than the first implantation angle. The method of claim 21, wherein: the first bias accelerates the dopant of the first species to the region; the second bias accelerates the dopant of the second species to the region; and the first species The dopant ions have a molecular weight greater than the molecular weight of the dopant ions of the second species. A method of plasma-doping a non-planar semiconductor device, comprising: providing a substrate having a non-planar semiconductor body formed on the substrate; forming a breakdown stop layer in the non-planar semiconductor body using an ion implantation process; placing the substrate into the cavity In the room; Forming a plasma in the chamber, the plasma containing dopant ions; generating a first bias to accelerate doping ions to a region of the non-planar semiconductor body, wherein the dopant ions accelerated by the first bias are a first implantation angle of the axis orthogonal to the substrate is directed to the substrate; and a second bias is generated to accelerate dopant ions to the region, wherein: the dopant ions accelerated by the second bias are A second implantation angle of the shaft is directed to the substrate; the first bias is greater than the second bias; and the first implant angle is less than the second implant angle.