TWI600955B - Pixel array - Google Patents

Description

Pixel array

The present invention relates to a pixel array, and more particularly to a pixel array suitable for use in a slim border design.

In general, in order to achieve a lightweight design and maximize the display area in response to the screen design, the display device is generally designed to meet the narrow bezel design by reducing the non-display area around the screen to shield the connection line. In recent years, a method for narrowing a frame has been developed, in which a selection line is disposed outside the scanning line and the data line, wherein the selection line is electrically connected to the corresponding scanning line through the bridge point. In this way, the chip can transmit the scan signal to the corresponding scan line through the selection lines. Since the wiring design allows the scan line and the data line to be drawn from the same side of the display area to the wafer, the width of the non-display area can be narrowed to meet the design requirements of the narrow bezel.

However, the design of the pull wire, which is limited by the selection line, often causes the bridge points to be discontinuous in distribution, so that the resistance (RC) is discontinuous. Therefore, when the signal is transmitted, for example, when the scan signal is transmitted to the corresponding pixel, the difference between the charging time of the adjacent pixels corresponding to the adjacent scanning line is easily caused by the difference in the distance from the bridge point, resulting in a strip. The generation of band mura affects the display quality.

The present invention provides a pixel array which can improve the stripe moiré phenomenon.

A pixel array of the present invention includes a plurality of first signal lines, a plurality of second signal lines, a plurality of active elements, a plurality of pixel electrodes, and a plurality of selection lines. The second signal line is electrically insulated from the first signal line and interleaved with the first signal line to define a plurality of pixel areas. The active component is located in the pixel area, and each active component is electrically connected to the corresponding first signal line and the corresponding second signal line. The pixel electrode is disposed corresponding to the pixel region and electrically connected to the active device. The selection line is interleaved with the first signal line, wherein each of the first signal lines is electrically connected to one of the selection lines and has a bridge point at the intersection with the one of the selection lines. The selection line is electrically insulated from the second signal line, and at least one selection line is disposed between the adjacent two second signal lines. The number of the first signal line and the selection line is greater than the number of the second signal line, respectively, and the connection between the bridge point of the first signal line of the ith and the bridge point of the (i+1)th first signal line The number of interleaved second signal lines is one, i=1 to N, and N is equal to the number of first signal lines.

In an embodiment of the invention, the sequential connection of the bridge point of the first first signal line to the bridge point of the last first signal line constitutes a fold line, and the fold line has at least one turning point.

In an embodiment of the invention, a plurality of selection lines are disposed between adjacent two second signal lines of the portion.

In an embodiment of the invention, there are a plurality of bridge points between adjacent two second signal lines of the above portion.

In an embodiment of the invention, the number of the bridge points between the adjacent two second signal lines is less than or equal to the number of the selection lines between the two adjacent second signal lines.

In an embodiment of the invention, the bridge points respectively intersect different strip selection lines.

In an embodiment of the invention, the number of the at least one inflection point is j, and the number of the at least one selection line between two adjacent second signal lines is j or (j+1), j≥ 1.

In an embodiment of the present invention, the number of the at least one selection line between the adjacent two second signal lines is k, and the number of the at least one inflection point is k or (k±1), K≥2.

In an embodiment of the invention, the selection line and the pixel electrode do not overlap each other.

In an embodiment of the invention, the selection line and the second signal line are in the same layer, and the selection line and the first signal line are in different layers.

Based on the above, the pixel array of the present invention causes the number of second signal lines interleaved by the connection between the bridge points of two adjacent first signal lines to be one to reduce the bridge point between adjacent first signal lines. The distance between the adjacent pixels corresponding to the adjacent first signal lines is reduced, thereby improving the stripe moiré and improving the display quality.

The above described features and advantages of the invention will be apparent from the following description.

1A is a top plan view of a pixel array in accordance with a first embodiment of the present invention. Fig. 1B is an enlarged schematic view of a region A in Fig. 1A. 1C and 1D are schematic cross-sectional views of the cross-sectional lines A-A' and B-B' in Fig. 1B, respectively.

Referring to FIG. 1A to FIG. 1D , the pixel array 100 of the embodiment includes a plurality of first signal lines 110 , a plurality of second signal lines 120 , a plurality of active elements 130 , a plurality of pixel electrodes 140 , and a plurality of selection lines. 150.

The second signal line 120 is electrically insulated from the first signal line 110 and interleaved with the first signal line 110 to define a plurality of pixel areas P. For example, the first signal lines 110 are arranged along the first direction D1 and extend in the second direction D2, respectively. The second signal lines 120 are arranged along the second direction D2 and extend in the first direction D1, respectively. The first direction D1 intersects the second direction D2, for example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto.

The active component 130 is located in the pixel area P, and each active component 130 is electrically connected to the corresponding first signal line 110 and the corresponding second signal line 120. In this embodiment, an active component 130 is disposed in each pixel region P, but is not limited thereto. In another embodiment, a plurality of active components 130 may be disposed in each pixel region P.

The active device 130 is disposed, for example, on the substrate S, and the active device 130 includes a gate GE, a gate insulating layer GI, a channel layer CH, a source SE, and a drain electrode DE. In this embodiment, the gate electrode GE and the first signal line 110 are disposed on the substrate S, and the first signal line 110 is electrically connected to the gate GE. The gate insulating layer GI covers the gate GE and the first signal line 110, and the gate insulating layer GI has a plurality of openings W1. The opening W1 exposes a partial area of the first signal line 110. The channel layer CH is disposed on the gate insulating layer GI and above the gate GE. The source SE and the drain DE are disposed on the channel layer CH, and the two are respectively located on opposite sides of the channel layer CH. The source SE is electrically connected to the second signal line 120.

In this embodiment, the implementation of the active device 130 is described in the bottom gate thin film transistor, but is not limited thereto. In another embodiment, the active component 130 can change its kind or stacked architecture depending on different design requirements. In addition, the present invention does not need to limit the types of signals respectively transmitted by the first signal line 110 and the second signal line 120. In this embodiment, the first signal line 110 is electrically connected to the gate GE, and the second signal line 120 is electrically connected to the source SE. Therefore, the first signal line 110 is used to transmit the scan signal, and the second signal is used. Line 120 is used to transmit data signals. In another embodiment, when the second signal line 120 is electrically connected to the gate GE, and the first signal line 110 is electrically connected to the source SE, the second signal line 120 is used to transmit the data signal, and the first The signal line 110 is used to transmit the scan signal.

In addition, the pixel array 100 of the present embodiment may further include an insulating layer OG to protect the above components, wherein the insulating layer OG covers the active device 130, the selection line 150, and the gate insulating layer GI. Further, the insulating layer OG includes a plurality of openings W2, and the opening W2 exposes a partial region of the drain DE. The pixel electrode 140 is disposed corresponding to the pixel region P and is electrically connected to the active device 130. Further, the pixel electrode 140 is in contact with the drain electrode DE, for example, through the opening W2. In this embodiment, the pixel electrode 140 further covers a portion of the first signal line 110 and the second signal line 120, and the selection line 150 and the pixel electrode 140 do not overlap each other, but are not limited thereto.

The selection line 150 is interleaved with the first signal line 110 and electrically insulated from the second signal line 120, wherein each of the first signal lines 110 is electrically connected to one of the selection lines 150 and is interleaved with the one of the selection lines 150. Has a bridge point X. Specifically, the selection lines 150 are arranged, for example, in the second direction D2 and extend in the first direction D1, respectively. In this embodiment, the selection line 150 is in the same layer as the second signal line 120, and the selection line 150 is located at a different layer from the first signal line 110. Further, the gate GE and the first signal line 110 may be patterned by the first metal layer, and the second signal line 120, the selection line 150, the source SE, and the drain DE may be patterned by the second metal layer. , but not limited to this. In another embodiment, the first signal line 110, the source electrode SE, and the drain electrode DE may be patterned by the first metal layer, and the gate GE, the second signal line 120, and the select line 150 may be patterned by the second metal layer. Made out. In this configuration, the first signal line 110 is electrically connected to the source SE for transmitting the data signal, and the second signal line 120 is electrically connected to the gate GE for transmitting the scan signal. In addition, the selection line 150 is electrically connected to the first signal line 110 through the opening W1 for transmitting the data signal. It should be noted that the first and second metal layers are only used to distinguish the film layers formed by different processes, and are not intended to limit the order in which the two are formed. In an actual process, the first metal layer can be formed before or after the second metal layer.

Through the setting of the selection line 150, the first signal line 110 and the second signal line 120 can be connected to the wafer C by the same side of the pixel array 100 to the wafer end, thereby contributing to narrowing the left and right of the pixel array 100. The width WD1 of the non-display areas on both sides makes the display device to which the pixel array 100 of the present embodiment is applied conform to the design requirements of the narrow bezel.

In the architecture of the present invention, the number of the first signal line 110 and the selection line 150 is greater than the number of the second signal lines 120, respectively, and the number of the selection lines 150 and the setting form thereof may be according to the first signal line 110 and the second signal line. The quantitative relationship between 120 varies. However, at least one selection line 150 is disposed between the adjacent two second signal lines 120, and the bridging point of the bridge point X of the i-th first signal line 110 and the (i+1)th first signal line 110 The number of second signal lines 120 interleaved by the line L between X is one, i=1 to N, and N is equal to the number of the first signal lines 110.

The number of the second signal lines 120 interleaved by the connection line L between the bridge points X of each two adjacent first signal lines 110 is one, and the bridge point X between the adjacent first signal lines 110 can be lowered. The distance in the second direction D2, that is, the difference between the distance between the adjacent pixel corresponding to the adjacent first signal line 110 and the corresponding bridge point X, for example, the pixel Px and the corresponding bridge point X1 The difference between the distance Dx and the distance Dy between the pixel Py and the corresponding bridge point X2 is reduced, so that the bridge point X (ie, the bridge point X1) of the first first signal line 110 is the first to the last The distribution of the bridge point X of the signal line 110 is relatively continuous. In this way, when the chip C transmits a signal (such as a scan signal) to the pixel (including the active component 130 and the pixel electrode 140), the charging time between adjacent pixels corresponding to the adjacent first signal line 110 can be reduced. The difference is to improve stripe moiré and improve display quality.

In this embodiment, the sequential connection of the bridge point X of the first first signal line 110 to the bridge point X of the last first signal line 110 constitutes a fold line PL, and the fold line PL has at least one turning point TP. The location of the at least one turning point TP is the position of at least one of the bridging points X. In FIG. 1A, it is assumed that the inflection point TP corresponds to the bridging point X of the nth first signal line 110. For convenience of explanation, the bridge point X of the nth first signal line 110, that is, the first to the first (n-1) the bridge point X of the first signal line 110, referred to as the front bridge contact, and the bridge point X after the nth first signal line 110, that is, the (n+1)th to the Nth The bridge point X of the first signal line 110 is simply referred to as a rear bridge contact.

Under the architecture that the number of the first signal lines 110 is greater than the number of the second signal lines 120, the pixel array 100 is not changed (increased) by the number of the second signal lines 120 by the design of the at least one turning point TP. More bridge points X can be formed. The design of the number of the at least one selection line 150 between the at least one inflection point TP and the two second signal lines 120 is as follows. When the number of the at least one turning point TP is j, the number of the at least one selection line 150 between the adjacent two second signal lines 120 is j or (j+1), and j≥1.

When the number of the at least one turning point TP is 0, the number of the at least one selection line 150 between the adjacent two second signal lines 120 may be one. However, when the number of the at least one turning point TP is ≥1, a selection line 150 connected to the rear bridge contact point is added between the second signal lines 120 to transmit a signal (such as a scanning signal) to correspond to the rear bridge contact point. The first signal line 110. By adding the number of the selection lines 150 between the adjacent two second signal lines 120, a plurality of selection lines 150 are disposed between the adjacent two second signal lines 120, and a part of the plurality of selection lines 150 can be bridged with the front The points are connected, and another portion of the plurality of selection lines 150 can be connected to the rear bridge contacts. In this way, the front bridge contact and the rear bridge contact can respectively intersect with different strip selection lines 150, that is, the first signal line 110 does not need to share the same selection line 150. In this architecture, each of the rear bridge contacts is located between the adjacent two second signal lines 120 together with one of the front bridge contacts, so that there are a plurality of bridge points X between the adjacent two second signal lines 120.

It should be noted that the selection line 150 between the adjacent two second signal lines 120 does not have to be electrically connected to the first signal line 110. That is, the number of bridge points X between adjacent two second signal lines 120 may be less than or equal to the number of select lines 150 between adjacent two second signal lines 120. For example, one of the two select lines 150 located between the two second signal lines 120 on the leftmost side of FIG. 1A may not be electrically connected to the first signal line 110. In another embodiment, the selection line 150 that is not electrically connected to the first signal line 110 may also be omitted.

Other embodiments of the pixel array 100 will be described below with reference to FIGS. 2 through 6, wherein the same or similar elements are designated by the same or similar reference numerals, and the relative arrangement of the elements or their effects will not be described again. 2 to 6 are top plan views of pixel arrays in accordance with second to sixth embodiments of the present invention, respectively.

Referring to FIG. 2, the main differences between the pixel array 200 and the pixel array 100 of FIG. 1A are as follows. In the pixel array 100, the number of the at least one inflection point TP is one, and the number of the at least one selection line 150 between the adjacent two second signal lines 120 is two. On the other hand, in the pixel array 200, the number of the at least one inflection point TP is two, and the number of the at least one selection line 150 between the adjacent two second signal lines 120 is three.

Further, when the number of the second signal lines 120 is constant, as the first signal line 110 increases, the number of the turning points TP and the selecting line 150 between the adjacent two second signal lines 120 can be increased. The number of pixels allows the pixel array 200 to form more bridge points X.

In FIGS. 1A and 2, the inflection point TP is located at the edge of the pixel array 100, 200 (near the last second signal line 120 or the first second signal line 120). However, the position of the turning point TP can be changed as needed. Referring to FIGS. 3 and 4, the turning point TP may also be located in the middle or edge of the pixel array 300, 400.

In addition, when the number of the at least one selection line 150 between the adjacent two second signal lines 120 is k, the number of the at least one inflection point TP may be k or (k±1), k≥2. As shown in FIG. 1A and FIG. 2, the number of the at least one selection line 150 between two adjacent second signal lines 120 may be equal to the number of the at least one inflection point TP plus one. As shown in FIG. 3, the number of the at least one selection line 150 between adjacent two second signal lines 120 may be equal to the number of the at least one turning point TP. As shown in FIG. 4, the number of the at least one selection line 150 between adjacent two second signal lines 120 may be equal to the number of the at least one inflection point TP minus one.

Referring to FIG. 5, the main difference between the pixel array 500 and the pixel array 100 of FIG. 1A is the arrangement of the bridge points X. In the pixel array 100, before the turning point TP, the bridge point X is arranged from the upper left to the lower right of the pixel array 100, and after the turning point TP, the bridge point X is arranged from the upper right to the lower left of the pixel array 100. On the other hand, in the pixel array 500, the arrangement tendency of the bridge point X before and after the turning point TP is exactly opposite to that of FIG. 1A. Figures 2 to 4 can also be modified as such, and will not be described again.

Referring to FIG. 6, the main differences between the pixel array 600 and the pixel array 100 of FIG. 1A are as follows. In the pixel array 100, the second signal line 120 and the selection line 150 are lined from the lower side of the pixel array 100, and contribute to narrowing the width WD1 of the non-display area on the left and right sides of the pixel array 100. In the pixel array 600, the second signal line 120 and the selection line 150 are outgoing from the right side of the pixel array 600, and contribute to narrowing the width WD2 of the non-display area on the upper and lower sides of the pixel array 600.

In summary, the pixel array of the present invention causes the number of second signal lines interleaved by the connection between the bridge points of adjacent first signal lines to be one to reduce the bridge point of the adjacent first signal lines. The distance between the adjacent pixels reduces the difference in charging time between adjacent pixels, thereby improving the stripe moiré and improving the display quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500, 600‧‧‧ pixel arrays
110‧‧‧First signal line
120‧‧‧second signal line
130‧‧‧Active components
140‧‧‧ pixel electrodes
150‧‧‧Selection line
A‧‧‧ area
C‧‧‧ wafer
CH‧‧‧ channel layer
D1‧‧‧ first direction
D2‧‧‧ second direction
DE‧‧‧汲
Dx, Dy‧‧‧ distance
GE‧‧‧ gate
GI‧‧‧ brake insulation
L‧‧‧ connection
OG‧‧‧Insulation
P‧‧‧Photo District
PL‧‧‧ fold line
Px, Py‧‧ pixels
S‧‧‧Substrate
SE‧‧‧ source
TP‧‧‧ turning point
W1, W2‧‧‧ openings
WD1, WD2‧‧‧ width
X, X1, X2‧‧‧ bridge points
A-A', B-B'‧‧‧ cut line

1A is a top plan view of a pixel array in accordance with a first embodiment of the present invention. Fig. 1B is an enlarged schematic view of a region A in Fig. 1A. 1C and 1D are schematic cross-sectional views of the cross-sectional lines A-A' and B-B' in Fig. 1B, respectively. 2 to 6 are top plan views of pixel arrays in accordance with second to sixth embodiments of the present invention, respectively.

100‧‧‧ pixel array

110‧‧‧First signal line

120‧‧‧second signal line

150‧‧‧Selection line

A‧‧‧ area

C‧‧‧ wafer

D1‧‧‧ first direction

D2‧‧‧ second direction

Dx, Dy‧‧‧ distance

L‧‧‧ connection

P‧‧‧Photo District

PL‧‧‧ fold line

Px, Py‧‧ pixels

TP‧‧‧ turning point

WD1‧‧‧Width

X, X1, X2‧‧‧ bridge points

Claims (10)

A pixel array includes: a plurality of first signal lines; a plurality of second signal lines electrically electrically insulated from the first signal lines and interleaved with the first signal lines to define a plurality of pixel areas a plurality of active components are located in the pixel regions, and each of the active components is electrically connected to the corresponding first signal line and the corresponding second signal line; a plurality of pixel electrodes corresponding to the pixel regions And electrically connected to the active components; and a plurality of select lines interlaced with the first signal lines, wherein each of the first signal lines is electrically connected to one of the select lines and is in a selected one of the lines The staggered portion has a bridge point, the select lines are electrically insulated from the second signal lines, and at least one select line is disposed between the adjacent two second signal lines, wherein the first signal lines and the The number of selected lines is greater than the number of the second signal lines, respectively, and the connection between the bridge point of the first signal line of the i th and the bridge point of the (i+1)th first signal line is staggered. The number of the second signal lines is one, i=1 to N, and N is equal to the first messages. The number of lines. The pixel array of claim 1, wherein the sequential connection of the bridging point of the first first signal line to the bridging point of the last first signal line forms a broken line, and the folding line has At least one turning point. The pixel array of claim 2, wherein a plurality of the selection lines are disposed between adjacent two second signal lines. The pixel array of claim 3, wherein a plurality of the bridge points are present between adjacent two second signal lines. The pixel array of claim 4, wherein the number of the bridge points between the adjacent two second signal lines is less than or equal to the selection between the adjacent two second signal lines. The number of lines. The pixel array of claim 2, wherein the bridge points respectively intersect different strip selection lines. The pixel array of claim 2, wherein the number of the at least one inflection point is j, and the number of the at least one selection line between adjacent two second signal lines is j or (j+1) ), j ≥ 1. The pixel array of claim 2, wherein the number of the at least one selection line between adjacent two second signal lines is k, and the number of the at least one turning point is k or (k±1) ), k ≥ 2. The pixel array of claim 1, wherein the selection lines and the pixel electrodes do not overlap each other. The pixel array of claim 1, wherein the selection lines are in the same layer as the second signal lines, and the selection lines are located at different layers from the first signal lines.