TWI596672B - Lateral double diffused metal oxide semiconductor transistor and method of making the same - Google Patents

Description

Later double-diffused metal oxide semiconductor transistor and manufacturing method thereof

The present invention generally relates to the field of semiconductor devices. More particularly, embodiments of the present invention relate to lateral double diffused metal oxide semiconductor (LDMOS) transistors and methods of fabricating the same.

In various electronic systems, voltage regulators such as DC to DC voltage converters are used to provide a stable voltage source. Battery management in low power devices (eg, notebooks, mobile phones, etc.) in particular requires a highly efficient DC to DC converter. The switching voltage regulator generates an output voltage by converting an input DC voltage into a high frequency voltage and then filtering the high frequency input voltage to generate an output DC voltage. In particular, the switching regulator includes a power switch for alternately coupling a DC voltage source (eg, a battery) to a load (eg, an integrated circuit (IC)) and decoupling the two. The output filter typically includes an inductor and a capacitor that can be coupled between the input voltage source and the load to filter the output of the switch, thereby providing an output DC voltage. A controller (eg, a pulse width modulator, a pulse frequency modulator, etc.) can control the power switch to maintain a substantially constant output DC voltage.

The power switch can be a semiconductor device including a metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT). The source region of the LDMOS transistor is formed in a body region of a doping type opposite to that of the LDMOS transistor, and the germanium region is formed in a high resistance drift region of the same doping type as the conductivity type of the device. Due to the presence of the drift region, the drain of the LDMOS can withstand high voltages. Therefore, LDMOS transistors have the advantages of large driving current, low on-resistance, and high breakdown voltage, and are widely used in switching regulators.

In the prior art process for forming LDMOS, field oxide (LOCOS) is used to form a field oxide FOX for defining an active region and a high voltage gate oxide HVGOX for a gate dielectric, and ion implantation using a gate conductor. The doped regions are formed in a self-aligned manner. In a self-aligned process, the gate conductor acts as a hard mask to define the location of the doped regions.

However, as the size of the power switch is reduced, the width and thickness of the gate conductor are getting smaller and smaller. When the gate conductor is relatively thin, the implanted ions can pass through the gate conductor into the semiconductor substrate. The gate conductor cannot act as a barrier to ion implantation and thus does not accurately define the exact location of the doped region.

In addition, due to the bird's beak phenomenon in the field oxide, the size is difficult to reduce. As the size of the power switch shrinks, the field area occupied by the field oxide becomes larger and larger relative to the area of the active area, thereby becoming a key factor limiting the size reduction of the power switch. The field oxide also causes surface steps, which result in uneven thickness of the gate conductor when the gate conductor is relatively thin, and it is difficult to pattern the gate conductor during etching. Therefore, in the formation of LDMOS with thin gate conductors, the existing process for forming LDMOS has low product yield and reliability. Poor question.

It is an object of the present invention to provide a lateral double diffused metal oxide semiconductor (LDMOS) transistor and a method of fabricating the same that can improve process window and product reliability.

According to an aspect of the present invention, a method of fabricating a lateral double-diffused metal oxide semiconductor transistor is provided, comprising: forming a semiconductor layer of a first doping type; forming a high voltage gate dielectric on a surface of the semiconductor layer; Forming at least a portion of a thin gate dielectric adjacent to the high voltage gate dielectric; forming a gate conductor on the thin gate dielectric and the high voltage gate dielectric; patterning the gate using the first mask a conductor defining a first sidewall of the gate conductor, wherein the first sidewall is above the thin gate dielectric; patterning the gate conductor with a second mask to define a second sidewall of the gate conductor, wherein At least a portion of the second sidewall is over the high voltage gate dielectric; forming a source region and a germanium region of the first doping type, wherein the method further includes implanting a dopant via the first mask Forming a body region of a second doping type, the second doping type being opposite to the first doping type.

Preferably, in the method, the step of defining a second sidewall of the gate conductor is performed prior to the step of defining the first sidewall of the gate conductor, or the defining gate is performed after the step of defining the first sidewall of the gate conductor The step of the second side wall of the pole conductor.

Preferably, the method further comprises: after forming the body region of the second doping type, implanting a dopant of the first doping type with a first mask, To form a source junction zone.

Preferably, in the method, forming the semiconductor layer of the first doping type comprises: implanting a dopant in the semiconductor substrate to form a deep well region of the first doping type as the semiconductor layer.

Preferably, in the method, forming the semiconductor layer of the first doping type comprises: epitaxially growing a semiconductor layer on the semiconductor substrate; and implanting a dopant of the first doping type in the semiconductor layer.

Preferably, in the method, before the step of forming the semiconductor layer, or between the step of forming the semiconductor layer and the step of forming the high voltage gate dielectric, further comprising forming a shallow trench for defining the active region Slot isolation.

Preferably, in the method, between the step of forming a semiconductor layer and the step of forming a high voltage gate dielectric, further comprising forming a field oxide for defining an active region.

Preferably, in the method, high voltage gate dielectric is formed by local oxidation of germanium.

Preferably, in the method, the high voltage gate dielectric extends laterally beyond the edge of the gate conductor on the side of the germanium region.

Preferably, in the method, after forming the gate stack composed of the thin gate dielectric, the high voltage gate dielectric and the gate conductor, the gate side is formed on the sidewall of the gate conductor. wall.

Preferably, in the method, after forming the source region and the germanium region, further comprising: forming a body contact region of a second doping type adjacent to the source region.

Preferably, in the method, the body contacting region is heavily doped with respect to the body region.

Preferably, in the method, a drift region of a first doping type adjacent to the high voltage gate dielectric is formed, wherein the source region and the germanium region are heavily doped with respect to the drift region.

Preferably, in the method, the thin gate dielectric and the high voltage gate dielectric are respectively composed of at least one selected from the group consisting of oxides, nitrides, and high-K dielectrics.

According to another aspect of the present invention, there is provided a lateral double-diffused metal oxide semiconductor transistor fabricated by the above method, comprising: a semiconductor layer of a first doping type; a second doping located in the semiconductor layer and spaced apart from each other a body region of a type and a drift region of a first doping type, the second doping type being opposite to the first doping type; a source region of a first doping type located in the body region; a first doping located in the drift region a type of germanium region; a thin gate dielectric and a high voltage gate dielectric between the source region and the germanium region, the thin gate dielectric being adjacent to the source region, the high voltage gate dielectric The electrical material is adjacent to the germanium region; and a gate conductor on the thin gate dielectric and the high voltage gate dielectric.

Preferably, the lateral double-diffused metal oxide semiconductor transistor further includes shallow trench isolation for defining an active region.

Preferably, in the lateral double-diffused metal oxide semiconductor transistor, the semiconductor layer is one selected from the group consisting of a deep well region located in the semiconductor substrate and a doped semiconductor layer on the semiconductor substrate.

Preferably, in the lateral double-diffused metal oxide semiconductor transistor, the high voltage gate dielectric extends laterally beyond the edge of the gate conductor on the side of the germanium region.

Preferably, the lateral double-diffused metal oxide semiconductor transistor further comprises: a body contact region of a second doping type located in the body region and adjacent to the source region.

Preferably, in the lateral double-diffused metal oxide semiconductor transistor, the body contact region is heavily doped with respect to the body region.

Preferably, in the lateral double-diffused metal oxide semiconductor transistor, the source region and the germanium region are heavily doped with respect to the drift region.

Preferably, in the lateral double-diffused metal oxide semiconductor transistor, the thin gate dielectric and the high voltage gate dielectric are respectively selected from the group consisting of oxides, nitrides, and high-k dielectrics. At least one of the components.

According to the manufacturing method of the semiconductor device of the above embodiment, after the oxide layer and the conductor layer are formed, the gate conductor is formed by two photolithography processes, wherein the mask of one photolithography process is used to define the first of the gate conductors. The sidewalls are again used to form body regions to achieve alignment of the gate conductors with the body regions. The ion implantation process window hardly deviates from the predetermined process window, which simplifies the process steps and improves the reliability of the final device while ensuring the performance of the semiconductor device.

In a preferred embodiment, the use of shallow trench isolation instead of field oxide facilitates reducing the size of the field region, thereby further reducing the size of the semiconductor device. Moreover, since a flat semiconductor structure surface can be obtained, a thin gate dielectric having a uniform thickness and good quality can be formed, thereby improving the yield and reliability of the semiconductor device. In a further preferred embodiment, shallow trench isolation is formed prior to formation of the semiconductor layer to be compatible with conventional CMOS processes.

101‧‧‧Semiconductor substrate

102‧‧‧ Deep Well Area

104‧‧‧Shallow trench isolation

105‧‧‧ Field oxide

106‧‧‧High-voltage gate oxide

107‧‧‧Thin gate oxide

108‧‧‧gate conductor

109‧‧‧ Body area

110‧‧‧drift area

112‧‧‧gate side wall

115‧‧‧ source area

116‧‧‧汲

118‧‧‧ Body contact area

PR1‧‧‧Photoresist mask

PR2‧‧‧Photoresist mask

PR3‧‧‧Photoresist mask

PR4‧‧‧Photoresist mask

PR5‧‧‧Photoresist mask

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the embodiments of the invention <RTIgt 2a and 2b are cross-sectional views showing a part of a stage of a method of fabricating an LDMOS transistor according to the prior art; and Figs. 3a and 3b respectively show exploded perspective views of an LDMOS transistor according to an embodiment of the present invention and FIG. 4a to 4j illustrate cross-sectional views of stages of a method of fabricating an LDMOS transistor in accordance with an embodiment of the present invention; and FIGS. 5a to 5c illustrate fabrication of an LDMOS transistor in accordance with another embodiment of the present invention. A cross-sectional view of a part of the method.

The invention will be described in more detail below with reference to the drawings. In the various figures, the same elements are represented by similar element symbols. For the sake of clarity, the various parts of the drawings are not drawn to scale. Moreover, some well-known parts may not be shown. For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "on" or "above" another layer, it may mean that it is directly on another layer, another region, or another There are other layers or regions between the layers and another region. Also, if the device is turned over, the one layer, one area will be located on the other layer, and the other area "below" or "below".

In the case of a description directly above another layer or another region, the expression "A is directly above B" or "A is above and adjacent to B" is used herein. In the present invention, "A directly in B" means that A is located in B, and A is directly adjacent to B, and not A is located in the doped region formed in B.

In the present invention, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in the respective steps of fabricating a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the device in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

1a and 1b show exploded perspective and cross-sectional views, respectively, of an LDMOS transistor according to the prior art. In Figure 1a, the various portions of the LDMOS transistor are shown separately from the semiconductor substrate for clarity. The cross-sectional view shown in Figure 1b is taken along line AA in Figure 1a.

As shown in Figures 1a and 1b, the LDMOS transistor includes a field oxide 105 for defining an active region. The LDMOS transistor further includes: a first doping type deep well region 102 on the semiconductor substrate 101; a second doping type body region 109 and a first doping type in the deep well region 102 and spaced apart from each other a drift region 110; a source region 115 of a first doping type located in the body region 109 and a body contact region 118 of a second doping type adjacent thereto; a first doping type germanium region 116 in the drift region 110; a thin gate oxide 107 and a high voltage gate oxide 106, a thin gate oxide 107 and a source between the source region 115 and the germanium region 116 of the LDMOS transistor The regions 115 are adjacent, the high voltage gate oxide 106 is adjacent to the germanium region 116; the gate conductor 108 is located on the thin gate oxide 107 and the high voltage gate oxide 106. The high voltage gate oxide 106 extends laterally beyond the edge of the gate conductor 108 on the side of the germanium region 116. The bulk contact region 118 has the same doping type but a higher doping concentration than the body region 109. Furthermore, the source region 115 and the germanium region 116 have the same doping type but a higher doping concentration than the drift region 110. The first doping type is opposite to the second doping type. For example, the first doping type is N-type, the second doping type is P-type, or vice versa.

The field oxide 105 formed by LOCOS has a thickness of between about 4,000 angstroms and about 5,000 angstroms, and the high-voltage gate oxide 106 formed by LOCOS has a thickness of from about 250 angstroms to about 1,500 angstroms, and a thin gate oxide formed by thermal oxidation. The thickness of 107 is between about 100 angstroms and about 300 angstroms. In the LOCOS process, field oxide 105 grows laterally under the nitride mask due to lateral diffusion of oxygen atoms. At the same time, since the oxide layer is thicker than the consumed germanium, the field oxide 105 is elevated relative to the surface of the semiconductor substrate. Therefore, the cross-sectional shape of the field oxide 105 is similar to the "bird's beak". The field oxide 105 is a key factor limiting the size reduction of the power switch, and results in uneven thickness of the subsequently formed gate conductor, which not only causes etching difficulties, but also introduces reliability problems.

2a and 2b show cross-sectional views of a portion of a method of fabricating an LDMOS transistor in accordance with the prior art. In the step shown in Figure 2a, A deep well region 102, a field oxide 105, and a high voltage gate oxide 106 have been formed on the semiconductor substrate 101. Further, after forming the thin oxide layer and the conductor layer, etching is performed using the photoresist mask PR1, and the thin oxide layer and the conductor layer are patterned to form the thin gate oxide 107 and the gate conductor 108, respectively.

The photoresist mask PR1 is then removed, and a photoresist mask PR2 is again formed on the surface of the semiconductor structure. The body region 109 is formed in the deep well region 102 by ion implantation through the photoresist mask PR2.

Although in an ideal situation, it is desirable for the photoresist mask PR2 to be aligned with the thin gate oxide 107 and the gate conductor 108 to serve as a mask during ion implantation, however, such alignment is difficult in the process. achieve. Even, it may happen that the photoresist mask PR2 is beyond the side of the gate conductor 108 such that no dopant is implanted in the region adjacent to the gate conductor 108.

It has been found that in the case where the gate conductor 108 is thick, the body region 109 can be formed using the gate conductor 108 as a hard mask. To this end, the opening in the photoresist mask PR2 exposes the sidewalls of the gate conductor 108. In ion implantation, at least a portion of body region 109 adjacent to gate conductor 108 is self-aligned with gate conductor 108. However, in the case where the gate conductor 108 is thin, the implanted ions can pass through the gate conductor 108 into the well region 102, with the result that the exact position of the body region 109 cannot be accurately defined.

3a and 3b show exploded perspective and cross-sectional views, respectively, of an LDMOS transistor in accordance with an embodiment of the present invention. In Figure 3a, the various portions of the LDMOS transistor are separated from the semiconductor substrate for clarity. Out. The cross-sectional view shown in Figure 3b is taken along line AA in Figure 3a.

The LDMOS transistor according to this embodiment differs from the prior art LDMOS transistor shown in Figures 2a and 2b in that a shallow trench isolation 104 is used instead of the field oxide 105 to define an active region.

The formation of shallow trench isolations 104 is compatible with conventional CMOS processes, for example, may be formed using etching and deposition processes, and may be planarized by chemical mechanical planarization to subsequently form gate conductors 108 of uniform thickness. Compared to the field oxide 105, the shallow trench isolation 104 can have a significantly reduced wafer footprint, achieve a reduction in size of the power switch, and can form a thin conductor layer of uniform thickness so that the gate conductor can be easily patterned. 108, improving the reliability of the final device.

Other aspects of the LDMOS transistor according to this embodiment are the same as the prior art LDMOS transistors shown in Figures 2a and 2b.

4a through 4j illustrate cross-sectional views of various stages of a method of fabricating an LDMOS transistor, in accordance with an embodiment of the present invention. The cross-sectional views shown in Figures 4a to 4j are each taken along line AA in Figure 3a.

The method begins with a semiconductor substrate 101. A shallow trench isolation 104 for defining an active region is formed in the semiconductor substrate 101. The process for forming shallow trench isolations 104 is compatible with conventional CMOS processes and can be formed simultaneously with shallow trench isolation of CMOS devices.

For example, the step of forming the shallow trench isolation 104 includes forming a photoresist layer on the semiconductor substrate 101. A pattern of shallow trench isolations 104 is defined by photolithography, i.e., an opening is formed in a portion of the photoresist layer corresponding to the shallow trench isolations 104 to form a photoresist mask (not shown). Of course Thereafter, etching is performed from the opening in the photoresist mask to form an opening in the semiconductor substrate 101. By controlling the etching time, the opening in the semiconductor substrate 101 is brought to a desired depth to form a shallow trench. The insulating material is then deposited to fill the shallow trenches to form shallow trench isolation. Optionally, chemical mechanical planarization is used to remove portions of the exterior of the shallow trench.

The above etching may be performed by dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or selective wet etching using an etchant solution. After etching, the photoresist mask is removed by dissolving or ashing in a solvent. The above deposition process is, for example, one selected from the group consisting of electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering.

Then, a deep well region 102 having a first volume and a first surface region is formed on the semiconductor substrate 101. Among them, the deep well region 102 has a first doping type. The semiconductor substrate 101 is composed of, for example, germanium. In the present invention, the first doping type is opposite to the second doping type. For example, the first doping type is one of an N type and a P type, and the second doping type is the other of an N type and a P type.

For example, the step of forming the deep well region 102 includes forming a photoresist layer on the semiconductor substrate 101. A pattern of the deep well region 102 is defined by photolithography, i.e., an opening is formed in a portion of the photoresist layer corresponding to the deep well region 102 to form a photoresist mask (not shown). Subsequently, ion implantation is performed using a conventional bulk implantation and driving technique to form a deep well region 102 in the semiconductor substrate 101.

In order to form an N-type semiconductor layer or region, it is possible to form a semiconductor layer and region An N-type dopant (eg, P, As) is implanted into the domain. In order to form a P-type semiconductor layer or region, a P-type dopant (for example, B) may be doped in the semiconductor layer and region.

By controlling the parameters of the ion implantation, such as the implantation energy and the dose, the desired depth can be achieved and the desired doping concentration can be achieved. The lateral extent of the deep well region 102 can be controlled using an additional photoresist mask.

Next, by using the LOCOS process, a high voltage gate oxide 106 is formed on a portion of the surface of the active region defined by the shallow trench isolation 104 in the deep well region 102, as shown in Figure 4b. The high voltage gate oxide 106 will extend from below the gate conductor to adjacent the germanium region. In the present embodiment, preferably, the high voltage gate oxide 106 is an oxide layer.

The LOCOS process includes, for example, forming a nitride protective layer on the surface of the deep well region 102; forming an opening in the nitride protective layer to expose a portion of the surface of the deep well region 102; performing thermal oxidation to cause oxide growth on the exposed surface of the deep well region The layers form a high voltage gate oxide 106.

Further, an oxide layer 107 is formed on the surface of the deep well region 102. The formation of the oxide layer 107 may employ thermal oxidation or a known deposition process as described above. The oxide layer 107 may be an oxide layer, a nitride, an oxynitride, a niobate, an aluminate, or a titanate. Preferably, in the present embodiment, the oxide layer 107 is an oxide layer. Preferably, in the present embodiment, the oxide layer 107 has a thickness less than the high voltage gate oxide 106. For example, the high voltage gate oxide 106 has a thickness of about 1000 angstroms, and the oxide layer 107 formed by thermal oxidation has a thickness of between about 100 angstroms and about 300 angstroms.

Then, a conductor layer 108 is formed on the surface of the oxide layer 107 as shown in Fig. 4c. Forming the conductor layer 108 can employ the known deposition process described above. The conductor layer 108 may be, for example, a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC. , TiAlN, TaN, PtSix, Ni ₃ Si, Pt, Ru, W, and combinations of the various conductive materials. Preferably, in this embodiment, the conductive layer is a polysilicon layer.

Further, a photoresist mask PR1 is formed over the semiconductor structure. The photoresist mask PR1 defines a pattern of the body region 109, that is, an opening is formed in a portion of the photoresist layer corresponding to the body region 109. Then, etching is performed from the opening in the photoresist mask to remove the exposed portion of the conductor layer 108. The etching may stop at the surface of the oxide layer 107 due to the selectivity of the etching. In practice, however, the exposed surface layer of oxide layer 107 will be overetched a small portion to ensure that conductor layer 108 is completely etched. The etching forms a first sidewall of the gate conductor as shown in Figure 4d. After the etching, the photoresist mask PR1 remains.

Further, ion implantation is performed via the photoresist mask PR1 using conventional bulk implantation and driving techniques to form a body region 109 of the second doping type in the deep well region 102, as shown in Figure 4e. After the ion implantation, the photoresist mask PR1 is removed by dissolving or ashing in a solvent.

Since etching and ion implantation are performed using the same photoresist mask PR1 in the steps shown in Figs. 4d and 4e, at least a portion of the sidewalls of the gate conductor are aligned with the body region 109.

Further preferably, in forming the body region 109 of the second doping type Thereafter, a dopant of the first doping type is implanted using a photoresist mask PR1 to form a source junction region.

Further, a photoresist mask PR2 is formed over the semiconductor structure. The photoresist mask PR2 defines a pattern of gate conductors and blocks the body region 109, i.e., the portion of the photoresist layer that corresponds to the gate conductor and body region 109.

Then, etching is performed downward from the opening in the photoresist mask PR2 to remove the exposed portion of the conductor layer 108. The etching may stop at the surface of the oxide layer 107 and the high voltage gate oxide 106 due to the selectivity of the etching. In practice, however, the surface layer of the exposed portions of oxide layer 107 and high voltage gate oxide 106 will be overetched a small portion to ensure that conductor layer 108 is completely etched. The etching forms a second sidewall of the gate conductor as shown in Figure 4f. After the etching, the photoresist mask PR2 is removed by dissolving or ashing in a solvent.

Further, a photoresist mask PR3 is formed over the semiconductor structure. The photoresist mask PR3 defines a pattern of the drift region 110, that is, an opening is formed in a portion of the photoresist layer corresponding to the drift region 110.

Then, ion implantation is performed via the photoresist mask PR3 using conventional bulk implantation and driving techniques to form a first doping type drift region 110 in the deep well region 102, as shown in Figure 4g. After the ion implantation, the photoresist mask PR3 is removed by dissolving or ashing in a solvent.

Further, a conformal nitride layer is formed on the surface of the semiconductor structure through the above known deposition process. Removing the laterally extending portion of the nitride layer through an anisotropic etching process (eg, reactive ion etching) The vertical portion of the nitride layer on the side of the gate conductor 108 is left to form the gate spacer 112, as shown in Figure 4h. In one example, the gate spacers 112 are tantalum nitride layers having a thickness of about 5-20 nm.

Further, a photoresist mask PR4 is formed over the semiconductor structure. The photoresist mask PR4 defines a pattern of the source region 115 and the germanium region 116, that is, an opening is formed in a portion of the photoresist layer corresponding to the source region 115 and the germanium region 116. In the present embodiment, preferably, the opening also exposes the gate conductor 108 and the gate spacer 112.

Then, ion implantation is performed via the photoresist mask PR4 by conventional bulk implantation and driving techniques to form a source region 115 in the body region 109 and a germanium region 116 in the drift region 110, as shown in FIG. 4i. Show. After the ion implantation, the photoresist mask PR4 is removed by dissolving or ashing in a solvent.

In ion implantation, if the opening of the photoresist mask PR4 also exposes the gate conductor 108 and the gate spacer 112, the gate conductor 108 and the gate spacer 112 can serve as a hard mask, and photodamage The etchant mask PR4 together define a source region 115 and a germanium region 116. The gate conductor 108 and the gate spacer 112 serve as hard masks, which can reduce the complexity and alignment difficulty of the photoresist mask PR4.

The source region 115 and/or the germanium region 116 may be formed using a double diffusion process. In the double diffusion process, two injections are made in the same area and a high temperature propulsion process is performed. For example, when the conductivity type of the LDMOS transistor is N-type, in order to form the source region 115, the dopant for the first ion implantation is, for example, arsenic, and the doping concentration is high, and the dopant for the second ion implantation is, for example, Is boron, and And the doping concentration is low. In the high-temperature propulsion process after two ion implantations, since boron diffusion is faster than arsenic diffusion, boron diffuses farther than arsenic in the horizontal direction, so that the lateral extension distance of the low-doped region is greater than the lateral extension distance of the highly doped region. , forming a lateral concentration gradient. The portion of source region 115 and germanium region 116 that extends laterally below gate conductor 108 is not shown in FIG. 4i for simplicity.

Further, a photoresist mask PR5 is formed over the semiconductor structure. The photoresist mask PR5 defines a pattern of body contact regions 118, i.e., an opening is formed in a portion of the photoresist layer corresponding to the body contact region 118.

Then, ion implantation is performed via the photoresist mask PR5 using a conventional bulk implantation and driving technique, and a body contact region 118 is formed in a portion of the body region 109 adjacent to the source region 115, as shown in Fig. 4j. . After the ion implantation, the photoresist mask PR5 is removed by dissolving or ashing in a solvent.

5a through 5c illustrate cross-sectional views of a portion of a method of fabricating an LDMOS transistor in accordance with another embodiment of the present invention. The cross-sectional views shown in Figures 5a to 5c are each taken along line AA in Figure 3a.

In this method, the steps shown in Figs. 5a to 5c are performed instead of the steps shown in Figs. 4d to 4f.

After forming the semiconductor structure shown in FIG. 4c, a photoresist mask PR1 is formed over the semiconductor structure. The photoresist mask PR1 defines a pattern of gate conductors and blocks the body regions, i.e., the portions of the photoresist layer that correspond to the gate conductors and body regions.

Then, etching down from the opening in the photoresist mask PR1 to The exposed portion of the conductor layer 108 is removed. The etching may stop at the surface of the oxide layer 107 due to the selectivity of the etching. In practice, however, the surface layer of the exposed portions of oxide layer 107 and high voltage gate oxide 106 will be overetched a small portion to ensure that conductor layer 108 is completely etched. The etching forms a first sidewall of the gate conductor, i.e., a sidewall adjacent the germanium region, as shown in Figure 5a. This etch can expose the high voltage gate oxide 106. After the etching, the photoresist mask PR1 is removed by dissolving or ashing in a solvent.

Further, a photoresist mask PR2 is formed over the semiconductor structure. The photoresist mask PR2 defines a pattern of the body region 109, that is, an opening is formed in a portion of the photoresist layer corresponding to the body region 109. Then, etching is performed from the opening in the photoresist mask to remove the exposed portion of the conductor layer 108. The etching may stop at the surface of the oxide layer 107 due to the selectivity of the etching. In practice, however, the exposed surface layer of oxide layer 107 will be overetched a small portion to ensure that conductor layer 108 is completely etched. The etch forms a second sidewall of the gate conductor that is aligned with body region 109. After the etching, the photoresist mask PR2 is still left.

Further, ion implantation is performed via the photoresist mask PR2 using conventional bulk implantation and driving techniques to form a body region 109 of the second doping type in the deep well region 102, as shown in Figure 5c. After the ion implantation, the photoresist mask PR2 is removed by dissolving or ashing in a solvent.

Since etching and ion implantation are performed using the same photoresist mask PR2 in the steps shown in Figs. 5b and 5c, at least a portion of the sidewalls of the gate conductor are aligned with the body region 109.

Further preferably, in forming the body region 109 of the second doping type Thereafter, a dopant of the first doping type is implanted using a photoresist mask PR2 to form a source junction region.

After the step shown in Figure 5c, the steps shown in Figures 4g through 4j are continued.

In the method of the above embodiment, after the source region and the germanium region are formed, a portion of the thin gate oxide 107 above the contact region may be removed on the obtained semiconductor structure to expose the contact region, but an interlayer insulating layer is formed. The interlayer insulating layer reaches the via hole of the contact region, the wiring or the electrode on the upper surface of the interlayer insulating layer, thereby completing other portions of the LDMOS transistor.

It should be noted that in the method of the above embodiment, the order of formation of the respective doping regions is not limited, and doped regions having the same doping type may be simultaneously formed. The above embodiments schematically list the order of the respective steps, but are not limited only to the order of the respective steps listed in the embodiment. In alternative embodiments, transistors and other devices that are compatible in the process can be arbitrarily added.

In an alternate embodiment, a doped epitaxial semiconductor layer can be used in place of the deep well region 102 in the semiconductor substrate 101, and a field oxide can be used instead of the shallow trench isolation 104, the gate spacers 112 can be omitted, and / A nitride or high K dielectric material may be used in place of the thin gate oxide 107 and the high voltage oxide 106.

In another alternative embodiment, instead of forming a shallow trench isolation 104 prior to forming the deep well region 102, a field oxide replacement may be formed between the steps of forming the deep well region 102 and the high voltage gate oxide 106. Trench isolation 104.

In another alternative embodiment, instead of the photoresist mask used in the various steps, a hard mask such as an oxide or nitride may be employed.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it should be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the scope of the claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the invention.

101‧‧‧Semiconductor substrate

102‧‧‧ Deep Well Area

105‧‧‧ Field oxide

106‧‧‧High-voltage gate oxide

108‧‧‧gate conductor

109‧‧‧ Body area

110‧‧‧drift area

112‧‧‧gate side wall

115‧‧‧ source area

116‧‧‧汲

118‧‧‧ Body contact area

Claims (14)

A method of fabricating a lateral double-diffused metal oxide semiconductor transistor, comprising: forming a semiconductor layer of a first doping type; forming a high voltage gate dielectric on a surface of the semiconductor layer; and using a mask on the semiconductor layer Forming at least a portion of the thin gate dielectric adjacent to the high voltage gate dielectric; forming a gate conductor on the thin gate dielectric and the high voltage gate dielectric without using a mask; Masking the gate conductor to define a first sidewall of the gate conductor, wherein the first sidewall is above the thin gate dielectric; patterning the gate conductor with a second mask, defining the a second sidewall of the gate conductor, wherein at least a portion of the second sidewall is above the high voltage gate dielectric; forming a source region and a drain region of a first doping type, wherein the method further comprises A mask is implanted to form a body region of a second doping type, the second doping type being opposite to the first doping type. The method of claim 1, wherein the step of defining the second sidewall of the gate conductor or the step of defining the first sidewall of the gate conductor is performed prior to the step of defining the first sidewall of the gate conductor A step of defining a second sidewall of the gate conductor is then performed. The method of claim 2, comprising: after forming the body region of the second doping type, using the first mask The dopant of the first doping type is implanted to form a source junction region. The method of claim 1, wherein the forming the semiconductor layer of the first doping type comprises implanting a dopant into the semiconductor substrate to form a deep well region of the first doping type as the semiconductor layer. The method of claim 1, wherein the forming the semiconductor layer of the first doping type comprises: epitaxially growing the semiconductor layer on the semiconductor substrate; and implanting the dopant of the first doping type in the semiconductor layer . According to the method of claim 1, in the step of forming the semiconductor layer, or between the step of forming the semiconductor layer and the step of forming the high-voltage gate dielectric, forming a region for defining an active region Shallow trench isolation. According to the method of claim 1, in the step of forming the semiconductor layer and the step of forming the high voltage gate dielectric, further comprising forming a field oxide for defining an active region. The method of claim 1, wherein the high voltage gate dielectric is formed by local oxidation of germanium. The method of claim 1, wherein the high voltage gate dielectric extends laterally beyond the edge of the gate conductor on the side of the germanium region. The method of claim 1, wherein after forming the gate stack of the thin gate dielectric, the high voltage gate dielectric and the gate conductor, the sidewall of the gate conductor is further included The gate side wall is formed on the upper side. Forming the source region according to the method of claim 1 And after the germanium region further comprising: forming a body contact region of the second doping type adjacent to the source region. The method of claim 11, wherein the body contacting region is heavily doped with respect to the body region. According to the method of claim 1, the first doping type drift region adjacent to the high voltage gate dielectric is formed, wherein the source region and the germanium region are heavily doped with respect to the drift region. The method of claim 1, wherein the thin gate dielectric and the high voltage gate dielectric are each composed of at least one selected from the group consisting of oxides, nitrides, and high-k dielectrics.