TWI594395B - Semiconductor structure and operation method of the same - Google Patents

Description

Semiconductor structure and method of operation thereof

The present disclosure is directed to a semiconductor structure and method of operation thereof. The present disclosure is particularly directed to a semiconductor structure suitable for use in electrostatic discharge (ESD) protection and methods of operation thereof.

Electrostatic discharge can cause damage to sensitive electronic devices. Therefore, electrostatic discharge protection is typically provided to the semiconductor structure. Semiconductor controlled rectifier (SCR) is an electrostatic discharge protection structure that is widely used in semiconductor structures such as input/output pads or high voltage pads. However, since the SCR collapses at the N/P junction before conduction, a typical SCR has too high a driving voltage for electrostatic discharge protection applications. Therefore, research and improvement on the application of electrostatic discharge protection are still in progress today.

In the present disclosure, a semiconductor structure and method of operation thereof are provided, and in particular, a semiconductor structure suitable for electrostatic discharge protection applications and methods of operation thereof.

In accordance with some embodiments, a semiconductor structure includes a first well, a second well, a first heavily doped region, a second heavily doped region, and at least one switch. The first well has a first conductivity type. The second well has a second conductivity type that is different from the first conductivity type. The second well is coupled to the first well. The first heavily doped region has a second conductivity type. The first heavily doped region is coupled to the first well. The first heavily doped region is coupled to a first node. The second heavily doped region has a first conductivity type. The second heavily doped region is coupled to the second well. The second heavily doped region is coupled to a second node. The at least one switch satisfies at least one of the following conditions (A) and (B): (A) the switch is coupled between the first well and the first node such that the first well is controlled by the switch and protected by an electrostatic discharge The mode is floated; and (B) the switch is coupled between the second well and the second node such that the second well is controlled by the switch and floats in an electrostatic discharge protection mode.

According to some embodiments, the method of operating a semiconductor structure as described above includes the following at least one of steps (a) and (b) corresponding to conditions (A) and (B), respectively: (a) in an electrostatic discharge protection mode Disconnecting the switch to float the first well; and (b) in the electrostatic discharge protection mode, opening the switch to float the second well.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

A semiconductor structure in accordance with an embodiment includes a first well, a second well, a first heavily doped region, a second heavily doped region, and at least one switch. The second well is coupled to the first well. The first heavily doped region is coupled to the first well. The first heavily doped region is coupled to a first node. The second heavily doped region is coupled to the second well. The second heavily doped region is coupled to a second node. The first well and the second heavily doped region have a first conductivity type. The second well and the first heavily doped region have a second conductivity type different from the first conductivity type. According to some embodiments, the first node may be an anode and the second node may be a cathode. According to some embodiments, the first conductivity type may be an N-type and the second conductivity type may be a P-type. According to some embodiments, the first transistor may be a P-type metal oxide semiconductor (PMOS) and the second transistor may be an N-type metal oxide semiconductor (NMOS).

In the semiconductor structure according to the embodiment, the at least one switch satisfies at least one of the following conditions (A) and (B): (A) the switch is coupled between the first well and the first node such that the first well is The switch is controlled and floats in an electrostatic discharge protection mode; and (B) the switch is coupled between the second well and the second node such that the second well is controlled by the switch and floats in an electrostatic discharge protection mode. Further, the method of operating the semiconductor structure includes the following at least one of steps (a) and (b) corresponding to the conditions (A) and (B), respectively: (a) in the electrostatic discharge protection mode, the switch is turned off, To float the first well; and (b) in the electrostatic discharge protection mode, open the switch to float the second well.

Various details of exemplary semiconductor structures in accordance with embodiments will be described below with reference to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated into another embodiment without additional enumeration.

FIG. 1 illustrates a semiconductor structure in accordance with an embodiment. The semiconductor structure includes a first well 102, a second well 104, a first heavily doped region 112, and a second heavily doped region 114. The first well 102 has a first conductivity type, such as an N-type. The second well 104 has a second conductivity type, such as a P-type. The second well 104 is coupled to the first well 102. The first heavily doped region 112 has a second conductivity type, such as a P-type. The first heavily doped region 112 is coupled to the first well 102, such as in the first well 102. The first heavily doped region 112 is coupled to a first node 122, such as an anode. The second heavily doped region 114 has a first conductivity type, such as an N-type. The second heavily doped region 114 is coupled to the second well 104, such as in the second well 104. The second heavily doped region 114 is coupled to a second node 124, such as a cathode. As such, the first well 102, the second well 104, the first heavily doped region 112, and the second heavily doped region 114 constitute an SCR.

At least one of the first well 102 and the second well 104 is coupled to the at least one switch 130 such that the at least one of the first well 102 and the second well 104 floats in an electrostatic discharge protection mode. In the present embodiment, both the first well 102 and the second well 104 are coupled to the at least one switch 130. An exemplary switch suitable for use in this case will be described with reference to Figures 2A and 2B.

Still referring to FIG. 1, the semiconductor structure can also include a third well 106. The third well 106 has a second conductivity type, such as a P-type. In the present embodiment, the first well 102 is disposed in a substrate 100, which is, for example, a substrate 100 having a second conductivity type such as a P-type. Additionally, the second well 104 is disposed in the first well 102. The third well 106 is disposed in the first well 102 and is separated from the second well 104. In the present embodiment, the first heavily doped region 112 is disposed in the third well 106.

The semiconductor structure can also include a third heavily doped region 116. The third heavily doped region 116 has a first conductivity type, such as an N-type. The third heavily doped region 116 is coupled to the first well 102, such as in the first well 102. In the present embodiment, the first well 102 is coupled to the switch 130 by a third heavily doped region 116. This switch 130 can further couple the first well 102 to the first node 122, such as an anode. By turning this switch 130 on or off, the first well 102 can be controlled to a state or a floating state that is connected to the first node 122.

The semiconductor structure can also include a fourth heavily doped region 118. The fourth heavily doped region 118 has a second conductivity type, such as a P-type. The fourth heavily doped region 118 is coupled to the second well 104, such as in the second well 104. In the present embodiment, the second well 104 is coupled to the switch 130 by a fourth heavily doped region 118. This switch 130 can further couple the second well 104 to a second node 124, such as a cathode. By turning this switch 130 on or off, the second well 104 can be controlled to a state connected to the second node 124 or to a floating state.

Referring now to Figures 2A and 2B, there is shown an exemplary switch that is particularly suitable for use in the semiconductor structure of Figure 1. Since both the first well 102 and the second well 104 in the semiconductor structure of FIG. 1 are controlled by the at least one switch 130, the two exemplary switches are particularly adapted to simultaneously control the first well 102 and the second well 104.

As shown in FIG. 2A, a switch can include a first transistor 202 and a second transistor 204. The first transistor 202 controls a current path from the first node 122 to the first well 102. The second transistor 204 controls a current path from the second node 124 to the second well 104. The second transistor 204 is complementary to the first transistor 202. In this exemplary switch, the first transistor 202 is a PMOS and the second transistor 204 is an NMOS. The switch 130 can also include at least one inverter 206 disposed between the first transistor 202 and the second transistor 204. The switch 130 can also include a capacitor C, and a resistor R. In this exemplary switch, a first end of the capacitor C is connected to the first node 122, a second end of the capacitor C is connected to a first end of the resistor R, and a second end of the resistor R is connected to The second node 124. The first transistor 202 is connected to the second end of the capacitor C. The second transistor 204 is connected to the second end of the capacitor C through an inverter 206.

In the normal mode, a low level signal is supplied to the first transistor 202 and turns on the first transistor 202. As such, the first transistor 202 allows the current path of the first node 122 to the first well 102. The first well 102 is thereby coupled to the first node 122. At the same time, the low level signal is converted into a high level signal and supplied to the second transistor 204. As such, the second transistor 204 is turned on and allows the current path of the second node 124 to the second well 104. The second well 104 is thereby coupled to the second node 124.

Capacitor C will allow current to pass when an electrostatic discharge event occurs. At this time, a high level signal turns off the first transistor 202, thereby floating the first well 102. The high level signal is converted to a low level signal and provided to the second transistor 204. Therefore, the second transistor 204 is also closed, thereby floating the second well 104.

FIG. 2B illustrates another exemplary switch that includes more inverters 206 and an additional transistor 208. However, similar to the exemplary switch of FIG. 2A, in the electrostatic discharge protection mode, the first transistor 202 and the second transistor 204 are turned off, such that the current path and the second node of the first node 122 to the first well 102 The current path from 124 to the second well 104 is severed, thereby causing the first well 102 and the second well 104 to float. In the normal mode, both the first transistor 202 and the second transistor 204 are turned on to allow the current path of the first node 122 to the first well 102 and the current path of the second node 124 to the second well 104, thereby The first well 102 is coupled to the first node 122 and the second well 104 is coupled to the second node 124. More specifically, in general, a low level signal at the second end of capacitor C is converted twice by two inverters 206 to provide a low level signal to first transistor 202 and to conduct first transistor 202. The low level signal at the second end of the capacitor C is converted only once by an inverter 206 to provide a high level signal to the second transistor 204 and to the second transistor 204. Moreover, since the transistor 208 coupled between the second transistor 204 and the second node 124 is an NMOS, it is turned off in the case of normal processing. As such, the first well 102 is coupled to the first node 122 and the second well 104 is coupled to the second node 124. When an electrostatic discharge event occurs, a high level signal is supplied to the first transistor 202 and the first transistor 202 is turned off, a low level signal is supplied to the second transistor 204 and the second transistor 204 is turned off, and the The low level signal is provided to the transistor 208 and the transistor 208 is turned on. Thus, both the first well 102 and the second well 104 are in a floating state.

While the above example is directed to controlling the switch 130 of the first well 102 and the second well 104 at the same time, a switch 130 that controls only one of the first well 102 and the second well 104 may also be used. As an example, the first transistor 202 is coupled between the first well 102 and the first node 122, but the second transistor 204 is not coupled between the second well 104 and the second node 124. As another example, the second transistor 204 is coupled between the second well 104 and the second node 124, but the first transistor 202 is not coupled between the first well 102 and the first node 122. Alternatively, other suitable types of switches 130 can be used. Such a switch 130 may in particular use an embodiment in which only one of the first well 102 and the second well 104 is controlled by the switch 130, such as shown in Figures 3-6. However, for the embodiment shown in FIG. 1, the first well 102 can be coupled to a switch 130 through a third heavily doped region 116, and the second well 104 can be coupled through a fourth heavily doped region 118. Another switch 130. In the case where one switch 130 controls only one of the first well 102 and the second well 104, when in the electrostatic discharge protection mode, the first transistor 202 that controls the current path of the first node 122 to the first well 102 is turned off. And controlling at least one of the second transistor 204 of the second node 124 to the current path of the second well 104 to cut off the current path of the first node 122 to the first well 102 and the second node 124 to the second well At least one of the current paths of 104, thereby floating at least one of the first well 102 and the second well 104.

By floating a well of the SCR, the displacement current is introduced, and the SCR can be turned on in a more efficient manner without a sudden collapse. Therefore, an SCR with a floating well can have a lower drive voltage. However, the floating well makes the SCR easy to latch at the ground node. Although N/P guard rings have been introduced into the structure to solve this problem, the results have been limited.

According to embodiments described herein, the floating state of the well is controlled by a switch. Therefore, when an electrostatic discharge event occurs, the well can be floated to provide a lower driving voltage for the electrostatic discharge protection mode. In the normal mode, the well is correspondingly coupled to the node. Thereby the latch-up effect of the SCR can be avoided.

Figure 3 illustrates a semiconductor structure in accordance with another embodiment. In the present embodiment, the first well 102 is directly coupled to the first node 122 by a third heavily doped region 116'. Here, the word "direct" means that there is no switch between the two. In the present embodiment, only the second well 104 is coupled to the switch 130, such as through the fourth heavily doped region 118.

Figure 4 illustrates a semiconductor structure in accordance with another embodiment. In the present embodiment, only the first well 102 is coupled to the switch 130, such as through the third heavily doped region 116. The second well 104 is directly coupled to the second node 124 by a fourth heavily doped region 118'.

Figure 5 illustrates a semiconductor structure in accordance with another embodiment. Similar to the embodiment of FIG. 4, only the first well 102 is coupled to the switch 130, such as through the third heavily doped region 116, and the second well 104 is directly coupled to the fourth heavily doped region 118'. Two nodes 124. However, in the present embodiment, the semiconductor structure further includes a fifth heavily doped region 120. The fifth heavily doped region 120 has a first conductivity type, such as an N-type. The fifth heavily doped region 120 is coupled to the third well 106, such as in the third well 106. The fifth heavily doped region 120 is coupled to the first node 122. This semiconductor structure is more symmetrical than the semiconductor structure shown in FIG.

Figure 6 illustrates a semiconductor structure in accordance with yet another embodiment. In the present embodiment, the second well 104' is disposed directly in the substrate 100, even a portion of the substrate 100. The second well 104' is adjacent to the first well 102'. In the present embodiment, only the first well 102' is coupled to the switch 130, such as through the third heavily doped region 116. The second well 104' is directly coupled to the second node 124 by a fourth heavily doped region 118'.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate
102, 102'‧‧‧ first well
104, 104'‧‧‧ second well
106‧‧‧The third well
112‧‧‧First heavily doped area
114‧‧‧Second heavily doped area
116, 116'‧‧‧ third heavily doped area
118, 118'‧‧‧ fourth heavily doped area
120‧‧‧5th heavily doped area
122‧‧‧ first node
124‧‧‧second node
130‧‧‧ switch
202‧‧‧First transistor
204‧‧‧Second transistor
206‧‧‧ reverser
208‧‧‧Optoelectronics
C‧‧‧ capacitor
R‧‧‧Resistors

FIG. 1 illustrates a semiconductor structure in accordance with an embodiment. 2A and 2B illustrate an exemplary switch that can be applied to the semiconductor structure shown in FIG. 1. Figure 3 illustrates a semiconductor structure in accordance with an embodiment. Figure 4 illustrates a semiconductor structure in accordance with an embodiment. Figure 5 illustrates a semiconductor structure in accordance with an embodiment. Figure 6 illustrates a semiconductor structure in accordance with an embodiment.

100‧‧‧Substrate

102‧‧‧First Well

104‧‧‧Second well

106‧‧‧The third well

112‧‧‧First heavily doped area

114‧‧‧Second heavily doped area

116‧‧‧ Third heavily doped area

118‧‧‧ fourth heavily doped area

122‧‧‧ first node

124‧‧‧second node

130‧‧‧ switch

Claims (10)

A semiconductor structure comprising: a first well having a first conductivity type; a second well having a second conductivity type different from the first conductivity type, the second well coupled to the first well; a first heavily doped region having the second conductivity type, the first heavily doped region coupled to the first well, the first heavily doped region coupled to a first node; and a second heavily doped a dummy region having the first conductivity type, the second heavily doped region coupled to the second well, the second heavily doped region coupled to a second node; and at least one switch satisfying the following conditions (A And (B) at least one of: (A) the switch is coupled between the first well and the first node such that the first well is controlled by the switch and floats in an electrostatic discharge protection mode; And (B) the switch is coupled between the second well and the second node such that the second well is controlled by the switch and floats in an electrostatic discharge protection mode. The semiconductor structure of claim 1, wherein in a normal mode, the first well is coupled to the first node and the second well is coupled to the second node. The semiconductor structure of claim 1, further comprising: a third heavily doped region having the first conductivity type, the third heavily doped region being coupled to the first well. The semiconductor structure of claim 3, further comprising: a fourth heavily doped region having the second conductivity type, the fourth heavily doped region being coupled to the second well. The semiconductor structure of claim 4, further comprising: a third well having the second conductivity type, wherein the second well is disposed in the first well, and the third well is disposed in the first well And being separated from the second well, the first heavily doped region is disposed in the third well. The semiconductor structure of claim 5, further comprising: a fifth heavily doped region having the first conductivity type, the fifth heavily doped region coupled to the third well, the fifth weight A doped region is coupled to the first node. The semiconductor structure of claim 1, wherein the second well is adjacent to the first well. The semiconductor structure of claim 1, wherein the switch comprises: a first transistor that controls a current path of the first node to the first well; and a second transistor that controls the first A current path from the second node to the second well. A method of operating a semiconductor structure according to claim 1, comprising at least one of steps (a) and (b) corresponding to conditions (A) and (B), respectively: (a) in the static electricity In the discharge protection mode, the switch is opened to float the first well; and (b) in the electrostatic discharge protection mode, the switch is opened to float the second well. The method of operation of claim 9, further comprising: coupling the first well to the first node and coupling the second well to the second node in a normal mode.