TWI588828B - Storage device and control method thereof - Google Patents

Description

Memory device and control method thereof

The present invention relates to a memory device, and more particularly to a resistive memory device.

The current novel volatile memory includes ferroelectric memory, phase change memory, magnetic memory and resistive memory. Resistive memory is widely used because of its simple structure, low cost, fast speed and low power consumption. In a resistive memory, the voltage across a particular metallic conductive layer is controlled to form a conductive filament in the metallic conductive layer. However, the conductive yarn produced by the prior art is too thick and small in number, and therefore, in the subsequent operation, the conductive yarn is not easily broken. Moreover, the number of conductive filaments produced by the prior art is small, so that it is difficult to reduce the impedance of the metal conductive layer.

The invention provides a memory device comprising a control unit and at least one memory cell. The control unit controls the levels of a word line, a bit line, and a source line. The memory cell includes a transistor and a variable resistor. The gate of the transistor is coupled to the word line. The variable resistor is coupled between the drain of the transistor and the bit line. The source of the transistor is coupled to the source line. During a predetermined period, the control unit provides a plurality of pulses to the first particular line of one of the word line, the bit line, and the source line. The preset period is at least greater than 1 microsecond.

The invention further provides a control method suitable for use in a memory device. The memory device has at least one memory cell. The memory cell has a transistor and a variable resistor. The gate of the transistor is coupled to a word line. The variable resistor is coupled between the drain of the transistor and a bit line. The source of the transistor is coupled to a source line. The control method of the present invention includes: providing a plurality of pulses to a first specific line of one of a word line, a bit line, and a source line during a predetermined period; and providing a first level and a second level of the word One of the first line and the third specific line of the source line, the bit line, and the source line. The preset period is at least greater than 1 microsecond.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100‧‧‧ memory device

110‧‧‧Control unit

120‧‧‧Array unit

WL ₁ ~ WL _n ‧‧‧ character line

BL ₁ ~BL _m ‧‧‧ bit line

SL ₁ ~SL _m ‧‧‧Source line

112‧‧‧ column decoder

114‧‧‧ line decoder

116‧‧‧Access controller

AD ₁ , AD ₂ ‧‧‧ Location Information

DATA _I , DATA _O ‧‧‧Information

M ₁₁ ~M _mn ‧‧‧ memory cells

T ₁₁ ‧‧‧O crystal

R ₁₁ ‧‧‧Variable resistor

210‧‧‧Upper electrode

220‧‧‧Metal Oxide

230‧‧‧ lower electrode

240‧‧‧Conductor wire

VL ₁₁ ~ VL ₁₆ , VL ₂₁ ~ VL ₂₆ , VL ₃₁ ~ VL ₃₄ , VL ₄₁ ~ VL ₄₄ , V ₁ ~ V ₄ ‧ ‧ level

210, 220, 230, 240, 250, 410, 420‧‧

PS ₁ ~ PS ₉ ‧‧‧pulse

S612, S614, S616, S622, S624, S626, S628‧‧ steps

Figure 1 is a schematic view of a memory device of the present invention.

The 2A~2E diagram is a schematic diagram of the resistance change of the variable resistor.

3A and 3B are diagrams of possible embodiments of the formatting operation of the present invention.

4A and 4B are diagrams of possible implementations of the initialization reset operation of the present invention.

The 5A~5I diagram is a schematic diagram of the possible shape and level of the pulse.

6A-6C are schematic diagrams showing possible processes of the control method of the present invention.

Figure 1 is a schematic view of a memory device of the present invention. As shown, the memory device 100 includes a control unit 110 and an array unit 120. The control unit 110 controls the levels of the word lines WL ₁ to WL _n , the bit lines BL ₁ to BL _{m ,} and the source lines SL ₁ to SL _m for accessing the array unit 120. The present invention does not limit the internal architecture of the control unit 110. As long as the circuit architecture capable of appropriately controlling the levels of the word lines WL ₁ to WL _n , the bit lines BL ₁ to BL _{m ,} and the source lines SL ₁ to SL _m can be used as the control unit 110. In the present embodiment, the control unit 110 includes a column decoder 112, a row of decoders 114, and an access controller 116.

Column decoder 112 decodes address information AD _1, and provides the appropriate bit grant word line WL ₁ ~ WL _n according to the decoding result. The row decoder 114 decodes the address information AD ₂ and provides an appropriate level of bit lines BL ₁ BLBL _m according to the decoding result. The access controller 116 writes the external data DATA _I to the array unit 120, or reads and outputs the data DATA _O stored by the array unit 120.

The array unit 120 includes memory cells M ₁₁ ~M _mn . Since the memory cells M ₁₁ to M _mn have the same circuit architecture, FIG. 1 only shows the circuit architecture of the memory cell M ₁₁ . As shown, the memory cell M ₁₁ includes a transistor T ₁₁ and a variable resistor R ₁₁ . The gate of the transistor T ₁₁ is coupled to the word line WL ₁ . The variable resistor R _{11 is} coupled between the drain of the transistor T ₁₁ and the bit line BL ₁ . The source of the transistor T ₁₁ is coupled to the source line SL ₁ . In this embodiment, the control unit 110 can make the variable resistor R ₁₁ by adjusting the levels of the word lines WL ₁ to WL _n , the bit lines BL ₁ to BL _{m ,} and the source lines SL ₁ to SL _m . It is either high impedance or low resistance.

The 2A~2D diagram is a schematic diagram of the resistance change of the variable resistor. As can be seen from FIG. 2A, the variable resistor R ₁₁ is composed of an upper electrode 210, a metal oxide 220, and a lower electrode 230. Metal oxide 220 is formed between upper electrode 210 and lower electrode 220. Referring to FIGS. 2B-2D, by controlling the levels of the upper electrode 210 and the lower electrode 230, a conductive filament (CF) 240 or a conductive filament 240 can be formed.

2B shows a forming operation that applies an appropriate formatting voltage to the upper electrode 210 and the lower electrode 230 to form a conductive filament 240 between the upper electrode 210 and the lower electrode 230. At this time, the variable resistor R ₁₁ is a low resistance state (LRS). FIG. 2C shows an initial reset operation by which the conductive wire 240 between the upper electrode 210 and the lower electrode 230 is interrupted by applying an appropriate initial reset voltage to the upper electrode 210 and the lower electrode 230. At this time, the variable resistor R ₁₁ is in a high resistance state (HRS).

The 2D drawing shows a set operation by which the conductive wire 240 between the upper electrode 210 and the lower electrode 230 can be recovered by applying an appropriate set voltage to the upper electrode 210 and the lower electrode 230. At this time, the variable resistor R ₁₁ is in a low resistance state. FIG. 2E shows a reset operation by which the conductive wire 240 between the upper electrode 210 and the lower electrode 230 is interrupted by applying an appropriate reset voltage to the upper electrode 210 and the lower electrode 230. At this time, the variable resistor R ₁₁ is in a high resistance state.

Generally, before the memory device 100 is shipped from the factory, the memory cells M ₁₁ to M _{mn must} be formatted to generate the conductive wires 240. In another possible embodiment, after the formatting operation is performed, an initialization reset operation is further performed to interrupt the conductive wire 240. After the factory, there is no need to format and initialize the memory cells M ₁₁ ~M _mn . The user can set and reset the memory cells M ₁₁ ~M _mn according to actual needs, and set the memory cells M ₁₁ ~M _mn to a low impedance state or a high resistance state.

Figure 3A is a possible embodiment of the formatting operation of the present invention. In the present embodiment, the control unit 110 provides the levels VL ₁₁ and VL ₁₂ to the bit line BL ₁ and the source line SL ₁ . In a possible embodiment, the level VL _{11 is} greater than the level VL ₁₂ . The level VL ₁₂ can be a ground level. During the preset period 210, the control unit 110 provides a complex pulse to the word line WL ₁ . In the present embodiment, the level of the word line WL ₁ varies between the levels VL ₁₃ and VL ₁₄ . In some embodiments, the level VL ₁₃ may or may not be equal to the level VL ₁₂ .

In this embodiment, the preset period 210 is at least greater than 1 microsecond. For example, the preset period 210 is between 200 and 250 microseconds. In other embodiments, the duration 220 of each pulse is between about 50 and 150 nanoseconds.

By providing a plurality of pulses to the word line WL ₁ , a plurality of elongated conductive wires can be formed. Therefore, the conductive filament can be easily broken in a subsequent initial reset or reset operation. In addition, by a large number of conductive wires, the impedance of the variable resistor R ₁₁ can be effectively reduced, thereby changing the data retention and the endurance stability. Moreover, by complex pulses, the formatting time can be greatly reduced.

After completion of the format operation, a setting operation can be performed on memory cell M _11. In the set period 230, the control unit 110 supplies the levels VL ₁₅ , VL _{16 ,} and V ₁₂ to the bit line BL ₁ , the word line WL _{1 ,} and the source line SL ₁ . In this embodiment, the level VL ₁₅ is less than the level VL ₁₁ to avoid excessive collapse. For example, when the level VL _{15 is} greater than or equal to the level VL ₁₁ , the current flowing through the metal oxide 220 will be excessively large, thereby causing excessive collapse, thereby damaging the conductive filament 240. Therefore, the level VL ₁₅ needs to be smaller than the level VL ₁₁ .

In another possible embodiment, the set period 230 is much smaller than the preset period 210. For example, when the setting period 230 is too large, such as reaching the microsecond level, excessive collapse may occur. Thus, in a possible embodiment, the set period 230 is a nanosecond (ns) level.

Figure 3B is another possible embodiment of the formatting operation of the present invention. 3B of FIG. 3A is similar to the first, except that the control unit 110 to provide the complex impulse bit line BL _1, and provides a level VL ₂₁ and VL ₂₂ to word line WL ₁ and the source line SL _1. In the present embodiment, during the preset period 240, the control unit 110 alternately supplies the level VL ₂₃ and the VL ₂₄ to the bit line BL ₁ for generating a plurality of elongated conductive wires. In other embodiments, the level VL ₂₂ may or may not be equal to the level VL ₂₃ . Since the characteristics of the preset period 240 are the same as those of the preset period 210, they will not be described again. In addition, the duration of the pulse 250 is approximately 50 to 150 nanoseconds.

During the set period 260, the control unit 110 provides the levels VL ₂₅ and VL ₂₆ to the word line WL ₁ and the bit line BL ₁ and provides the level VL ₂₂ to the source line SL ₁ . In the present embodiment, the level VL _{26 is} less than the level VL ₂₄ and the set period 260 is much smaller than the preset period 240 to avoid excessive collapse. In a possible embodiment, the set period 260 is approximately equal to the duration period 250. The present invention does not limit the relationship between the quasi VL ₂₁ and the VL ₂₅ . In a possible embodiment, the level VL _{21 is} less than the level VL ₂₅ .

Figure 4A is a possible embodiment of the initialization reset operation of the present invention. As shown, control unit 110 provides levels VL ₃₁ and VL ₃₂ to source line SL ₁ and bit line BL ₁ . In a possible embodiment, the level VL ₃₂ is a ground level. In the preset period 410, the control unit 110 supplies a complex pulse to the word line WL ₁ . In the present embodiment, the level of the word line WL ₁ varies between the levels VL ₃₃ and VL ₃₄ . The duration of the preset period 410 is at least greater than 1 microsecond.

Figure 4B is another possible embodiment of the initialization reset operation of the present invention. Figure 4B is similar to Figure 4A, except that the control unit 110 to provide a plurality of pulses of the source line SL _1, and provides a level VL ₄₁ and VL ₄₂ to word line WL ₁ and the bit line BL _1. As shown, during the preset period 420, the control unit 110 alternately supplies the levels VL ₄₃ and VL ₄₄ to the source line SL ₁ . In a possible embodiment, the level VL ₄₂ is a ground level. The characteristics of the preset period 420 are similar to the preset period 410, and therefore will not be described again.

In other embodiments, the initialization reset operations shown in FIGS. 4A and 4B may be set between the formatting operation and the setting operation of FIGS. 3A and 3B. In a possible embodiment, the control unit 110 only provides a complex pulse under the formatting operation (ie, the preset period 210, 240), or provides a complex pulse only under the initial reset operation (ie, during the period 410, 420). or providing a plurality of pulses at the initialization formatting operation for the reset operation to the transmission line, such as _a word line WL, bit line BL ₁ and the source line SL by one of _a.

Under the formatting operation, when the control unit 110 provides a complex pulse to the word line or the bit line, a plurality of elongated conductive wires can be formed in the memory cell, thereby reducing the impedance of the memory cell. In addition, under the initial reset operation, when the control unit 110 supplies a plurality of pulses to the word line or the source line, the conductive wires can be evenly interrupted without causing some of the conductive wires to be uninterrupted. Moreover, when the control unit 110 provides a plurality of pulses under both the formatting operation and the initial reset operation, not only a plurality of fine conductive wires can be formed, but also each conductive wire is broken.

Further, the present invention does not limit the shape and number of pulses in the drawings 3A, 3B, 4A, and 4B. Taking Figure 3A as an example, the pulses have the same shape and level. In another possible embodiment, the shape or level of one of the pulses is different from the shape or level of the other of the pulses. The 5A~5I diagram is a schematic diagram of the possible shape and level of the pulse. As shown, the pulses PS ₁ ~PS ₉ vary between levels V ₁ and V ₂ . The pulse PS _{2 of} Fig. 5B varies only between the levels V ₁ and V ₂ . The other illustrated pulses other than Figure 5B vary between multiple levels. Taking Figure 5A as an example, the pulse PS ₁ varies between levels V ₁ VV ₃ . In Fig. 5E, the pulse PS ₅ varies between levels V ₁ VV ₄ .

In some embodiments, any of Figures 5A-5I can be applied to Figures 3A, 3B, 4A, 4B. Taking FIG. 3A as an example, in FIG. 3A, only the pulse PS ₂ shown in FIG. 5B is used, but it is not intended to limit the present invention. In other embodiments, the pulses PS ₁ to PS ₉ shown in FIGS. 5A to 5I can be arbitrarily combined to form a complex pulse as shown in FIG. 3A.

Figure 6A is a schematic flow chart of one of the control methods of the present invention. The control method of the present invention is applicable to a memory device. The memory device has at least one memory cell as shown in FIG. The memory cell M ₁₁ has a transistor T ₁₁ and a variable resistor R ₁₁ . Since the connection relationship between the transistor T ₁₁ and the variable resistor R ₁₁ has been disclosed above, it will not be described again. For convenience of explanation, the memory cell M ₁₁ will be exemplified below.

During a predetermined period, a plurality of pulses are supplied to one of the first specific line of the word line WL ₁ , the bit line BL _{1 ,} and the source line SL (step S612). In a possible embodiment, the level of the pulse varies between the two levels. Next, providing a first level and a second grant word line WL _1, one bit line BL ₁ and the source line SL in _a specific line a second and a third specific line (step S614). In a possible embodiment, by controlling the levels of the first to third specific lines, the memory cell M ₁₁ can be formatted and initialized.

For example, if a complex pulse is supplied to the word line WL ₁ or the bit line BL ₁ and the first and second bits are supplied to the transmission line that does not receive the pulse, the memory cell M ₁₁ can be formatted. . In a possible embodiment, after the formatting operation is performed, the memory cell is in a low resistance state. Additionally, in other embodiments, the first or second level is a ground level.

In other embodiments, if a complex pulse is supplied to the word line WL ₁ or the source line SL ₁ and the first and second bits are supplied to the transmission line that does not receive the pulse, the memory cell M ₁₁ can be initialized. Reset operation. In a possible embodiment, after performing the initial reset operation, the memory cell M ₁₁ is in a high impedance state. In addition, the first or second level is a ground level.

In this embodiment, the predetermined period of providing the plurality of pulses is at least greater than 1 microsecond. Further, the present invention does not limit the shape and level of the complex pulses. In a possible embodiment, the shapes of the pulses are the same. In another possible embodiment, the levels of the pulses vary between the two levels. In some embodiments, one of the pulses has a shape different from a second pulse of the pulses. In other embodiments, the duration of each pulse is between about 50 and 150 nanoseconds.

Figure 6B is a schematic diagram of another possible flow of the control method of the present invention. Fig. 6B is similar to Fig. 6A except that step 6B is further step S616 for performing a setting operation on the memory cell. In this embodiment, steps S612 and S614 perform a formatting operation and an initialization reset operation on the memory cells.

In a possible embodiment, if steps S612 and S614 perform a formatting operation on the memory cell, the memory cell can be directly set, as in step S616. If steps S612 and S614 are to perform an initial reset operation on the memory cell, then before the step S612, the memory cell needs to be formatted (not shown) to form the conductive filament.

In the present embodiment, after the formatting operation and the initial reset operation are performed, the corresponding level is supplied to the word line WL ₁ , the bit line BL _{1 ,} and the source line SL ₁ (step S616). The present invention is not limited to the level of the word line WL ₁ , the bit line BL _{1 ,} and the source line SL ₁ under the setting operation.

In a possible embodiment, if steps S612 and S614 are a formatting operation, the level of the bit line BL ₁ under the formatting operation may be continuously or intermittently larger than the bit line BL under the setting operation. ₁ level. In another possible embodiment, under the formatting operation and the setting operation, the level of the source line SL ₁ is the ground level, and the level of the bit line BL ₁ is greater than the level of the source line SL ₁ . In addition, the level of the word line WL ₁ may be the same or different under the formatting operation and the setting operation.

Figure 6C is a schematic diagram of another possible flow of the control method of the present invention. In this embodiment, steps S622 and S624 perform a formatting operation on the memory cells to generate conductive filaments. Since steps S622 and S624 are similar to steps S612 and S614, they are not described again. In addition, step S628 performs a setting operation on the memory cell, and the principle thereof is similar to step S616, and therefore will not be described again.

Step S626 performs an initialization reset operation on the memory cell. In a possible embodiment, step S626 provides a complex pulse to the word line WL ₁ or the source line SL ₁ and provides a corresponding level to the word line WL ₁ , the source line SL _{1 that} does not receive the complex pulse. Or bit line BL ₁ . In this example, step S626 provides a plurality of pulses for a time greater than at least 1 microsecond, wherein the duration of each pulse is a nanosecond level.

In another possible embodiment, steps S624 and S628 provide a ground level to the source line SL ₁ , and step S626 provides the ground level to the bit line BL ₁ . In addition, the levels of the word line WL ₁ , the bit line BL _{1 ,} and the source line SL ₁ of step S624 may be the same or different from the word line WL ₁ , the bit line BL _{1 ,} and the source line of steps S626 and S628 . The level of SL _{1 is} the same.

By providing a complex pulse to the corresponding word line WL ₁ , source line SL ₁ and bit line BL _{1 under} a format or initialization reset operation, the time for formatting or initializing the reset operation can be greatly reduced. And can improve the efficiency of formatting or initializing reset operations. For example, if a plurality of pulses are applied during a formatting operation, a plurality of thin conductive wires can be produced. If the complex pulse is applied during the initial reset operation, the conductive filament can be evenly interrupted without causing some of the conductive filaments to be uninterrupted.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S612, S614‧‧‧ steps

Claims (8)

A memory device includes: a control unit for controlling a level of a word line, a bit line, and a source line; and at least one memory cell including a transistor and a variable resistor, the transistor The gate is coupled to the word line, the variable resistor is coupled between the drain of the transistor and the bit line, and the source of the transistor is coupled to the source line; wherein, a preset During the period, the control unit provides a plurality of pulses to the word line, the bit line, and one of the first specific lines of the source line, the preset period being at least greater than 1 microsecond, wherein the preset During the period, the control unit provides a first level and a second bit to the character line, the bit line, and one of the source line and the second specific line, and a third specific line, wherein, in a setting During the period, the control unit provides a third level, a fourth level, and a fifth level to the first to third specific lines, the setting period is later than the preset period, the first level is greater than the first Four standards. The memory device of claim 1, wherein the levels of the pulses are changed between a sixth level and a seventh level, the seventh level being greater than the fourth and sixth positions. quasi. The memory device of claim 1, wherein one of the pulses has a shape different from a shape of one of the pulses. The memory device of claim 1, wherein the duration of each pulse is in the range of 50 to 150 nanoseconds. A control method is applicable to a memory device having at least one memory cell having a transistor and a variable resistor, the gate of the transistor being coupled to a word line, the variable resistance coupling Connected between the drain of the transistor and a bit line, the source of the transistor is coupled to a source line, and the control method includes: providing a plurality of pulses to the word line during a predetermined period, a bit line and one of the first specific lines of the source line; providing a first level and a second bit to the word line, the bit line, and a second specific line of the source line and a third specific line, wherein the preset period is at least greater than 1 microsecond; and during a set period, providing a third level, a fourth level, and a fifth level to the first to third specific lines, The level of the first specific line is changed between a sixth level and a seventh level, and the seventh level is greater than the fourth and sixth levels. The control method of claim 5, wherein the fourth level is greater than the first level. The control method of claim 5, wherein one of the pulses has a shape different from a second pulse of the pulses. The control method of claim 5, wherein the duration of each pulse is in the range of 50 to 150 nanoseconds.