TWI587053B - Conductive line structure and active device array substrate - Google Patents
Conductive line structure and active device array substrate Download PDFInfo
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- TWI587053B TWI587053B TW105143023A TW105143023A TWI587053B TW I587053 B TWI587053 B TW I587053B TW 105143023 A TW105143023 A TW 105143023A TW 105143023 A TW105143023 A TW 105143023A TW I587053 B TWI587053 B TW I587053B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Description
本發明是關於一種導線結構及應用該導線結構之主動元件陣列基板。 The present invention relates to a wire structure and an active device array substrate to which the wire structure is applied.
平面顯示器,例如液晶顯示器、等離子體顯示器等,具有高畫質、體積小、重量輕及應用範圍廣等優點,因此被廣泛應用於行動電話、筆記型電腦、桌上型顯示器以及電視等消費性電子產品,並已逐漸取代傳統的陰極射線管顯示器而成為顯示器的主流。而所謂大面積、高解析度等要求,也成為這些平面顯示器訴求的關鍵所在。 Flat panel displays, such as liquid crystal displays and plasma displays, are widely used in mobile phones, notebook computers, desktop displays, and televisions because of their high image quality, small size, light weight, and wide application range. Electronic products have gradually replaced traditional cathode ray tube displays and become the mainstream of displays. The so-called large-area, high-resolution requirements, etc., have become the key to these flat-panel display appeals.
平面顯示器中,電訊號透過導線及其連接的信號線,而傳遞至各個畫素。然而,隨著平面顯示器的解析度提高以及顯示器邊框尺寸變窄,導線間的間距也被縮小而逼近設計規則(design rule)所允許的極限。由於焊腳緊密排列而信號線分散排列,也就是說焊腳間距以及信號線間距不相同,造成了各個導線的長度不同而形成扇形走線(fanout),不同長度的導線會使信號的波形發生變形,從而會影響液晶顯示裝置的顯示品質。 In a flat panel display, an electrical signal is transmitted to each pixel through a wire and its connected signal line. However, as the resolution of flat panel displays increases and the frame size of the display becomes narrower, the spacing between the wires is also reduced to approach the limits allowed by the design rules. Since the soldering legs are closely arranged and the signal lines are dispersed, that is to say, the spacing between the soldering legs and the spacing of the signal lines are different, the lengths of the individual wires are different to form a fanout, and the wires of different lengths cause the waveform of the signal to occur. Deformation, which affects the display quality of the liquid crystal display device.
本發明之多個實施方式中,導線結構具有相互堆疊的第一導線與第二導線,第二導線的設置位置可以有一定的偏差容許範圍,而因製程偏差不會影響到第一導線與第二導線的重疊面積,進而確保導線結構的電容不因第二導線些微偏移而變化。此外,隨著各個導線結構的長度變化,各個導線結構之第二導線可以而作相應調整,而使各個導線結構的電容實質相同。 In various embodiments of the present invention, the wire structure has a first wire and a second wire stacked on each other, and the position of the second wire may have a certain tolerance range, and the process deviation does not affect the first wire and the first wire. The overlap area of the two wires, thereby ensuring that the capacitance of the wire structure does not change due to slight offset of the second wire. In addition, as the length of each wire structure changes, the second wires of each wire structure can be adjusted accordingly, so that the capacitances of the respective wire structures are substantially the same.
根據本發明之部份實施方式,導線結構包含第一導線以及第二導線。第一導線具有第一部、第二部以及緩衝部,其中緩衝部電性連接於第一部與第二部之間,第一部之延伸方向與緩衝部之延伸方向不同。第二導線具有第一側邊以及相對第一側邊之第二側邊,其中第一側邊至少重疊於第一導線之第一部以及緩衝部且不重疊於第一導線之第二部,第二側邊至少重疊於第一導線之第二部。 According to some embodiments of the invention, the wire structure comprises a first wire and a second wire. The first wire has a first portion, a second portion, and a buffer portion, wherein the buffer portion is electrically connected between the first portion and the second portion, and the extending direction of the first portion is different from the extending direction of the buffer portion. The second wire has a first side and a second side opposite to the first side, wherein the first side overlaps at least the first portion of the first wire and the buffer portion and does not overlap the second portion of the first wire, The second side overlaps at least the second portion of the first wire.
於本發明之一或多個實施方式,第二側邊重疊於第一導線之緩衝部且不重疊於第一導線之第一部。 In one or more embodiments of the present invention, the second side overlaps the buffer portion of the first wire and does not overlap the first portion of the first wire.
於本發明之一或多個實施方式,第一導線之第一部之延伸方向與第一導線之第二部之延伸方向實質相同。 In one or more embodiments of the present invention, the extending direction of the first portion of the first wire is substantially the same as the extending direction of the second portion of the first wire.
於本發明之一或多個實施方式,第二導線具有第一部、第二部以及緩衝部,第二導線之緩衝部電性連接於第二導線之第一部與第二部之間,其中第二導線之第一部的延伸方向與第二導線之緩衝部的延伸方向不同。 In one or more embodiments of the present invention, the second wire has a first portion, a second portion, and a buffer portion, and the buffer portion of the second wire is electrically connected between the first portion and the second portion of the second wire. The extending direction of the first portion of the second wire is different from the extending direction of the buffer portion of the second wire.
於本發明之一或多個實施方式,第一導線之緩衝部之延伸方向與第二導線之緩衝部之延伸方向實質相同。 In one or more embodiments of the present invention, the direction in which the buffer portion of the first wire extends is substantially the same as the direction in which the buffer portion of the second wire extends.
於本發明之一或多個實施方式,第一導線之緩衝部與第二導線之緩衝部重疊。 In one or more embodiments of the present invention, the buffer portion of the first wire overlaps with the buffer portion of the second wire.
於本發明之一或多個實施方式,第一導線之緩衝部與第二導線之緩衝部不重疊。 In one or more embodiments of the present invention, the buffer portion of the first wire does not overlap with the buffer portion of the second wire.
於本發明之一或多個實施方式,第一導線之第一部之延伸方向與第二導線之第一部之延伸方向實質相同。 In one or more embodiments of the present invention, the extending direction of the first portion of the first wire is substantially the same as the extending direction of the first portion of the second wire.
於本發明之一或多個實施方式,第一導線之第二部之延伸方向與第二導線之第二部之延伸方向實質相同。 In one or more embodiments of the present invention, the extending direction of the second portion of the first wire is substantially the same as the extending direction of the second portion of the second wire.
於本發明之一或多個實施方式,第一導線之第一部與第二部於投影面上的垂直投影具有第一間距於其中,第二導線之第一部與第二部於投影面上的垂直投影具有第二間距於其中,第一間距不大於第二間距與第二導線之第一部之寬度之合。 In one or more embodiments of the present invention, a vertical projection of the first portion and the second portion of the first wire on the projection surface has a first pitch therebetween, and the first portion and the second portion of the second wire are on the projection surface The upper vertical projection has a second pitch therein, and the first pitch is no greater than a combination of the second pitch and the width of the first portion of the second wire.
於本發明之一或多個實施方式,第二導線包含長直導線,且長直導線與第一導線之緩衝部至少部分重疊。 In one or more embodiments of the present invention, the second wire includes a long straight wire, and the long straight wire at least partially overlaps the buffer portion of the first wire.
於本發明之一或多個實施方式,第一導線之第一部與第二部於投影面上之垂直投影實質相連。 In one or more embodiments of the present invention, the vertical projections of the first portion and the second portion of the first wire on the projection surface are substantially connected.
於本發明之一或多個實施方式,導線結構更包含中間層,設置於第一導線與第二導線之間,其中中間層 將第一導線與第二導線分隔開來。 In one or more embodiments of the present invention, the wire structure further includes an intermediate layer disposed between the first wire and the second wire, wherein the intermediate layer The first wire is separated from the second wire.
根據本發明之部分實施方式,主動元件陣列基板包含基板、多個傳輸線、驅動器以及多個前述之導線結構。基板具有顯示區與非顯示區。傳輸線設置於基板之顯示區。驅動器設置於基板之非顯示區。導線結構分別連接於傳輸線以及驅動器之間。 According to some embodiments of the present invention, an active device array substrate includes a substrate, a plurality of transmission lines, a driver, and a plurality of the aforementioned wire structures. The substrate has a display area and a non-display area. The transmission line is disposed on the display area of the substrate. The driver is disposed in a non-display area of the substrate. The wire structures are respectively connected between the transmission line and the driver.
於本發明之一或多個實施方式,每一導線結構中之第一導線之緩衝部與第二導線構成重疊部。至少二個重疊部之面積不同。 In one or more embodiments of the present invention, the buffer portion of the first wire and the second wire in each wire structure constitute an overlap portion. The area of at least two overlapping portions is different.
於本發明之一或多個實施方式,至少部分導線結構之第二導線具有第一部、第二部以及緩衝部,第二導線之緩衝部電性連接於第二導線之第一部與第二部之間,其中第二導線之第一部的延伸方向與第二導線之緩衝部的延伸方向不同,其中至少部分導線結構之第二導線之緩衝部的尺寸不同。 In one or more embodiments of the present invention, the second wire of the at least part of the wire structure has a first portion, a second portion, and a buffer portion, and the buffer portion of the second wire is electrically connected to the first portion and the second portion of the second wire Between the two parts, wherein the extending direction of the first portion of the second wire is different from the extending direction of the buffer portion of the second wire, wherein the buffer portion of the second wire of at least part of the wire structure is different in size.
於本發明之一或多個實施方式,每一導線結構之第一導線之緩衝部的尺寸實質上相同。 In one or more embodiments of the present invention, the buffer portions of the first wires of each of the wire structures are substantially the same size.
於本發明之一或多個實施方式,第一導線之第二部連接驅動器,第一導線之第一部連接傳輸線之一,其中第一導線之第一部之長度大致上等於第一導線之第二部之長度。 In one or more embodiments of the present invention, the second portion of the first wire is connected to the driver, and the first portion of the first wire is connected to one of the transmission lines, wherein the length of the first portion of the first wire is substantially equal to the length of the first wire The length of the second part.
於本發明之一或多個實施方式,每一導線結構之該第一導線包含一第一連接部,其中第一導線之第一連接部墊性連接第一導線之第一部與一傳輸線之間,每一導 線結構之第二導線包含一第一連接部,其中第二導線之第一連接部連接第二導線之第一部與另一傳輸線之間,其中第一導線之第一連接部與第二導線之第一連接部不重疊。 In one or more embodiments of the present invention, the first wire of each wire structure includes a first connecting portion, wherein the first connecting portion of the first wire is paddedly connected to the first portion of the first wire and a transmission line Every guide The second wire of the wire structure includes a first connecting portion, wherein the first connecting portion of the second wire is connected between the first portion of the second wire and the other transmission line, wherein the first connecting portion and the second wire of the first wire The first connecting portions do not overlap.
100‧‧‧主動元件陣列基板 100‧‧‧Active component array substrate
110‧‧‧基板 110‧‧‧Substrate
120‧‧‧傳輸線 120‧‧‧ transmission line
120a~120b‧‧‧傳輸線 120a~120b‧‧‧ transmission line
130‧‧‧驅動器 130‧‧‧ drive
224‧‧‧第二部 224‧‧‧ second
226‧‧‧緩衝部 226‧‧‧ buffer
227‧‧‧第一連接部 227‧‧‧First connection
228‧‧‧第二連接部 228‧‧‧Second connection
229‧‧‧長直導線 229‧‧‧Long straight wire
140‧‧‧扇入導線 140‧‧‧Fan-in wire
200‧‧‧導線結構 200‧‧‧Wire structure
200a~200d‧‧‧導線結構 200a~200d‧‧‧ wire structure
210‧‧‧第一導線 210‧‧‧First wire
212‧‧‧第一部 212‧‧‧ first
214‧‧‧第二部 214‧‧‧Part II
216‧‧‧緩衝部 216‧‧‧ buffer
217‧‧‧第一連接部 217‧‧‧First connection
218‧‧‧第二連接部 218‧‧‧Second connection
220‧‧‧第二導線 220‧‧‧second wire
220a‧‧‧第一側邊 220a‧‧‧ first side
220b‧‧‧第二側邊 220b‧‧‧ second side
222‧‧‧第一部 222‧‧‧ first
230‧‧‧中間層 230‧‧‧Intermediate
X-、X+‧‧‧方向 X-, X+‧‧‧ directions
Y-、Y+‧‧‧方向 Y-, Y+‧‧‧ direction
AA‧‧‧顯示區 AA‧‧‧ display area
NA‧‧‧非顯示區 NA‧‧‧Non-display area
P1‧‧‧投影面 P1‧‧‧projection surface
L1‧‧‧第一間距 L1‧‧‧ first spacing
L2‧‧‧第二間距 L2‧‧‧second spacing
W2‧‧‧寬度 W2‧‧‧Width
OV‧‧‧重疊部 OV‧‧‧ overlap
1C-1C‧‧‧線 1C-1C‧‧‧ line
300‧‧‧軟性電路板 300‧‧‧Soft circuit board
第1A圖為根據本發明之部分實施方式之主動元件陣列基板的上視示意圖。 1A is a top plan view of an active device array substrate according to some embodiments of the present invention.
第1B圖為第1A圖主動元件陣列基板之局部上視放大示意圖。 Fig. 1B is a partially enlarged plan view showing the active device array substrate of Fig. 1A.
第1C圖為第1B圖沿線1C-1C的剖面示意圖。 Fig. 1C is a schematic cross-sectional view taken along line 1C-1C of Fig. 1B.
第1D圖為第1B圖之主動元件陣列基板之導線結構之第一導線之上視放大示意圖。 FIG. 1D is an enlarged schematic view showing the first wire of the wire structure of the active device array substrate of FIG. 1B.
第1E圖為第1B圖之主動元件陣列基板之導線結構的上視放大示意圖。 Fig. 1E is a top plan enlarged view showing the wire structure of the active device array substrate of Fig. 1B.
第2A、2B圖為第1B圖之導線結構於製程偏移狀況下的上視示意圖。 2A and 2B are top views of the wire structure of Fig. 1B in a process offset state.
第3圖為根據本發明之部分實施方式之導線結構的上視示意圖。 Figure 3 is a top plan view of a wire structure in accordance with some embodiments of the present invention.
第4圖為根據本發明之部分實施方式之導線結構的上視示意圖。 Figure 4 is a top plan view of a wire structure in accordance with some embodiments of the present invention.
第5圖為根據本發明之部分實施方式之導線結構的上視示意圖。 Figure 5 is a top plan view of a wire structure in accordance with some embodiments of the present invention.
第6A至6C圖為根據本發明之部分實施方式之導線結 構的上視示意圖。 6A to 6C are diagrams showing wire junctions according to some embodiments of the present invention A schematic view of the structure.
以下將以圖式揭露本發明之多個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式為之。 The various embodiments of the present invention are disclosed in the drawings, and in the claims However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified manner.
第1A圖為根據本發明之部分實施方式之主動元件陣列基板100的上視示意圖。主動元件陣列基板100包含基板110、多個傳輸線120、驅動器130以及多個導線結構200。基板110具有顯示區AA與非顯示區NA。於部分實施方式中,顯示區AA內設有多個畫素單元(未繪示)以控制液晶層或有機發光層。傳輸線120設置於基板110之顯示區AA,以連接畫素單元。驅動器130設置於基板100之非顯示區NA。導線結構200分別連接於傳輸線120以及驅動器130之間,以作為扇出導線使用。除上述配置外,主動元件陣列基板100還可包含扇入導線140,以連接驅動器130以及軟性電路板300。 FIG. 1A is a top plan view of an active device array substrate 100 in accordance with some embodiments of the present invention. The active device array substrate 100 includes a substrate 110, a plurality of transmission lines 120, a driver 130, and a plurality of wire structures 200. The substrate 110 has a display area AA and a non-display area NA. In some embodiments, a plurality of pixel units (not shown) are disposed in the display area AA to control the liquid crystal layer or the organic light emitting layer. The transmission line 120 is disposed in the display area AA of the substrate 110 to connect the pixel units. The driver 130 is disposed on the non-display area NA of the substrate 100. The wire structure 200 is connected between the transmission line 120 and the driver 130, respectively, for use as a fan-out wire. In addition to the above configuration, the active device array substrate 100 may further include a fan-in wire 140 to connect the driver 130 and the flexible circuit board 300.
同時參照第1B圖與第1C圖,第1B圖為第1A圖主動元件陣列基板100之局部上視放大示意圖。第1C圖為第1B圖沿線1C-1C的剖面示意圖。導線結構200包含第一導線210、第二導線220以及中間層230。第一導線210電性 連接傳輸線120a與驅動器130之間,第二導線220電性連接傳輸線120b與驅動器130之間。第一導線210以及第二導線220相互堆疊,中間層230設置於第一導線210以及第二導線220之間,以將第一導線210以及第二導線220分隔開來。如此一來,可以在有限的空間內同時傳送兩種不同的訊號。 Referring to FIGS. 1B and 1C, FIG. 1B is a partially enlarged plan view of the active device array substrate 100 of FIG. 1A. Fig. 1C is a schematic cross-sectional view taken along line 1C-1C of Fig. 1B. The wire structure 200 includes a first wire 210, a second wire 220, and an intermediate layer 230. First wire 210 electrical The second wire 220 is electrically connected between the transmission line 120b and the driver 130. The first wire 210 and the second wire 220 are stacked on each other, and the intermediate layer 230 is disposed between the first wire 210 and the second wire 220 to separate the first wire 210 and the second wire 220. In this way, two different signals can be transmitted simultaneously in a limited space.
同時參考第1B圖與第1D圖。第1D圖為第1B圖之主動元件陣列基板之導線結構200的第一導線210之上視示意圖。於本發明之多個實施方式中,第一導線210具有第一部212、第二部214以及緩衝部216,其中緩衝部216電性連接於第一部212與第二部214之間。第一部212之延伸方向與緩衝部214之延伸方向不同。於部分實施方式中,第二部214之延伸方向與緩衝部216之延伸方向不同。於本文名詞定義中,如第1D圖所標示的,第一部212與第二部214於延伸方向上的投影皆與緩衝部216重疊,第一部212與第二部214被定義為分別連接緩衝部216之相對兩端的第一導線210之二個部分。在第1D圖中,僅以虛線標示第一部212、緩衝部216以及第二部214的劃分界線。 Reference is also made to FIG. 1B and FIG. 1D. 1D is a top plan view of the first wire 210 of the wire structure 200 of the active device array substrate of FIG. 1B. In the embodiment of the present invention, the first wire 210 has a first portion 212 , a second portion 214 , and a buffer portion 216 . The buffer portion 216 is electrically connected between the first portion 212 and the second portion 214 . The extending direction of the first portion 212 is different from the extending direction of the buffer portion 214. In some embodiments, the extending direction of the second portion 214 is different from the extending direction of the buffer portion 216. In the definition of the noun in this document, as indicated by the 1D figure, the projections of the first portion 212 and the second portion 214 in the extending direction overlap with the buffer portion 216, and the first portion 212 and the second portion 214 are defined as respectively connected. Two portions of the first wire 210 at opposite ends of the buffer portion 216. In the first DD, the dividing line of the first portion 212, the buffer portion 216, and the second portion 214 is indicated by a broken line.
另一方面,於本實施方式中,第二導線220具有第一部222、第二部224以及緩衝部226,第二導線220之緩衝部226電性連接於第二導線220之第一部222與第二部224之間,其中第二導線220之第一部222的延伸方向與第二導線220之緩衝部226的延伸方向不同。於部分實施方式中,第二部224之延伸方向與緩衝部226之延伸方向不式中,第二部224之延伸方向與緩衝部226之延伸方向不同。於本文名詞定義中,第一部222與第二部224於延伸方向上的投影皆與緩衝部226重疊,第一部222與第二部224分別連接緩衝部226之相對兩端。第二導線220之第一部222、第二部224以及緩衝部226之定義大致與第一導線210相同,而不再另以圖式繪示劃分界線。 On the other hand, in the present embodiment, the second wire 220 has a first portion 222, a second portion 224, and a buffer portion 226. The buffer portion 226 of the second wire 220 is electrically connected to the first portion 222 of the second wire 220. Between the second portion 224, the extending direction of the first portion 222 of the second wire 220 is different from the extending direction of the buffer portion 226 of the second wire 220. In some embodiments, the extending direction of the second portion 224 and the extending direction of the buffer portion 226 are different, and the extending direction of the second portion 224 is different from the extending direction of the buffer portion 226. In the definition of the nouns herein, the projections of the first portion 222 and the second portion 224 in the extending direction overlap with the buffer portion 226, and the first portion 222 and the second portion 224 are respectively connected to opposite ends of the buffer portion 226. The definition of the first portion 222, the second portion 224, and the buffer portion 226 of the second wire 220 is substantially the same as that of the first wire 210, and the dividing line is not illustrated in the drawings.
於此,第一導線210之第一部212與第二導線220之第一部222之延伸方向大致相同,第一導線210之第二部214與第二導線220之第二部224之延伸方向大致相同,使得第一導線210以及第二導線220相互堆疊,而可以在有限的空間內同時傳送兩種不同的訊號。 Herein, the first portion 212 of the first wire 210 and the first portion 222 of the second wire 220 extend substantially the same direction, and the second portion 214 of the first wire 210 and the second portion 224 of the second wire 220 extend. Roughly the same, the first wire 210 and the second wire 220 are stacked on each other, and two different signals can be simultaneously transmitted in a limited space.
在部份情況下,因為光罩對準精度有限,第二導線220可能無法如第1B圖剛好設置於第一導線210的中央位置,而使得第一導線210與第二導線220的相對位置有偏移的問題。此偏移問題可能會造成第一導線210與第二導線220的重疊面積有劇烈的變化,進而影響第一導線210與第二導線220之間的電容。可以參考平行板電容器的公式:C=ε A/d,其中C為導線結構200中的電容,ε為中間層130的介電常數,A為第一導線210與第二導線220的重疊面積,d為第一導線210與第二導線220的距離,其中電容正比於重疊面積。至此,可能因為精準度問題,而難以控制導線結構200的電容。 In some cases, because the reticle alignment accuracy is limited, the second wire 220 may not be disposed at the center of the first wire 210 as in FIG. 1B, so that the relative positions of the first wire 210 and the second wire 220 are The problem of offset. This offset problem may cause a drastic change in the overlapping area of the first wire 210 and the second wire 220, thereby affecting the capacitance between the first wire 210 and the second wire 220. Reference can be made to the formula of the parallel plate capacitor: C = ε A / d, where C is the capacitance in the wire structure 200, ε is the dielectric constant of the intermediate layer 130, and A is the overlapping area of the first wire 210 and the second wire 220, d is the distance between the first wire 210 and the second wire 220, wherein the capacitance is proportional to the overlap area. At this point, it is difficult to control the capacitance of the wire structure 200 due to the accuracy problem.
同時參照第1B圖與第1E圖,第1E圖為第1B圖主動元件陣列基板100之一導線結構200的上視放大示意 邊220a之第二側邊220b。於本發明之多個實施方式中,設計第二導線220之第一側邊220a至少重疊於第一導線210之第一部212以及緩衝部216且不重疊於第一導線210之第二部214,第二導線220之第二側邊220b至少重疊於第一導線210之第二部214,第二導線220之第二側邊220b可不與第一導線210之第一部212重疊。如此一來,即使第一導線210與第二導線220在方向X+/X-、方向Y+/Y-上偏移,第一導線210與第二導線220的重疊面積仍能維持大致相同,進而確保導線結構200的電容不因第二導線220些微偏移而變化。 Referring to FIG. 1B and FIG. 1E simultaneously, FIG. 1E is a top view enlarged view of one of the conductor structures 200 of the active device array substrate 100 of FIG. 1B. The second side 220b of the side 220a. In the various embodiments of the present invention, the first side 220a of the second wire 220 is designed to overlap at least the first portion 212 of the first wire 210 and the buffer portion 216 and does not overlap the second portion 214 of the first wire 210. The second side 220b of the second wire 220 overlaps at least the second portion 214 of the first wire 210, and the second side 220b of the second wire 220 may not overlap with the first portion 212 of the first wire 210. In this way, even if the first wire 210 and the second wire 220 are offset in the direction X+/X- and the direction Y+/Y-, the overlapping area of the first wire 210 and the second wire 220 can be maintained substantially the same, thereby ensuring The capacitance of the wire structure 200 does not change due to the slight offset of the second wire 220.
具體而言,第一導線210之第一部212與第二導線220之第一部222具有一第一重疊面積,第一導線210之第二部214與第二導線220之第二部224具有一第二重疊面積。一方面,第一重疊面積與第二重疊面積的寬度隨在方向X+/X-、方向Y+/Y-上的偏移而有相反的變化量。舉例而言,第一重疊面積隨著第二導線220往方向X-偏移而增加一定面積,第二重疊面積隨著第二導線220往方向X-偏移而減少一定面積。另一方面,第一導線210與第二導線220有特殊配置,而使第一重疊面積與第二重疊面積的長度相似。如此一來,有鑑於第一重疊面積與第二重疊面積的長度相似,第一重疊面積與第二重疊面積的寬度隨偏移方向而有相反的變化量,因此第一重疊面積與第二重疊面積的和仍能維持大致相同,進而使導線結構200的電容不因第二導線220些微偏移而變化。 Specifically, the first portion 212 of the first wire 210 and the first portion 222 of the second wire 220 have a first overlapping area, and the second portion 214 of the first wire 210 and the second portion 224 of the second wire 220 have A second overlapping area. In one aspect, the width of the first overlap area and the second overlap area have opposite amounts of change with respect to the offset in the direction X+/X-, direction Y+/Y-. For example, the first overlap area is increased by a certain area as the second wire 220 is X-shifted in the direction, and the second overlap area is decreased by a certain area as the second wire 220 is X-shifted in the direction. On the other hand, the first wire 210 and the second wire 220 have a special configuration such that the first overlap area is similar to the length of the second overlap area. In this way, in view of the fact that the first overlap area is similar to the length of the second overlap area, the widths of the first overlap area and the second overlap area have opposite changes with the offset direction, so the first overlap area overlaps with the second overlap. The sum of the areas can still be maintained substantially the same, so that the capacitance of the wire structure 200 does not change due to the slight offset of the second wire 220.
關於設計特殊配置以使第一重疊面積與第二重疊面積的長度相似,可以設計緩衝部216與緩衝部226分別盡可能位於第一導線210與第二導線220的中央,而使第一導線210之第一部212之長度盡可能等於第一導線210之第二部214之長度,第二導線220之第一部222之長度盡可能等於第二導線220之第二部224之長度。然而,有鑑於傳輸線120與驅動器130腳位的關係,實際設計上,第一導線210之第一部212與第二部214之長度難以相同,第二導線220之第一部222與第二部224之長度難以相同,舉例而言,於此,第一導線210之第一部212之長度大於第一導線210之第二部214之長度,第二導線220之第二部224之長度大於第二導線220之第一部222之長度。於本發明之部分實施方式中,可以設計為第一部212之長度大約等於第二部224之長度,第一部222長度大約等於第二部214之長度,如此一來,可以使第一重疊面積與第二重疊面積的長度相似,以確保第一重疊面積與第二重疊面積的和仍能維持大致相同。 Regarding the design of the special configuration such that the first overlapping area is similar to the length of the second overlapping area, the buffer portion 216 and the buffer portion 226 may be designed to be located as far as possible in the center of the first wire 210 and the second wire 220, respectively, so that the first wire 210 is made. The length of the first portion 212 is as equal as possible to the length of the second portion 214 of the first wire 210, and the length of the first portion 222 of the second wire 220 is as equal as possible to the length of the second portion 224 of the second wire 220. However, in view of the relationship between the transmission line 120 and the driver 130, in actual design, the lengths of the first portion 212 and the second portion 214 of the first wire 210 are difficult to be the same, and the first portion 222 and the second portion of the second wire 220 are The length of the first portion 212 of the first wire 210 is greater than the length of the second portion 214 of the first wire 210, and the length of the second portion 224 of the second wire 220 is greater than the length. The length of the first portion 222 of the two wires 220. In some embodiments of the present invention, the length of the first portion 212 may be approximately equal to the length of the second portion 224, and the length of the first portion 222 is approximately equal to the length of the second portion 214, such that the first overlap can be made. The area is similar to the length of the second overlap area to ensure that the sum of the first overlap area and the second overlap area remains substantially the same.
為方便說明起見,於此先定義投影面P1為垂直於第二導線220之第一部222之延伸方向的平面。第一導線210之第一部212與第二部214於投影面P1上的垂直投影具有第一間距L1於其中,第二導線220之第一部222與第二部224於投影面P1上的垂直投影具有第二間距L2於其中。第二間距L2小於第一間距L1。換句話說,第二導線220之第一部222與第二部224之間的距離小於第一導線210之第一 部212與第二部214之間的距離,而使得第二導線220之緩衝部226的長度可小於第一導線210之緩衝部216。 For convenience of explanation, the projection plane P1 is defined as a plane perpendicular to the extending direction of the first portion 222 of the second wire 220. The vertical projection of the first portion 212 and the second portion 214 of the first wire 210 on the projection surface P1 has a first pitch L1 therein, and the first portion 222 and the second portion 224 of the second wire 220 are on the projection surface P1. The vertical projection has a second pitch L2 therein. The second pitch L2 is smaller than the first pitch L1. In other words, the distance between the first portion 222 of the second wire 220 and the second portion 224 is less than the first of the first wire 210 The distance between the portion 212 and the second portion 214 is such that the length of the buffer portion 226 of the second wire 220 can be smaller than the buffer portion 216 of the first wire 210.
為了使第二導線220之第一側邊220a至少重疊於第一導線210之第一部212以及緩衝部216且不重疊於第一導線210之第二部214,第二導線220之第二側邊220b至少重疊於第一導線210之第二部214,此時可設計第一間距L1不大於第二間距L2與第二導線220之第一部222之寬度W2之合。於部分實施方式中,第二導線220之第一部222之寬度W2即第二導線220之第一部222於投影面P1上的垂直投影的寬度。如此一來,第二導線220的設置位置可以有一定的偏差容許範圍。具體而言,於本實施方式中,第一間距L1大約等於第二間距L2與第二導線220之第一部222(與第二部224)之寬度W2之合,於投影面P1上,該偏差容許範圍於投影面P1上大約等於寬度W2的值。於其他實施方式中,第一間距L1小於第二間距L2與第二導線220之第一部222之寬度W2之合,於投影面P1上,該偏差容許範圍於投影面P1上大約等於第一間距L1減去第二間距L2的值。 In order to make the first side 220a of the second wire 220 overlap at least the first portion 212 of the first wire 210 and the buffer portion 216 and not overlap the second portion 214 of the first wire 210, the second side of the second wire 220 The edge 220b overlaps at least the second portion 214 of the first wire 210. At this time, the first pitch L1 can be designed to be no greater than the width W2 of the first portion 222 of the second wire 220. In some embodiments, the width W2 of the first portion 222 of the second wire 220 is the width of the vertical projection of the first portion 222 of the second wire 220 on the projection surface P1. In this way, the position of the second wire 220 can be set to a certain tolerance range. Specifically, in the embodiment, the first pitch L1 is approximately equal to the width of the second portion L2 and the width W2 of the first portion 222 (and the second portion 224) of the second wire 220 on the projection surface P1. The deviation tolerance range is approximately equal to the value of the width W2 on the projection surface P1. In other embodiments, the first pitch L1 is smaller than the width W2 of the first portion 222 of the second wire 220, and the tolerance range is approximately equal to the first on the projection surface P1 on the projection surface P1. The pitch L1 is subtracted from the value of the second pitch L2.
第2A圖與第2B圖為第1B圖之導線結構200於製程偏移狀況下的上視示意圖。於此,以第2A圖與第2B圖分別展示方向X+/X-上可容許偏移範圍內的兩個極端例子,其中第2A圖的實施例中第二導線220往方向X-偏移。第2A圖的實施例中,第二導線220之第一側邊220a重疊於第一導線210之緩衝部216且不重疊於第一導線210之第二 部214,第二側邊220b恰好重疊於第一導線210之第二部214的邊緣,如此一來,第一重疊面積與第二重疊面積的和仍能等於第2A圖中第一重疊面積與第二重疊面積的和。第2B圖的實施例中第二導線220往方向X+偏移,第二導線220之第二側邊220b重疊於第一導線210之緩衝部216且不重疊於第一導線210之第一部212,第一側邊220a恰好重疊於第一導線210之第一部212以及緩衝部216的邊緣,如此一來,第一重疊面積與第二重疊面積的和仍能等於第2A圖中第一重疊面積與第二重疊面積的和。 2A and 2B are top views of the wire structure 200 of FIG. 1B in a process offset state. Here, two extreme examples within the allowable offset range in the direction X+/X- are shown in Figures 2A and 2B, respectively, wherein the second wire 220 in the embodiment of Figure 2A is offset X-direction. In the embodiment of FIG. 2A, the first side 220a of the second wire 220 overlaps the buffer portion 216 of the first wire 210 and does not overlap the second wire 210. 214, the second side 220b just overlaps the edge of the second portion 214 of the first wire 210, so that the sum of the first overlap area and the second overlap area can still be equal to the first overlap area in FIG. 2A and The sum of the second overlapping areas. In the embodiment of FIG. 2B, the second wire 220 is offset in the direction X+, and the second side 220b of the second wire 220 is overlapped with the buffer portion 216 of the first wire 210 and does not overlap the first portion 212 of the first wire 210. The first side 220a overlaps the first portion 212 of the first wire 210 and the edge of the buffer portion 216, so that the sum of the first overlap area and the second overlap area can still be equal to the first overlap in FIG. 2A. The sum of the area and the second overlapping area.
於本發明之一或多個實施方式,第一導線210之第一部212與第二部214的寬度實質相同,第二導線220之第一部222與第二部224的寬度實質相同,以達到前述抗偏移目的。於本實施方式中,第一導線210之寬度(即第一部212與第二部214的寬度)可以等於第二導線220之寬度(即第一部222與第二部224的寬度)。當然不應以此限制本發明之範圍,於其他實施方式中,第一導線210之寬度(即第一部212與第二部214的寬度)可以不等於第二導線220之寬度(即第一部222與第二部224的寬度),此時仍可設計第一間距L1不大於第二間距L2與第二導線220之第一部222(或第二部224)之寬度W2之合,亦可有前述之偏差容許功效。 In one or more embodiments of the present invention, the widths of the first portion 212 and the second portion 214 of the first wire 210 are substantially the same, and the widths of the first portion 222 and the second portion 224 of the second wire 220 are substantially the same, Achieve the aforementioned anti-offset purpose. In the present embodiment, the width of the first wire 210 (ie, the width of the first portion 212 and the second portion 214) may be equal to the width of the second wire 220 (ie, the width of the first portion 222 and the second portion 224). The scope of the present invention should not be limited in this way. In other embodiments, the width of the first wire 210 (ie, the width of the first portion 212 and the second portion 214) may not be equal to the width of the second wire 220 (ie, the first The width of the portion 222 and the second portion 224 can be designed to be no longer than the width W2 of the first portion 222 (or the second portion 224) of the second wire 220. There may be deviations as described above to allow for efficacy.
於本發明之一或多個實施方式,第一導線210之第一部212與第二部214之延伸方向實質相同,第二導線220之第一部222與第二部224之延伸方向實質相同。藉 此,所形成的第一重疊面積與第二重疊面積形狀大致相同。當然不應以此限制本發明之範圍,於部分實施方式中,重疊面積主要受到第一部212、222與第二部214、224長度的影響,在確保第一部212與第一部222延伸方向實質相同、第二部214與第二部224延伸方向實質相同時,此第一部212與第二部214之延伸方向的差異對於重疊面積的影響不大,因此第一導線210之第一部212與第二部214之延伸方向可以不同,第二導線220之第一部222與第二部224之延伸方向可以不同。 In one or more embodiments of the present invention, the first portion 212 of the first wire 210 and the second portion 214 extend substantially the same direction, and the first portion 222 of the second wire 220 and the second portion 224 extend substantially the same direction. . borrow Thus, the first overlapping area formed is substantially the same as the second overlapping area shape. The scope of the invention should not be limited thereby, in some embodiments, the overlap area is primarily affected by the length of the first portion 212, 222 and the second portion 214, 224, ensuring that the first portion 212 and the first portion 222 extend When the directions of the second portion 214 and the second portion 224 are substantially the same, the difference between the extending directions of the first portion 212 and the second portion 214 has little effect on the overlapping area, so the first wire 210 is first. The extending direction of the portion 212 and the second portion 214 may be different, and the extending direction of the first portion 222 and the second portion 224 of the second wire 220 may be different.
於本實施方式,第一導線210之緩衝部216與第二導線220之緩衝部226重疊,第一導線210之緩衝部216之延伸方向與第二導線220之緩衝部226之延伸方向實質相同,舉例而言,於此平行於方向X-與方向X+,以達到節省空間的目的。於其他實施方式中,第一導線210之緩衝部216與第二導線220之緩衝部226的延伸方向可不平行於方向X-與方向X+。再於其他實施方式中,如前所述,重疊面積主要受到第一部212、222與第二部214、224長度的影響,因此第一導線210之緩衝部216之延伸方向與第二導線220之緩衝部226之延伸方向可以不同。 In the present embodiment, the buffer portion 216 of the first wire 210 overlaps with the buffer portion 226 of the second wire 220, and the buffer portion 216 of the first wire 210 extends in substantially the same direction as the buffer portion 226 of the second wire 220. For example, this is parallel to the direction X- and the direction X+ to achieve space saving. In other embodiments, the buffer portion 216 of the first wire 210 and the buffer portion 226 of the second wire 220 may extend in a direction not parallel to the direction X- and the direction X+. In other embodiments, as described above, the overlap area is mainly affected by the lengths of the first portions 212, 222 and the second portions 214, 224, so that the direction of extension of the buffer portion 216 of the first wire 210 and the second wire 220 The direction in which the buffer portion 226 extends may be different.
再回到第1B圖。本實施方式中,每一導線結構200之第一導線210包含第一連接部217與第二連接部218,其中第一連接部217連接第一導線210之第一部212與傳輸線120a,第二連接部218連接第一導線210之第二部214與驅動器130。另一方面,每一導線結構200之第二導 線220包含第一連接部227與第二連接部228,其中第一連接部227連接第二導線220之第一部222與傳輸線120b,第二連接部228連接第二導線220之第二部224與驅動器130。 Go back to Figure 1B. In this embodiment, the first wire 210 of each wire structure 200 includes a first connecting portion 217 and a second connecting portion 218, wherein the first connecting portion 217 connects the first portion 212 of the first wire 210 with the transmission line 120a, and the second The connecting portion 218 connects the second portion 214 of the first wire 210 with the driver 130. On the other hand, the second guide of each wire structure 200 The wire 220 includes a first connecting portion 227 and a second connecting portion 228, wherein the first connecting portion 227 is connected to the first portion 222 of the second wire 220 and the transmission line 120b, and the second connecting portion 228 is connected to the second portion 224 of the second wire 220. With the drive 130.
於此,第一導線210之第一連接部217不與第二導線220之第一連接部227重疊,第一導線210之第二連接部218不與第二導線220之第二連接部228重疊。因此,第一連接部217、227以及第二連接部218、228的長度不影響前述之電容值,第一連接部217、227以及第二連接部218、228的長度可以作任意適當配置。 The first connecting portion 217 of the first wire 210 does not overlap with the first connecting portion 227 of the second wire 220, and the second connecting portion 218 of the first wire 210 does not overlap with the second connecting portion 228 of the second wire 220. . Therefore, the lengths of the first connecting portions 217, 227 and the second connecting portions 218, 228 do not affect the aforementioned capacitance values, and the lengths of the first connecting portions 217, 227 and the second connecting portions 218, 228 may be arbitrarily configured as appropriate.
至此,透過上述設置導線結構200可以有抗偏移的效果。 So far, the anti-offset effect can be obtained by the above-described provision of the wire structure 200.
於本發明之多個實施方式中,第一導線210與第二導線220可以由各種導電材料所形成,例如金屬。中間層230與保護層240可以由各種絕緣材料所形成,例如無機材料(例如:氧化矽、氮化矽、氮氧化矽、其它合適的材料、或上述之組合)或有機材料(例如:光阻、聚醯亞胺(polyimide;PI)、苯並環丁烯(BCB)、環氧樹脂(Epoxy)、過氟環丁烷(PFCB)、其它合適的材料、或上述之組合)、或其它合適的材料、或上述之組合。中間層230與保護層240可以由相同或不同材料所形成。中間層230採用絕緣材料,可以電性隔絕第一導線210以及第二導線220。於其他實施方式中,中間層230也可以由半導體材料所形成,例如為經摻雜的半導體材料。此半導體材料可容許第一導線210以及第二導線220在適當的電位差範圍(例如為0至8伏特)內不 互相影響。舉例而言,此半導體材料可以是單晶矽。 In various embodiments of the present invention, the first wire 210 and the second wire 220 may be formed of various conductive materials, such as metal. The intermediate layer 230 and the protective layer 240 may be formed of various insulating materials such as inorganic materials (for example, yttria, tantalum nitride, yttrium oxynitride, other suitable materials, or a combination thereof) or organic materials (for example, photoresist). , polyimide (PI), benzocyclobutene (BCB), epoxy (Epoxy), perfluorocyclobutane (PFCB), other suitable materials, or combinations thereof, or other suitable Material, or a combination of the above. The intermediate layer 230 and the protective layer 240 may be formed of the same or different materials. The intermediate layer 230 is made of an insulating material, and the first wire 210 and the second wire 220 can be electrically insulated. In other embodiments, the intermediate layer 230 can also be formed from a semiconductor material, such as a doped semiconductor material. The semiconductor material can allow the first wire 210 and the second wire 220 to be within a suitable potential difference range (eg, 0 to 8 volts) Influence each other. For example, the semiconductor material can be a single crystal germanium.
第3圖為根據本發明之部分實施方式之導線結構200的上視示意圖。本實施方式與第1B圖的實施方式相似,差別在於:於本實施方式中,第一導線210之第一部212與第二部214之延伸方向不同,第二導線220之第一部222與第二部224之延伸方向不同。如前所述,重疊面積主要受到第一部212、222與第二部214、224長度的影響,在確保第一部212與第一部222延伸方向實質相同、第二部214與第二部224延伸方向實質相同時,可以設計第一部212、222的延伸方向不同於第二部214、224的延伸方向,以利於活用空間以搭配其他元件的配置。本實施方式的其他細節大致如前所述,在此不再贅述。 3 is a top plan view of a wire structure 200 in accordance with some embodiments of the present invention. This embodiment is similar to the embodiment of FIG. 1B. The difference is that in the embodiment, the first portion 212 of the first wire 210 and the second portion 214 extend in different directions, and the first portion 222 of the second wire 220 is The second portion 224 extends in a different direction. As previously mentioned, the overlap area is primarily affected by the length of the first portions 212, 222 and the second portions 214, 224, ensuring that the first portion 212 and the first portion 222 extend substantially the same direction, the second portion 214 and the second portion When the extending direction of the 224 is substantially the same, the extending direction of the first portions 212, 222 may be different from the extending direction of the second portions 214, 224 to facilitate the utilization of the space to match the configuration of other components. Other details of the present embodiment are substantially as described above, and are not described herein again.
第4圖為根據本發明之部分實施方式之導線結構200的上視示意圖。本實施方式與第1B圖的實施方式相似,差別在於:於本實施方式中,第一導線210之緩衝部216與第二導線220之緩衝部226不重疊。 4 is a top plan view of a wire structure 200 in accordance with some embodiments of the present invention. This embodiment is similar to the embodiment of FIG. 1B except that in the present embodiment, the buffer portion 216 of the first wire 210 and the buffer portion 226 of the second wire 220 do not overlap.
如前所述,重疊面積主要受到第一部212、222與第二部214、224長度的影響,相對來說,而較無關乎緩衝部216、緩衝部226的配置。因此,可以設計緩衝部216、緩衝部226錯開。於其他實施方式中,導線210之緩衝部216之延伸方向與第二導線220之緩衝部226之延伸方向可以不同。本實施方式的其他細節大致如前所述,在此不再贅述。 As previously mentioned, the overlap area is primarily affected by the length of the first portions 212, 222 and the second portions 214, 224, and relatively independent of the arrangement of the buffer portion 216 and the buffer portion 226. Therefore, the buffer portion 216 and the buffer portion 226 can be designed to be shifted. In other embodiments, the extending direction of the buffer portion 216 of the wire 210 may be different from the extending direction of the buffer portion 226 of the second wire 220. Other details of the present embodiment are substantially as described above, and are not described herein again.
第5圖為根據本發明之部分實施方式之導線結構200的上視示意圖。本實施方式與第1B圖的實施方式相 似,差別在於:於本實施方式中,第二導線220包含長直導線229,而不具有緩衝部226(參考第1B圖)。長直導線229連接於第一連接部227與第二連接部228之間,長直導線229的延伸方向不同於第一連接部227與第二連接部228的延伸方向。於此,第一導線210之第一部212與第二部214的延伸方向實質相同,且第一導線210之第一部212與第二部214的延伸方向與長直導線229的延伸方向實質相同。於部分實施方式中,此長直導線229與第一導線210之緩衝部216至少部分重疊。在此,長直導線229係指具有單一延伸方向的導線。 Figure 5 is a top plan view of a wire structure 200 in accordance with some embodiments of the present invention. This embodiment is similar to the embodiment of FIG. 1B. The difference is that in the present embodiment, the second wire 220 includes the long straight wire 229 without the buffer portion 226 (refer to FIG. 1B). The long straight wire 229 is connected between the first connecting portion 227 and the second connecting portion 228. The extending direction of the long straight wire 229 is different from the extending direction of the first connecting portion 227 and the second connecting portion 228. Herein, the first portion 212 of the first wire 210 and the second portion 214 extend substantially the same direction, and the extending direction of the first portion 212 and the second portion 214 of the first wire 210 and the extending direction of the long straight wire 229 are substantially the same. In some embodiments, the long straight wire 229 at least partially overlaps the buffer portion 216 of the first wire 210. Here, the long straight wire 229 refers to a wire having a single extending direction.
於本發明之一或多個實施方式,第一導線210之第一部212與第二部214於投影面P1之垂直投影實質相連。換句話說,第一導線210之緩衝部216於投影面P1上的投影即為第一部212與第二部214共同於投影面P1之垂直投影集合。 In one or more embodiments of the present invention, the first portion 212 of the first wire 210 and the second portion 214 are substantially connected to the vertical projection of the projection surface P1. In other words, the projection of the buffer portion 216 of the first wire 210 on the projection surface P1 is a vertical projection set in which the first portion 212 and the second portion 214 are common to the projection surface P1.
透過上述設計,可以確保第一導線210與第二導線220在適當的偏移範圍內,第一導線210與第二導線220的重疊面積相同,進而確保導線結構200的電容不因偏移而變化。 Through the above design, it can be ensured that the first wire 210 and the second wire 220 are within the proper offset range, and the overlapping area of the first wire 210 and the second wire 220 is the same, thereby ensuring that the capacitance of the wire structure 200 does not change due to the offset. .
本實施方式的其他細節大致如前所述,在此不再贅述。 Other details of the present embodiment are substantially as described above, and are not described herein again.
再回到第1A圖。本發明之多個實施方式中,因驅動器130的腳位(未繪示)分布與位於主動區AA之傳輸線120的分布並不相同,使得各個導線結構200的長度並不相 同。舉例而言,位於外側的導線結構200a的長度大於位於內側的導線結構200c的長度。於本發明之多個實施方式中,針對導線結構200的長度調整各個導線結構200的第一重疊面積與第二重疊面積。 Go back to Figure 1A. In various embodiments of the present invention, the distribution of the pins (not shown) of the driver 130 is not the same as the distribution of the transmission lines 120 located in the active area AA, so that the lengths of the respective wire structures 200 are not the same. with. For example, the length of the wire structure 200a located on the outer side is greater than the length of the wire structure 200c located on the inner side. In various embodiments of the invention, the first overlap area and the second overlap area of each of the wire structures 200 are adjusted for the length of the wire structure 200.
第6A圖至第6C圖為第1A圖之主動元件陣列基板100之多個導線結構200a~200c的上視示意圖。同時參照第6A圖至第6C圖,每一導線結構200a~200c中之第一導線210之緩衝部216與第二導線220構成重疊部OV,其中至少二個重疊部OV之面積不同。 6A to 6C are top plan views of a plurality of wire structures 200a to 200c of the active device array substrate 100 of Fig. 1A. Referring to FIGS. 6A-6C, the buffer portion 216 of the first wire 210 in each of the wire structures 200a-200c and the second wire 220 constitute an overlapping portion OV, wherein at least two overlapping portions OV have different areas.
為方便說明起見,於此先定義第一導線210之第一部212與第二部216於投影面P1上的垂直投影具有第一間距L1於其中,第二導線220之第一部222與第二部226於投影面P1上的垂直投影具有第二間距L2於其中。 For convenience of description, the vertical projection of the first portion 212 and the second portion 216 of the first wire 210 on the projection surface P1 is first defined to have a first pitch L1 therein, and the first portion 222 of the second wire 220 is The vertical projection of the second portion 226 on the projection surface P1 has a second pitch L2 therein.
於本實施方式中,針對導線結構200a~200c的長度,在維持第一導線210之第一間距L1的情況下,調整第二導線220之第二間距L2之間的距離。詳細而言,導線結構200a~200c的長度與第二導線220之第二間距L2可以有負相關關係。舉例而言,導線結構200a之長度大於導線結構200b之長度,導線結構200a之第二間距L2(未標示)為零,小於導線結構200b之第二間距L2。同樣地,導線結構200b之長度大於導線結構200c之長度,導線結構200b之第二間距L2小於導線結構200c之第二間距L2。 In the present embodiment, for the length of the wire structures 200a to 200c, the distance between the second pitches L2 of the second wires 220 is adjusted while maintaining the first pitch L1 of the first wires 210. In detail, the length of the wire structures 200a-200c and the second pitch L2 of the second wire 220 may have a negative correlation. For example, the length of the wire structure 200a is greater than the length of the wire structure 200b, and the second spacing L2 (not labeled) of the wire structure 200a is zero, which is less than the second spacing L2 of the wire structure 200b. Similarly, the length of the wire structure 200b is greater than the length of the wire structure 200c, and the second spacing L2 of the wire structure 200b is less than the second spacing L2 of the wire structure 200c.
如此一來,雖然各個導線結構200a~200c的長度不同,但因為第二導線220之第二間距L2的調整,可以 使導線結構200a~200c的重疊面積(即前述的第一重疊面積與第二重疊面積之和)大致相同。 In this way, although the lengths of the respective wire structures 200a to 200c are different, because the second pitch L2 of the second wire 220 is adjusted, The overlapping area of the wire structures 200a to 200c (i.e., the sum of the aforementioned first overlapping area and the second overlapping area) is substantially the same.
於本實施方式中,以上調整第二導線220之第二間距L2可以反映在緩衝部226的尺寸。每一導線結構200a~200c之第一導線210之緩衝部216的尺寸相同。針對導線結構200的長度,調整至少部分導線結構200a~200c之第二導線220之緩衝部226的尺寸,至少部分導線結構200a~200c之第二導線220之緩衝部226的尺寸不同,進而調整重疊部OV的面積。詳細而言,導線結構200a~200c的長度與重疊部OV的面積可以有負相關關係。舉例而言,導線結構200a之長度大於導線結構200b之長度,導線結構200a之重疊部OV的面積小於導線結構200b之重疊部OV的面積。同樣地,導線結構200b之長度大於導線結構200c之長度,導線結構200b之重疊部OV的面積小於導線結構200c之重疊部OV的面積。換句話說,該些導線結構之一第一者之長度大於該些導線結構之一第二者之長度,且該些導線結構之該第一者之該重疊部的面積小於該些導線結構之該第二者之該重疊部的面積。 In the present embodiment, the second pitch L2 of the above adjustment second wire 220 may be reflected in the size of the buffer portion 226. The buffer portions 216 of the first wires 210 of each of the wire structures 200a to 200c have the same size. For the length of the wire structure 200, the size of the buffer portion 226 of the second wire 220 of at least part of the wire structures 200a-200c is adjusted, and the size of the buffer portion 226 of the second wire 220 of at least part of the wire structures 200a-200c is different, and the overlap is adjusted. The area of the OV. In detail, the length of the wire structures 200a to 200c may have a negative correlation with the area of the overlapping portion OV. For example, the length of the wire structure 200a is greater than the length of the wire structure 200b, and the area of the overlapping portion OV of the wire structure 200a is smaller than the area of the overlapping portion OV of the wire structure 200b. Similarly, the length of the wire structure 200b is greater than the length of the wire structure 200c, and the area of the overlap OV of the wire structure 200b is smaller than the area of the overlap OV of the wire structure 200c. In other words, the length of the first one of the wire structures is greater than the length of the second one of the wire structures, and the area of the overlapping portion of the first one of the wire structures is smaller than the wire structure The area of the overlapping portion of the second one.
以上,第二間距L2與重疊部OV的面積調整與導線結構200a~200c的長度呈現負相關關係。如此一來,即使各個導線結構200a~200c的長度不盡相同,各個導線結構200a~200c的重疊面積(即第一重疊面積與第二重疊面積的和)能維持大致相同。 As described above, the area adjustment of the second pitch L2 and the overlapping portion OV has a negative correlation with the length of the wire structures 200a to 200c. In this way, even if the lengths of the respective wire structures 200a to 200c are not the same, the overlapping area of the respective wire structures 200a to 200c (that is, the sum of the first overlapping area and the second overlapping area) can be maintained substantially the same.
於此,僅以導線結構200a~200c來說明設計概 念,各個導線結構200a~200c大致採用如前導線結構200(參考第1B圖)的配置,實際應用上並不應此導線結構200a~200c之數量來限制本發明之範圍。 Here, the design of the design is only described by the wire structures 200a to 200c. It is to be noted that the respective wire structures 200a to 200c are generally configured as the front wire structure 200 (refer to FIG. 1B), and the actual application does not limit the scope of the present invention by the number of the wire structures 200a to 200c.
本實施方式的其他細節大致如前所述,在此不再贅述。 Other details of the present embodiment are substantially as described above, and are not described herein again.
本發明之多個實施方式中,設計導線結構具有相互堆疊的第一導線與第二導線,第二導線的設置位置可以有一定的偏差容許範圍,而因製程偏差不會影響到第一導線與第二導線的重疊面積,進而確保導線結構的電容不因第二導線些微偏移而變化。此外,隨著各個導線結構的長度變化,各個導線結構之第二導線可以而作相應調整,而使各個導線結構的電容實質相同。 In various embodiments of the present invention, the design wire structure has a first wire and a second wire stacked on each other, and the second wire is disposed at a certain tolerance range, and the process deviation does not affect the first wire and The overlapping area of the second wire, thereby ensuring that the capacitance of the wire structure does not change due to slight offset of the second wire. In addition, as the length of each wire structure changes, the second wires of each wire structure can be adjusted accordingly, so that the capacitances of the respective wire structures are substantially the same.
雖然本發明已以多種實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.
120‧‧‧傳輸線 120‧‧‧ transmission line
120a~120b‧‧‧傳輸線 120a~120b‧‧‧ transmission line
130‧‧‧驅動器 130‧‧‧ drive
200‧‧‧導線結構 200‧‧‧Wire structure
210‧‧‧第一導線 210‧‧‧First wire
212‧‧‧第一部 212‧‧‧ first
214‧‧‧第二部 214‧‧‧Part II
216‧‧‧緩衝部 216‧‧‧ buffer
217‧‧‧第一連接部 217‧‧‧First connection
218‧‧‧第二連接部 218‧‧‧Second connection
220‧‧‧第二導線 220‧‧‧second wire
220a‧‧‧第一側邊 220a‧‧‧ first side
220b‧‧‧第二側邊 220b‧‧‧ second side
222‧‧‧第一部 222‧‧‧ first
224‧‧‧第二部 224‧‧‧ second
226‧‧‧緩衝部 226‧‧‧ buffer
227‧‧‧第一連接部 227‧‧‧First connection
228‧‧‧第二連接部 228‧‧‧Second connection
X-‧‧‧方向 X-‧‧‧ direction
X+‧‧‧方向 X+‧‧‧ direction
Y-‧‧‧方向 Y-‧‧‧ direction
Y+‧‧‧方向 Y+‧‧‧ direction
1C-1C‧‧‧線 1C-1C‧‧‧ line
Claims (21)
Priority Applications (2)
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TW105143023A TWI587053B (en) | 2016-12-23 | 2016-12-23 | Conductive line structure and active device array substrate |
CN201710095737.XA CN107039464B (en) | 2016-12-23 | 2017-02-22 | Wire structure and active element array substrate |
Applications Claiming Priority (1)
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TW105143023A TWI587053B (en) | 2016-12-23 | 2016-12-23 | Conductive line structure and active device array substrate |
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TWI587053B true TWI587053B (en) | 2017-06-11 |
TW201823827A TW201823827A (en) | 2018-07-01 |
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TW (1) | TWI587053B (en) |
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CN113325640B (en) * | 2018-06-29 | 2022-12-30 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200713408A (en) * | 2005-09-05 | 2007-04-01 | Au Optronics Corp | Fan-out wire structure |
CN103399434B (en) * | 2013-08-01 | 2015-09-16 | 深圳市华星光电技术有限公司 | Display panel and Fanout line structure thereof |
TW201636715A (en) * | 2015-04-15 | 2016-10-16 | 元太科技工業股份有限公司 | Display panel and manufacturing method thereof |
Family Cites Families (3)
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KR20080057035A (en) * | 2006-12-19 | 2008-06-24 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating the same |
TWI461806B (en) * | 2011-06-16 | 2014-11-21 | Au Optronics Corp | Lead line strcuture and display panel having the same |
TWI571989B (en) * | 2014-01-28 | 2017-02-21 | 友達光電股份有限公司 | Display substrate |
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2016
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200713408A (en) * | 2005-09-05 | 2007-04-01 | Au Optronics Corp | Fan-out wire structure |
CN103399434B (en) * | 2013-08-01 | 2015-09-16 | 深圳市华星光电技术有限公司 | Display panel and Fanout line structure thereof |
TW201636715A (en) * | 2015-04-15 | 2016-10-16 | 元太科技工業股份有限公司 | Display panel and manufacturing method thereof |
Also Published As
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CN107039464A (en) | 2017-08-11 |
CN107039464B (en) | 2019-07-23 |
TW201823827A (en) | 2018-07-01 |
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