TWI584120B - 用於動態調適快取的方法及系統 - Google Patents

用於動態調適快取的方法及系統 Download PDF

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Publication number
TWI584120B
TWI584120B TW102105705A TW102105705A TWI584120B TW I584120 B TWI584120 B TW I584120B TW 102105705 A TW102105705 A TW 102105705A TW 102105705 A TW102105705 A TW 102105705A TW I584120 B TWI584120 B TW I584120B
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TW
Taiwan
Prior art keywords
data
space
storage device
host
amount
Prior art date
Application number
TW102105705A
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English (en)
Chinese (zh)
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TW201342063A (zh
Inventor
荷莉雅 席米歐尼斯庫
馬克 艾許
路卡 伯特
羅伯特 昆恩
厄爾Ｔ 寇翰
提摩希 卡尼帕
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Lsi公司
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Priority claimed from US13/566,204 external-priority patent/US9158695B2/en
Application filed by Lsi公司 filed Critical Lsi公司
Publication of TW201342063A publication Critical patent/TW201342063A/zh
Application granted granted Critical
Publication of TWI584120B publication Critical patent/TWI584120B/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
TW102105705A 2012-03-23 2013-02-19 用於動態調適快取的方法及系統 TWI584120B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261614548P 2012-03-23 2012-03-23
US201261614545P 2012-03-23 2012-03-23
US13/566,204 US9158695B2 (en) 2011-08-09 2012-08-03 System for dynamically adaptive caching

Publications (2)

Publication Number Publication Date
TW201342063A TW201342063A (zh) 2013-10-16
TWI584120B true TWI584120B (zh) 2017-05-21

Family

ID=47845763

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102105705A TWI584120B (zh) 2012-03-23 2013-02-19 用於動態調適快取的方法及系統

Country Status (5)

Country Link
EP (1) EP2642397A1 (enExample)
JP (1) JP6228374B2 (enExample)
KR (1) KR102022721B1 (enExample)
CN (1) CN103324586B (enExample)
TW (1) TWI584120B (enExample)

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TWI874641B (zh) * 2020-07-08 2025-03-01 南韓商三星電子股份有限公司 儲存元件以及管理儲存元件中命名空間之系統與方法

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CN104699219B (zh) * 2013-12-10 2020-06-23 联想(北京)有限公司 一种电子设备及信息处理方法
CN104852812B (zh) * 2015-04-03 2018-08-07 上海航天电子通讯设备研究所 1553b总线远置单元自适应收发数据方法
CN106484310B (zh) * 2015-08-31 2020-01-10 华为数字技术（成都）有限公司 一种存储阵列操作方法和装置
CN106484331B (zh) * 2015-09-29 2019-04-12 华为技术有限公司 一种数据处理方法、装置及闪存设备
WO2019165004A1 (en) * 2018-02-21 2019-08-29 Patchd, Inc. Systems and methods for subject monitoring
US10963332B2 (en) * 2018-12-17 2021-03-30 Western Digital Technologies, Inc. Data storage systems and methods for autonomously adapting data storage system performance, capacity and/or operational requirements
US12099747B2 (en) * 2020-12-22 2024-09-24 Red Hat, Inc. Managing write removal for solid-state drives
CN113722241B (zh) * 2021-08-30 2025-04-18 锐掣(杭州)科技有限公司 数据处理方法、装置、设备、可读存储介质及程序产品
CN117056246A (zh) * 2023-07-04 2023-11-14 山东日照发电有限公司 一种数据缓存方法及系统

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US7779056B2 (en) * 2006-09-15 2010-08-17 Sandisk Corporation Managing a pool of update memory blocks based on each block's activity and data order
US20120072641A1 (en) * 2010-09-21 2012-03-22 Hitachi, Ltd. Semiconductor storage device and data control method thereof

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KR100750036B1 (ko) * 2001-08-24 2007-08-16 인텔 코오퍼레이션 플로우 제어를 구현하는 범용 입출력 아키텍쳐, 프로토콜및 관련 방법
US6968424B1 (en) * 2002-08-07 2005-11-22 Nvidia Corporation Method and system for transparent compressed memory paging in a computer system
US20050132161A1 (en) * 2003-12-15 2005-06-16 Nokia Corporation Creation of virtual memory space in a memory
US7243191B2 (en) * 2004-08-31 2007-07-10 Intel Corporation Compressing data in a cache memory
WO2007135602A1 (en) * 2006-05-24 2007-11-29 Koninklijke Philips Electronics N.V. Electronic device and method for storing and retrieving data
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
TW200608198A (en) * 2004-05-03 2006-03-01 Microsoft Corp Non-volatile memory cache performance improvement
US7779056B2 (en) * 2006-09-15 2010-08-17 Sandisk Corporation Managing a pool of update memory blocks based on each block's activity and data order
US20080189485A1 (en) * 2007-02-01 2008-08-07 Samsung Electronics Co., Ltd. Cooperative memory management
US20120072641A1 (en) * 2010-09-21 2012-03-22 Hitachi, Ltd. Semiconductor storage device and data control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI874641B (zh) * 2020-07-08 2025-03-01 南韓商三星電子股份有限公司 儲存元件以及管理儲存元件中命名空間之系統與方法

Also Published As

Publication number Publication date
TW201342063A (zh) 2013-10-16
JP6228374B2 (ja) 2017-11-08
CN103324586B (zh) 2018-01-12
KR20130108117A (ko) 2013-10-02
JP2013200868A (ja) 2013-10-03
KR102022721B1 (ko) 2019-09-18
EP2642397A1 (en) 2013-09-25
CN103324586A (zh) 2013-09-25

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