TWI582933B - Fabrication process for making embedded package structure - Google Patents

Description

Method for manufacturing embedded package structure

The present invention relates to a method of fabricating a package structure, and more particularly to a method of fabricating an embedded package structure.

In today's highly information society, the multimedia application market continues to expand rapidly, and the integrated circuit packaging technology has also evolved toward the digitalization, networking, regional connectivity and user-friendliness of electronic devices. In order to achieve the above requirements, electronic components must meet the requirements of high-speed processing, multi-function, integration, and small size and light weight. Therefore, integrated circuit packaging technology is also becoming miniaturized and high-density. development of. Among them, Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip Package (F/C), Multi-Chip Module (Multi-Chip) Module, MCM) and other high-density integrated circuit packaging technology also came into being.

The flip chip mounting technology mainly forms a ball bottom metal layer (UBM, Under Bump Metallurgy) on the external contact (usually a wafer pad) on a wafer on which a plurality of wafers are formed, and then on the bottom metal layer. A bump or implanted solder ball is formed thereon as a connection interface for subsequent electrical connection between the wafer (or wafer) and the substrate. Since the flip chip mounting technology can be applied to a high pin count chip package structure, and has many advantages such as reducing the package area and shortening the signal transmission path, the flip chip mounting technology has been widely used in The field of chip packaging.

Moreover, in order to create a larger space in a limited substrate area to enhance the function of the electronic device, conventional techniques embed electronic components in the substrate to form an embedded package structure. The user can select the substrate material with a suitable dielectric constant and resistance value according to his needs to adjust the circuit characteristics. Reduce circuit layout, reduce the number of non-embedded electronic units, and reduce signals The transmission distance is used to improve the performance of the embedded package structure.

Hereinafter, a method of manufacturing a general embedded package structure will be briefly described with reference to FIGS. 1A to 1I. First, as shown in FIG. 1A, after drilling, plating a first metal layer 11 and a plug hole on a substrate 10, a portion of the first metal layer 11 is removed by a photolithography technique to expose Part of the substrate 10. Further, as shown in FIG. 1B, the substrate 10 exposed to the first metal layer 11 is removed by laser etching or stamping to form a plurality of openings 101. Further, as shown in FIG. 1C, the processed substrate 10 is placed and fixed on a carrier 12 such as an adhesive tape, and the electronic components 131 and 132 are aligned with the corresponding opening 101 to be fixed to the carrier 12. Further, as shown in FIG. 1D, the substrate 10, the first metal layer 11, and the electronic components 131 and 132 are filled and fixed by a dielectric material 14, and a second surface 141 is formed on the first surface 141 of the dielectric material 14. Metal layer 15. As further shown in FIG. 1E, since the dielectric material 14 described above has fixed the substrate 10, the first metal layer 11, and the electronic components 131, 132, the carrier 12 can be removed and the second metal layer 15 is opposite to the other. The side is also filled with a dielectric material 14 and a third metal layer 16 is formed on the second surface 142 of the dielectric material 14.

Further, as shown in FIG. 1F, a portion of the second metal layer 15, a portion of the dielectric material 14, and a portion of the third metal layer 16 are removed by laser etching to form holes H1 to H13, respectively. Further, as shown in FIG. 1G, the metal is plated in the holes H1 to H13 to be filled, so that the corresponding first metal layer 11, second metal layer 15, and third metal layer 16 are electrically connected. Further, as shown in FIG. 1H, a portion of the second metal layer 15 and the third metal layer 16 are removed by a photolithography technique. Finally, as shown in FIG. 1I, a solder resist layer 17 is formed on the second metal layer 15 and the third metal layer 16 at appropriate positions, so that an embedded package structure 1 is completed.

The above-described embedded package structure 1 has the following technical defects. First, the distance from the center of the electronic components 131 and 132 to the second metal layer 15 and the third metal layer 16 is the same. In other words, the embedded package structure 1 has a symmetrical structure, and must be as shown in FIG. 1D and 1E. As shown in the figure, performing a double-sided layering process will result in a decrease in yield.

Second, as shown in the above FIG. 1F, since the bottom metal layer (UBM) of the electronic component must be subjected to a laser etching process, the thickness thereof usually needs to be 1 Millimeter to withstand the damage suffered by the process. In addition, as shown in the above FIG. 1G, it is a blind via plating process, and because of this process, the ball metal layer (UBM) of the electronic component must be limited to copper metal, resulting in insufficient design flexibility.

In view of the above, it is an object of the present invention to provide a method of fabricating an embedded package structure such that a wafer having a different ball-bottom metal layer (UBM) can be applied.

In addition, another object of the present invention is to provide a method for fabricating an embedded package structure, which can make the design more flexible without limiting the thickness of the metal layer of the ball bottom.

Furthermore, it is still another object of the present invention to provide a method of fabricating an embedded package structure that can reduce manufacturing time.

To achieve the above object, the present invention provides a method of fabricating an embedded package structure comprising the following steps. Step S01 forms a first conductive pattern layer on a carrier. Step S02 is to form a first conductive pillar layer on the first conductive pattern layer, and expose a portion of the first conductive pattern layer. Step S03 forms a conductive bonding layer on the exposed first conductive pattern layer. Step S04 connects an electronic component to the conductive bonding layer. Step S05 is to form a first dielectric layer covering the electronic component, the first conductive pillar layer and the first conductive pattern layer, and expose a surface of the first conductive pillar layer. Step S06 is to form a second conductive pattern layer on the first dielectric layer and the first conductive pillar layer. Step S07 forms a second conductive pillar layer on the second conductive pattern layer. Step S08 is to form a second dielectric layer covering the first dielectric layer, the second conductive pattern layer and the second conductive pillar layer, and expose a surface of the second conductive pillar layer. Step S09 removes the carrier to form an embedded package structure.

Further, in order to achieve the above object, the present invention provides a method of manufacturing another embedded package structure comprising the following steps. Step S11 forms a first conductive pattern layer on a carrier. Step S12 is to form a first conductive pattern layer of a fixed layer covering portion. In step S13, an electronic component is disposed on the fixed layer, and at least one electrical connection pad is exposed. Step S14 is to form a first conductive pillar layer on the exposed first conductive pattern layer and the electrical connection pad. Step S15 is to form a first dielectric layer to cover the An electronic component, the first conductive pillar layer and the first conductive pattern layer, and exposing a surface of one of the first conductive pillar layers. Step S16 is to form a second conductive pattern layer on the first dielectric layer and the first conductive pillar layer. Step S17 forms a second conductive pillar layer on the second conductive pattern layer. Step S18 is to form a second dielectric layer covering the first dielectric layer, the second conductive pattern layer and the second conductive pillar layer, and expose one surface of the second conductive pillar layer. Step S19 removes the carrier to form an embedded package structure.

According to an embodiment of the invention, at least one of the first conductive pattern layer and the second conductive pattern layer has a thickness of less than 7 micrometers.

According to an embodiment of the invention, a first distance between the electronic component and the first surface of the first dielectric layer, and a fourth surface between the electronic component and the fourth surface of the second dielectric layer The second distance, the first distance being different from the second distance.

As described above, the process of the embedded package structure according to the present invention is manufactured by lamination, which eliminates the need for a substrate and eliminates the need for time-consuming processes such as laser etching to embed electronic components in the substrate. An embedded package structure can be manufactured. Since the laser etching process is discarded, the selection of the electronic components will not be more limited by the thickness of the metal layer of the ball bottom.

1, 2, 3‧‧‧ embedded package structure

10‧‧‧Substrate

101‧‧‧ opening

11‧‧‧First metal layer

12‧‧‧ Carrier

131, 132‧‧‧ Electronic components

14‧‧‧ dielectric materials

141, 251, 351‧‧‧ first surface

142, 252, 352‧‧‧ second surface

15‧‧‧Second metal layer

16‧‧‧ Third metal layer

17‧‧‧ solder mask

20, 30‧‧‧ carrier board

21, 31‧‧‧ first conductive pattern layer

211, 221, 261, 271, 311, 321, 361, 371 ‧ ‧ surface

22, 32‧‧‧ first conductive column

23‧‧‧Electrical bonding layer

24, 24A, 34‧‧‧ Electronic components

241, 341‧‧‧ electrical connection pads

241A‧‧‧ copper stud bump

25, 35‧‧‧ first dielectric layer

26, 36‧‧‧Second conductive pattern layer

27, 37‧‧‧Second conductive column

28, 38‧‧‧Second dielectric layer

281, 381‧‧‧ third surface

282, 382‧‧‧ fourth surface

33‧‧‧Fixed layer

D01, D11‧‧‧ first distance

D02, D12‧‧‧Second distance

H1~H13‧‧‧ hole

1A to 1I are schematic views showing a manufacturing procedure of a conventional embedded package structure.

2 is a schematic view showing one of the embedded package structures according to the first embodiment of the present invention.

Fig. 3 is a view showing another aspect of the electronic component of the first embodiment.

Figure 4 is a schematic view showing one of the embedded package structures according to the second embodiment of the present invention.

Fig. 5 is a flow chart showing a method of manufacturing the embedded package structure of the first embodiment of the present invention.

6A to 6I are views showing a manufacturing procedure of the embedded package structure according to the first embodiment of the present invention.

Fig. 7 is a flow chart showing a method of manufacturing the embedded package structure of the second embodiment of the present invention.

8A to 8I are views showing a manufacturing procedure of the embedded package structure of the second embodiment of the present invention.

The present invention is not limited by the embodiment, and the embodiment of the present invention is not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that, in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the components in the drawings are merely for ease of understanding and are not intended to limit the actual ratio. In the following embodiments, the same elements will be described with the same element symbols.

Referring to FIG. 2, it is a schematic diagram of an embedded package structure 2 according to a first embodiment of the present invention. The embedded package structure 2 includes a first conductive pattern layer 21, a first conductive pillar layer 22, a conductive bonding layer 23, an electronic component 24, a first dielectric layer 25, and a second conductive pattern layer 26. A second conductive pillar layer 27 and a second dielectric layer 28.

The material of the first dielectric layer 25 may include a Novolac-Based Resin, an Epoxy-Based Resin, and a Silicone-Based Resin having a first surface. 251 and a second surface 252.

The first conductive pattern layer 21 is disposed in the first dielectric layer 25, and one surface 211 of the first conductive pattern layer 21 is exposed to the first surface 251 of the first dielectric layer 25 and exposed to the first dielectric The first conductive pattern layer 21 of the first surface 251 of the layer 25 is substantially the same plane as the first surface 251 of the first dielectric layer 25. The material of the first conductive pattern layer 21 is a metal, such as but not limited to copper, which may be formed by electroplating, sputtering or evaporation, so the thickness thereof may be less than 1 mm (mm), preferably, the first The thickness of a conductive pattern layer 21 is less than 7 micrometers (um). In this embodiment, the first conductive pattern layer 21 may include a conductive line and an electrical connection pad.

The first conductive pillar layer 22 is disposed in the first dielectric layer 25, and the first A conductive pattern layer 21 is electrically connected. One surface 221 of the first conductive pillar layer 22 is exposed on the second surface 252 of the first dielectric layer 25 and exposed to the first conductive pillar layer 22 of the second surface 252 of the first dielectric layer 25, substantially The second surface 252 of the first dielectric layer 25 is in the same plane. The first conductive pillar layer 22 may be formed by plating, sputtering or vapor deposition, and the material thereof is metal, such as but not limited to copper.

The electronic component 24 is disposed in the first dielectric layer 25 and has a plurality of electrical connection pads 241 disposed toward the first conductive pattern layer 21 of the portion, and corresponding to the first layer by the conductive bonding layer 23 The conductive pattern layer 21 is electrically connected. The material of the electrical connection pad 241 is, for example but not limited to, copper (Cu), titanium tungsten copper (TiWCu) aluminum (Al) or other metal electrical connection pads. In this embodiment, the electronic component 24 can be an active component or a passive component, which is not limited herein. The so-called active components are, for example but not limited to, a chip, a die, or an integrated circuit (IC). The so-called passive components are for example but not limited to capacitors or resistors. In addition, the conductive bonding layer 23 is, for example but not limited to, a solder paste, a solder ball, or a gold bump or the like for electrically connecting. In the case of a solder paste, it is formed on the first conductive pattern layer 21 by, for example, printing, solder paste or solder paste.

The material of the second dielectric layer 28 may include a Novolac-Based Resin, an Epoxy-Based Resin, and a Silicone-Based Resin, which have a relative third. Surface 281 and a fourth surface 282.

The second conductive pattern layer 26 is disposed in the second dielectric layer 28 , and one surface 261 of the second conductive pattern layer 26 is exposed on the third surface 281 of the second dielectric layer 28 . The second conductive pattern layer 26 is electrically connected to the first conductive pillar layer 22 exposed on the second surface 252 of the first dielectric layer 25. The second conductive pattern layer 26 exposed to the third surface 281 of the second dielectric layer 28 is substantially flush with the third surface 281 of the second dielectric layer 28. The material of the second conductive pattern layer 26 is a metal, such as but not limited to copper, which may be formed by electroplating, sputtering or vapor deposition, so the thickness thereof may be less than 1 mm (mm), preferably, the first The thickness of the second conductive pattern layer 26 is less than 7 micrometers (um).

The second conductive pillar layer 27 is disposed in the second dielectric layer 28, and The two conductive pattern layers 26 are electrically connected, and one surface 271 of the second conductive pillar layer 27 is exposed on the fourth surface 282 of the second dielectric layer 28. The second conductive pillar layer 27 exposed to the fourth surface 282 of the second dielectric layer 28 is substantially flush with the fourth surface 282 of the second dielectric layer 28. The second conductive pillar layer 27 can be formed by plating, sputtering or vapor deposition, and the material thereof is metal, such as but not limited to copper.

In addition, it is worth mentioning that the electronic component 24 has a first distance D01 between the first surface 251 of the first dielectric layer 25 and the fourth surface 282 of the electronic component 24 and the second dielectric layer 28. There is a second distance D02. In this embodiment, the first distance D01 is different from the second distance D02. In other words, the embedded package structure is an asymmetric structure from the lateral view, and thus the distance between the electrical connection pads 241 of the electronic component 24 and the first conductive pattern layer 21 is shorter, and the electrons can be shortened. Passing the path, which in turn increases its electrical performance.

Referring again to Fig. 3, it shows another aspect of the electronic component of the first embodiment. In this embodiment, the electronic component 24A can be a Cu post die/Cu-pillar die having a plurality of copper pillar bumps 241A as electrical connection pads to effectively shorten the solder balls. Or the spacing between the solder pastes, and the number of pins of the electronic component 24A can be increased.

Hereinafter, please refer to FIG. 4 for explaining the embedded package structure 3 of the second embodiment of the present invention.

The embedded package structure 3 includes a first conductive pattern layer 31, a first conductive pillar layer 32, a fixed layer 33, an electronic component 34, a first dielectric layer 35, a second conductive pattern layer 36, and a first conductive layer 32. The second conductive pillar layer 37 and a second dielectric layer 38.

The material of the first dielectric layer 35 may include a phenolic resin, an epoxy resin, a ruthenium-based resin having a first surface 351 and a second surface 352.

The first conductive pattern layer 31 is disposed in the first dielectric layer 35, and one surface 311 of the first conductive pattern layer 31 is exposed to the first surface 351 of the first dielectric layer 35 and exposed to the first dielectric The first conductive pattern layer 31 of the first surface 351 of the layer 35 is substantially the same plane as the first surface 351 of the first dielectric layer 35. The material of the first conductive pattern layer 31 is a metal, such as but not limited to copper, which can be formed by electroplating, sputtering or evaporation, so that the thickness can be less than 1 mm (mm). Preferably, the thickness of the first conductive pattern layer 31 is less than 7 micrometers (um). In the embodiment, the first conductive pattern layer 31 may include a conductive line and an electrical connection pad.

The first conductive pillar layer 32 is disposed in the first dielectric layer 35 and electrically connected to the first conductive pattern layer 31. One surface 321 of the first conductive pillar layer 32 is exposed on the second surface 352 of the first dielectric layer 35, and is exposed to the first conductive pillar layer 32 of the second surface 352 of the first dielectric layer 35, substantially The second surface 352 of the first dielectric layer 35 is in the same plane. The first conductive pillar layer 32 may be formed by plating, sputtering or vapor deposition, and the material thereof is metal, such as but not limited to copper.

The electronic component 34 is disposed in the first dielectric layer 35 and has a plurality of electrical connection pads 341 disposed toward the other side of the first conductive pattern layer 31. The electronic component 34 is connected to the corresponding first conductive pattern layer 31 by the pinned layer 33. The pinned layer 33 is, for example but not limited to, a glue or a bonding film. It is worth mentioning that a portion of the first conductive pillar layer 32 is electrically connected to the electrical connection pad 341.

The material of the electrical connection pad 341 of the electronic component 34 is, for example but not limited to, copper, titanium tungsten copper, aluminum or other metal electrical connection pads. In this embodiment, the electronic component 34 can be an active component and/or a passive component, which is not limited herein. So-called active components such as, but not limited to, wafers, dies or integrated circuits. The so-called passive components are for example but not limited to capacitors or resistors.

The material of the second dielectric layer 38 may include a phenolic resin, an epoxy resin, a ruthenium-based resin having a third surface 381 and a fourth surface 382 opposite to each other.

The second conductive pattern layer 36 is disposed in the second dielectric layer 38 , and one surface 361 of the second conductive pattern layer 36 is exposed on the third surface 381 of the second dielectric layer 38 . The second conductive pattern layer 36 is electrically connected to the first conductive pillar layer 32 exposed on the second surface 352 of the first dielectric layer 35 . The second conductive pattern layer 36 exposed to the third surface 381 of the second dielectric layer 38 is substantially flush with the third surface 381 of the second dielectric layer 38. The material of the second conductive pattern layer 36 is a metal, such as but not limited to copper, which can be formed by electroplating, sputtering or evaporation, so the thickness can be less than 1 mm (mm), preferably, the first The thickness of the two conductive pattern layers 36 is less than 7 micrometers (um).

The second conductive pillar layer 37 is disposed in the second dielectric layer 38 and electrically connected to the second conductive pattern layer 36, and one surface 371 of the second conductive pillar layer 37 is exposed to the second dielectric layer 38. Fourth surface 382. The second conductive pillar layer 37 exposed to the fourth surface 382 of the second dielectric layer 38 is substantially flush with the fourth surface 382 of the second dielectric layer 38. The second conductive pillar layer 37 may be formed by plating, sputtering or vapor deposition, and the material thereof is metal, such as but not limited to copper.

In addition, as in the first embodiment, the electronic component 34 has a first distance D11 between the first surface 351 of the first dielectric layer 35 and the fourth surface 382 of the electronic component 34 and the second dielectric layer 38. There is a second distance D12 between them. In the embodiment, the first distance D11 is different from the second distance D12. In other words, the embedded package structure 3 is an asymmetric structure from the lateral view, and thus the distance between the electrical connection pads 341 of the electronic component 34 and the first conductive pattern layer 31 is shorter, and can be shortened. The electron transfer path, in turn, increases its electrical performance.

Referring to FIG. 5, it is a flowchart of a manufacturing method of the embedded package structure 2 according to the first embodiment of the present invention, which includes steps S01 to S09. Hereinafter, please refer to FIGS. 6A to 6I to explain the manufacturing method of the embedded package structure 2.

In step S01, as shown in FIG. 6A, a first conductive pattern layer 21 is formed on a carrier 20. The carrier 20 is a metal carrier such as, but not limited to, stainless steel copper. The first conductive pattern layer 21 can be formed on the carrier 20 by techniques such as electroplating, sputtering, evaporation, or a lithography process.

Step S02, as shown in FIG. 6B, a first conductive pillar layer 22 is formed on the first conductive pattern layer 21. The first conductive pillar layer 22 does not completely cover the first conductive pattern layer 21, that is, a part of the first conductive pattern layer 21 is exposed. The first conductive pillar layer 22 can be formed on the first conductive pattern layer 21 by a technique such as electroplating, sputtering, evaporation, or a lithography process.

Step S03, as shown in FIG. 6C, a conductive bonding layer 23 is formed on the exposed first conductive pattern layer 21. The conductive bonding layer 23 is, for example but not limited to, a solder paste, a solder ball, or a gold bump or the like for electrically connecting. In the case of a solder paste, it is formed on the first conductive pattern layer 21 by, for example, printing, solder paste or solder paste.

Step S04, as shown in FIG. 6D, an electronic component 24 and a conductive junction The layer 23 is connected. The electrical bonding layer 23 electrically connects the electrical connection pads 241 of the electronic component 24 to the first conductive pattern layer 21 by using a reflow process.

Step S05, as shown in FIG. 6E, a first dielectric layer 25 is formed to cover the electronic component 24, the first conductive pillar layer 22 and the first conductive pattern layer 21, and is polished to expose one of the first conductive pillar layers 22. Surface 221.

Step S06, as shown in FIG. 6F, a second conductive pattern layer 26 is formed on the first dielectric layer 25 and the first conductive pillar layer 22. The second conductive pattern layer 26 can be formed on the first dielectric layer 25 and the first conductive pillar layer 22 by techniques such as electroplating, sputtering, evaporation, or a lithography process.

Step S07, as shown in FIG. 6G, a second conductive pillar layer 27 is formed on the second conductive pattern layer 26. The second conductive pillar layer 27 can be formed on the second conductive pattern layer 26 by a technique such as electroplating, sputtering, evaporation, or a lithography process.

Step S08, as shown in FIG. 6H, forming a second dielectric layer 28 covering the first dielectric layer 25, the second conductive pattern layer 26, and the second conductive pillar layer 27, and exposing the second conductive pillar after the polishing process One surface 271 of layer 27.

In step S09, as shown in FIG. 6H and FIG. 6I, the carrier 20 is removed and flipped 180 degrees to form an embedded package structure 2. The carrier 20 can be removed, for example, but not limited to, by an etching process, a debonding process, or a polishing process.

Referring to FIG. 7, a flow chart of a method for manufacturing the embedded package structure 3 of the second embodiment of the present invention includes steps S11 to S19. Hereinafter, please refer to FIGS. 8A to 8I to illustrate a method of manufacturing the embedded package structure 3.

Step S11, as shown in FIG. 8A, a first conductive pattern layer 31 is formed on a carrier 30. The carrier 30 is a metal carrier such as, but not limited to, stainless steel copper. The first conductive pattern layer 31 can be formed on the carrier 30 by plating, sputtering, evaporation, or a lithography process.

Step S12, as shown in FIG. 8B, a first conductive pattern layer 31 covering a portion of the fixed layer 33 is formed. The pinned layer 33 is formed, for example but not limited to, a bonding glue or a bonding film, which may be formed on the first conductive pattern layer 31 by a coating process or a dispensing process.

Step S13, as shown in FIG. 8C, an electronic component 34 is disposed on the solid The layer 33 is fixed and at least one electrical connection pad 341 is exposed. In the present embodiment, the electronic component 34 is fixed on the carrier 30 by the adhesiveness of the fixing layer 33.

Step S14, as shown in FIG. 8D, a first conductive pillar layer 32 is formed on the exposed first conductive pattern layer 31 and the electrical connection pad 341. The first conductive pillar layer 32 can be formed on the first conductive pattern layer 31 and the electrical connection pad 341 by using techniques such as electroplating, sputtering, evaporation, or a lithography process.

Step S15, as shown in FIG. 8E, a first dielectric layer 35 is formed to cover the electronic component 34, the first conductive pillar layer 32 and the first conductive pattern layer 31, and is polished to expose one of the first conductive pillar layers 32. Surface 321.

Step S16, as shown in FIG. 8F, a second conductive pattern layer 36 is formed on the first dielectric layer 35 and the first conductive pillar layer 32. The second conductive pattern layer 36 can be formed on the first dielectric layer 35 and the first conductive pillar layer 32 by techniques such as electroplating, sputtering, evaporation, or a lithography process.

Step S17, as shown in FIG. 8G, a second conductive pillar layer 37 is formed on the second conductive pattern layer 36. The second conductive pillar layer 37 can be formed on the second conductive pattern layer 36 by a technique such as electroplating, sputtering, evaporation, or a lithography process.

Step S18, as shown in FIG. 8H, a second dielectric layer 38 is formed to cover the first dielectric layer 35, the second conductive pattern layer 36, and the second conductive pillar layer 37, and is polished to expose the second conductive pillar layer. One of the surfaces 371 of 37.

Step S19, as shown in FIG. 8H and FIG. 8I, the carrier 30 is removed and flipped 180 degrees to form an embedded package structure 3. The carrier 30 can be removed, for example, but not limited to, by an etching process, a lift process, or a polishing process.

In summary, the manufacturing method of the embedded package structure according to the present invention is manufactured by lamination, which does not require the use of a substrate, and does not require a time-consuming process such as laser etching to embed the electronic component in the substrate. , the embedded package structure can be manufactured. Since the laser etching process is discarded, the selection of the electronic components will not be more limited by the thickness of the metal layer of the ball bottom. In addition, since the embedded package structure of the present invention is asymmetric from the side view, that is, the distance between the electronic component and the first conductive pattern layer is short, the electron transfer path can be shortened, thereby increasing the power thereof. Sexual effectiveness.

The invention complies with the requirements of the invention patent, and proposes a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Any person who is familiar with the skill of the case, equivalent modifications or changes made in accordance with the spirit of the invention shall be included in the scope of the following patent application.

2‧‧‧ embedded package structure

21‧‧‧First conductive pattern layer

211, 221, 261, 271‧‧‧ surface

22‧‧‧First conductive column

23‧‧‧Electrical bonding layer

24‧‧‧Electronic components

241‧‧‧Electrical connection pads

25‧‧‧First dielectric layer

251‧‧‧ first surface

252‧‧‧ second surface

26‧‧‧Second conductive pattern layer

27‧‧‧Second conductive column

28‧‧‧Second dielectric layer

281‧‧‧ third surface

282‧‧‧ fourth surface

D01‧‧‧First distance

D02‧‧‧Second distance

Claims (8)

A method for manufacturing an embedded package structure includes: forming a first conductive pattern layer on a carrier; forming a first conductive pillar layer on the first conductive pattern layer, and exposing a portion of the first conductive pattern Forming a conductive bonding layer on the exposed first conductive pattern layer; connecting an electronic component to the conductive bonding layer; forming a first dielectric layer covering the electronic component, the first conductive pillar layer, and the first Conducting a pattern layer and exposing a surface of the first conductive pillar layer; forming a second conductive pattern layer on the first dielectric layer and the first conductive pillar layer; forming a second conductive pillar layer in the second Forming a second dielectric layer covering the first dielectric layer, the second conductive pattern layer and the second conductive pillar layer, and exposing a surface of the second conductive pillar layer; and removing the Carrier board. The method of manufacturing the embedded package structure of claim 1, wherein the first conductive pattern layer, the first conductive pillar layer, the second conductive pattern layer, and the second conductive pillar layer are plated or sputtered. Formed by evaporation or lithography. The method of fabricating an embedded package structure according to claim 1, wherein at least one of the first conductive pattern layer and the second conductive pattern layer has a thickness of less than 7 micrometers. The method of manufacturing an embedded package structure according to claim 1, wherein the carrier is a metal carrier. A manufacturing method of an embedded package structure includes: forming a first conductive pattern layer on a carrier; forming a first conductive pattern layer of a fixed layer covering portion; and disposing an electronic component on the fixed layer, and Exposing at least one electrical connection pad; forming a first conductive pillar layer on the exposed first conductive pattern layer and the electrical connection pad; forming a first dielectric layer covering the electronic component, the first conductive pillar layer and The first conductive pattern layer and exposing a surface of the first conductive pillar layer; Forming a second conductive pattern layer on the first dielectric layer and the first conductive pillar layer; forming a second conductive pillar layer on the second conductive pattern layer; forming a second dielectric layer covering the first a dielectric layer, the second conductive pattern layer and the second conductive pillar layer, and exposing a surface of the second conductive pillar layer; and removing the carrier. The method of manufacturing the embedded package structure of claim 5, wherein the first conductive pattern layer, the first conductive pillar layer, the second conductive pattern layer, and the second conductive pillar layer are plated or sputtered. Formed by evaporation or lithography. The method of fabricating an embedded package structure according to claim 5, wherein at least one of the first conductive pattern layer and the second conductive pattern layer has a thickness of less than 7 micrometers. The method of manufacturing an embedded package structure according to claim 5, wherein the carrier is a metal carrier.