TWI581409B - Solid-state imaging device, method of producing the same, and imaging device - Google Patents
Solid-state imaging device, method of producing the same, and imaging device Download PDFInfo
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- TWI581409B TWI581409B TW102111569A TW102111569A TWI581409B TW I581409 B TWI581409 B TW I581409B TW 102111569 A TW102111569 A TW 102111569A TW 102111569 A TW102111569 A TW 102111569A TW I581409 B TWI581409 B TW I581409B
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- Prior art keywords
- film
- imaging device
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- 238000003384 imaging method Methods 0.000 title claims description 209
- 238000000034 method Methods 0.000 title description 45
- 230000000903 blocking effect Effects 0.000 claims description 153
- 238000009792 diffusion process Methods 0.000 claims description 126
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 89
- 239000000758 substrate Substances 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 59
- 238000009834 vaporization Methods 0.000 claims description 27
- 230000008016 vaporization Effects 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 23
- 239000013078 crystal Substances 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 239000010408 film Substances 0.000 description 589
- 238000004519 manufacturing process Methods 0.000 description 124
- 238000006243 chemical reaction Methods 0.000 description 123
- 230000002093 peripheral effect Effects 0.000 description 121
- 238000005468 ion implantation Methods 0.000 description 115
- 239000010410 layer Substances 0.000 description 110
- 238000002955 isolation Methods 0.000 description 107
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 85
- 238000005530 etching Methods 0.000 description 58
- 229910000449 hafnium oxide Inorganic materials 0.000 description 39
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 39
- 230000015572 biosynthetic process Effects 0.000 description 35
- 230000000694 effects Effects 0.000 description 21
- 241000894007 species Species 0.000 description 21
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 229910052796 boron Inorganic materials 0.000 description 18
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 17
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 15
- 229910052785 arsenic Inorganic materials 0.000 description 15
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 15
- 238000000151 deposition Methods 0.000 description 15
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 15
- 229910052698 phosphorus Inorganic materials 0.000 description 15
- 239000011574 phosphorus Substances 0.000 description 15
- 229910052732 germanium Inorganic materials 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 14
- 238000000137 annealing Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 10
- 238000004151 rapid thermal annealing Methods 0.000 description 10
- 238000001039 wet etching Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 9
- 239000007787 solid Substances 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 230000004913 activation Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000002513 implantation Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000007943 implant Substances 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 7
- 229910001936 tantalum oxide Inorganic materials 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 230000003595 spectral effect Effects 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- 241000519995 Stachys sylvatica Species 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000000593 degrading effect Effects 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 150000002815 nickel Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000000638 solvent extraction Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 238000004780 2D liquid chromatography Methods 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- IAOQICOCWPKKMH-UHFFFAOYSA-N dithieno[3,2-a:3',2'-d]thiophene Chemical compound C1=CSC2=C1C(C=CS1)=C1S2 IAOQICOCWPKKMH-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- MWRJCEDXZKNABM-UHFFFAOYSA-N germanium tungsten Chemical compound [Ge].[W] MWRJCEDXZKNABM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- QVLTXCYWHPZMCA-UHFFFAOYSA-N po4-po4 Chemical compound OP(O)(O)=O.OP(O)(O)=O QVLTXCYWHPZMCA-UHFFFAOYSA-N 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 150000004772 tellurides Chemical group 0.000 description 1
- SITVSCPRJNYAGV-UHFFFAOYSA-L tellurite Chemical compound [O-][Te]([O-])=O SITVSCPRJNYAGV-UHFFFAOYSA-L 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
本發明係關於一種固態成像裝置、一種製造該固態成像裝置之方法及一種成像裝置。 The present invention relates to a solid-state imaging device, a method of manufacturing the same, and an imaging device.
已揭示一種製造一固態成像裝置之方法，其中在該固態成像裝置之MOS電晶體之閘極電極上形成一具有一三層式結構之側壁，在該固態成像裝置之一感測器部分上形成一係相同於具有該三層式結構之該側壁之膜之膜(下稱「側壁膜」)以使用該側壁膜作為一用於防止一矽化物形成於該感測器部分上之矽化物阻斷物(參見，例如，第WO2003/096421號PCT國際專利申請公開案(文獻'421)之國內再版(特定而言，圖64及與其相關之說明))。 A method of manufacturing a solid-state imaging device in which a sidewall having a three-layer structure is formed on a gate electrode of a MOS transistor of the solid-state imaging device, and a sensor portion is formed on one of the solid-state imaging devices a film similar to the film having the sidewall of the three-layer structure (hereinafter referred to as "sidewall film") to use the sidewall film as a germanium resist for preventing a germanide from being formed on the sensor portion Broken matter (see, for example, domestic reprint of PCT International Patent Application Publication No. WO2003/096421 (Document '421) (specifically, Figure 64 and its associated description)).
然而，根據文獻'421中所述之方法，為了形成該等MOS電晶體之源極-汲極區，經由具有該三層式結構之該側壁膜來實施用於形成該等源極-汲極區之離子植入。因此，一直難以在抑制寄生電阻的同時改善短通道效應。此外，在一其中該等源極-汲極區由具有該三層式結構之側壁膜完全覆蓋之狀態下退火該等源極-汲極區，且因此因該側壁膜而引起之應力增大(應力記憶技術(SMT)，參見，例如，K.Ota等人，「Novel Locally Strained Channel Technique for High Performance 55 nm CMOS(用於高效能55 nm CMOS之新穎局部應變通 道技術)」IEDM Tech.Dig.,pp.27-30,2002)。此外，假定必需使用於形成一邏輯部分中之MOS電晶體之源極-汲極區之離子植入之條件不同於用於形成像素部分中之MOS電晶體之源極-汲極區之離子植入之條件。此理由在於針對該像素部分中之MOS電晶體之離子植入係經由側壁膜實施，而針對該邏輯部分中之MOS電晶體之離子植入係在沒有此一膜之情況下實施。因而，該邏輯部分中之該等MOS電晶體中之每一者之一雜質擴散層之深度不同於該像素部分中之該等MOS電晶體中之每一者之一雜質擴散層之深度。該邏輯部分中之該等MOS電晶體之閘極長度短於該像素部分中之該等MOS電晶體之閘極長度。相應地，難以在抑制接面洩漏的同時改善短通道效應，並同時抑制寄生電阻之增大。當然，用於形成該邏輯部分中之該等MOS電晶體之源極-汲極區之離子植入與用於形成該像素部分中之該等MOS電晶體之源極-汲極區之離子植入分開實施，但此並未闡述於文獻'421中。 However, according to the method described in the '421, in order to form the source-drain regions of the MOS transistors, the formation of the source-drain electrodes is performed via the sidewall film having the three-layer structure. Ion implantation in the area. Therefore, it has been difficult to improve the short channel effect while suppressing the parasitic resistance. Further, in the state in which the source-drain regions are completely covered by the sidewall film having the three-layer structure, the source-drain regions are annealed, and thus the stress caused by the sidewall film is increased. (Stress Memory Technology (SMT), see, for example, K. Ota et al., "Novel Locally Strained Channel Technique for High Performance 55 nm CMOS (for high-performance 55 nm CMOS novel local strain pass) Road Technology)" IEDM Tech. Dig., pp. 27-30, 2002). Further, it is assumed that the ion implantation conditions necessary for forming the source-drain region of the MOS transistor in a logic portion are different from the ion implantation for forming the source-drain region of the MOS transistor in the pixel portion. Into the conditions. The reason for this is that ion implantation for the MOS transistor in the pixel portion is performed via the sidewall film, and ion implantation for the MOS transistor in the logic portion is performed without such a film. Thus, the depth of one of the impurity diffusion layers of each of the MOS transistors in the logic portion is different from the depth of one of the impurity diffusion layers of each of the MOS transistors in the pixel portion. The gate length of the MOS transistors in the logic portion is shorter than the gate length of the MOS transistors in the pixel portion. Accordingly, it is difficult to improve the short-channel effect while suppressing the junction leakage while suppressing the increase in the parasitic resistance. Of course, ion implantation for forming the source-drain regions of the MOS transistors in the logic portion and ion implantation for forming the source-drain regions of the MOS transistors in the pixel portion The implementation is separate, but this is not stated in the literature '421.
此外，當在一其中提供一完全覆蓋閘極電極之覆蓋膜之狀態下退火該等源極-汲極區時，一拉伸應力施加至該覆蓋膜(SMT)。此膜應力可在一感測器部分之一矽層中產生晶體瑕疵，此可導致隨機雜訊之增大以及白疵點數及暗電流之增大。 Further, when the source-drain regions are annealed in a state in which a cover film completely covering the gate electrodes is provided, a tensile stress is applied to the cover film (SMT). This film stress can create crystal defects in one of the layers of the sensor portion, which can result in an increase in random noise and an increase in chalk points and dark current.
如上文所述，用於形成該等源極-汲極區之離子植入係經由該側壁膜實施。相應地，難以將一雜質擴散層之深度設定至一所期望值同時在矽(Si)表面處維持一高離子濃度。因而，該等源極-汲極區之寄生電阻增大，從而減小一像素電晶體之一驅動力。 As described above, ion implantation for forming the source-drain regions is performed via the sidewall film. Accordingly, it is difficult to set the depth of an impurity diffusion layer to a desired value while maintaining a high ion concentration at the cerium (Si) surface. Thus, the parasitic resistance of the source-drain regions is increased, thereby reducing one of the driving forces of a pixel transistor.
亦已揭示一種製造方法，其中不使用上述側壁膜作為一矽化物阻斷膜而是單獨地提供用於矽化物阻斷之另一膜(參見，例如，第2008-85104號日本未經審查的專利申請公開案)。在此製造方法中，一矽基板容易因對一用於在閘極電極之每一側壁上形成一側壁之側壁膜之回蝕刻而受損。此導致暗電流增大之問題。此外，在此方法中， 在實施用於形成源極-汲極區之離子植入之前移除一設置於一光電二極體上之氧化物膜。相應地，一抗蝕劑遮罩直接形成於該光電二極體上。因而，該光電二極體被該抗蝕刻劑污染，從而增大暗電流。此外，一表面積中之一P型雜質因對該光電二極體所實施之濕蝕刻而被丟失。由此，增大暗電流。在用於移除光電二極體上之氧化物膜之濕蝕刻期間，增大藉由該蝕刻所移除之一邏輯部分中之一隔離區(淺溝槽隔離(STI))之一上部分的大小。相應地，當一矽化物形成於邏輯區中之隔離區之一邊緣處之源極-汲極區上時，增大因矽化物而引起之接面洩漏。當移除光電二極體上之氧化物膜時，舉離側壁膜之一部分之問題變得嚴重。由此，降低良率。 A manufacturing method has also been disclosed in which the above-mentioned side wall film is not used as a telluride blocking film, but another film for telluride blocking is separately provided (see, for example, Japanese Unexamined Patent No. 2008-85104) Patent application publication). In this manufacturing method, a substrate is easily damaged by etch back of a sidewall film for forming a sidewall on each sidewall of the gate electrode. This causes a problem of an increase in dark current. Also, in this method, An oxide film disposed on a photodiode is removed prior to performing ion implantation for forming the source-drain region. Accordingly, a resist mask is directly formed on the photodiode. Thus, the photodiode is contaminated by the etchant to increase dark current. In addition, one of the surface areas of the P-type impurity is lost due to the wet etching performed on the photodiode. Thereby, the dark current is increased. During the wet etching for removing the oxide film on the photodiode, one of the isolation regions (shallow trench isolation (STI)) in one of the logic portions removed by the etching is increased the size of. Accordingly, when a germanide is formed on the source-drain region at one of the edges of the isolation region in the logic region, the junction leakage due to the germanide is increased. When the oxide film on the photodiode is removed, the problem of lifting a part of the sidewall film becomes serious. Thereby, the yield is lowered.
在一固態成像裝置之一MOS電晶體中，當一具有一兩層式結構之側壁形成於一閘極電極之每一側壁上時，該閘極電極形成於一矽基板上，而一閘極絕緣膜位於其之間。接著，在該矽基板上形成一覆蓋該閘極電極之氧化矽膜。此外，在該氧化矽膜上形成氧化矽膜。接下來，對該氮化矽膜之整個表面實施回蝕刻以使該氮化矽膜繼續存在於該閘極電極之側壁上而該氧化矽膜位於其之間。在此回蝕刻中，該氧化矽膜起一蝕刻阻擋件的作用。接下來，蝕刻該氧化矽膜。由此，曝露該閘極電極之上表面，且亦曝露該矽基板。在此步驟中，亦移除形成於該固態成像裝置之一光電二極體上之氧化矽膜。 In a MOS transistor of a solid-state imaging device, when a sidewall having a two-layer structure is formed on each sidewall of a gate electrode, the gate electrode is formed on a germanium substrate, and a gate is formed The insulating film is located between them. Next, a ruthenium oxide film covering the gate electrode is formed on the ruthenium substrate. Further, a ruthenium oxide film is formed on the ruthenium oxide film. Next, the entire surface of the tantalum nitride film is etched back so that the tantalum nitride film continues to exist on the sidewall of the gate electrode with the tantalum oxide film therebetween. In this etch back, the ruthenium oxide film functions as an etch stop. Next, the hafnium oxide film is etched. Thereby, the upper surface of the gate electrode is exposed and the germanium substrate is also exposed. In this step, the hafnium oxide film formed on one of the photodiodes of the solid-state imaging device is also removed.
在上述方法中，因減小像素尺寸及電晶體尺寸，故亦減小該氧化矽層之膜厚度。因此，在對該氮化矽膜之回蝕刻中，難以止擋該蝕刻而不損壞充當一下伏層之矽基板。一般而言，當在蝕刻氮化矽膜中使用氧化矽膜作為一蝕刻止擋時，難以保證一足夠的蝕刻選擇比。 In the above method, the film thickness of the ruthenium oxide layer is also reduced by reducing the pixel size and the transistor size. Therefore, in the etch back of the tantalum nitride film, it is difficult to stop the etching without damaging the germanium substrate serving as the underlying layer. In general, when a ruthenium oxide film is used as an etch stop in etching a tantalum nitride film, it is difficult to ensure a sufficient etching selectivity.
另外，在該氧化矽膜之移除期間，亦藉由該濕蝕刻來移除位於由該氮化矽膜組成之側壁下方之氧化矽膜之一部分。因而，該側壁處於一由一因一後續熱處理或諸如此類而引起之應力舉離之狀態下。處 於此狀態下之側壁可成為一可導致良率降低之污染原因。 In addition, during the removal of the hafnium oxide film, a portion of the hafnium oxide film located under the sidewall composed of the tantalum nitride film is also removed by the wet etching. Thus, the side wall is in a state of stress lift caused by a subsequent heat treatment or the like. At The side wall in this state can be a cause of contamination that can lead to a decrease in yield.
當蝕刻該氧化矽膜時，亦移除位於該固態成像裝置之一光電二極體上之氧化矽膜。接著，實施用於形成一nFET及一pFET之源極及汲極之離子植入。在此種情況下，一用於此離子植入之抗蝕劑遮罩直接形成於該光電二極體上。因此，該光電二極體可由含於該抗蝕刻劑中之鈉(Na)及類似物污染。此等污染物可造成白疵點數增大之問題。 When the hafnium oxide film is etched, the hafnium oxide film on one of the photodiodes of the solid-state imaging device is also removed. Next, ion implantation for forming the source and drain of an nFET and a pFET is performed. In this case, a resist mask for the ion implantation is directly formed on the photodiode. Therefore, the photodiode can be contaminated with sodium (Na) and the like contained in the anti-etching agent. These contaminants can cause an increase in the number of chalk points.
圖95係一CMOS感測器之一佈置圖。如圖95中所示，一光電二極體PD及一連接至該光電二極體PD之作用區15提供於一矽基板上。一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL依序配置於作用區15上。一浮動擴散部分FD提供於該傳送閘TRG與該重設電晶體RST之間。圖96顯示上文所述之平面佈置之一等效電路。在圖96中所示之佈置中，一像素包括一單一光電二極體PD、一浮動擴散部分FD及四個電晶體(亦即，一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL)。此佈置顯示一其中分享複數個光電二極體之結構。另一選擇係，可分享若干光電二極體PD，或一像素可包括三個電晶體而不是該四個電晶體。 Figure 95 is a layout diagram of a CMOS sensor. As shown in FIG. 95, a photodiode PD and an active region 15 connected to the photodiode PD are provided on a substrate. A transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially disposed on the active region 15. A floating diffusion portion FD is provided between the transfer gate TRG and the reset transistor RST. Figure 96 shows an equivalent circuit of the planar arrangement described above. In the arrangement shown in FIG. 96, a pixel includes a single photodiode PD, a floating diffusion portion FD, and four transistors (ie, a transfer gate TRG, a reset transistor RST, and an amplifying transistor). Amp and a selection transistor SEL). This arrangement shows a structure in which a plurality of photodiodes are shared. Alternatively, a plurality of photodiodes PD may be shared, or a pixel may include three transistors instead of the four transistors.
期望減小隨機雜訊、白疵點數及暗電流。 It is desirable to reduce random noise, chalk points and dark current.
根據本發明之一實施例，形成兩個不同的矽化物阻斷膜以彼此部分地重疊於一像素部分中之一MOS電晶體上，從而減小隨機雜訊、白疵點數及暗電流。 In accordance with an embodiment of the present invention, two different telluride blocking films are formed to partially overlap one another in one of the MOS transistors in a pixel portion, thereby reducing random noise, chalk points, and dark current.
一種根據本發明之一實施例之固態成像裝置，其包括：一半導體基板，其包括一具有一經組態以光電轉換入射光以獲得一電信號之光電轉換部分之像素部分及一設置於該像素部分之周邊處之周邊電路部分；一第一側壁，其由一側壁膜組成且設置於該像素部分中之MOS電晶體之閘極電極之每一側壁上；一第二側壁，其由相同於該側壁膜 之膜組成且設置於該周邊電路部分中之MOS電晶體之閘極電極之每一側壁上；一第一矽化物阻斷膜，其由相同於該側壁膜之膜組成且設置於該像素部分中之該光電轉換部分及該等MOS電晶體之一部分上；及一第二矽化物阻斷膜，其設置於該像素部分中之該等MOS電晶體上以與該第一矽化物阻斷膜之一部分重疊，其中該像素部分中之該等MOS電晶體由該第一矽化物阻斷膜及該第二矽化物阻斷膜覆蓋。 A solid-state imaging device according to an embodiment of the present invention, comprising: a semiconductor substrate comprising: a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal; and a pixel portion disposed on the pixel a peripheral portion of the peripheral portion; a first sidewall formed by a sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the pixel portion; a second sidewall, which is the same as The sidewall film a film composition and disposed on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion; a first vaporization blocking film composed of a film identical to the sidewall film and disposed in the pixel portion And a portion of the MOS transistor; and a second vaporization blocking film disposed on the MOS transistors in the pixel portion to interface with the first germanide blocking film A portion of the overlap is performed, wherein the MOS transistors in the pixel portion are covered by the first telluride blocking film and the second germanide blocking film.
在根據本發明之一實施例之固態成像裝置中，該像素部分中之該等MOS電晶體由兩個膜(亦即，由相同於該側壁膜之膜組成之該第一矽化物阻斷膜及由一不同於該第一矽化物阻斷膜之膜組成之該第二矽化物阻斷膜)覆蓋。因此，該像素部分中之該等MOS電晶體不由一單一矽化物阻斷膜完全覆蓋。因而，可減小隨機雜訊，且可減小白疵點數及暗電流。 In a solid-state imaging device according to an embodiment of the present invention, the MOS transistors in the pixel portion are composed of two films (that is, the first vapor blocking film composed of a film identical to the sidewall film) And covering by the second telluride blocking film composed of a film different from the first telluride blocking film. Therefore, the MOS transistors in the pixel portion are not completely covered by a single telluride blocking film. Thus, random noise can be reduced, and white point and dark current can be reduced.
一種根據本發明之一實施例製造一固態成像裝置之方法，其用以在一半導體基板上形成一具有一經組態以光電轉換入射光以獲得一電信號之光電轉換部分之像素部分及一形成於該像素部分之周邊處之周邊電路部分，該方法包括以下步驟：形成一覆蓋該像素部分及該周邊電路部分之側壁膜；形成一由該像素部分中之MOS電晶體之閘極電極之每一側壁上之側壁膜組成之第一側壁、一由該周邊電路部分中之MOS電晶體之閘極電極之每一側壁上之側壁膜組成之第二側壁及一由該像素部分中之該光電轉換部分及該等MOS電晶體之一部分上之側壁膜組成之第一矽化物阻斷膜；及在該像素部分中之該等MOS電晶體上形成一第二矽化物阻斷膜以與該第一矽化物阻斷膜重疊，其中該像素部分中之該等MOS電晶體由該第一矽化物阻斷膜及該第二矽化物阻斷膜覆蓋。 A method of fabricating a solid-state imaging device according to an embodiment of the present invention, for forming a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal, and forming a semiconductor substrate a peripheral circuit portion at a periphery of the pixel portion, the method comprising the steps of: forming a sidewall film covering the pixel portion and the peripheral circuit portion; forming a gate electrode of the MOS transistor in the pixel portion a first sidewall of the sidewall film on a sidewall, a second sidewall formed by a sidewall film on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion, and a photocell in the pixel portion Converting a portion and a first vapor blocking film composed of a sidewall film on a portion of the MOS transistors; and forming a second germanide blocking film on the MOS transistors in the pixel portion to A telluride blocking film overlaps, wherein the MOS transistors in the pixel portion are covered by the first telluride blocking film and the second germanide blocking film.
在根據本發明之一實施例製造一固態成像裝置之方法中，該像素部分中之該等MOS電晶體由兩個膜(亦即，由相同於該側壁膜之膜 組成之該第一矽化物阻斷膜及由一不同於該第一矽化物阻斷膜之膜組成之該第二矽化物阻斷膜)覆蓋。因此，該像素部分中之該等MOS電晶體不由一單一矽化物阻斷膜完全覆蓋。因而，可減小隨機雜訊，且可減小白疵點數及暗電流。 In a method of fabricating a solid-state imaging device according to an embodiment of the present invention, the MOS transistors in the pixel portion are composed of two films (that is, a film identical to the sidewall film) The first telluride blocking film composed of the second telluride blocking film composed of a film different from the first telluride blocking film is covered. Therefore, the MOS transistors in the pixel portion are not completely covered by a single telluride blocking film. Thus, random noise can be reduced, and white point and dark current can be reduced.
一種根據本發明之一實施例之成像裝置包括：一光聚焦光學單元，其經組態以聚焦入射光；一固態成像裝置，其經組態以接收聚焦於該光聚焦光學單元中之光並光電轉換該光；及一信號處理單元，其經組態以處理一由於光電轉換而獲得之信號。在此成像裝置中，該固態成像裝置包括：一半導體基板，其包括一具有一經組態以光電轉換入射光以獲得一電信號之光電轉換部分之像素部分及一設置於該像素部分之周邊處之周邊電路部分；一第一側壁，其由一側壁膜組成且設置於該像素部分中之MOS電晶體之閘極電極之每一側壁上；一第二側壁，其由相同於該側壁膜之膜組成且設置於該周邊電路部分中之MOS電晶體之閘極電極之每一側壁上；一第一矽化物阻斷膜，其由相同於該側壁膜之膜組成且設置於該像素部分中之該光電轉換部分及該等MOS電晶體之一部分上；及一第二矽化物阻斷膜，其設置於該像素部分中之該等MOS電晶體上以與該第一矽化物阻斷膜之一部分重疊，其中該像素部分中之該等MOS電晶體由該第一矽化物阻斷膜及該第二矽化物阻斷膜覆蓋。 An imaging apparatus according to an embodiment of the present invention includes: a light focusing optical unit configured to focus incident light; a solid state imaging device configured to receive light focused in the light focusing optical unit and Photoelectrically converting the light; and a signal processing unit configured to process a signal obtained by photoelectric conversion. In the image forming apparatus, the solid-state imaging device includes: a semiconductor substrate including a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal, and a peripheral portion disposed at the periphery of the pixel portion a peripheral circuit portion; a first sidewall, which is composed of a sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the pixel portion; and a second sidewall which is identical to the sidewall film a film composition and disposed on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion; a first vaporization blocking film composed of a film identical to the sidewall film and disposed in the pixel portion And the second vaporization blocking film disposed on the MOS transistors in the pixel portion to be opposite to the first germanide blocking film A portion overlaps, wherein the MOS transistors in the pixel portion are covered by the first vapor blocking film and the second germanide blocking film.
根據本發明之一實施例之成像裝置包括根據本發明之一實施例之固態成像裝置。相應地，可減小隨機雜訊，且可減小白疵點數及暗電流。 An image forming apparatus according to an embodiment of the present invention includes a solid-state image forming apparatus according to an embodiment of the present invention. Accordingly, random noise can be reduced, and white point and dark current can be reduced.
根據本發明之一實施例之固態成像裝置係有利的，因為可減小隨機雜訊且可減小白疵點數及暗電流。 A solid-state imaging device according to an embodiment of the present invention is advantageous in that random noise can be reduced and white point and dark current can be reduced.
根據本發明之一實施例製造一固態成像裝置之方法係有利的，因為可減小隨機雜訊且可減小白疵點數及暗電流。 A method of fabricating a solid-state imaging device according to an embodiment of the present invention is advantageous because random noise can be reduced and white point and dark current can be reduced.
由於根據本發明之一實施例之成像裝置包括根據本發明之一實施例之固態成像裝置，因此可減小隨機雜訊，且可減小白疵點數及暗電流。因此，可改善影像品質。 Since the image forming apparatus according to an embodiment of the present invention includes the solid-state image forming apparatus according to an embodiment of the present invention, random noise can be reduced, and white point and dark current can be reduced. Therefore, the image quality can be improved.
1‧‧‧固態成像裝置 1‧‧‧Solid imaging device
1A‧‧‧固態成像裝置 1A‧‧‧ Solid-state imaging device
1B‧‧‧固態成像裝置 1B‧‧‧ Solid-state imaging device
11‧‧‧半導體基板 11‧‧‧Semiconductor substrate
12‧‧‧像素部分 12‧‧‧pixel section
13‧‧‧周邊電路部分 13‧‧‧ peripheral circuit section
14‧‧‧第一隔離區 14‧‧‧First isolation area
15‧‧‧第二隔離區 15‧‧‧Second isolation zone
16‧‧‧隔離區 16‧‧‧Isolated area
17‧‧‧像素電晶體部分 17‧‧‧Pixel transistor section
21‧‧‧光電轉換部分 21‧‧‧Photoelectric conversion section
21A‧‧‧光電轉換部分 21A‧‧‧Photoelectric conversion section
21B‧‧‧光電轉換部分 21B‧‧‧Photoelectric conversion section
21C‧‧‧光電轉換部分 21C‧‧‧Photoelectric conversion section
21D‧‧‧光電轉換部分 21D‧‧‧ photoelectric conversion part
23‧‧‧波導 23‧‧‧Band
25‧‧‧聚焦透鏡 25‧‧‧focus lens
27‧‧‧濾色片 27‧‧‧ Filters
31‧‧‧閘極絕緣膜 31‧‧‧Gate insulation film
32‧‧‧閘極電極 32‧‧‧gate electrode
33‧‧‧第一側壁 33‧‧‧First side wall
34‧‧‧源極-汲極區 34‧‧‧Source-Bungee Area
35‧‧‧源極-汲極區 35‧‧‧Source-bungee area
38‧‧‧LDD區 38‧‧‧LDD area
39‧‧‧LDD區 39‧‧‧LDD District
50‧‧‧MOS電晶體 50‧‧‧MOS transistor
51H‧‧‧閘極絕緣膜 51H‧‧‧gate insulating film
51L‧‧‧閘極絕緣膜 51L‧‧‧gate insulating film
51‧‧‧閘極絕緣膜 51‧‧‧gate insulating film
52‧‧‧閘極電極 52‧‧‧gate electrode
52P‧‧‧閘極電極 52P‧‧‧gate electrode
52N‧‧‧閘極電極 52N‧‧‧gate electrode
53‧‧‧第二側壁 53‧‧‧second side wall
54‧‧‧源極-汲極區 54‧‧‧Source-bungee area
54N‧‧‧源極-汲極區 54N‧‧‧Source-Bungee Area
54P‧‧‧源極-汲極區 54P‧‧‧Source-Bungee Area
55‧‧‧源極-汲極區 55‧‧‧Source-bungee area
55N‧‧‧源極-汲極區 55N‧‧‧Source-Bungee Area
55P‧‧‧源極-汲極區 55P‧‧‧Source-Bungee Area
56‧‧‧矽化物層 56‧‧‧ Telluride layer
57‧‧‧矽化物層 57‧‧‧ Telluride layer
58‧‧‧矽化物層 58‧‧‧ Telluride layer
61‧‧‧LDD區 61‧‧‧LDD area
62‧‧‧LDD區 62‧‧‧LDD area
63‧‧‧LDD區 63‧‧‧LDD area
64‧‧‧LDD區 64‧‧‧LDD area
71‧‧‧第一矽化物阻斷膜 71‧‧‧First Telluride Blocking Film
72‧‧‧第二矽化物阻斷膜 72‧‧‧Second Telluride Blocking Film
74‧‧‧蝕刻止擋膜 74‧‧‧etch stop film
76‧‧‧層間絕緣層 76‧‧‧Interlayer insulation
77‧‧‧接觸孔 77‧‧‧Contact hole
78‧‧‧接觸孔 78‧‧‧Contact hole
79‧‧‧接觸孔 79‧‧‧Contact hole
81‧‧‧接觸孔 81‧‧‧Contact hole
82‧‧‧接觸孔 82‧‧‧Contact hole
84‧‧‧障壁金屬層 84‧‧‧ barrier metal layer
85‧‧‧塞柱 85‧‧‧
111‧‧‧墊氧化物膜 111‧‧‧Mat oxide film
112‧‧‧氮化矽膜 112‧‧‧ nitride film
113‧‧‧周邊電路部分 113‧‧‧ peripheral circuit section
114‧‧‧第一元件隔離溝槽 114‧‧‧First component isolation trench
115‧‧‧第二元件隔離溝槽 115‧‧‧Second component isolation trench
121‧‧‧p井 121‧‧‧p well
123‧‧‧n井 123‧‧‧n well
131‧‧‧閘極電極形成膜 131‧‧‧Gate electrode forming film
132‧‧‧抗蝕劑遮罩 132‧‧‧resist mask
133‧‧‧氧化物膜 133‧‧‧Oxide film
134‧‧‧氧化矽膜 134‧‧‧Oxide film
135‧‧‧氮化矽膜 135‧‧‧ nitride film
136‧‧‧氧化矽膜 136‧‧‧Oxide film
137‧‧‧側壁膜 137‧‧‧ sidewall film
137H‧‧‧開口 137H‧‧‧ openings
138‧‧‧抗蝕劑遮罩 138‧‧‧resist mask
139‧‧‧氮化矽膜 139‧‧‧ nitride film
140‧‧‧氧化矽膜 140‧‧‧Oxide film
141‧‧‧抗蝕劑遮罩 141‧‧‧resist mask
151‧‧‧犧牲氧化層 151‧‧‧ Sacrificial oxide layer
152‧‧‧抗蝕劑遮罩 152‧‧‧resist mask
153‧‧‧開口 153‧‧‧ openings
200‧‧‧成像裝置 200‧‧‧ imaging device
201‧‧‧成像單元 201‧‧‧ imaging unit
202‧‧‧成像光學系統 202‧‧‧ imaging optical system
203‧‧‧信號處理單元 203‧‧‧Signal Processing Unit
Amp‧‧‧放大電晶體 Amp‧‧‧Amplified Transistor
FD‧‧‧浮動擴散部分 FD‧‧‧Floating diffusion part
N‧‧‧通道 N‧‧‧ channel
N+‧‧‧層 N + ‧ ‧ layer
P‧‧‧通道 P‧‧‧ channel
P+‧‧‧層 P + ‧ ‧ layer
RST‧‧‧重設電晶體 RST‧‧‧Reset the transistor
SEL‧‧‧選擇電晶體 SEL‧‧‧Selecting a crystal
TRG‧‧‧傳送閘 TRG‧‧‧Transmission gate
圖1係一示意性結構剖視圖，其顯示一根據本發明之一實施例之固態成像裝置之結構之一第一實例；圖2係一示意性結構剖視圖，其顯示根據本發明之一實施例之固態成像裝置之結構之第一實例；圖3係一示意性結構剖視圖，其顯示一根據本發明之一實施例之固態成像裝置之結構之一第二實例；圖4係一示意性結構剖視圖，其顯示根據本發明之一實施例之固態成像裝置之結構之第二實例；圖5A係一平面佈置圖，其顯示根據本發明之一實施例之固態成像裝置之第一實例；圖5B係一平面佈置圖，其顯示根據本發明之一實施例之固態成像裝置之第二實例；圖6係一剖視圖，其顯示一根據本發明之一實施例製造一固態成像裝置之方法之一第一實例；圖7係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖8係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖9係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖10係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例； 圖11係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖12係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖13係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖14係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖15係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖16係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖17係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖18係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖19係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖20係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖21係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖22係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖23係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例； 圖24係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖25係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖26係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖27係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖28係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖29係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖30係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖31係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖32係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖33係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖34係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖35係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖36係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例； 圖37係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖38係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖39係一剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第一實例；圖40係一平面佈置圖，其顯示其中一個像素電晶體部分分享四個像素之結構之一實例；圖41係平面佈置圖，其顯示一根據本發明之一實施例製造一固態成像裝置之方法之一第二實例；圖42A及42B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第二實例；圖43C及43D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第二實例；圖44係一平面佈置圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第二實例；圖45A及45B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第二實例；圖46C及46D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第二實例；圖47係一示意性結構剖視圖，其圖解闡釋一蝕刻損壞效應；圖48係一平面佈置圖，其顯示一根據本發明之一實施例之固態成像裝置之一第三實例；圖49A及49B係局部剖視圖，其顯示根據本發明之一實施例之固態成像裝置之第三實例；圖50C及50D係局部剖視圖，其顯示根據本發明之一實施例之固 態成像裝置之第三實例；圖51係一平面佈置圖，其顯示根據本發明之一實施例之固態成像裝置之一第四實例；圖52A及52B係局部剖視圖，其顯示根據本發明之一實施例之固態成像裝置之第四實例；圖53C及53D係局部剖視圖，其顯示根據本發明之一實施例之固態成像裝置之第四實例；圖54係一平面佈置圖，其顯示一根據本發明之一實施例製造一固態成像裝置之方法之一第三實例，圖55A及55B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第三實例；圖56C及56D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第三實例；圖57係一平面佈置圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第三實例；圖58A及58B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第三實例；圖59C及59D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第三實例；圖60係一平面佈置圖，其顯示一根據本發明之一實施例製造一固態成像裝置之方法之一第四實例；圖61A及61B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第四實例；圖62C及62D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第四實例；圖63係一平面佈置圖，其顯示根據本發明之一實施例製造一固 態成像裝置之方法之第四實例；圖64A及64B係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第四實例；圖65C及65D係局部剖視圖，其顯示根據本發明之一實施例製造一固態成像裝置之方法之第四實例；圖66係一平面佈置圖，其顯示一對該固態成像裝置及其製造方法之第三及第四實例之修改；圖67係一平面佈置圖，其顯示一對該固態成像裝置及其製造方法之第一實例之修改；圖68係一局部剖視圖，其顯示對該固態成像裝置及其製造方法之第一實例之修改；圖69A及69B係局部剖視圖，其顯示對該固態成像裝置及其製造方法之第一實例之修改；圖70A及70B係剖視圖，其顯示一製造一具有一其中一單一像素電晶體部分分享四個像素之結構(四像素分享結構)之固態成像裝置之方法之一詳細實例；圖71C及71D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖72A及72B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖73C及73D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖74A及74B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖75C及75D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例； 圖76A及76B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖77C及77D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖78A及78B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖79C及79D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖80A及80B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖81C及81D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖82A及82B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖83C及83D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖84A及84B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖85C及85D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖86A及86B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖87C及87D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖88A及88B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例； 圖89C及89D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖90A及90B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖91C及91D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖92A及92B係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖93C及93D係剖視圖，其顯示製造一具有該四像素分享結構之固態成像裝置之方法之該詳細實例；圖94係一方塊圖，其顯示一根據本發明之一實施例之成像裝置；圖95係相關技術中之一CMOS感測器之一佈置圖；及圖96係相關技術中之該CMOS感測器之一平面佈置之一等效電路圖。 1 is a schematic structural cross-sectional view showing a first example of a structure of a solid-state imaging device according to an embodiment of the present invention; and FIG. 2 is a schematic structural cross-sectional view showing an embodiment of the present invention A first example of the structure of a solid-state imaging device; FIG. 3 is a schematic structural cross-sectional view showing a second example of the structure of a solid-state imaging device according to an embodiment of the present invention; and FIG. 4 is a schematic structural cross-sectional view. A second example of the structure of a solid-state imaging device according to an embodiment of the present invention is shown; FIG. 5A is a plan view showing a first example of a solid-state imaging device according to an embodiment of the present invention; FIG. A plan view showing a second example of a solid-state imaging device according to an embodiment of the present invention; and FIG. 6 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention Figure 7 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; Figure 8 is a cross-sectional view showing A first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 9 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 10 is a cross-sectional view thereof. A first example of a method of fabricating a solid-state imaging device in accordance with an embodiment of the present invention; 11 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 12 is a cross-sectional view showing a method of manufacturing a solid-state imaging device according to an embodiment of the present invention. First Embodiment; FIG. 13 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 14 is a cross-sectional view showing the manufacture of a solid-state imaging according to an embodiment of the present invention. A first example of a method of apparatus; FIG. 15 is a cross-sectional view showing a first example of a method of fabricating a solid-state imaging apparatus according to an embodiment of the present invention; and FIG. 16 is a cross-sectional view showing an embodiment of the present invention A first example of a method of manufacturing a solid-state imaging device; FIG. 17 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 18 is a cross-sectional view showing the present invention A first example of a method of fabricating a solid state imaging device; FIG. 19 is a cross-sectional view showing a fabrication according to an embodiment of the present invention A first example of a method of forming an image forming apparatus; FIG. 20 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging apparatus according to an embodiment of the present invention; and FIG. 21 is a cross-sectional view showing one of the present invention A first example of a method of manufacturing a solid-state imaging device; FIG. 22 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 23 is a cross-sectional view showing A first example of a method of fabricating a solid state imaging device in accordance with an embodiment of the present invention; Figure 24 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and Figure 25 is a cross-sectional view showing a method of manufacturing a solid-state imaging device according to an embodiment of the present invention. 1 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 27 is a cross-sectional view showing a solid-state imaging process according to an embodiment of the present invention. A first example of a method of apparatus; FIG. 28 is a cross-sectional view showing a first example of a method of fabricating a solid-state imaging apparatus according to an embodiment of the present invention; and FIG. 29 is a cross-sectional view showing an embodiment of the present invention A first example of a method of manufacturing a solid-state imaging device; FIG. 30 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 31 is a cross-sectional view showing the present invention A first example of a method of fabricating a solid state imaging device; FIG. 32 is a cross-sectional view showing a fabrication according to an embodiment of the present invention A first example of a method of an image forming apparatus; FIG. 33 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging apparatus according to an embodiment of the present invention; and FIG. 34 is a cross-sectional view showing one of the present inventions A first example of a method of manufacturing a solid-state imaging device; FIG. 35 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 36 is a cross-sectional view showing A first example of a method of fabricating a solid state imaging device in accordance with an embodiment of the present invention; 37 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 38 is a cross-sectional view showing a method of manufacturing a solid-state imaging device according to an embodiment of the present invention. First Embodiment; FIG. 39 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 40 is a plan view showing that one pixel transistor portion shares four An example of a structure of a pixel; FIG. 41 is a plan view showing a second example of a method of fabricating a solid-state imaging device according to an embodiment of the present invention; and FIGS. 42A and 42B are partial cross-sectional views showing the present invention. A second example of a method of fabricating a solid-state imaging device; FIGS. 43C and 43D are partial cross-sectional views showing a second example of a method of fabricating a solid-state imaging device in accordance with an embodiment of the present invention; A layout view showing a second example of a method of fabricating a solid-state imaging device according to an embodiment of the present invention; FIGS. 45A and 45B are partial cross-sectional views showing A second example of a method of fabricating a solid-state imaging device in accordance with an embodiment of the present invention; FIGS. 46C and 46D are partial cross-sectional views showing a second example of a method of fabricating a solid-state imaging device in accordance with an embodiment of the present invention; A schematic structural cross-sectional view illustrating an etch damage effect; FIG. 48 is a plan view showing a third example of a solid-state imaging device according to an embodiment of the present invention; and FIGS. 49A and 49B are partial cross-sectional views. A third example of a solid-state imaging device according to an embodiment of the present invention; FIGS. 50C and 50D are partial cross-sectional views showing a solid according to an embodiment of the present invention A third example of a state imaging device; FIG. 51 is a plan view showing a fourth example of a solid-state imaging device according to an embodiment of the present invention; and FIGS. 52A and 52B are partial cross-sectional views showing one of the present invention. A fourth example of the solid-state imaging device of the embodiment; FIGS. 53C and 53D are partial cross-sectional views showing a fourth example of the solid-state imaging device according to an embodiment of the present invention; and FIG. 54 is a plan view showing a layout according to the present invention. EMBODIMENT OF THE INVENTION A third example of a method of manufacturing a solid-state imaging device, FIGS. 55A and 55B are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; 56D is a partial cross-sectional view showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 57 is a plan view showing a method of manufacturing a solid-state imaging device according to an embodiment of the present invention. FIG. 58A and FIG. 58B are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; FIG. 59C 59D is a partial cross-sectional view showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 60 is a plan view showing a solid-state imaging device according to an embodiment of the present invention. A fourth embodiment of the method; FIGS. 61A and 61B are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIGS. 62C and 62D are partial cross-sectional views showing the present invention in accordance with the present invention. A fourth example of a method of fabricating a solid-state imaging device; FIG. 63 is a plan view showing a fabrication of a solid according to an embodiment of the present invention. A fourth embodiment of the method of the image forming apparatus; FIGS. 64A and 64B are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIGS. 65C and 65D are partial cross-sectional views showing A fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention; and FIG. 66 is a plan view showing a modification of the third and fourth examples of the solid-state imaging device and the method of manufacturing the same; A plan view showing a modification of a first example of the solid-state imaging device and its manufacturing method; and FIG. 68 is a partial cross-sectional view showing a modification of the first example of the solid-state imaging device and the method of manufacturing the same; 69A and 69B are partial cross-sectional views showing modifications of the first example of the solid-state imaging device and the method of fabricating the same; FIGS. 70A and 70B are cross-sectional views showing a manufacturing one having a single pixel transistor portion sharing four A detailed example of a method of a solid-state imaging device of a structure of a pixel (four-pixel sharing structure); FIGS. 71C and 71D are cross-sectional views showing the manufacture of one having the four pixels This detailed example of the method of the solid-state imaging device of the structure; FIGS. 72A and 72B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 73C and 73D are cross-sectional views showing This detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 74A and 74B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIG. 75C and 75D is a cross-sectional view showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; 76A and 76B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 77C and 77D are cross-sectional views showing the manufacture of a solid-state imaging device having the four-pixel sharing structure. This detailed example of the method; FIGS. 78A and 78B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 79C and 79D are cross-sectional views showing that the manufacturing has a four-pixel sharing. This detailed example of the method of the solid-state imaging device of the structure; FIGS. 80A and 80B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 81C and 81D are cross-sectional views showing the manufacture A detailed example of a method of a solid-state imaging device having the four-pixel sharing structure; FIGS. 82A and 82B are cross-sectional views showing the detailed example of a method of fabricating a solid-state imaging device having the four-pixel sharing structure; FIGS. 83C and 83D A cross-sectional view showing the detail of a method of fabricating a solid-state imaging device having the four-pixel sharing structure 84A and 84B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 85C and 85D are cross-sectional views showing the manufacture of a solid-state imaging having the four-pixel sharing structure. This detailed example of the method of the apparatus; FIGS. 86A and 86B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 87C and 87D are cross-sectional views showing that the manufacturing one has the four This detailed example of the method of the solid-state imaging device of the pixel sharing structure; FIGS. 88A and 88B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; 89C and 89D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 90A and 90B are cross-sectional views showing the manufacture of a solid-state imaging device having the four-pixel sharing structure. This detailed example of the method; FIGS. 91C and 91D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 92A and 92B are cross-sectional views showing that the manufacturing has a four-pixel sharing This detailed example of the method of the solid-state imaging device of the structure; FIGS. 93C and 93D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIG. 94 is a block diagram showing a An imaging device according to an embodiment of the present invention; FIG. 95 is a layout diagram of one of CMOS sensors in the related art; and FIG. 96 is an equivalent circuit diagram of one of the planar arrangements of the CMOS sensor in the related art. .
下文將闡述用於實施本發明(下稱「實施例」)之模式。 The mode for carrying out the invention (hereinafter referred to as "the embodiment") will be explained below.
將參照圖1之一像素部分之一示意性結構剖視圖、圖2之一周邊電路部分之一示意性結構剖視圖及圖5A之像素部分之一平面佈置圖來闡述一根據本發明之一第一實施例之固態成像裝置之結構之一第一實例。圖5A顯示一其中一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL彼此連接成一作用區之情形。應注意，圖1中所示之像素部分及圖2中所示之周邊電路部分形成於同一半導體基板上。圖1顯示一沿圖5A中線I-I剖切之截面。此外，將參照圖3之一像素部分之一示意性結構剖視圖、圖4之一周邊電路部分之一示意 性結構剖視圖及圖5B之像素部分之一平面佈置圖來闡述一根據第一實施例之固態成像裝置之結構之一第二實例。圖5B顯示一其中一由一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL組成之作用區由淺溝槽隔離(STI)隔開之情形。應注意，圖3中所示之像素部分及圖4中所示之周邊電路部分形成於同一半導體基板上。圖3顯示一沿圖5B中線III-III剖切之截面。為了減小處於相同大小之飽和電荷Qs中之像素尺寸，圖5中所示之佈置係更可取的。 A first embodiment of the present invention will be described with reference to a schematic structural cross-sectional view of one of the pixel portions of FIG. 1, a schematic structural cross-sectional view of one of the peripheral circuit portions of FIG. 2, and a planar layout of the pixel portion of FIG. 5A. A first example of the structure of a solid-state imaging device. Fig. 5A shows a case where one of the transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are connected to each other as an active region. It should be noted that the pixel portion shown in FIG. 1 and the peripheral circuit portion shown in FIG. 2 are formed on the same semiconductor substrate. Figure 1 shows a section taken along line I-I of Figure 5A. In addition, a schematic structural cross-sectional view of one of the pixel portions of FIG. 3 and one of the peripheral circuit portions of FIG. 4 will be referred to. A second example of the structure of the solid-state imaging device according to the first embodiment is explained in a sectional view of a structural structure and a plan view of a pixel portion of FIG. 5B. FIG. 5B shows a case where an active region composed of a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a select transistor SEL is separated by shallow trench isolation (STI). It should be noted that the pixel portion shown in FIG. 3 and the peripheral circuit portion shown in FIG. 4 are formed on the same semiconductor substrate. Figure 3 shows a section taken along line III-III of Figure 5B. In order to reduce the pixel size in the same size of the saturated charge Qs, the arrangement shown in Fig. 5 is preferable.
如圖1、2及5A中所示，一固態成像裝置1(A)包括一半導體基板11，該半導體基板包括一具有一光電轉換入射光以獲得一電信號之光電轉換部分21之像素部分12及一設置於像素部分12之周邊處之周邊電路部分13。在半導體基板11之像素部分12中，提供光電轉換部分21，且以串聯方式依序提供一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL以連接至光電轉換部分21。光電轉換部分21由例如一光電二極體構成。 As shown in Figs. 1, 2 and 5A, a solid-state imaging device 1 (A) includes a semiconductor substrate 11 including a pixel portion 12 having a photoelectric conversion portion 21 for photoelectrically converting incident light to obtain an electrical signal. And a peripheral circuit portion 13 disposed at the periphery of the pixel portion 12. In the pixel portion 12 of the semiconductor substrate 11, a photoelectric conversion portion 21 is provided, and a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially connected in series to be connected to the photoelectric conversion Part 21. The photoelectric conversion portion 21 is composed of, for example, a photodiode.
一由一側壁膜組成之第一側壁33提供於像素部分12中之MOS電晶體30(傳送閘TRG、重設電晶體RST、放大電晶體Amp及選擇電晶體SEL)之每一閘極電極32之側壁上。另外，一由相同於該側壁膜之膜組成之第二側壁53提供於周邊電路部分13之MOS電晶體50之每一閘極電極52之側壁上。此外，一由相同於該側壁膜之膜組成之第一矽化物阻斷膜71提供於光電轉換部分21上。此外，一與第一矽化物阻斷膜71之一部分重疊之第二矽化物阻斷膜72提供於像素部分12中之MOS電晶體30中之每一者上。第一矽化物阻斷膜71具有一包括例如氧化矽膜及氮化矽膜之堆疊結構。第二矽化物阻斷膜72具有一包括例如氧化矽膜及氮化矽膜之堆疊結構。因此，像素部分12由第一矽化物阻斷膜71及第二矽化物阻斷膜72覆蓋。其中第二矽化物阻斷膜72與第一矽化物阻斷 膜71重疊之部分形成於像素部分12中。 A first sidewall 33 composed of a sidewall film is provided to each of the gate electrodes 32 of the MOS transistor 30 (transfer gate TRG, reset transistor RST, amplifier transistor Amp, and select transistor SEL) in the pixel portion 12. On the side wall. Further, a second side wall 53 composed of a film identical to the side wall film is provided on the side wall of each of the gate electrodes 52 of the MOS transistor 50 of the peripheral circuit portion 13. Further, a first telluride blocking film 71 composed of a film identical to the film of the side wall is provided on the photoelectric conversion portion 21. Further, a second vaporization blocking film 72 partially overlapping one of the first telluride blocking films 71 is provided on each of the MOS transistors 30 in the pixel portion 12. The first telluride blocking film 71 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. The second telluride blocking film 72 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. Therefore, the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72. Wherein the second telluride blocking film 72 and the first telluride block A portion where the film 71 overlaps is formed in the pixel portion 12.
針對周邊電路部分13中之MOS電晶體50中之每一者，例如，一矽化層58提供於閘極電極52上，且矽化層56及57分別提供於源極-汲極區54及55上。以此方式，為了減小寄生電阻以達成一高速運作，矽化周邊電路部分13中之MOS電晶體50中之每一者。 For each of the MOS transistors 50 in the peripheral circuit portion 13, for example, a deuterated layer 58 is provided on the gate electrode 52, and the deuterated layers 56 and 57 are provided on the source-drain regions 54 and 55, respectively. . In this manner, in order to reduce the parasitic resistance to achieve a high speed operation, each of the MOS transistors 50 in the peripheral circuit portion 13 is deuterated.
分隔像素部分12之第一隔離區14提供於半導體基板11中。分隔一其中形成周邊電路部分13中之MOS電晶體之區之第二隔離區15提供於半導體基板11中。該等第一隔離區14及該等第二隔離區15中之每一者皆具有一STI結構。該等第一隔離區14經形成以淺於該等第二隔離區15。另外，該等第一隔離區14經形成以使每一隔離區14自半導體基板11凸出之一部分之一高度為低。 The first isolation region 14 that separates the pixel portion 12 is provided in the semiconductor substrate 11. A second isolation region 15 partitioning a region in which the MOS transistors in the peripheral circuit portion 13 are formed is provided in the semiconductor substrate 11. Each of the first isolation regions 14 and the second isolation regions 15 has an STI structure. The first isolation regions 14 are formed to be shallower than the second isolation regions 15. In addition, the first isolation regions 14 are formed such that the height of one of the portions of each of the isolation regions 14 protruding from the semiconductor substrate 11 is low.
如上文所述，固態成像裝置1(A)包括一其中使用該側壁膜來形成第一矽化物阻斷膜71之區、一其中形成第二矽化物阻斷膜72(其係藉由單獨地形成一用於矽化物阻斷之絕緣膜而形成)之區、及其中如同在周邊電路部分13中之MOS電晶體50中一樣形成矽化層56或57之區。另外，由該側壁膜組成之第一矽化物阻斷膜71形成於光電轉換部分21上。 As described above, the solid-state imaging device 1 (A) includes a region in which the sidewall film is used to form the first vapor blocking film 71, and a second vapor blocking film 72 is formed therein (by separately A region in which an insulating film for silicide blocking is formed, and a region in which the deuterated layer 56 or 57 is formed as in the MOS transistor 50 in the peripheral circuit portion 13 is formed. Further, a first telluride blocking film 71 composed of the side wall film is formed on the photoelectric conversion portion 21.
如圖3、4及5B中所示，一固態成像裝置1(B)包括一半導體基板11，該半導體基板包括一具有一光電轉換入射光以獲得一電信號之光電轉換部分21之像素部分12及一設置於像素部分12之周邊處之周邊電路部分13。在半導體基板11之像素部分12中，提供光電轉換部分21，且以串聯方式依序提供一傳送閘TRG、一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL以連接至光電轉換部分21。光電轉換部分21由例如一光電二極體構成。 As shown in Figs. 3, 4 and 5B, a solid-state imaging device 1 (B) includes a semiconductor substrate 11 including a pixel portion 12 having a photoelectric conversion portion 21 for photoelectrically converting incident light to obtain an electrical signal. And a peripheral circuit portion 13 disposed at the periphery of the pixel portion 12. In the pixel portion 12 of the semiconductor substrate 11, a photoelectric conversion portion 21 is provided, and a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially connected in series to be connected to the photoelectric conversion Part 21. The photoelectric conversion portion 21 is composed of, for example, a photodiode.
一由一側壁膜組成之第一側壁33提供於像素部分12中之MOS電 晶體(傳送閘TRG、重設電晶體RST、放大電晶體Amp及選擇電晶體SEL)之每一閘極電極32之側壁上。另外，一由相同於該側壁膜之膜組成之第二側壁53提供於周邊電路部分13中之MOS電晶體50之每一閘極電極52之側壁上。此外，一由相同於該側壁膜之膜組成之第一矽化物阻斷膜71提供於光電轉換部分21上。此外，一與第一矽化物阻斷膜71之一部分重疊之第二矽化物阻斷膜72提供於像素部分12中之MOS電晶體30中之每一者上。第一矽化物阻斷膜71具有一包括例如氧化矽膜及氮化矽膜之堆疊結構。第二矽化物阻斷膜72具有一包括例如氧化矽膜及氮化矽膜之堆疊結構。因此，像素部分12由第一矽化物阻斷膜71及第二矽化物阻斷膜72覆蓋。其中第二矽化物阻斷膜72與第一矽化物阻斷膜71重疊之部分形成於像素部分12中。 A first sidewall 33 composed of a sidewall film is provided in the MOS electrode in the pixel portion 12 The side walls of each of the gate electrodes 32 of the crystals (transfer gate TRG, reset transistor RST, amplifier transistor Amp, and selection transistor SEL). Further, a second side wall 53 composed of a film identical to the side wall film is provided on the side wall of each of the gate electrodes 52 of the MOS transistor 50 in the peripheral circuit portion 13. Further, a first telluride blocking film 71 composed of a film identical to the film of the side wall is provided on the photoelectric conversion portion 21. Further, a second vaporization blocking film 72 partially overlapping one of the first telluride blocking films 71 is provided on each of the MOS transistors 30 in the pixel portion 12. The first telluride blocking film 71 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. The second telluride blocking film 72 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. Therefore, the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72. A portion in which the second telluride blocking film 72 overlaps with the first telluride blocking film 71 is formed in the pixel portion 12.
針對周邊電路部分13中之MOS電晶體50中之每一者，例如，一矽化層58提供於閘極電極52上，且矽化層56及57分別提供於源極-汲極區54及55上。以此方式，為了減小寄生電阻以達成一高速運作，矽化周邊電路部分13中之MOS電晶體50中之每一者。 For each of the MOS transistors 50 in the peripheral circuit portion 13, for example, a deuterated layer 58 is provided on the gate electrode 52, and the deuterated layers 56 and 57 are provided on the source-drain regions 54 and 55, respectively. . In this manner, in order to reduce the parasitic resistance to achieve a high speed operation, each of the MOS transistors 50 in the peripheral circuit portion 13 is deuterated.
分隔一其中形成像素部分12中之MOS電晶體之區之第一隔離區14提供於半導體基板11中。分隔一其中形成周邊電路部分13中之MOS電晶體之區之第二隔離區15提供於半導體基板11中。該等第一隔離區14及該等第二隔離區15中之每一者皆具有一STI結構。該等第一隔離區14經形成以淺於該等第二隔離區15。另外，該等第一隔離區14經形成以使每一第一隔離區14自半導體基板11凸出之一部分之一高度為低。 A first isolation region 14 partitioning a region in which the MOS transistors in the pixel portion 12 are formed is provided in the semiconductor substrate 11. A second isolation region 15 partitioning a region in which the MOS transistors in the peripheral circuit portion 13 are formed is provided in the semiconductor substrate 11. Each of the first isolation regions 14 and the second isolation regions 15 has an STI structure. The first isolation regions 14 are formed to be shallower than the second isolation regions 15. In addition, the first isolation regions 14 are formed such that the height of one of the portions of each of the first isolation regions 14 protruding from the semiconductor substrate 11 is low.
如上文中所述，固態成像裝置1(B)包括一其中使用該側壁膜來形成第一矽化物阻斷膜71之區、一其中形成第二矽化物阻斷膜72(其係藉由單獨地形成一矽化物阻斷絕緣膜而形成)之區、及如同在周邊電路部分13中之MOS電晶體50中一樣形成矽化層56或57之區。另外，由 該側壁膜組成之第一矽化物阻斷膜71形成於光電轉換部分21上。 As described above, the solid-state imaging device 1 (B) includes a region in which the sidewall film is used to form the first vapor blocking film 71, and a second vapor blocking film 72 is formed therein (by separately A region where a germanide blocking insulating film is formed, and a region where the germanium layer 56 or 57 is formed as in the MOS transistor 50 in the peripheral circuit portion 13 are formed. In addition, by The first telluride blocking film 71 composed of the side wall film is formed on the photoelectric conversion portion 21.
在固態成像裝置1(1A及1B)中之每一者中，為了防止因一矽化物而引起之雜質污染及瑕疵產生，像素部分12較佳由第一矽化物阻斷膜71及第二矽化物阻斷膜72完全覆蓋。第一矽化物阻斷膜71及第二矽化矽阻斷膜72可不提供於第一及第二隔離區14及15上。然而，必需使相同像素尺寸中之光電轉換部分21之光接收面積最大化以增大飽和電荷(Qs)，從而減小雜訊效應。相應地，為了不必考量該等隔離區上之重疊邊際，該等隔離區之上表面亦較佳由第一矽化物阻斷膜71及第二矽化物阻斷膜72覆蓋。此結構可減小該等隔離區之面積以增大光電轉換部分21之光接收面積。 In each of the solid-state imaging devices 1 (1A and 1B), in order to prevent impurity contamination and flaw generation due to a telluride, the pixel portion 12 is preferably composed of a first telluride blocking film 71 and a second deuteration. The barrier film 72 is completely covered. The first telluride blocking film 71 and the second germanium germanium blocking film 72 may not be provided on the first and second isolation regions 14 and 15. However, it is necessary to maximize the light receiving area of the photoelectric conversion portion 21 in the same pixel size to increase the saturation charge (Qs), thereby reducing the noise effect. Accordingly, in order not to consider the overlapping margins on the isolation regions, the upper surface of the isolation regions is preferably covered by the first vapor blocking film 71 and the second vapor blocking film 72. This structure can reduce the area of the isolation regions to increase the light receiving area of the photoelectric conversion portion 21.
因而，在固態成像裝置1之上述佈置中，為了減小該等隔離區之一分隔寬度以增大光電二極體之面積之比例，提供其中第二矽化物阻斷膜72與第一矽化物阻斷膜71重疊之部分。由此，像素部分12中之閘極電極32中之每一者上之位準差增大，且難以保證一層間絕緣膜之平坦度。舉例而言，在闡述於第2005-347325號日本未經審查的專利申請公開案中之分隔技術中，一像素中自一矽(Si)基板之表面凸出之一氧化物膜隔離部分之高度增大，且因此更難以保證平坦度。在本發明之此實施例中，使用具有淺溝槽隔離(STI)結構之第一隔離區14以使第一隔離區14自半導體基板11凸出之一部分之高度為低。然而，若第一隔離區14之STI之深度相同於周邊電路部分13中之第二隔離區15之STI之深度，則構成光電轉換部分21之光電二極體上之應力及蝕刻損壞增大，從而導致白疵點數之增大。因此，第一隔離區14經形成以淺於周邊電路部分13中之第二隔離區15。為了實現一高速運作，周邊電路部分13中之第二隔離區15之STI具有一大深度以減小佈線與基板之間的寄生電阻。 Thus, in the above arrangement of the solid-state imaging device 1, in order to reduce the separation width of one of the isolation regions to increase the ratio of the area of the photodiode, the second vaporization blocking film 72 and the first germanide are provided therein. The portion where the film 71 overlaps is blocked. Thereby, the level difference on each of the gate electrodes 32 in the pixel portion 12 is increased, and it is difficult to ensure the flatness of the interlayer insulating film. For example, in the separation technique described in Japanese Unexamined Patent Application Publication No. Hei No. 2005-347325, the height of one oxide film isolation portion protruding from the surface of a silicon (Si) substrate in one pixel Increased, and thus it is more difficult to ensure flatness. In this embodiment of the invention, the first isolation region 14 having a shallow trench isolation (STI) structure is used to make the height of the portion of the first isolation region 14 protruding from the semiconductor substrate 11 low. However, if the depth of the STI of the first isolation region 14 is the same as the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13, the stress and etching damage on the photodiode constituting the photoelectric conversion portion 21 are increased. This leads to an increase in the number of chalk points. Therefore, the first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. In order to achieve a high speed operation, the STI of the second isolation region 15 in the peripheral circuit portion 13 has a large depth to reduce the parasitic resistance between the wiring and the substrate.
在根據本發明之一實施例之固態成像裝置1(1A)中，像素部分12 由兩層(亦即，由相同於一側壁膜之膜組成之第一矽化物阻斷膜71及由一不同於第一矽化物阻斷膜71之膜組成之第二矽化物阻斷膜72)覆蓋。相應地，像素部分12中之MOS電晶體30不由一單一矽化物阻斷膜完全覆蓋。此結構係有利的，因為可減小隨機雜訊，並可減小白疵點數及暗電流。 In the solid-state imaging device 1 (1A) according to an embodiment of the present invention, the pixel portion 12 The second telluride blocking film 72 consists of two layers (that is, a first telluride blocking film 71 composed of a film identical to the one side wall film and a film different from the first telluride blocking film 71). )cover. Accordingly, the MOS transistor 30 in the pixel portion 12 is not completely covered by a single telluride blocking film. This structure is advantageous because random noise can be reduced and white point and dark current can be reduced.
現將參照圖6至39(其係顯示製造步驟之剖視圖)來闡述一根據本發明之一實施例製造一固態成像裝置之方法之一第一實例。 A first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention will now be described with reference to Figs. 6 to 39, which are cross-sectional views showing manufacturing steps.
如圖6中所示，例如，使用一矽基板作為一半導體基板11。在半導體基11上形成一墊氧化物膜111及氮化矽膜112。墊氧化物膜111係藉由例如一熱氧化方法來氧化半導體基板11之一表面而形成。此墊氧化物膜111經形成以具有一例如15 nm之厚度。接下來，藉由例如一低溫化學氣相沈積(LP-CVD)方法在墊氧化物膜111上形成氮化矽膜112。此氮化矽膜112經形成以具有一例如160 nm之厚度。上述裝置具有氮化矽膜/墊氧化物膜之結構。另一選擇係，該裝置可具有氮化矽膜/多晶矽膜之結構或一非晶矽膜/墊氧化物膜之結構。 As shown in FIG. 6, for example, a germanium substrate is used as a semiconductor substrate 11. A pad oxide film 111 and a tantalum nitride film 112 are formed on the semiconductor substrate 11. The pad oxide film 111 is formed by oxidizing one surface of the semiconductor substrate 11 by, for example, a thermal oxidation method. This pad oxide film 111 is formed to have a thickness of, for example, 15 nm. Next, a tantalum nitride film 112 is formed on the pad oxide film 111 by, for example, a low temperature chemical vapor deposition (LP-CVD) method. This tantalum nitride film 112 is formed to have a thickness of, for example, 160 nm. The above device has a structure of a tantalum nitride film/pad oxide film. Alternatively, the device may have a structure of a tantalum nitride film/polysilicon film or a structure of an amorphous germanium film/pad oxide film.
接下來，如圖7中所示，在氮化矽膜112上形成一具有一位於一其中欲形成一隔離區之區域上之開口之抗蝕劑遮罩(未顯示)。然後，藉由蝕刻在氮化矽膜112及墊氧化物膜111中形成一開口113。舉例而言，一反應離子蝕刻(RIE)設備或一電子回旋共振(ECR)蝕刻設備可用於此蝕刻。在該蝕刻過程之後，藉助一灰化設備或類似設備來移除該抗蝕劑遮罩。 Next, as shown in Fig. 7, a resist mask (not shown) having an opening in a region in which an isolation region is to be formed is formed on the tantalum nitride film 112. Then, an opening 113 is formed in the tantalum nitride film 112 and the pad oxide film 111 by etching. For example, a reactive ion etching (RIE) device or an electron cyclotron resonance (ECR) etching device can be used for this etch. After the etching process, the resist mask is removed by means of an ashing device or the like.
接下來，如圖8中所示，使用氮化矽膜112作為一蝕刻遮罩來在半導體基板11中形成一第一元件隔離溝槽114。舉例而言，一RIE設備或一ECR蝕刻設備用於此蝕刻。首先，對一周邊電路部分13(及一像 素部分12)之一第二元件隔離溝槽115(及第一元件隔離溝槽114)實施一第一蝕刻。在此種情況下，像素部分12(及周邊電路部分13)之第一元件隔離溝槽114(及第二元件隔離溝槽115)之深度介於50至160 nm之範圍內。接著，儘管未顯示於該等圖式中，但在像素部分12上形成一抗蝕劑遮罩，並隨後實施一用於延伸僅周邊電路部分13中之第二元件隔離溝槽115之第二蝕刻。因此，僅周邊電路部分13中之第二元件隔離溝槽115具有一例如0.3 μm之深度。隨後移除該抗蝕劑遮罩。 Next, as shown in FIG. 8, a first element isolation trench 114 is formed in the semiconductor substrate 11 using the tantalum nitride film 112 as an etch mask. For example, an RIE device or an ECR etching device is used for this etching. First, a peripheral circuit portion 13 (and an image) The first element isolation trench 115 (and the first element isolation trench 114) of the element portion 12) performs a first etch. In this case, the depth of the first element isolation trench 114 (and the second element isolation trench 115) of the pixel portion 12 (and the peripheral circuit portion 13) is in the range of 50 to 160 nm. Next, although not shown in the drawings, a resist mask is formed on the pixel portion 12, and then a second for extending the second element isolation trench 115 in only the peripheral circuit portion 13 is implemented. Etching. Therefore, only the second element isolation trench 115 in the peripheral circuit portion 13 has a depth of, for example, 0.3 μm. The resist mask is then removed.
藉由在像素部分12中形成一淺第一元件隔離溝槽114，可達成一減小因蝕刻損壞而引起之白疵點數之效應。藉由減小第一元件隔離溝槽114之深度，一有效光電轉換部分之面積增大。此係有利的，因為可增大飽和電荷(Qs)。 By forming a shallow first element isolation trench 114 in the pixel portion 12, an effect of reducing the number of white spots caused by etching damage can be achieved. By reducing the depth of the first element isolation trench 114, the area of an effective photoelectric conversion portion is increased. This is advantageous because the saturated charge (Qs) can be increased.
接下來，儘管未顯示於該等圖式中，但形成一線性膜。此線性膜係藉由例如在一介於約800℃至900℃之範圍內的溫度下之熱氧化而形成。此線性膜可係氧化矽膜、一包含氮的氧化矽膜、或一CVD氮化矽膜。該線性膜之厚度介於約4至10 nm之範圍內。儘管未顯示於該等圖式中，但使用一抗蝕劑遮罩在像素部分12中實施用於抑制暗電流之硼(B)之離子植入。至於該離子植入之條件之一實例，植入能量設定為約10 keV，且劑量設定為介於1×1012至1×1014 cm-2之範圍內。在一其中欲形成像素部分12中之一隔離區之位於第一元件隔離溝槽114周圍之區域中，因硼濃度增大，故可更有效地抑制暗電流以抑制一寄生電晶體運作。然而，若硼濃度太高，則構成光電轉換部分之光電二極體之面積減小，從而減小飽和電荷(Qs)。由於此等緣故，如上文所述指定劑量。 Next, although not shown in the drawings, a linear film is formed. The linear film is formed by, for example, thermal oxidation at a temperature ranging from about 800 ° C to 900 ° C. The linear film may be a hafnium oxide film, a hafnium oxide film containing nitrogen, or a CVD tantalum nitride film. The linear film has a thickness in the range of about 4 to 10 nm. Although not shown in the drawings, ion implantation for suppressing dark current boron (B) is performed in the pixel portion 12 using a resist mask. As an example of the conditions of the ion implantation, the implantation energy is set to about 10 keV, and the dose is set to be in the range of 1 × 10 12 to 1 × 10 14 cm -2 . In a region in which the isolation region of the pixel portion 12 is to be formed around the first element isolation trench 114, since the boron concentration is increased, the dark current can be more effectively suppressed to suppress the operation of a parasitic transistor. However, if the boron concentration is too high, the area of the photodiode constituting the photoelectric conversion portion is reduced, thereby reducing the saturation charge (Qs). For these reasons, the dose is specified as described above.
接下來，如圖9中所示，在氮化矽膜112上形成一絕緣膜以填充第二元件隔離溝槽115(及第一元件隔離溝槽114)之內部。此絕緣膜係藉由例如一高密度電漿(CVD)方法來沈積氧化矽而形成。接著，藉由 例如化學機械研磨(CMP)來移除形成於氮化矽膜112上之絕緣膜之一過剩部分。因而，該絕緣膜繼續存在於第二元件隔離溝槽115(第一元件隔離溝槽114)內部以形成由該絕緣膜組成之第二隔離區15(第一隔離區14)。在該CMP中，氮化矽膜112起一用於止擋CMP之阻擋件的作用。第一隔離區14經形成以淺於周邊電路部分13中之第二隔離區15。然而，氮化矽膜112通常用作該阻擋件，且因此第一隔離區14之凸出量設定為相同於第二隔離區15之凸出量。在本文中，在片語「第一隔離區14之一凸出高度相同於第二隔離區15之一凸出高度」中，該等凸出高度界定為相同，只要凸出高度之差處於一因製造中之一處理精度而引起之過程變化範圍內。特定而言，當一在一溝槽過程中用作一遮罩之氮化矽膜112具有一約160 nm之厚度時，形成於一晶圓上之氮化矽膜112之厚度通常在一平面中變化達約±10%。因化學機械研磨(CMP)而引起之厚度變化為約±20至±30 nm。相應地，甚至在第一隔離區14及第二隔離區15經形成以使像素部分12中之凸出量相同於周邊電路部分13中之凸出量時，該凸出量亦可在約20至30 nm之範圍內變化。假定密切觀察一晶片表面並在該表面上之某些位置處將一像素部分12與一周邊電路部分13相比較。在此種情況下，即使該等凸出高度並非係完全相同之值，該等高度亦可包括於本發明之此實施例中之「相同高度」之範疇內，只要像素部分12與周邊電路部分13之間的凸出高度差不超過30 nm。最後，將第一隔離區14及第二隔離區15之凸出高度之一中心條件設定為低；例如，介於距該矽表面約0至20 nm之範圍內。 Next, as shown in FIG. 9, an insulating film is formed on the tantalum nitride film 112 to fill the inside of the second element isolation trench 115 (and the first element isolation trench 114). This insulating film is formed by depositing yttrium oxide, for example, by a high density plasma (CVD) method. Then, by For example, chemical mechanical polishing (CMP) is used to remove a surplus portion of the insulating film formed on the tantalum nitride film 112. Thus, the insulating film continues to exist inside the second element isolation trench 115 (first element isolation trench 114) to form the second isolation region 15 (first isolation region 14) composed of the insulating film. In this CMP, the tantalum nitride film 112 functions as a stopper for stopping CMP. The first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. However, the tantalum nitride film 112 is generally used as the blocking member, and thus the amount of protrusion of the first isolation region 14 is set to be the same as the amount of protrusion of the second isolation region 15. Herein, in the phrase "one of the first isolation regions 14 has a convex height equal to one of the convexities of the second isolation region 15," the convex heights are defined to be the same as long as the difference in the convex heights is in one. The range of process variations due to one of the processing precisions in manufacturing. In particular, when a tantalum nitride film 112 used as a mask in a trench process has a thickness of about 160 nm, the thickness of the tantalum nitride film 112 formed on a wafer is usually in a plane. The change is about ±10%. The thickness variation due to chemical mechanical polishing (CMP) is about ±20 to ±30 nm. Accordingly, even when the first isolation region 14 and the second isolation region 15 are formed such that the amount of protrusion in the pixel portion 12 is the same as the amount of protrusion in the peripheral circuit portion 13, the amount of protrusion may be about 20 Change to a range of 30 nm. It is assumed that a wafer surface is closely observed and a pixel portion 12 is compared with a peripheral circuit portion 13 at some position on the surface. In this case, even if the protrusion heights are not completely identical values, the heights may be included in the "same height" in this embodiment of the invention as long as the pixel portion 12 and the peripheral circuit portion The difference in bulge height between 13 does not exceed 30 nm. Finally, the center condition of one of the protrusion heights of the first isolation region 14 and the second isolation region 15 is set to be low; for example, within a range of about 0 to 20 nm from the surface of the crucible.
接下來，如圖10中所示，為了調整第一隔離區14自半導體基板11之表面凸出之一部分之高度，對該氧化物膜實施濕蝕刻。對該氧化物膜之蝕刻量例如介於40至100 nm之範圍內。在本發明之此實施例中，使用具有淺溝槽隔離(STI)結構之第一隔離區14以使第一隔離區 14自半導體基板11凸出之該部分之高度為低。然而，若第一隔離區14之STI之深度相同於周邊電路部分13中之第二隔離區15之STI之深度，則構成光電轉換部分21之光電二極體上之應力及蝕刻損壞增大，從而導致白疵點數之增大。因此，第一隔離區14經形成以淺於周邊電路部分13中之第二隔離區15。為了實現一高速運作，增大周邊電路部分13中之第二隔離區15之STI之深度以減小佈線與基板之間的寄生電阻。接著，移除氮化矽112(參見圖9)以曝露墊氧化物膜111。氮化矽膜112係使用熱磷酸藉由例如濕蝕刻來移除。 Next, as shown in FIG. 10, in order to adjust the height of a portion of the first isolation region 14 protruding from the surface of the semiconductor substrate 11, the oxide film is subjected to wet etching. The etching amount of the oxide film is, for example, in the range of 40 to 100 nm. In this embodiment of the invention, a first isolation region 14 having a shallow trench isolation (STI) structure is used to cause the first isolation region The height of the portion protruding from the semiconductor substrate 11 is low. However, if the depth of the STI of the first isolation region 14 is the same as the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13, the stress and etching damage on the photodiode constituting the photoelectric conversion portion 21 are increased. This leads to an increase in the number of chalk points. Therefore, the first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. In order to achieve a high speed operation, the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13 is increased to reduce the parasitic resistance between the wiring and the substrate. Next, the tantalum nitride 112 (see FIG. 9) is removed to expose the pad oxide film 111. The tantalum nitride film 112 is removed using, for example, wet etching using hot phosphoric acid.
接下來，如圖11中所示，在一其中提供墊氧化物膜111之情況下，使用一抗蝕劑遮罩(未顯示)藉由離子植入在半導體基板11上形成一p井121，該抗蝕劑遮罩具有一位於一其中欲形成該p井121之區域上之開口。進一步實施通道離子植入。隨後移除該抗蝕劑遮罩。另外，在一其中提供墊氧化物膜111之情況下，使用一抗蝕劑遮罩(未顯示)藉由離子植入在半導體基板11上形成一n井123，該抗蝕劑遮罩具有一位於一其中欲形成該n井123之區域上之開口。進一步實施通道離子植入。隨後移除該抗蝕劑遮罩。使用硼(B)作為一離子植入種類來對p井121實施離子植入。在此離子植入中，植入能量設定為例如約200 keV且劑量設定為例如1×1013 cm-2。使用硼(B)作為一離子植入種類來對p井121實施通道離子植入。在此通道離子植入中，植入能量設定為介於例如約10至20 keV之範圍內且劑量設定為介於例如1×1011至1×1013 cm-2之範圍內。使用例如磷(P)作為一離子植入種類來對n井123實施離子植入。在此離子植入中，植入能量設定為介於例如約200 keV之範圍內且劑量設定為例如1×1013 cm-2。使用例如砷(As)作為一離子植入種類來對n井123實施通道離子植入。在此通道離子植入中，植入能量設定為例如約100 keV且劑量設定為介於例如1×1011至1×1013 cm-2之範圍內。此外，儘管未顯示於該等圖式中，但實施用於在該光電轉換部 分中形成一光電二極體之離子植入以形成一p型區。舉例而言，對其中欲形成該光電轉換區之該半導體基板之一表面實施硼(B)之離子植入。進一步使用砷(As)或磷(P)在一深區中實施離子植入以形成一n型區，該n型區形成一與該p型區之一下部分之接面。因此，形成具有一p-n接面之光電轉換部分。 Next, as shown in FIG. 11, in the case where the pad oxide film 111 is provided, a p well 121 is formed on the semiconductor substrate 11 by ion implantation using a resist mask (not shown). The resist mask has an opening in a region in which the p-well 121 is to be formed. Further implementation of channel ion implantation. The resist mask is then removed. Further, in the case where the pad oxide film 111 is provided, a n well 123 is formed on the semiconductor substrate 11 by ion implantation using a resist mask (not shown) having a resist mask Located in an opening in the area in which the n-well 123 is to be formed. Further implementation of channel ion implantation. The resist mask is then removed. Ion implantation of the p-well 121 is performed using boron (B) as an ion implantation species. In this ion implantation, the implantation energy is set to, for example, about 200 keV and the dose is set to, for example, 1 × 10 13 cm -2 . Channel ion implantation is performed on p-well 121 using boron (B) as an ion implantation species. In this channel ion implantation, the implantation energy is set to be, for example, in the range of about 10 to 20 keV and the dose is set to be, for example, in the range of 1 × 10 11 to 1 × 10 13 cm -2 . Ion implantation of n well 123 is performed using, for example, phosphorus (P) as an ion implantation species. In this ion implantation, the implantation energy is set to be, for example, in the range of about 200 keV and the dose is set to, for example, 1 × 10 13 cm -2 . Channel ion implantation is performed on the n-well 123 using, for example, arsenic (As) as an ion implantation species. In this channel ion implantation, the implantation energy is set to, for example, about 100 keV and the dose is set to be, for example, in the range of 1 × 10 11 to 1 × 10 13 cm -2 . Further, although not shown in the drawings, ion implantation for forming a photodiode in the photoelectric conversion portion is performed to form a p-type region. For example, ion implantation of boron (B) is performed on one surface of the semiconductor substrate in which the photoelectric conversion region is to be formed. Ion implantation is further carried out in a deep region using arsenic (As) or phosphorus (P) to form an n-type region which forms a junction with a lower portion of the p-type region. Therefore, a photoelectric conversion portion having a pn junction is formed.
接下來，如圖12中所示，藉由例如濕蝕刻來移除墊氧化物膜111(參見圖11)。接下來，在半導體基板11上形成一具有一針對一高壓之大厚度之閘極絕緣膜51H。閘極絕緣膜51H之厚度在一針對一3.3 V之電力供應電壓之電晶體中為約7.5 nm，而在一針對一2.5 V之電力供應電壓之電晶體中為約5.5 nm。接著，在具有一針對一高壓之大厚度之閘極絕緣膜51H上形成一抗蝕劑遮罩(未顯示)，並移除具有一形成於一針對一低壓之電晶體區上之大厚度之閘極絕緣膜51H。在移除該抗蝕劑遮罩之後，在半導體基板11上之針對一低壓之電晶體區中形成一具有一小厚度之閘極絕緣膜51L。閘極絕緣膜51L之厚度在一針對一1.0 V之電力供應電壓之電晶體中介於約1.2至1.8 nm之範圍內。同時在該像素部分中之電晶體形成區中形成一具有一小厚度之閘極絕緣膜31(未顯示)。閘極絕緣膜51H、51L及31中之每一者皆係由例如一熱氧化矽膜組成。另一選擇係，閘極絕緣膜51H、51L及31中之每一者可由一藉由快速熱氧化(RTO)生長而成之氧氮化矽膜組成。另一選擇係，為了進一步減小一閘極洩漏，可使用一高介電膜，例如一氧化物膜或一由鉿(Hf)、鋯(Zr)或類似物組成之氧氮化物膜。在後續圖中，為了方便起見，將具有一大厚度之閘極絕緣膜51H及具有一小厚度之閘極絕緣膜51L顯示為具有相同厚度之膜。 Next, as shown in FIG. 12, the pad oxide film 111 is removed by, for example, wet etching (see FIG. 11). Next, a gate insulating film 51H having a large thickness for a high voltage is formed on the semiconductor substrate 11. The thickness of the gate insulating film 51H is about 7.5 nm in a transistor for a power supply voltage of 3.3 V, and about 5.5 nm in a transistor for a power supply voltage of 2.5 V. Next, a resist mask (not shown) is formed on the gate insulating film 51H having a large thickness for a high voltage, and is removed to have a large thickness formed on a region of the transistor for a low voltage. Gate insulating film 51H. After the resist mask is removed, a gate insulating film 51L having a small thickness is formed on the semiconductor substrate 11 for a low voltage transistor region. The thickness of the gate insulating film 51L is in the range of about 1.2 to 1.8 nm in a transistor for a power supply voltage of 1.0 V. At the same time, a gate insulating film 31 (not shown) having a small thickness is formed in the transistor formation region in the pixel portion. Each of the gate insulating films 51H, 51L, and 31 is composed of, for example, a thermal yttrium oxide film. Alternatively, each of the gate insulating films 51H, 51L, and 31 may be composed of a hafnium oxynitride film grown by rapid thermal oxidation (RTO). Alternatively, in order to further reduce a gate leakage, a high dielectric film such as an oxide film or an oxynitride film composed of hafnium (Hf), zirconium (Zr) or the like may be used. In the subsequent drawings, for the sake of convenience, a gate insulating film 51H having a large thickness and a gate insulating film 51L having a small thickness are shown as films having the same thickness.
接下來，如圖13之像素部分之剖視圖及圖14之周邊電路部分之剖視圖中所示，在閘極絕緣膜51(51H及51L)及閘極絕緣膜31上形成一閘極電極形成膜131。閘極電極形成膜131係藉由例如一LP-CVD方法 來沈積多晶矽而形成。該沈積膜厚度取決於技術節點，但在一90-nm節點中介於150至200 nm之範圍內。膜厚度趨於針對每一節點而減小，此乃因從該過程之可控性之觀點出發，通常不增大一閘極長寬比。作為一對抗閘極空乏之措施，可使用矽鍺(SiGe)來代替多晶矽。閘極空乏係指下面一個問題：因一閘極氧化物膜之厚度減小，故不僅該閘極氧化物膜之實體厚度之一效應而且一閘極多晶矽中之一空乏層之厚度之一效應不可忽視，且因此不減小該閘極氧化物膜之一有效厚度，從而使電晶體效能退化。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 13 and the cross-sectional view of the peripheral circuit portion of FIG. 14, a gate electrode forming film 131 is formed on the gate insulating film 51 (51H and 51L) and the gate insulating film 31. . The gate electrode forming film 131 is by, for example, an LP-CVD method It is formed by depositing polycrystalline germanium. The thickness of the deposited film depends on the technology node, but is in the range of 150 to 200 nm in a 90-nm node. The film thickness tends to decrease for each node, since a gate aspect ratio is generally not increased from the viewpoint of controllability of the process. As a measure against gate depletion, germanium (SiGe) can be used instead of polysilicon. The gate depletion refers to the following problem: because the thickness of a gate oxide film is reduced, not only one effect of the physical thickness of the gate oxide film but also one of the thicknesses of one of the gate polysilicon layers It cannot be ignored, and therefore does not reduce the effective thickness of one of the gate oxide films, thereby degrading the transistor performance.
接下來，如圖15之像素部分之剖視圖及圖16之周邊電路部分之剖視圖中所示，採取一對抗閘極空乏之措施。首先，在一p-MOS電晶體形成區上形成一抗蝕劑遮罩132，並隨後將一n型雜質摻雜至一n-MOS電晶體形成區中之閘極電極形成膜131中。此摻雜係藉由例如磷(P)或砷(As)之離子植入來實施。所植入離子之量介於約1×1015至1×1016 cm-2之範圍內。隨後移除抗蝕劑遮罩132。接下來，儘管未顯示於該等圖式中，但在該n-MOS電晶體形成區上形成一抗蝕劑遮罩(未顯示)，並將一p型雜質摻雜至該p-MOS電晶體形成區中之閘極電極形成膜131中。此摻雜係藉由例如硼(B)、二氟化硼(BF2)或銦(In)之離子植入來實施。所植入之離子量介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。可首先實施前者植入或後者植入。在上述離子植入中之每一者中，為了防止由離子植入而引入之雜質抵達該閘極絕緣膜之正下方，可組合氮(N2)之離子植入。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 15 and the cross-sectional view of the peripheral circuit portion of FIG. 16, a measure against the gate depletion is taken. First, a resist mask 132 is formed on a p-MOS transistor formation region, and then an n-type impurity is doped into the gate electrode formation film 131 in an n-MOS transistor formation region. This doping is carried out by ion implantation such as phosphorus (P) or arsenic (As). The amount of implanted ions is in the range of about 1 x 10 15 to 1 x 10 16 cm -2 . The resist mask 132 is then removed. Next, although not shown in the drawings, a resist mask (not shown) is formed on the n-MOS transistor formation region, and a p-type impurity is doped to the p-MOS The gate electrode in the crystal formation region is formed in the film 131. This doping is carried out by ion implantation such as boron (B), boron difluoride (BF 2 ) or indium (In). The amount of ions implanted is in the range of 1 x 10 15 to 1 x 10 16 cm -2 . The resist mask is then removed. The former implant or the latter implant may be performed first. In each of the above ion implantations, in order to prevent impurities introduced by ion implantation from reaching directly below the gate insulating film, nitrogen (N 2 ) ion implantation may be combined.
接下來，如圖17之像素部分之剖視圖及圖18之周邊電路部分之剖視圖中所示，在閘極電極形成膜131上形成一用於形成閘極電極之抗蝕劑遮罩(未顯示)。使用此抗蝕劑遮罩作為一蝕刻遮罩藉由反應離子蝕刻來對閘極電極形成膜131進行蝕刻處理以形成像素部分12中之MOS電晶體之閘極電極32及周邊電路部分13中之MOS電晶體之閘極 電極52。接著，氧化閘極電極32及52之表面以形成一氧化物膜133。氧化物膜133之厚度例如介於1至10 nm之範圍內。氧化物膜133不僅形成於該等側壁上而且形成於閘極電極32及52中之每一者之頂表面上。此外，在上述氧化步驟中修圓閘極電極32及52之邊緣部分具有一改善該氧化物膜之崩潰電壓之效應。另外，可藉由實施熱處理來減小蝕刻損壞。此外，在對該等閘極電極之上述處理中，即使移除形成於光電轉換部分21上之閘極絕緣膜，氧化物膜133亦形成於光電轉換部分21上。因此，當在下一微影步驟中在光電轉換部分21上形成一抗蝕劑膜時，該抗蝕劑膜不直接形成於一矽表面上，且因此可防止因此抗蝕劑而引起之污染。相應地，針對像素部分12中之光電轉換部分21，此結構充當一對抗白疵點之措施。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 17 and the cross-sectional view of the peripheral circuit portion of FIG. 18, a resist mask (not shown) for forming the gate electrode is formed on the gate electrode forming film 131. . The gate electrode forming film 131 is etched by reactive ion etching using the resist mask as an etch mask to form the gate electrode 32 of the MOS transistor in the pixel portion 12 and the peripheral circuit portion 13 Gate of MOS transistor Electrode 52. Next, the surfaces of the gate electrodes 32 and 52 are oxidized to form an oxide film 133. The thickness of the oxide film 133 is, for example, in the range of 1 to 10 nm. The oxide film 133 is formed not only on the sidewalls but also on the top surface of each of the gate electrodes 32 and 52. Further, the edge portions of the rounded gate electrodes 32 and 52 in the above oxidation step have an effect of improving the breakdown voltage of the oxide film. In addition, etching damage can be reduced by performing heat treatment. Further, in the above-described processing of the gate electrodes, the oxide film 133 is formed on the photoelectric conversion portion 21 even if the gate insulating film formed on the photoelectric conversion portion 21 is removed. Therefore, when a resist film is formed on the photoelectric conversion portion 21 in the next lithography step, the resist film is not directly formed on a crucible surface, and thus contamination due to the resist can be prevented. Accordingly, for the photoelectric conversion portion 21 in the pixel portion 12, this structure serves as a measure against the chalk point.
接下來，如圖19之像素部分之剖視圖及圖20之周邊電路部分之剖視圖中所示，形成像素部分12中之MOS電晶體之LDD區38、39等及周邊電路部分13中之MOS電晶體之LDD區61、62、63、64等。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 19 and the cross-sectional view of the peripheral circuit portion of FIG. 20, the LDD regions 38, 39 and the like of the MOS transistor in the pixel portion 12 and the MOS transistor in the peripheral circuit portion 13 are formed. The LDD areas 61, 62, 63, 64, and the like.
首先，至於形成於周邊電路部分13中之NMOS電晶體，在半導體基板11中之閘極電極52(52N)中之每一者之兩側處形成凹處擴散層65及66。此等凹處擴散層65及66係使用例如二氟化硼(BF2)、硼(B)或銦(In)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1012至1×1014 cm-2之範圍內。此外，LDD區61及62形成於半導體基板11中之閘極電極52(52N)中之每一者之兩側處。LDD區61及62係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1013至1×1015 cm-2之範圍內。 First, as for the NMOS transistors formed in the peripheral circuit portion 13, recess diffusion layers 65 and 66 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. These recessed diffusion layers 65 and 66 are formed by ion implantation using, for example, boron difluoride (BF 2 ), boron (B) or indium (In) as an ion implantation species, and the dose thereof is set to, for example, It is in the range of 1 × 10 12 to 1 × 10 14 cm -2 . Further, LDD regions 61 and 62 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. The LDD regions 61 and 62 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 13 to 1 × 10 15 cm - Within the scope of 2 .
至於形成於像素部分12中之MOS電晶體，LDD區38及39形成於半導體基板11中之閘極電極32中之每一者之兩側處。LDD區38及39係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1013至1×1015 cm-2之範圍內。另外，可形成 若干凹處擴散層。至於形成於像素分部12中之MOS電晶體，從減小步驟數之觀點出發，可不形成該等LDD區。另一選擇係，用於形成形成於像素部分12中之MOS電晶體之LDD區之離子植入亦可起形成於周邊電路部分13中之MOS電晶體之LDD離子植入的作用。 As for the MOS transistors formed in the pixel portion 12, LDD regions 38 and 39 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11. The LDD regions 38 and 39 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose is set to, for example, between 1 × 10 13 and 1 × 10 15 cm - Within the scope of 2 . In addition, a plurality of recessed diffusion layers can be formed. As for the MOS transistor formed in the pixel division 12, the LDD regions may not be formed from the viewpoint of reducing the number of steps. Alternatively, ion implantation for forming the LDD region of the MOS transistor formed in the pixel portion 12 may function as an LDD ion implantation of the MOS transistor formed in the peripheral circuit portion 13.
至於形成於周邊電路部分13中之PMOS電晶體，在半導體基板11中之閘極電極52(52P)中之每一者之兩側處形成凹處擴散層67及68。此等凹處擴散層67及68係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1012至1×1014 cm-2之範圍內。此外，LDD區63及64形成於半導體基板11中之閘極電極52(52P)中之每一者之兩側處。LDD區63及64係使用例如二氟化硼(BF2)、硼(B)或銦(In)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1013至1×1015 cm-2之範圍內。 As for the PMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 67 and 68 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. These recessed diffusion layers 67 and 68 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 12 to 1 ×. Within the range of 10 14 cm -2 . Further, LDD regions 63 and 64 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. The LDD regions 63 and 64 are formed by ion implantation using, for example, boron difluoride (BF 2 ), boron (B), or indium (In) as an ion implantation species, and the dose thereof is set to, for example, 1 ×. 10 13 to 1 × 10 15 cm -2 .
在該周邊電路部分中之NMOS電晶體及PMOS電晶體之凹處離子植入之前，可藉由進行鍺(Ge)之離子植入來實施預非晶化作為一用於抑制植入中之通道效應之技術。此外，為了減小可造成瞬時增強擴散(TED)或諸如此類之植入瑕疵數，可在該等LDD區之形成之後添加在一介於約800℃ to 900℃之範圍內的溫度下之快速熱退火(RTA)。 Before the ion implantation of the NMOS transistor and the PMOS transistor in the peripheral circuit portion, pre-amorphization can be performed by performing ion implantation of germanium (Ge) as a channel for suppressing implantation. The technology of effects. In addition, in order to reduce the number of implant turns that can cause transient enhanced diffusion (TED) or the like, rapid thermal annealing at a temperature ranging from about 800 ° C to 900 ° C can be added after the formation of the LDD regions. (RTA).
接下來，如圖21之像素部分之剖視圖及圖22之周邊電路部分之剖視圖中所示，在像素部分12之整個表面及周邊電路部分13上形成一氧化矽(SiO2)膜134。此氧化矽膜134係藉由沈積一非摻雜矽酸鹽玻璃(NSG)膜、一低壓原矽酸四乙酯(LP-TEOS)膜、一高溫氧化(HTO)膜或類似膜而形成。氧化矽膜134經形成以具有一介於例如5至20 nm之範圍內的厚度。接下來，在氧化矽膜134上形成氮化矽膜135。此氮化矽膜135係由例如一藉由低壓光學氣相沈積(LPCVD)而形成之氮化矽膜組成。其厚度介於例如10至100 nm之範圍內。氮化矽膜135可係一藉由一可用以在一低溫下形成該膜之原子層沈積方法而形成之ALD氮化 矽膜。在像素部分12中之光電轉換部分21上，因設置於氮化矽膜135正下方之氧化矽膜134之厚度減小，故防止光反射，且因此光電轉換部分21之感光度變高。接下來，視需要在氮化矽膜135上沈積一係一第三層之氧化矽(SiO2)膜136。此氧化矽膜136係藉由沈積一NSG膜、一LP-TEOS膜、一HTO膜或類似膜而形成。氧化矽膜136經形成以具有一介於例如10至100 nm之範圍內的厚度。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 21 and the cross-sectional view of the peripheral circuit portion of FIG. 22, a tantalum oxide (SiO 2 ) film 134 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The hafnium oxide film 134 is formed by depositing an undoped tellurite glass (NSG) film, a low pressure tetraethyl orthophthalate (LP-TEOS) film, a high temperature oxidation (HTO) film or the like. The hafnium oxide film 134 is formed to have a thickness in the range of, for example, 5 to 20 nm. Next, a tantalum nitride film 135 is formed on the hafnium oxide film 134. The tantalum nitride film 135 is composed of, for example, a tantalum nitride film formed by low pressure optical vapor deposition (LPCVD). Its thickness is, for example, in the range of 10 to 100 nm. The tantalum nitride film 135 may be an ALD tantalum nitride film formed by an atomic layer deposition method which can form the film at a low temperature. In the photoelectric conversion portion 21 in the pixel portion 12, since the thickness of the ruthenium oxide film 134 disposed directly under the tantalum nitride film 135 is reduced, light reflection is prevented, and thus the sensitivity of the photoelectric conversion portion 21 becomes high. Next, a third layer of yttrium oxide (SiO 2 ) film 136 is deposited on the tantalum nitride film 135 as needed. This ruthenium oxide film 136 is formed by depositing an NSG film, an LP-TEOS film, an HTO film or the like. The hafnium oxide film 136 is formed to have a thickness ranging, for example, from 10 to 100 nm.
相應地，形成一側壁膜137作為一具有氧化矽膜136/氮化矽膜135/氧化矽膜134之結構之三層式膜。另一選擇係，側壁膜137可係一具有氮化矽膜/氧化矽膜之結構之兩層式膜。下文將闡述具有該三層式結構之側壁膜137之一情形。 Accordingly, a sidewall film 137 is formed as a three-layer film having a structure of a hafnium oxide film 136 / a tantalum nitride film 135 / a hafnium oxide film 134. Alternatively, the sidewall film 137 may be a two-layer film having a structure of a tantalum nitride film/yttria film. A case of the side wall film 137 having the three-layer structure will be explained below.
接下來，如圖23之像素部分之剖視圖及圖24之周邊電路部分之剖視圖中所示，對提供作為該頂層之氧化矽膜136實施回蝕刻以使氧化矽膜136僅留在閘極電極32及52等中之每一者之側部分上。該回蝕刻係藉由例如反應離子蝕刻(RIE)來實施。在此回蝕刻中，使用氮化矽膜135來止擋蝕刻。由於該蝕刻由氮化矽膜135以此方式止擋，因此可減小像素部分12中之光電轉換部分21上之蝕刻損壞，且因此可減小白疵點數。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 23 and the cross-sectional view of the peripheral circuit portion of FIG. 24, the ruthenium oxide film 136 provided as the top layer is etched back to leave the yttrium oxide film 136 only at the gate electrode 32. And on the side of each of 52 and so on. This etch back is performed by, for example, reactive ion etching (RIE). In this etch back, a tantalum nitride film 135 is used to stop the etching. Since the etching is stopped by the tantalum nitride film 135 in this manner, the etching damage on the photoelectric conversion portion 21 in the pixel portion 12 can be reduced, and thus the number of chalk dots can be reduced.
接下來，如圖25之像素部分之剖視圖及圖26之周邊電路部分之剖視圖中所示，在像素部分12中之光電轉換部分21之整個表面及傳送閘TRG之一部分上形成一抗蝕劑遮罩138。接下來，對氮化矽膜135及氧化矽膜134實施回蝕刻以形成一位於閘極電極32中之每一者之側壁上之第一側壁33及一位於閘極電極52中之每一者之側壁上之第二側壁53，第一側壁33及第二側壁53係由氧化矽膜134、氮化矽膜135及氧化矽膜136組成。在此步驟中，位於光電轉換部分21上之氮化矽膜135及氧化矽膜134因其由抗蝕劑遮罩138覆蓋而未被蝕刻。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 25 and the cross-sectional view of the peripheral circuit portion of FIG. 26, a resist is formed on the entire surface of the photoelectric conversion portion 21 in the pixel portion 12 and a portion of the transfer gate TRG. Cover 138. Next, the tantalum nitride film 135 and the tantalum oxide film 134 are etched back to form a first sidewall 33 on the sidewall of each of the gate electrodes 32 and a gate electrode 52. The second sidewall 53 on the sidewall, the first sidewall 33 and the second sidewall 53 are composed of a hafnium oxide film 134, a tantalum nitride film 135, and a hafnium oxide film 136. In this step, the tantalum nitride film 135 and the hafnium oxide film 134 on the photoelectric conversion portion 21 are not etched because they are covered by the resist mask 138.
接下來，如圖27之像素部分之剖視圖及圖28之周邊電路部分之 剖視圖中所示，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成周邊電路部分13中之NMOS電晶體之區中。使用該抗蝕劑遮罩藉由離子植入在其中欲形成周邊電路部分13中之NMOS電晶體之區中形成深源極-汲極區54(54N)及55(55N)。特定而言，源極-汲極區54N及55N形成於半導體基板11中之閘極電極52中之每一者之兩側處，而LDD區61、62等位於其之間。源極-汲極區54N及55N係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 27 and the cross-sectional view of the peripheral circuit portion of FIG. 28, a resist mask (not shown) having an opening in which the peripheral circuit portion is to be formed is formed. In the area of the NMOS transistor in the 13th. The deep source-drain regions 54 (54N) and 55 (55N) are formed in the region in which the NMOS transistors in the peripheral circuit portion 13 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 54N and 55N are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 61, 62 and the like interposed therebetween. The source-drain regions 54N and 55N are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 ×. Within the range of 10 16 cm -2 . The resist mask is then removed.
接下來，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成像素部分12中之NMOS電晶體之區中。使用該抗蝕劑遮罩藉由離子植入在其中欲形成像素部分12中之NMOS電晶體之區中形成深源極-汲極區34及35。特定而言，源極-汲極區34及35形成於半導體基板11中之閘極電極32中之每一者之兩側處，而LDD區38、39等位於其之間。此處，毗鄰於傳送閘TRG之源極-汲極區35起一浮動擴散的作用。源極-汲極區34及35係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。此離子植入亦可起用於形成周邊電路部分13中之NMOS電晶體之源極-汲極區54N及55N之離子植入的作用。在闡述於相關技術中所述之文獻'421中之源極-汲極區之形成期間，經由三層來實施一個離子植入，而在沒有此等層之情況下直接實施另一離子植入。相應地，難以同時實施此等離子植入。 Next, a resist mask (not shown) having an opening is formed in a region in which the NMOS transistor in the pixel portion 12 is to be formed. The deep source-drain regions 34 and 35 are formed in the region in which the NMOS transistors in the pixel portion 12 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 34 and 35 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11, with the LDD regions 38, 39 and the like interposed therebetween. Here, the source-drain region 35 adjacent to the transfer gate TRG functions as a floating diffusion. The source-drain regions 34 and 35 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 ×. Within the range of 10 16 cm -2 . The resist mask is then removed. This ion implantation can also function as an ion implantation for forming the source-drain regions 54N and 55N of the NMOS transistor in the peripheral circuit portion 13. During the formation of the source-drain region in the document '421 described in the related art, one ion implantation is performed via three layers, and another ion implantation is directly performed without such layers. . Accordingly, it is difficult to implement this plasma implantation at the same time.
接下來，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成周邊電路部分13中之PMOS電晶體之區中。使用該抗蝕劑遮罩藉由離子植入在其中欲形成周邊電路部分13中之PMOS電晶體之區中形成深源極-汲極區54(54P)及55(55P)。特定而言，源極-汲極 區54P及55P形成於半導體基板11中之閘極電極52中之每一者之兩側處，而LDD區63、64等位於其之間。源極-汲極區54P及55P係使用例如硼(B)或二氟化硼(BF2)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。接下來，對該等源極-汲極區實施活化退火。此活化退火係在一介於例如約800℃至1,100℃之範圍內的溫度下實施。針對此活化退火，可使用一快速熱退火(RTA)設備、一尖峰式RTA設備或類似設備。 Next, a resist mask (not shown) having an opening is formed in a region in which the PMOS transistor in the peripheral circuit portion 13 is to be formed. The deep source-drain regions 54 (54P) and 55 (55P) are formed in the region in which the PMOS transistors in the peripheral circuit portion 13 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 54P and 55P are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 63, 64 and the like interposed therebetween. The source-drain regions 54P and 55P are formed by ion implantation using, for example, boron (B) or boron difluoride (BF 2 ) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 × 10 16 cm -2 . The resist mask is then removed. Next, activation annealing is performed on the source-drain regions. This activation anneal is carried out at a temperature ranging, for example, from about 800 ° C to 1,100 ° C. For this activation anneal, a rapid thermal annealing (RTA) device, a spiked RTA device, or the like can be used.
在對該等源極-汲極區進行活化退火之前，將覆蓋光電轉換部分21之側壁膜137與由像素部分12中之MOS電晶體之閘極電極32上之側壁膜137組成之側壁33分隔開。此結構防止一因相關技術中所述之應力記憶技術(SMT)而引起之應力之退化。相應地，可抑制白疵點、隨機雜訊及諸如此類。此外，光電轉換部分21由側壁膜137覆蓋，且在用於形成源極-汲極區之離子植入中所使用之抗蝕劑遮罩形成於光電轉換部分21上，而側壁膜137位於其之間。換句話說，該抗蝕劑遮罩不直接形成於光電轉換部分21之表面上。因此，光電轉換部分21不被該抗蝕劑中之污染物污染，從而抑制白疵點數、暗電流及諸如此類的增大。另外，用於形成源極-汲極區之離子植入並非係一經由一膜之離子植入，且因此可設定源極-汲極區之深度同時保證表面處之一高濃度。因此，可抑制源極-汲極區之串聯電阻之增大。此外，在後續步驟中，使用覆蓋光電轉換部分21之側壁膜137作為一第一矽化物阻斷膜71。 The sidewall film 137 covering the photoelectric conversion portion 21 and the sidewall 33 composed of the sidewall film 137 on the gate electrode 32 of the MOS transistor in the pixel portion 12 are divided before the activation annealing of the source-drain regions. Separated. This structure prevents degradation of stress caused by stress memory technology (SMT) as described in the related art. Accordingly, chalk spots, random noise, and the like can be suppressed. Further, the photoelectric conversion portion 21 is covered by the sidewall film 137, and a resist mask used in ion implantation for forming a source-drain region is formed on the photoelectric conversion portion 21, and the sidewall film 137 is located thereon between. In other words, the resist mask is not directly formed on the surface of the photoelectric conversion portion 21. Therefore, the photoelectric conversion portion 21 is not contaminated by the contaminants in the resist, thereby suppressing the increase in chalk dots, dark current, and the like. In addition, the ion implantation used to form the source-drain region is not ion implantation through a film, and thus the depth of the source-drain region can be set while ensuring a high concentration at the surface. Therefore, an increase in the series resistance of the source-drain region can be suppressed. Further, in the subsequent step, the sidewall film 137 covering the photoelectric conversion portion 21 is used as a first vaporization blocking film 71.
接下來，如圖29之像素部分之剖視圖及圖30之周邊電路部分之剖視圖中所示，在像素部分12之整個表面及周邊電路部分13上形成一第二矽化物阻斷膜72。第二矽化物阻斷膜72係由一包括一氧化矽(SiO2)膜140及氮化矽膜139之堆疊膜組成。舉例而言，氧化矽膜140經 形成以具有一介於例如5至40 nm之範圍內的厚度，且氮化矽膜139經形成以具有一介於例如5至60 nm之範圍內的厚度。氧化矽膜140係由一NSG膜、一LP-TEOS膜、一HTO膜或類似膜組成。氮化矽膜139係由一ALD-SiN膜、一氮化電漿膜、一LP-SiN膜或類似膜組成。若該兩個膜之沈積溫度為高，則硼之去活化出現在PMOSFET之閘極電極中。因而，該等PMOSFET之一電流驅動能力因閘極空乏而降低。相應地，氧化矽膜140及氮化矽膜139之沈積溫度較佳低於側壁膜137之沈積溫度。該沈積溫度較佳例如處於700℃或更低下。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 29 and the cross-sectional view of the peripheral circuit portion of FIG. 30, a second germanide blocking film 72 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The second telluride blocking film 72 is composed of a stacked film including a tantalum oxide (SiO 2 ) film 140 and a tantalum nitride film 139. For example, the hafnium oxide film 140 is formed to have a thickness ranging from, for example, 5 to 40 nm, and the tantalum nitride film 139 is formed to have a thickness ranging from, for example, 5 to 60 nm. The ruthenium oxide film 140 is composed of an NSG film, an LP-TEOS film, an HTO film or the like. The tantalum nitride film 139 is composed of an ALD-SiN film, a nitride film, an LP-SiN film or the like. If the deposition temperature of the two films is high, deactivation of boron occurs in the gate electrode of the PMOSFET. Thus, one of the PMOSFETs has a current drive capability that is reduced due to gate depletion. Accordingly, the deposition temperature of the yttrium oxide film 140 and the tantalum nitride film 139 is preferably lower than the deposition temperature of the sidewall film 137. The deposition temperature is preferably, for example, at 700 ° C or lower.
接下來，如圖31之像素部分之剖視圖及圖32之周邊電路部分之剖視圖中所示，形成一抗蝕劑遮罩141以大致覆蓋其中形成像素部分12中之MOS電晶體之區。使用此抗蝕劑遮罩141作為一蝕刻遮罩藉由蝕刻來移除位於像素部分12中之光電轉換部分21(及於傳送閘TRG之一部分上)上及周邊電路部分13上之第二矽化物阻斷膜72。由此，自該頂層，氮化矽膜135及氧化矽膜134按彼次序設置於光電轉換部分21上，且因此可防止光譜漣波。與此相反，若不實施上述蝕刻，則自該頂層，氮化矽膜139、氧化矽膜140、氮化矽膜135及氧化矽膜134按彼次序設置於光電轉換部分21上。在此種情況下，入射光經受多次反射，從而使光譜漣波特性退化。由於使該等漣波特性退化，因此晶片-晶片光譜變化增大。為了解決此問題，在此實施例中，故意移除光電轉換部分21上之第二矽化物阻斷膜72。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 31 and the cross-sectional view of the peripheral circuit portion of FIG. 32, a resist mask 141 is formed to substantially cover the region in which the MOS transistor in the pixel portion 12 is formed. The resist mask 141 is used as an etch mask to remove the second morphing on the photoelectric conversion portion 21 (and on one portion of the transfer gate TRG) and the peripheral circuit portion 13 in the pixel portion 12 by etching. The membrane 72 is blocked. Thereby, from the top layer, the tantalum nitride film 135 and the tantalum oxide film 134 are disposed on the photoelectric conversion portion 21 in this order, and thus spectral chopping can be prevented. On the contrary, if the etching is not performed, the tantalum nitride film 139, the hafnium oxide film 140, the tantalum nitride film 135, and the hafnium oxide film 134 are provided on the photoelectric conversion portion 21 in this order from the top layer. In this case, the incident light is subjected to multiple reflections, thereby degrading the spectral chopping characteristics. Due to the degradation of these chopping characteristics, the wafer-wafer spectral variation increases. In order to solve this problem, in this embodiment, the second vaporization blocking film 72 on the photoelectric conversion portion 21 is intentionally removed.
接下來，如圖33之像素部分之剖視圖及圖34之周邊電路部分之剖視圖中所示，分別在周邊電路部分13中之MOS電晶體50中之每一者之源極-汲極區54及55以及閘極電極52上形成矽化層56、57及58。矽化層56、57及58係由矽化鈷(CoSi2)、矽化鎳(NiSi)、矽化鈦(TiSi2)、矽化鉑(PtSi)、矽化鎢(WSi2)或類似物組成。將闡述矽化鎳之形成之一實例作為矽化層56、57及58之形成之一實例。首先，在整個膜上形 成一鎳(Ni)膜。此鎳膜係使用一濺鍍設備或類似設備而形成以具有一例如10 nm之厚度。接著，在一介於約300℃至400℃之範圍內的溫度下實施一退火處理以使該鎳膜與係該下伏層之矽起反應，從而形成一矽化鎳層。然後，藉由濕蝕刻來移除未起反應的鎳。藉由此濕蝕刻，矽化層56、57及58以一自動對準方式形成於矽或多晶矽表面而不是該等絕緣膜上。接著，在一介於約500℃至600℃之範圍內的溫度下再次實施一退火處理以穩定該矽化鎳層。在上述矽化步驟中，該矽化層不形成於像素部分12中之MOS電晶體之源極-汲極區34及35以及閘極電極32上。此結構用來防止由組成光電轉換部分21上之矽化物之金屬之擴散而引起之白疵點數及暗電流之增大。相應地，除非像素部分12中之MOS電晶體之源極-汲極區34及35之表面具有一高雜質濃度，否則接觸電阻顯著增大。此實施例係有利的，因為可相對抑制接觸電阻之增大，此乃因源極-汲極區34及35之表面可具有一高雜質濃度。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 33 and the cross-sectional view of the peripheral circuit portion of FIG. 34, the source-drain region 54 of each of the MOS transistors 50 in the peripheral circuit portion 13 and Deuterated layers 56, 57 and 58 are formed on 55 and gate electrode 52. The deuterated layers 56, 57 and 58 are composed of cobalt silicide (CoSi 2 ), nickel (NiSi), titanium (TiSi 2 ), platinum (PtSi), tungsten (WSi 2 ) or the like. An example of the formation of deuterated nickel will be described as an example of the formation of deuterated layers 56, 57 and 58. First, a nickel (Ni) film is formed on the entire film. This nickel film is formed using a sputtering apparatus or the like to have a thickness of, for example, 10 nm. Next, an annealing treatment is performed at a temperature ranging from about 300 ° C to 400 ° C to cause the nickel film to react with the underlying layer to form a nickel-deposited layer. The unreacted nickel is then removed by wet etching. By this wet etching, the deuterated layers 56, 57 and 58 are formed on the tantalum or polysilicon surface in an automatic alignment manner instead of the insulating films. Next, an annealing treatment is again performed at a temperature ranging from about 500 ° C to 600 ° C to stabilize the nickel telluride layer. In the above-described deuteration step, the deuterated layer is not formed on the source-drain regions 34 and 35 and the gate electrode 32 of the MOS transistor in the pixel portion 12. This structure serves to prevent an increase in the number of white spots and dark current caused by the diffusion of the metal constituting the telluride on the photoelectric conversion portion 21. Accordingly, unless the surface of the source-drain regions 34 and 35 of the MOS transistor in the pixel portion 12 has a high impurity concentration, the contact resistance is remarkably increased. This embodiment is advantageous because the increase in contact resistance can be relatively suppressed because the surface of the source-drain regions 34 and 35 can have a high impurity concentration.
接下來，如圖35之像素部分之剖視圖及圖36之周邊電路部分之剖視圖中所示，在像素部分12之整個表面及周邊電路部分13上形成一蝕刻止擋膜74。蝕刻止擋膜74係由例如氮化矽膜組成。舉例而言，使用一藉由一減壓CVD方法沈積而成之氮化矽膜或一藉由一電漿CVD方法沈積而成之氮化矽膜作為此氮化矽膜。該氮化矽膜之厚度例如介於10至100 nm之範圍內。此氮化矽膜具有一使在用於形成接觸孔之蝕刻期間之過蝕刻最小化之效應。此外，此氮化矽膜具有一抑制因蝕刻損壞而引起之接面洩漏之增大之效應。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 35 and the cross-sectional view of the peripheral circuit portion of FIG. 36, an etch stop film 74 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The etch stop film 74 is composed of, for example, a tantalum nitride film. For example, a tantalum nitride film deposited by a reduced pressure CVD method or a tantalum nitride film deposited by a plasma CVD method is used as the tantalum nitride film. The thickness of the tantalum nitride film is, for example, in the range of 10 to 100 nm. This tantalum nitride film has an effect of minimizing overetching during etching for forming contact holes. Further, the tantalum nitride film has an effect of suppressing an increase in junction leakage due to etching damage.
接下來，如圖37之像素部分之剖視圖及圖38之周邊電路部之剖視圖中所示，在蝕刻止擋膜74上形成一層間絕緣膜76。層間絕緣膜76係由例如氧化矽膜組成且具有一例如介於100至1,000 nm之範圍內的厚度。該氧化矽膜係藉由例如一CVD方法而形成。使用一原矽酸四乙酯(TEOS)膜、一磷矽酸鹽玻璃(PSG)膜、一硼磷矽酸鹽(BPSG)膜或類 似膜作為此氧化矽膜。另一選擇係，亦可使用氮化矽膜或類似膜。接下來，平坦化層間絕緣層76之表面。此平坦化係藉由例如化學機械研磨(CMP)來實施。接下來，形成一用於形成接觸孔之抗蝕劑遮罩(未顯示)接著，藉由例如蝕刻像素部分12中之層間絕緣膜76、蝕刻止擋膜74及第二矽化物阻斷膜72來形成接觸孔77、78及79。同樣地，在周邊電路部分13中形成接觸孔81及82。在像素部分12中，作為一實例，分別抵達傳送閘TRG、重設電晶體RST之閘極電極32及放大電晶體Amp之閘極電極32之接觸孔77、78及79顯示於圖37中。在周邊電路部分13中，作為一實例，分別抵達一N通道(Nch)低崩潰電壓電晶體之源極-汲極區55及一P通道(Pch)低崩潰電壓電晶體之源極-汲極區55之接觸孔81及82顯示於圖38中。然而，同時亦形成抵達其他電晶體之閘極電極及源極-汲極區之接觸孔，但其未顯示於該等圖式中。在形成接觸孔77至79、81及82時，在一第一步驟中，蝕刻層間絕緣膜76。該蝕刻被暫時止擋於蝕刻止擋膜74上。由此，可吸收層間絕緣膜76之厚度之變化、該蝕刻之變化及類似變化。在一第二步驟中，蝕刻由氮化矽組成之蝕刻止擋膜74，並進一步繼續蝕刻以完成接觸孔77至79、81及82。舉例而言，使用一反應離子蝕刻設備來蝕刻該等接觸孔。 Next, as shown in the cross-sectional view of the pixel portion of FIG. 37 and the cross-sectional view of the peripheral circuit portion of FIG. 38, an interlayer insulating film 76 is formed on the etching stopper film 74. The interlayer insulating film 76 is composed of, for example, a hafnium oxide film and has a thickness of, for example, in the range of 100 to 1,000 nm. The ruthenium oxide film is formed by, for example, a CVD method. Use a tetraethyl orthophthalate (TEOS) membrane, a monophosphoric acid phosphate (PSG) membrane, a borophosphonate (BPSG) membrane or a class A film like this is used as the yttrium oxide film. Alternatively, a tantalum nitride film or the like may be used. Next, the surface of the interlayer insulating layer 76 is planarized. This planarization is performed by, for example, chemical mechanical polishing (CMP). Next, a resist mask (not shown) for forming a contact hole is formed, followed by, for example, etching the interlayer insulating film 76, the etch stop film 74, and the second germanide blocking film 72 in the pixel portion 12. Contact holes 77, 78, and 79 are formed. Similarly, contact holes 81 and 82 are formed in the peripheral circuit portion 13. In the pixel portion 12, as an example, the contact holes 77, 78, and 79 which respectively reach the transfer gate TRG, the gate electrode 32 of the reset transistor RST, and the gate electrode 32 of the amplifying transistor Amp are shown in FIG. In the peripheral circuit portion 13, as an example, respectively reach the source-drain region 55 of an N-channel (Nch) low breakdown voltage transistor and the source-drain of a P-channel (Pch) low breakdown voltage transistor. Contact holes 81 and 82 of the region 55 are shown in FIG. However, contact holes reaching the gate electrode and the source-drain region of other transistors are also formed, but they are not shown in the drawings. In forming the contact holes 77 to 79, 81 and 82, the interlayer insulating film 76 is etched in a first step. This etching is temporarily stopped on the etch stop film 74. Thereby, the change in the thickness of the interlayer insulating film 76, the change in the etching, and the like can be absorbed. In a second step, an etch stop film 74 composed of tantalum nitride is etched, and etching is further continued to complete the contact holes 77 to 79, 81 and 82. For example, a reactive ion etching apparatus is used to etch the contact holes.
接下來，在接觸孔77至79、81及82中之每一者內部形成一塞柱85，而一黏著層(未顯示)及一障壁金屬層84位於其之間。作為該黏著層，例如，使用一鈦(Ti)膜或一鉭(Ta)膜。作為障壁金屬層84，例如，使用一氮化鈦膜或一氮化鉭膜。此等膜係藉由例如一濺鍍方法或一CVD方法而形成。塞柱85係由鎢(W)組成。舉例而言，在層間絕緣膜76上形成一鎢膜以用該鎢膜來填充接觸孔77至79、81及82。隨後移除設置於層間絕緣膜76上之鎢膜。因此，由該鎢膜組成之塞柱85形成於接觸孔77至79、81及82中之每一者中。代替鎢，塞柱85可由例如具有一低於鎢之電阻之電阻之鋁(Al)或銅(Cu)組成。舉例而言，當使用 銅(Cu)作為塞柱85時，例如，使用一鉭膜作為該黏著層並使用一氮化鉭膜作為障壁金屬層84。接著，儘管未顯示於該等圖式中，但形成多層佈線。若必要，則可使佈線層數增大至兩層、三層、四層等等。 Next, a plug 85 is formed inside each of the contact holes 77 to 79, 81 and 82, and an adhesive layer (not shown) and a barrier metal layer 84 are interposed therebetween. As the adhesive layer, for example, a titanium (Ti) film or a tantalum (Ta) film is used. As the barrier metal layer 84, for example, a titanium nitride film or a tantalum nitride film is used. These films are formed by, for example, a sputtering method or a CVD method. The plug 85 is composed of tungsten (W). For example, a tungsten film is formed on the interlayer insulating film 76 to fill the contact holes 77 to 79, 81, and 82 with the tungsten film. The tungsten film provided on the interlayer insulating film 76 is then removed. Therefore, a plug 85 composed of the tungsten film is formed in each of the contact holes 77 to 79, 81, and 82. Instead of tungsten, the plug 85 may be composed of, for example, aluminum (Al) or copper (Cu) having a resistance lower than that of tungsten. For example, when using When copper (Cu) is used as the plug 85, for example, a tantalum film is used as the adhesive layer and a tantalum nitride film is used as the barrier metal layer 84. Next, although not shown in the drawings, a multilayer wiring is formed. If necessary, the number of wiring layers can be increased to two, three, four, and the like.
接下來，如圖39之像素部分之剖視圖中所示，可在光電轉換部分21上形成一波導23。另外，為了將入射光聚焦至光電轉換部分21，可形成一聚焦透鏡25。可在波導23與聚焦透鏡25之間形成一用於光譜分離光之濾色片27。 Next, as shown in a cross-sectional view of the pixel portion of Fig. 39, a waveguide 23 can be formed on the photoelectric conversion portion 21. In addition, in order to focus the incident light to the photoelectric conversion portion 21, a focus lens 25 can be formed. A color filter 27 for spectrally separating light may be formed between the waveguide 23 and the focus lens 25.
在製造一固態成像裝置之上述方法(第一實例)中，像素部分12由兩層(亦即，由相同於該側壁膜之膜組成之第一矽化物阻斷膜及由一不同於第一矽化物阻斷膜之膜組成之第二矽化物阻斷膜)覆蓋。相應地，像素部分12中之MOS電晶體不由一單一矽化物阻斷膜完全覆蓋。因而，可減小隨機雜訊且亦可減小白疵點數及暗電流。 In the above method (first example) for manufacturing a solid-state imaging device, the pixel portion 12 is composed of two layers (that is, a first telluride blocking film composed of a film identical to the sidewall film and different from the first The second telluride blocking film of the film composition of the telluride blocking film is covered. Accordingly, the MOS transistor in the pixel portion 12 is not completely covered by a single telluride blocking film. Thus, random noise can be reduced and white point and dark current can be reduced.
在上述製造方法中，形成參照圖3、4及5B所述之固態成像裝置1(1B)。在該製造方法中，當不形成像素部分12中之傳送閘TRG、重設電晶體RST、放大電晶體Amp與選擇電晶體SEL之間的隔離區14時，形成上文所述之固態成像裝置1(1A)。在此種情況下，浮動擴散部分FD為係重設電晶體RST之雜質擴散層之一的源極-汲極區34所共有。 In the above manufacturing method, the solid-state imaging device 1 (1B) described with reference to Figs. 3, 4, and 5B is formed. In the manufacturing method, when the isolation region 14 between the transfer gate TRG, the reset transistor RST, the amplification transistor Amp, and the selection transistor SEL in the pixel portion 12 is not formed, the above-described solid-state imaging device is formed 1 (1A). In this case, the floating diffusion portion FD is shared by the source-drain region 34 which is one of the impurity diffusion layers of the reset transistor RST.
在對該固態成像裝置及製造該固態成像裝置之方法之上述說明中，已闡述一其中針對第一像素形成一單一像素電晶體部分(包括，例如，一重設電晶體、一放大電晶體及一選擇電晶體)之結構。本發明之該實施例不僅適用於一具有一個像素-一個像素部分之此一結構之固態成像裝置而且同樣適用於一具有一其中兩個像素由一單一像素電晶體部分分享之結構之固態成像裝置、一具有一其中四個像素由一單一像素電晶體部分分享之結構之固態成像裝置、以及製造此等固態成像裝置之方法。 In the above description of the solid-state imaging device and the method of manufacturing the solid-state imaging device, a single pixel transistor portion (including, for example, a reset transistor, an amplifying transistor, and a first pixel) is formed for the first pixel. Select the structure of the transistor). This embodiment of the present invention is applicable not only to a solid-state imaging device having such a structure of one pixel to one pixel portion but also to a solid-state imaging device having a structure in which two pixels are shared by a single pixel transistor portion. A solid-state imaging device having a structure in which four pixels are shared by a single pixel transistor portion, and a method of manufacturing such solid-state imaging devices.
下文將對在其中例如一個像素電晶體部分分享四個像素之情況下一製造方法之要點進行說明。首先，將參照圖40之一平面佈置圖來闡述其中一個像素電晶體部分分享四個像素之結構之一實例。 The main points of the manufacturing method in the case where, for example, one pixel transistor portion shares four pixels will be described below. First, an example of a structure in which one pixel transistor portion shares four pixels will be explained with reference to a plan view of FIG.
如圖40中所示，四個像素之光電轉換部分21(21A、21B、21C及21D)配置成兩列及兩行。在光電轉換部分21之配置之中心處，一浮動擴散部分FD提供於一與光電轉換部分21中之每一者接續之作用區中。此外，傳送閘TRG(TRG-A、TRG-B、TRG-C及TRG-D)提供於光電轉換部分21中之每一者與浮動擴散部分FD之間的邊界處，而一閘極絕緣膜(未顯示)位於其之間。除位於傳送閘TRG下方之區以外，光電轉換部分21之周邊由隔離區16(其由一雜質擴散層組成)電分離。。另外，一像素電晶體部分17提供於一毗鄰於光電轉換部分21之區中，而一隔離區14位於其之間。像素電晶體部分17經組態以使例如一重設電晶體RST、一放大電晶體Amp及一選擇電晶體SEL串聯配置。 As shown in Fig. 40, the photoelectric conversion portions 21 (21A, 21B, 21C, and 21D) of four pixels are arranged in two columns and two rows. At the center of the configuration of the photoelectric conversion portion 21, a floating diffusion portion FD is provided in an active region which is continuous with each of the photoelectric conversion portions 21. Further, transfer gates TRG (TRG-A, TRG-B, TRG-C, and TRG-D) are provided at the boundary between each of the photoelectric conversion portions 21 and the floating diffusion portion FD, and a gate insulating film (not shown) is located between them. The periphery of the photoelectric conversion portion 21 is electrically separated by the isolation region 16 (which is composed of an impurity diffusion layer) except for the region under the transfer gate TRG. . Further, a pixel transistor portion 17 is provided in a region adjacent to the photoelectric conversion portion 21 with an isolation region 14 interposed therebetween. The pixel transistor portion 17 is configured such that, for example, a reset transistor RST, an amplifying transistor Amp, and a select transistor SEL are arranged in series.
下文將對在其中製造一固態成像裝置之上述方法之第一實例適用於一製造一其中一單一像素電晶體部分17由四個像素分享之固態成像裝置之方法之情況下之要點進行說明。在其中該像素電晶體部分由四個像素分享之情況下，此固態成像裝置之結構不同於藉由該製造方法之上述第一實例製造而成之固態成像裝置，因為浮動擴散部分FD形成於光電轉換部分21之配置之中心處而傳送閘TRG形成於光電轉換部分21中之每一者與浮動擴散部分FD之間。然而，此固態成像裝置之製造方法之運作相同於第一實施之運作，只是光電轉換部分21、浮動擴散部分FD及傳送閘TRG之配置不同於第一實例中之配置罷了。相應地，製造該周邊電路部分之方法相同於第一實例。下文將闡述該方法之一部分。 A description will be given below of a point in the case where the first example of the above-described method of manufacturing a solid-state imaging device is applied to a method of manufacturing a solid-state imaging device in which a single pixel transistor portion 17 is shared by four pixels. In the case where the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method because the floating diffusion portion FD is formed in the photovoltaic The transfer gate TRG is formed at the center of the configuration of the conversion portion 21 and is formed between each of the photoelectric conversion portions 21 and the floating diffusion portion FD. However, the manufacturing method of the solid-state imaging device operates in the same manner as in the first embodiment, except that the configurations of the photoelectric conversion portion 21, the floating diffusion portion FD, and the transfer gate TRG are different from those in the first example. Accordingly, the method of manufacturing the peripheral circuit portion is the same as the first example. A part of this method will be explained below.
首先，將參照圖41、42A、42B、43C、43D等來闡述一形成一側 壁之步驟。圖41係一像素部分之一平面佈置圖，圖42A係一沿圖41中線XLIIA-XLIIA剖切之剖視圖，圖42B係一沿圖41中線XLIIB-XLIIB剖切之剖視圖，圖43C係一沿圖41中線XLIIIC-XLIIIC剖切之剖視圖，且圖43D係一沿圖41中線XLIIID-XLIIID剖切之剖視圖。在形成一側壁膜膜137(第一矽化物阻斷膜71)之後，對側壁膜137實施回蝕刻以在像素電晶體部分17之每一閘極電極32及該周邊電路部分中之每一閘極電極(未顯示)之側壁上形成側壁(未顯示)。在此種情況下，使側壁膜137留在光電轉換部分21上。此乃因光電轉換部分21由一抗蝕劑遮罩(未顯示)覆蓋以使該等側壁之形成期間之蝕刻損壞不進入光電轉換部分21。一開口137H提供於一其中形成浮動擴散部分FD之區上側壁膜137中以曝露其中形成浮動擴散部分FD之區。此開口137H之一部分設置於傳送閘TRG上。 First, a side will be described with reference to FIGS. 41, 42A, 42B, 43C, 43D, and the like. The steps of the wall. Figure 41 is a plan view of a pixel portion, Figure 42A is a cross-sectional view taken along the line XLIIA-XLIIA of Figure 41, Figure 42B is a cross-sectional view taken along line XXLIB-XLIIB of Figure 41, Figure 43C is a A cross-sectional view taken along line XLIIIC-XLIIIC of Fig. 41, and Fig. 43D is a cross-sectional view taken along line XLIIID-XLIIID of Fig. 41. After forming a sidewall film 137 (first vapor blocking film 71), the sidewall film 137 is etched back to each gate electrode 32 and each of the peripheral circuit portions of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21. This is because the photoelectric conversion portion 21 is covered by a resist mask (not shown) so that the etching damage during the formation of the side walls does not enter the photoelectric conversion portion 21. An opening 137H is provided in a region of the upper sidewall film 137 in which the floating diffusion portion FD is formed to expose a region in which the floating diffusion portion FD is formed. A portion of this opening 137H is disposed on the transfer gate TRG.
接著，形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區34及35。 Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed.
接下來，將參照圖44、45A、45B、46C、46D等來闡述一後續步驟。圖44係該像素部分之一平面佈置圖，圖45A係一沿圖44中線XLVA-XLVA剖切之剖視圖，圖45B係一沿圖44中線XLVB-XLVB剖切之剖視圖，圖46C係一沿圖44中線XLVIC-XLVIC剖切之剖視圖，且圖46D係一沿圖44中線XLVID-XLVID剖切之剖視圖。在形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區之後，在該周邊電路部分中之源極-汲極區及諸如此類上形成一矽化層。在此步驟中，必要的係使該矽化層不形成於該像素電晶體部分、光電轉換部分21等上。出於此目的，在該矽化層之形成之前，形成一覆蓋像素電晶體部分17之第二矽化物阻斷膜72。在此步驟中，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於隔離區14上。在此步驟中，亦在浮動擴散部分FD上，形成第二矽化物阻斷膜72以與第一矽化物阻斷膜 71之開口137H之周邊重疊。接著，如同在第一實例中一樣，對該周邊電路部分中之MOS電晶體之閘極電極及源極-汲極區之該矽化步驟及該等後續步驟。 Next, a subsequent step will be explained with reference to FIGS. 44, 45A, 45B, 46C, 46D and the like. Figure 44 is a plan view of a portion of the pixel portion, Figure 45A is a cross-sectional view taken along line XLVA-XLVA of Figure 44, Figure 45B is a cross-sectional view taken along line XLVB-XLVB of Figure 44, Figure 46C is a A cross-sectional view taken along line XLVIC-XLVIC of Fig. 44, and Fig. 46D is a cross-sectional view taken along line XLVID-XLVID of Fig. 44. After forming the source-drain region of the transistor in the pixel portion and the peripheral circuit portion, a deuterated layer is formed on the source-drain region and the like in the peripheral circuit portion. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion, the photoelectric conversion portion 21, and the like. For this purpose, a second telluride blocking film 72 covering the pixel transistor portion 17 is formed prior to the formation of the germanide layer. In this step, the second telluride blocking film 72 is formed to overlap the first vapor blocking film 71 on the isolation region 14. In this step, also on the floating diffusion portion FD, a second vaporization blocking film 72 is formed to interact with the first vaporization blocking film. The periphery of the opening 137H of 71 overlaps. Next, as in the first example, the deuteration step and the subsequent steps of the gate electrode and the source-drain region of the MOS transistor in the peripheral circuit portion.
在上述製造方法之第一實例及第二實例中，當側壁33及53分別形成於像素部分12及周邊電路部分13中之閘極電極32及52之側壁上時，浮動擴散部分FD上之側壁膜137不由一抗蝕劑遮罩覆蓋。在其中側壁33及53藉由蝕刻而分別形成於閘極電極32及52之側壁上之情況下，蝕刻損壞可出現在浮動擴散部分FD中。 In the first and second examples of the above manufacturing method, when the side walls 33 and 53 are respectively formed on the sidewalls of the gate electrodes 32 and 52 in the pixel portion 12 and the peripheral circuit portion 13, the sidewalls on the floating diffusion portion FD Film 137 is not covered by a resist mask. In the case where the side walls 33 and 53 are respectively formed on the sidewalls of the gate electrodes 32 and 52 by etching, etching damage may occur in the floating diffusion portion FD.
下文將闡述關於蝕刻損壞之考慮事項。舉例而言，如圖47中所示，當藉由蝕刻在每一閘極電極(未顯示)之側壁上形成側壁(未顯示)時，蝕刻損壞可出現在浮動擴散部分FD中。若蝕刻損壞出現在浮動擴散部分FD中，則在一包括於浮動擴散部分FD中之p-n接面中產生一洩漏路徑，從而增大FD白疵點數。 Considerations regarding etch damage are set forth below. For example, as shown in FIG. 47, when sidewalls (not shown) are formed on the sidewalls of each of the gate electrodes (not shown) by etching, etching damage may occur in the floating diffusion portion FD. If the etching damage occurs in the floating diffusion portion FD, a leak path is generated in the p-n junction included in the floating diffusion portion FD, thereby increasing the number of FD chalk points.
此處將闡述FD白疵點。光電轉換於該光電轉換部分中之電子被傳送至浮動擴散部分FD且被轉換至一電壓。在此種情況下，在其中浮動擴散部分FD中存在一洩漏路徑之情況下，即使浮動擴散部分FD中不存在光電轉換電子，洩漏電子亦輸出且以白斑點的形式出現。此稱作「FD白疵點」。 The FD white point will be explained here. The electrons photoelectrically converted into the photoelectric conversion portion are transferred to the floating diffusion portion FD and converted to a voltage. In this case, in the case where there is a leak path in the floating diffusion portion FD, even if photoelectric conversion electrons are not present in the floating diffusion portion FD, the leaked electrons are output and appear as white spots. This is called "FD white point".
有時，使用一由一p型擴散層組成之隔離區16來分隔該等光電轉換部分(未顯示)與浮動擴散部分FD。當使用一p型擴散層來以此一方式分隔像素時，尤其，顯著增大FD白疵點數。舉例而言，此之一可能原因係在一用於活化源極-汲極區之處於1,000℃或更高下之熱處理期間之一雜質外擴散效應。舉例而言，由該熱處理期間之外擴散所散佈之雜質黏著於浮動擴散部分FD與由一p型擴散層組成之隔離區16之間。因而，形成一大的洩漏路徑，從而導致FD白疵點之產生之問題。換句話說，當一洩漏電流流向浮動擴散部分FD時，甚至在一暗 狀態下，亦看似如存在信號一般。因而，產生白疵點。看似如存在信號一般之原因如下。若上文所提及之洩漏出現在一從一其中重設浮動擴散部分FD之一電位之狀態到一對一信號電位之偵測之週期期間，則一因一洩漏電流而引起之電壓波動疊加於該重設電位上。 Sometimes, an isolating region 16 composed of a p-type diffusion layer is used to separate the photoelectric conversion portions (not shown) from the floating diffusion portion FD. When a p-type diffusion layer is used to separate pixels in this manner, in particular, the number of FD chalk points is significantly increased. For example, one of the possible causes is an impurity out-diffusion effect during heat treatment at 1,000 ° C or higher for activating the source-drain region. For example, impurities dispersed by diffusion outside the heat treatment are adhered between the floating diffusion portion FD and the isolation region 16 composed of a p-type diffusion layer. Thus, a large leak path is formed, which causes a problem of the occurrence of FD white spots. In other words, when a leakage current flows to the floating diffusion portion FD, even in a dark In the state, it also seems to be like a signal. Thus, a white point is produced. The reason that seems to be the existence of a signal is as follows. If the leakage mentioned above occurs during a period from the state in which one of the floating diffusion portions FD is reset to the detection of the one-to-one signal potential, the voltage fluctuation due to a leakage current is superimposed. At this reset potential.
在上述實例中，已對其中一單一像素電晶體部分分享四個像素之結構進行了說明。同樣地，亦在其中一像素電晶體部分分享兩個像素之情況下或在其中一像素電晶體部分經形成以對應於一個像素之情況下，蝕刻損壞可出現在浮動擴散部分FD中。 In the above examples, the structure in which a single pixel transistor portion shares four pixels has been described. Similarly, in the case where one pixel transistor portion shares two pixels or in a case where one pixel transistor portion is formed to correspond to one pixel, etching damage may occur in the floating diffusion portion FD.
下文將根據已參照圖1及2或圖3及4闡述之固態成像裝置1來闡述一其中蝕刻損壞不出現在浮動擴散部分FD中之結構。舉例而言，第一矽化物阻斷膜71經形成以覆蓋光電轉換部分21、傳送閘TRG、浮動擴散部分FD、以及重設電晶體RST之閘極電極32之一部分。在此種情況下，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於重設電晶體RST之閘極電極32上。 Hereinafter, a structure in which etching damage does not occur in the floating diffusion portion FD will be described based on the solid-state imaging device 1 which has been explained with reference to FIGS. 1 and 2 or FIGS. 3 and 4. For example, the first telluride blocking film 71 is formed to cover a portion of the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, and the gate electrode 32 of the reset transistor RST. In this case, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on the gate electrode 32 of the reset transistor RST.
藉由形成第一矽化物阻斷膜71及第二矽化物阻斷膜72以具有上述結構，當形成側壁33及該周邊電路部分中之側壁(未顯示)時，浮動擴散部分FD亦由係一側壁膜之第一矽化物阻斷膜71覆蓋。相應地，在該等側壁之形成期間，蝕刻損壞不出現在浮動擴散部分FD中。 By forming the first vapor blocking film 71 and the second vapor blocking film 72 to have the above structure, when the sidewalls 33 and the sidewalls (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also The first telluride blocking film 71 of a sidewall film is covered. Accordingly, during the formation of the sidewalls, the etching damage does not occur in the floating diffusion portion FD.
接下來，將對一具有其中一單一像素電晶體部分分享四個像素之結構之固態成像裝置之一第三實例進行說明，此固態成像裝置係參考圖40予以描述。將參照圖48、49A、49B、50C、50D等來闡述該固態成像裝置。圖48係一像素部分之一平面佈置圖，圖49A係一沿圖48中線XLIXA-XLIXA剖切之剖視圖，圖49B係一沿圖48中線XLIXB- XLIXB剖切之剖視圖，圖50C係一沿圖48中線LC-LC剖切之剖視圖，圖50D係一沿圖48中線LD-LD剖切之剖視圖。 Next, a third example of a solid-state imaging device having a structure in which one single pixel transistor portion shares four pixels will be described, which is described with reference to FIG. The solid-state imaging device will be explained with reference to FIGS. 48, 49A, 49B, 50C, 50D, and the like. Figure 48 is a plan view of a pixel portion, Figure 49A is a cross-sectional view taken along line XLIXA-XLIXA of Figure 48, and Figure 49B is a line along line XLIXB- of Figure 48. A cross-sectional view of the XLIXB cutaway, Fig. 50C is a cross-sectional view taken along line LC-LC of Fig. 48, and Fig. 50D is a cross-sectional view taken along line LD-LD of Fig. 48.
一第一矽化物阻斷膜71經形成以覆蓋光電轉換部分21、傳送閘TRG及浮動擴散部分FD。在此種情況下，一第二矽化物阻斷膜72經形成以覆蓋一上面不以第二矽化物阻斷膜72與第一矽化物阻斷膜71重疊例如於隔離區14上之方式形成第一矽化物阻斷膜71之區。 A first vaporization blocking film 71 is formed to cover the photoelectric conversion portion 21, the transfer gate TRG, and the floating diffusion portion FD. In this case, a second vaporization blocking film 72 is formed to cover an upper surface without forming a second vaporization blocking film 72 overlapping the first vapor blocking film 71, for example, on the isolation region 14. The region of the first telluride blocking film 71.
相應地，當形成像素電晶體部分17中之側壁33及該周邊電路部分中之側壁(未顯示)時，浮動擴散部分FD亦由係一側壁膜之第一矽化物阻斷膜71覆蓋。此結構可防止在該等側壁之形成期間在浮動擴散部分FD中出現蝕刻損壞。另外，此結構可防止浮動擴散部分FD接收一外擴散效應。相應地，可抑制一洩漏路徑之產生，從而抑制FD白疵點之產生。因而，此結構可實現具有高影像品質之成像。 Accordingly, when the side wall 33 in the pixel transistor portion 17 and the side wall (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vaporization blocking film 71 which is a side wall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving an external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Thus, this structure enables imaging with high image quality.
接下來，將對一具有其中一單一像素電晶體部分分享四個像素之結構之固態成像裝置之一第四實例進行說明，該固態成像裝置參照圖40來加以闡述。將參照圖51、52A、52B、53C、53D等來闡述該固態成像裝置。圖51係一像素部分之一平面佈置圖，圖52A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖52B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖53C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖53D係一沿圖51中線LIIID-LIIID剖切之剖視圖。 Next, a fourth example of a solid-state imaging device having a structure in which one single pixel transistor portion shares four pixels will be described, which is explained with reference to FIG. The solid-state imaging device will be explained with reference to FIGS. 51, 52A, 52B, 53C, 53D, and the like. Figure 51 is a plan view of a pixel portion, Figure 52A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 52B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, Figure 53C is a A cross-sectional view taken along line LIIIC-LIIIC of Fig. 51, and Fig. 53D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51.
一第一矽化物阻斷膜71經形成以覆蓋光電轉換部分21、傳送閘TRG、浮動擴散部分FD、以及重設電晶體之源極-汲極區34。在此種情況下，一第二矽化物阻斷膜72經形成以覆蓋一上面不以第二矽化物阻斷膜72與第一矽化物阻斷膜71重疊例如於隔離區14及重設電晶體RST之閘極電極32上之方式形成第一矽化物阻斷膜71之區。 A first vaporization blocking film 71 is formed to cover the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor. In this case, a second vaporization blocking film 72 is formed to cover an upper surface without overlapping the first vapor blocking film 72 with the first vapor blocking film 71, for example, in the isolation region 14 and resetting the electricity. The region of the first telluride blocking film 71 is formed in such a manner as to be on the gate electrode 32 of the crystal RST.
相應地，浮動擴散部分FD及連接至此浮動擴散部分FD之重設電 晶體RST之源極-汲極區34亦由係一側壁膜之第一矽化物阻斷膜71覆蓋。因此，當在該像素電晶體部分及該周邊電路部分(未顯示)中形成側壁時，可防止出現對浮動擴散部分FD及重設電晶體RST之源極-汲極區34之蝕刻損壞。此外，此結構可防止浮動擴散部分FD及重設電晶體RST之源極-汲極區34接收該外擴散效應。相應地，可抑制一洩漏路徑之產生，從而抑制FD白疵點之產生。因而，此結構可實現具有高影像品質之成像。 Correspondingly, the floating diffusion portion FD and the reset power connected to the floating diffusion portion FD The source-drain region 34 of the crystal RST is also covered by a first telluride blocking film 71 that is a sidewall film. Therefore, when sidewalls are formed in the pixel transistor portion and the peripheral circuit portion (not shown), etching damage to the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST can be prevented. In addition, this structure prevents the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST from receiving the external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Thus, this structure enables imaging with high image quality.
在該固態成像裝置之第三及第四實例中之每一者中，該周邊電路部分之結構相同於圖2或4中所示之結構。 In each of the third and fourth examples of the solid-state imaging device, the peripheral circuit portion has the same structure as that shown in Fig. 2 or 4.
接下來，將使用一製造一具有一其中一單一像素電晶體部分分享四個像素之結構之固態成像裝置之方法作為一實例來闡述一用於防止對一浮動擴散部分FD之蝕刻損壞之製造方法(第三實例)之要點。 Next, a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels will be used as an example to explain a manufacturing method for preventing etching damage to a floating diffusion portion FD. (The third example) points.
當該像素電晶體部分由四個像素分享時，此固態成像裝置之結構不同於藉由該製造方法之上述第一實例製造而成之固態成像裝置，因為一浮動擴散部分形成於光電轉換部分之一配置之中心處且一傳送閘形成於該等光電轉換部分中之每一者與該浮動擴散部分之間。然而，此固態成像裝置之該製造過程之運作相同於第一實例之運作，只是該等光電轉換部分、該浮動擴散部分及該等傳送閘之佈置不同於第一實例中之佈置，且一側壁膜及一第二矽化物阻斷膜之圖案形狀不同於第一實例中之圖案形狀罷了。下文將闡述該方法之一部分。 When the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method, since a floating diffusion portion is formed in the photoelectric conversion portion A transfer gate is formed at a center of a configuration between each of the photoelectric conversion portions and the floating diffusion portion. However, the manufacturing process of the solid-state imaging device operates in the same manner as the first example, except that the arrangement of the photoelectric conversion portion, the floating diffusion portion, and the transfer gates is different from the arrangement in the first example, and a side wall The pattern shape of the film and a second telluride blocking film is different from the pattern shape in the first example. A part of this method will be explained below.
首先，將參照圖54、55A、55B、56C、56D等來闡述一形成一側壁之步驟。圖54係一像素部分之一平面佈置圖，圖55A係一沿圖54中線LVA-LVA剖切之剖視圖，圖55B係一沿圖54中線LVB-LVB剖切之剖視圖，圖56C係一沿圖54中線LVIC-LVIC剖切之剖視圖，且圖56D 係一沿圖54中線LVID-LVID剖切之剖視圖。在形成一側壁膜137(第一矽化物阻斷膜71)之後，對側壁膜137實施回蝕刻以在一像素電晶體部分17之每一閘極電極32及一周邊電路部分中之每一閘極電極(未顯示)之側壁上形成側壁(未顯示)。在此種情況下，使側壁膜137留在該等光電轉換部分21及一浮動擴散部分FD(及傳送閘TRG)上。此乃因該等光電轉換部分21及該浮動擴散部分FD由一抗蝕劑遮罩(未顯示)覆蓋以使該等側壁之形成期間之蝕刻損壞不進入該等光電轉換部分21及該浮動擴散部分FD。換句話說，此方法不同於上文所述之製造方法之第一實例，只因為抗蝕劑遮罩138(參見圖25)經形成以延伸至該浮動擴散部分FD。在抗蝕劑遮罩138之形成之前的其他步驟相同於第一實例之步驟。應注意，在此級中尚未形成浮動擴散部分FD、源極-汲極區34及諸如此類。為了便於理解位置關係，浮動擴散部分FD及源極-汲極區34顯示於該等圖式中。 First, a step of forming a side wall will be described with reference to Figs. 54, 55A, 55B, 56C, 56D and the like. Figure 54 is a plan view of a pixel portion, Figure 55A is a cross-sectional view taken along line LVA-LVA of Figure 54, and Figure 55B is a cross-sectional view taken along line LVB-LVB of Figure 54, Figure 56C is a A cross-sectional view taken along line LVIC-LVIC in Figure 54, and Figure 56D A cross-sectional view taken along the line LVID-LVID in Fig. 54. After forming a sidewall film 137 (the first vaporization blocking film 71), the sidewall film 137 is etched back to each of the gate electrodes 32 and a peripheral circuit portion of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21 and a floating diffusion portion FD (and the transfer gate TRG). This is because the photoelectric conversion portion 21 and the floating diffusion portion FD are covered by a resist mask (not shown) so that etching damage during formation of the sidewalls does not enter the photoelectric conversion portion 21 and the floating diffusion. Partial FD. In other words, this method is different from the first example of the manufacturing method described above only because the resist mask 138 (see FIG. 25) is formed to extend to the floating diffusion portion FD. The other steps before the formation of the resist mask 138 are the same as those of the first example. It should be noted that the floating diffusion portion FD, the source-drain region 34, and the like have not been formed in this stage. In order to facilitate understanding of the positional relationship, the floating diffusion portion FD and the source-drain region 34 are shown in the drawings.
接著，形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區34及35。在此步驟中，由於浮動擴散部分FD由側壁膜137覆蓋，因此較佳與用於形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區之離子植入分開實施離子植入。 Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed. In this step, since the floating diffusion portion FD is covered by the sidewall film 137, ion implantation is preferably performed separately from ion implantation for forming the source-drain region of the pixel portion and the transistor in the peripheral circuit portion. In.
接下來，將參照圖57、58A、58B、59C、59D等來闡述一後續步驟。圖57係該像素部分之一平面佈置圖，圖58A係一沿圖57中線LVIIIA-LVIIIA剖切之剖視圖，圖58B係一沿圖57中線LVIIIB-LVIIIB剖切之剖視圖，圖59C係一沿圖57中線LIXC-LIXC剖切之剖視圖，且圖59D係一沿圖57中線LIXD-LIXD剖切之剖視圖。在形成像素部分12及該周邊電路部分(未顯示)中之電晶體之源極-汲極區之後，在該周邊電路部分中之源極-汲極區及諸如此類上形成一矽化層。在此步驟中，必要的係使該矽化層不形成於像素電晶體部分17、光電轉換部分21等上。出於此目的，在該矽化層之形成之前，形成一覆蓋像素電晶 體部分17之第二矽化物阻斷膜72。在此步驟中，第二矽化阻斷膜72經形成以與第一矽化物阻斷膜71重疊。此外，在其他部分中，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於一隔離區14上。接著，如同在第一實例中一樣，實施對該周邊電路部分中之閘極電極及源極-汲極區之該矽化步驟以及該等後續步驟。 Next, a subsequent step will be explained with reference to FIGS. 57, 58A, 58B, 59C, 59D, and the like. 57 is a plan view of a portion of the pixel portion, FIG. 58A is a cross-sectional view taken along line LVIIIA-LVIIIA of FIG. 57, and FIG. 58B is a cross-sectional view taken along line LVIIIB-LVIIIB of FIG. 57, and FIG. 59C is a cross-sectional view. A cross-sectional view taken along line LIXC-LIXC of Fig. 57, and Fig. 59D is a cross-sectional view taken along line LIDD-LIXD of Fig. 57. After forming the source-drain regions of the transistors in the pixel portion 12 and the peripheral circuit portion (not shown), a deuterated layer is formed on the source-drain regions in the peripheral circuit portion and the like. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion 17, the photoelectric conversion portion 21, and the like. For this purpose, a blanket pixel crystal is formed before the formation of the germanide layer The second telluride blocking film 72 of the body portion 17. In this step, the second deuterated blocking film 72 is formed to overlap the first telluride blocking film 71. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on an isolation region 14. Next, as in the first example, the deuteration step of the gate electrode and the source-drain region in the peripheral circuit portion and the subsequent steps are performed.
相應地，當形成像素電晶體部分17中之側壁33及該周邊電路部分中之側壁(未顯示)時，浮動擴散部分FD亦由係該側壁膜之第一矽化物阻斷膜71覆蓋。此結構可防止在該等側壁之形成期間在浮動擴散部分FD中出現蝕刻損壞。另外，此結構可防止浮動擴散部分FD接收該外擴散效應。相應地，可抑制一洩漏路徑之產生，從而抑制FD白疵點之產生。因此，可製造一可實現具有高影像品質之成像之固態成像裝置。此外，在該矽化層之形成之前，像素電晶體部分17可由第二矽化物阻斷膜72覆蓋。 Accordingly, when the sidewall 33 in the pixel transistor portion 17 and the sidewall (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vapor blocking film 71 which is the sidewall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving the external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Therefore, it is possible to manufacture a solid-state imaging device that can realize imaging with high image quality. Further, the pixel transistor portion 17 may be covered by the second vaporization blocking film 72 before the formation of the deuterated layer.
接下來，將使用一製造一具有一其中一單一像素電晶體部分分享四個像素之結構之固態成像裝置之方法作為一實例來闡述一用於防止對一浮動擴散部分FD之蝕刻損壞之製造方法(第四實例)之要點。 Next, a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels will be used as an example to explain a manufacturing method for preventing etching damage to a floating diffusion portion FD. (The fourth example) points.
當該像素電晶體部分由四個像素分享時，此固態成像裝置之結構不同於藉由該製造方法之上述第一實例製造而成之固態成像裝置，因為一浮動擴散部分形成於光電轉換部分之一配置之中心處且一傳送閘形成於該等光電轉換部分中之每一者與該浮動擴散部分之間。然而，此固態成像裝置之製造過程之運作相同於第一實例之運作，只是該等光電轉換部分、該浮動擴散部分及該等傳送閘之配置不同於第一實例中之配置，且一側壁膜及一第二矽化物阻斷膜之圖案形狀不同於第一實例中之圖案形狀罷了。下文將闡述該方法之一部分。 When the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method, since a floating diffusion portion is formed in the photoelectric conversion portion A transfer gate is formed at a center of a configuration between each of the photoelectric conversion portions and the floating diffusion portion. However, the manufacturing process of the solid-state imaging device operates in the same manner as the first example, except that the configurations of the photoelectric conversion portion, the floating diffusion portion, and the transfer gates are different from those in the first example, and a sidewall film And the pattern shape of a second telluride blocking film is different from the pattern shape in the first example. A part of this method will be explained below.
首先，將參照圖60、61A、61B、62C、62D等來闡述一形成一側 壁之步驟。圖60係一像素部分之一平面佈置圖，圖61A係一沿圖60中線LXIA-LXIA剖切之剖視圖，圖61B係一沿圖60中線LXIB-LXIB剖切之剖視圖，圖62C係一沿圖60中線LXIIC-LXIIC剖切之剖視圖，且圖62D係一沿圖60中線LXIID-LXIID剖切之剖視圖。在形成一側壁膜137(第一矽化物阻斷膜71)之後，對側壁膜137實施回蝕刻以在一像素電晶體部分17之每一閘極電極32及一周邊電路部分中之每一閘極電極(未顯示)之側壁上形成側壁(未顯示)。在此種情況下，使側壁膜137留在光電轉換部分21、一浮動擴散部分FD(及傳送閘TRG)以及一重設電晶體RST之一源極-汲極區34上。此乃因光電轉換部分21、該浮動擴散部分FD及重設電晶體RST之源極-汲極區34由一抗蝕劑遮罩(未顯示)覆蓋以使該等側壁之形成期間的蝕刻損壞不進入光電轉換部分21、該浮動擴散部分FD(及傳送閘TRG)以及重設電晶體RST之源極-汲極區34。換句話說，此方法不同於上文所述之製造方法之第一實例，只因為抗蝕劑遮罩138(參見圖25)經形成以延伸至浮動擴散部分FD、重設電晶體RST之源極-汲極區34及重設電晶體RST之閘極電極32之一部分。在抗蝕劑遮罩138之形成之前的其他步驟相同於第一實例之步驟。應注意，在此級中尚未形成浮動擴散部分FD、源極-汲極區34及諸如此類。為了便於理解位置關係，浮動擴散部分FD及源極-汲極區34顯示於該等圖式中。 First, a side will be described with reference to FIGS. 60, 61A, 61B, 62C, 62D, and the like. The steps of the wall. Figure 60 is a plan view of a pixel portion, Figure 61A is a cross-sectional view taken along line LXIA-LXIA of Figure 60, Figure 61B is a cross-sectional view taken along line LXIB-LXIB of Figure 60, Figure 62C is a A cross-sectional view taken along line LXIIC-LXIIC of Fig. 60, and Fig. 62D is a cross-sectional view taken along line LXIID-LXIID of Fig. 60. After forming a sidewall film 137 (the first vaporization blocking film 71), the sidewall film 137 is etched back to each of the gate electrodes 32 and a peripheral circuit portion of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21, a floating diffusion portion FD (and the transfer gate TRG), and one source-drain region 34 of a reset transistor RST. This is because the photoelectric conversion portion 21, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor RST are covered by a resist mask (not shown) to damage the etching during formation of the sidewalls. The photoelectric conversion portion 21, the floating diffusion portion FD (and the transfer gate TRG), and the source-drain region 34 of the reset transistor RST are not entered. In other words, this method is different from the first example of the manufacturing method described above only because the resist mask 138 (see FIG. 25) is formed to extend to the floating diffusion portion FD, resetting the source of the transistor RST The pole-drain region 34 and a portion of the gate electrode 32 of the reset transistor RST. The other steps before the formation of the resist mask 138 are the same as those of the first example. It should be noted that the floating diffusion portion FD, the source-drain region 34, and the like have not been formed in this stage. In order to facilitate understanding of the positional relationship, the floating diffusion portion FD and the source-drain region 34 are shown in the drawings.
接著，形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區34及35。在此步驟中，由於浮動擴散部分FD及重設電晶體RST之源極-汲極區34由側壁膜137覆蓋，因此較佳與用於形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區之離子植入分開實施離子植入。 Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed. In this step, since the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST are covered by the sidewall film 137, it is preferably used for forming the pixel portion and the transistor in the peripheral circuit portion. Ion implantation is performed separately from ion implantation in the source-drain region.
接下來，將參照圖63、64A、64B、65C、65D等來闡述一後續步驟。圖63係該像素部分之一平面佈置圖，圖64A係一沿圖63中線 LXIVA-LXIVA剖切之剖視圖，圖64B係一沿圖63中線LXIVB-LXIVB剖切之剖視圖，圖65C係一沿圖63中線LXVC-LXVC剖切之剖視圖，且圖65D係一沿圖63中線LXVD-LXVD剖切之剖視圖。在形成該像素部分及該周邊電路部分中之電晶體之源極-汲極區之後，在該周邊電路部分中之源極-汲極區及諸如此類上形成一矽化層。在此步驟中，必要的係使該矽化層不形成於像素電晶體部分17、光電轉換部分21等上。出於此目的，在該矽化層之形成之前，形成一覆蓋像素電晶體部分17之第二矽化物阻斷膜72。在此步驟中，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊。在此步驟中，由於第一矽化物阻斷膜71經形成以延伸至重設電晶體RST之閘極電極32之該部分，因此第二矽化物阻斷膜72可經形成以與第一矽化物阻斷膜71重疊於重設電晶體RST之閘極電極32上。此外，在其他部分中，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於一隔離區14上。接著，如在第一實例中一樣，實施對該周邊電路部分中之MOS電晶體之閘極電極及源極-汲極區之該矽化步驟及該等後續步驟。 Next, a subsequent step will be explained with reference to FIGS. 63, 64A, 64B, 65C, 65D, and the like. Figure 63 is a plan view of one of the pixel portions, and Figure 64A is a line along the line of Figure 63. A cross-sectional view taken along line LXIVB-LXIVB of Fig. 63, Fig. 65C is a cross-sectional view taken along line LXVC-LXVC of Fig. 63, and Fig. 65D is a cross-sectional view taken along line 63 of Fig. 63. Cutaway view of the midline LXVD-LXVD. After forming the source-drain region of the transistor in the pixel portion and the peripheral circuit portion, a deuterated layer is formed on the source-drain region and the like in the peripheral circuit portion. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion 17, the photoelectric conversion portion 21, and the like. For this purpose, a second telluride blocking film 72 covering the pixel transistor portion 17 is formed prior to the formation of the germanide layer. In this step, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71. In this step, since the first telluride blocking film 71 is formed to extend to the portion of the gate electrode 32 of the reset transistor RST, the second telluride blocking film 72 can be formed to be the first deuterated The material blocking film 71 is overlaid on the gate electrode 32 of the reset transistor RST. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on an isolation region 14. Next, as in the first example, the deuteration step and the subsequent steps of the gate electrode and the source-drain region of the MOS transistor in the peripheral circuit portion are carried out.
相應地，當形成像素部分17中之側壁33及該周邊電路部分中之該等側壁(未顯示)時，浮動擴散部分FD亦由係該側壁膜之第一矽化物阻斷膜71覆蓋。此結構可防止在該等側壁之形成期間在浮動擴散部分FD中出現蝕刻損壞。另外，此結構可防止浮動擴散部分FD接收一外擴散效應。相應地，可抑制一洩漏路徑之產生，從而抑制FD白疵點之產生。因此，可製造一可實現具有高影像品質之成像之固態成像裝置。此外，在該矽化層之形成之前，像素電晶體部分17可由第二矽化物阻斷膜72覆蓋。 Accordingly, when the side walls 33 in the pixel portion 17 and the side walls (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vapor blocking film 71 which is the side wall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving an external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Therefore, it is possible to manufacture a solid-state imaging device that can realize imaging with high image quality. Further, the pixel transistor portion 17 may be covered by the second vaporization blocking film 72 before the formation of the deuterated layer.
在其中四個像素由一單一像素電晶體部分17分享之第三實例及第四實例之結構中，光電轉換部分21周圍之元件隔離係使用一雜質擴 散層(P+型擴散層)而達成，且像素電晶體部分17周圍之元件隔離係藉由一淺溝槽隔離(STI)結構而達成。另一選擇係，例如，如圖66中所示，光電轉換部分21周圍之元件隔離及像素電晶體部分17周圍之元件隔離可藉由一由一雜質擴散層(P+型擴散層)組成之隔離區16而形成。在此種情況下，第一矽化物阻斷膜71可如同在第三實例、第四實例及諸如此類中一樣形成。第二矽化物阻斷膜72亦可如同在第三實例、第四實例及諸如此類中一樣形成。 In the structures of the third and fourth examples in which four pixels are shared by a single pixel transistor portion 17, the element isolation around the photoelectric conversion portion 21 is achieved by using an impurity diffusion layer (P + -type diffusion layer). And the element isolation around the pixel transistor portion 17 is achieved by a shallow trench isolation (STI) structure. Alternatively, for example, as shown in FIG. 66, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion 17 may be composed of an impurity diffusion layer (P + -type diffusion layer). The isolation region 16 is formed. In this case, the first telluride blocking film 71 can be formed as in the third example, the fourth example, and the like. The second telluride blocking film 72 can also be formed as in the third example, the fourth example, and the like.
在圖5A中所示之結構中，光電轉換部分21周圍之元件隔離及該像素電晶體部分周圍之元件隔離係藉由一淺溝槽隔離(STI)結構而達成。另一選擇係，例如，如圖67至69B中所示，光電轉換部分21周圍之元件隔離及像素電晶體部分17周圍之元件隔離可藉由一由一雜質擴散層(P+型擴散層)組成之隔離區16而達成。在此種情況下，第一矽化物阻斷膜71形成於光電轉換部分21、傳送閘TRG、浮動擴散部分FD、重設電晶體RST之源極-汲極區34及重設電晶體RST之閘極電極32之一部分上。第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊。在此種情況下，由於第一矽化物阻斷膜71形成於重設電晶體RST之閘極電極32之該部分上，因此第二矽化物阻斷膜72可經形成以與第一矽化物阻斷膜71重疊於重設電晶體RST之閘極電極32上。此外，在其他部分中，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於隔離區16上。圖68係一沿圖67中線LXVIII-LXVIII剖切之剖視圖，且圖69A及69B係沿圖67中線LXIX-LXIX剖切之剖視圖。 In the structure shown in Fig. 5A, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion are achieved by a shallow trench isolation (STI) structure. Alternatively, for example, as shown in FIGS. 67 to 69B, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion 17 can be separated by an impurity diffusion layer (P + type diffusion layer). The composition of the isolation zone 16 is achieved. In this case, the first telluride blocking film 71 is formed in the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, the source-drain region 34 of the reset transistor RST, and the reset transistor RST. One portion of the gate electrode 32. The second telluride blocking film 72 is formed to overlap the first telluride blocking film 71. In this case, since the first telluride blocking film 71 is formed on the portion of the gate electrode 32 of the reset transistor RST, the second telluride blocking film 72 can be formed to be combined with the first germanide The blocking film 71 is overlaid on the gate electrode 32 of the reset transistor RST. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on the isolation region 16. Figure 68 is a cross-sectional view taken along line LXVIII-LXVIII of Figure 67, and Figures 69A and 69B are cross-sectional views taken along line LXIX-LXIX of Figure 67.
在製造一固態成像裝置之方法之第三及第四實例中之每一者中，該周邊電路部分之結構相同於上述製造方法之第一實例之結構。 In each of the third and fourth examples of the method of manufacturing a solid-state imaging device, the peripheral circuit portion has the same structure as the first example of the above manufacturing method.
接下來，將參照圖70A至93D之剖視圖來闡述一製造一具有一其 中一單一像素電晶體部分分享四個像素之結構之固態成像裝置之方法之一詳細實例。此方法係一製造參照圖51之一像素部分之平面佈置圖所述之結構之方法。圖70A、72A、74A、76A、78A、80A、82A、84A、86A、88A、90A及92A係沿圖51中線LIIA-LIIA剖切之剖視圖。圖70B、72B、74B、76B、78B、80B、82B、84B、86B、88B、90B及92B係沿圖51中線LIIB-LIIB剖切之剖視圖。圖71C、73C、75C、77C、79C、81C、83C、85C、87C、89C、91C及93C係沿圖51中線LIIIC-LIIIC剖切之剖視圖。圖71D、73D、75D、77D、79D、81D、83D、85D、87D、89D、91D及93D係沿圖51中線LIIID-LIIID部分之剖視圖。 Next, a manufacturing one having one of them will be explained with reference to the cross-sectional views of FIGS. 70A to 93D. A detailed example of a method of a solid-state imaging device in which a single pixel transistor portion shares a structure of four pixels. This method is a method of fabricating the structure described with reference to the plan layout of one of the pixel portions of FIG. 70A, 72A, 74A, 76A, 78A, 80A, 82A, 84A, 86A, 88A, 90A, and 92A are cross-sectional views taken along line LIIA-LIIA of Fig. 51. 70B, 72B, 74B, 76B, 78B, 80B, 82B, 84B, 86B, 88B, 90B, and 92B are cross-sectional views taken along line LIIB-LIIB of Fig. 51. 71C, 73C, 75C, 77C, 79C, 81C, 83C, 85C, 87C, 89C, 91C, and 93C are cross-sectional views taken along line LIIIC-LIIIC of Fig. 51. 71D, 73D, 75D, 77D, 79D, 81D, 83D, 85D, 87D, 89D, 91D and 93D are cross-sectional views along the line LIIID-LIIID of Fig. 51.
首先，實施圖6至12中所示之步驟。舉例而言，使用一矽基板作為一半導體基板11。在一像素電晶體部分之周邊處形成第一隔離區14，並形成一周邊電路部分13中之第二隔離區15。接下來，儘管未顯示於圖6至12中，但在半導體基板11中形成一p井及一n井。進一步實施通道離子植入。此外，實施用於形成光電轉換部分中之光電二極體之離子植入以形成p型區。舉例而言，對上面形成光電轉換部分之半導體基板之表面實施硼(B)之離子植入，並使用砷(As)或磷(P)在深區中實施離子植入以形成若干n型區，該等n型區形成一與該等p型區之一下部分之接面。因此，形成包括一p-n接面之該等光電轉換部分。 First, the steps shown in Figs. 6 to 12 are carried out. For example, a germanium substrate is used as a semiconductor substrate 11. A first isolation region 14 is formed at a periphery of a pixel transistor portion, and a second isolation region 15 in a peripheral circuit portion 13 is formed. Next, although not shown in FIGS. 6 to 12, a p well and an n well are formed in the semiconductor substrate 11. Further implementation of channel ion implantation. Further, ion implantation for forming a photodiode in the photoelectric conversion portion is performed to form a p-type region. For example, boron (B) ion implantation is performed on the surface of the semiconductor substrate on which the photoelectric conversion portion is formed, and ion implantation is performed in the deep region using arsenic (As) or phosphorus (P) to form a plurality of n-type regions. The n-type regions form a junction with a lower portion of the p-type regions. Therefore, the photoelectric conversion portions including a p-n junction are formed.
接下來，將參照70A、70B、71C、71D等來進行說明。圖70A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖70B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖71C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖71D係一沿圖51中線LIIID-LIIID剖切之剖視圖。在半導體基板11上形成一犧牲氧化層151。接著，在犧牲氧化層151上形成一抗蝕劑遮罩152。抗蝕劑遮罩152具有提供於形成於光電轉換部分21周圍之隔離區上之開口153。特定而言，抗蝕劑遮罩152覆蓋光電轉換部分21 及其中形成傳送閘、一浮動擴散部分及像素電晶體部分之區域。接下來，使用抗蝕劑遮罩152作為一離子植入遮罩在半導體基板11中實施離子植入以形成p+型隔離區16。在此離子植入中，例如，使用硼(B)作為一離子植入種類，並將劑量設定為介於1×1012至1×1013 cm-2之範圍內。將植入能量設定為介於10至30 keV之範圍內。該離子植入可根據深度以多級來實施。因而，光電轉換部分21由隔離區16彼此分隔開，且由隔離區14與一形成一重設電晶體、一放大電晶體、一選擇電晶體及諸如此類之像素電晶體部分形成區分隔開。儘管未顯示於該等圖式中，但該周邊電路部分由第二隔離區15分隔開，如上文所述。 Next, description will be made with reference to 70A, 70B, 71C, 71D, and the like. Figure 70A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 70B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 71C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 71D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. A sacrificial oxide layer 151 is formed on the semiconductor substrate 11. Next, a resist mask 152 is formed on the sacrificial oxide layer 151. The resist mask 152 has an opening 153 provided on an isolation region formed around the photoelectric conversion portion 21. Specifically, the resist mask 152 covers the photoelectric conversion portion 21 and a region where the transfer gate, a floating diffusion portion, and the pixel transistor portion are formed. Next, ion implantation is performed in the semiconductor substrate 11 using the resist mask 152 as an ion implantation mask to form the p + -type isolation region 16. In this ion implantation, for example, boron (B) is used as an ion implantation species, and the dose is set to be in the range of 1 × 10 12 to 1 × 10 13 cm -2 . The implant energy is set to be in the range of 10 to 30 keV. The ion implantation can be performed in multiple stages depending on the depth. Thus, the photoelectric conversion portions 21 are separated from each other by the isolation regions 16, and are separated by an isolation region 14 from a pixel crystal portion forming a reset transistor, an amplifying transistor, a selection transistor, and the like. Although not shown in the figures, the peripheral circuit portions are separated by a second isolation region 15, as described above.
接著，移除抗蝕劑遮罩152，並進一步移除犧牲氧化層151。該圖式顯示一就在移除抗蝕劑遮罩152之前的狀態。 Next, the resist mask 152 is removed and the sacrificial oxide layer 151 is further removed. This figure shows a state just before the resist mask 152 is removed.
接下來，將參照72A、72B、73C、73D等來進行說明。圖72A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖72B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖73C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖73D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖72A至73D中所示，在半導體基板11上形成一閘極絕緣膜31，並進一步在閘極絕緣膜31上形成一閘極電極形成膜131。在此步驟中，儘管未顯示於該等圖式中，但如圖14中所示，亦在周邊電路部分13中之半導體基板11上形成一閘極絕緣膜51，並在閘極絕緣膜51上形成閘極電極形成膜131。閘極電極形成膜131係藉由一LP-CVD方法來沈積多晶矽而形成。所沈積膜厚度在一90-nm節點中介於150至200 nm之範圍內，但其取決於技術節點。該膜厚度趨於針對第一節點而減小，此乃因從該過程之可控性之觀點出發通常不增大一閘極長寬比。作為一對抗閘極空乏之措施，可使用矽鍺(SiGe)來代替多晶矽。閘極空乏係指下面一個問題：因一閘極氧化物膜之厚度減小，故不僅該閘極氧化物膜之實體厚度之一效應而且該閘極多晶矽中之一空乏層之厚度之一效應不可 忽視，且因此不減小該閘極氧化物膜之一有效厚度，從而使電晶體效能退化。 Next, description will be made with reference to 72A, 72B, 73C, 73D, and the like. Figure 72A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 72B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 73C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 73D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 72A to 73D, a gate insulating film 31 is formed on the semiconductor substrate 11, and a gate electrode forming film 131 is further formed on the gate insulating film 31. In this step, although not shown in the drawings, as shown in Fig. 14, a gate insulating film 51 is also formed on the semiconductor substrate 11 in the peripheral circuit portion 13, and is provided in the gate insulating film 51. A gate electrode formation film 131 is formed thereon. The gate electrode formation film 131 is formed by depositing polysilicon by an LP-CVD method. The deposited film thickness is in the range of 150 to 200 nm in a 90-nm node, but it depends on the technology node. The film thickness tends to decrease for the first node, since a gate aspect ratio is generally not increased from the viewpoint of controllability of the process. As a measure against gate depletion, germanium (SiGe) can be used instead of polysilicon. The gate depletion refers to the following problem: because the thickness of a gate oxide film is reduced, not only one effect of the physical thickness of the gate oxide film but also one of the thicknesses of one of the gate polysilicon layers Not Neglect, and therefore does not reduce the effective thickness of one of the gate oxide films, thereby degrading the transistor performance.
接下來，將參照74A、74B、75C、75D等來進行說明。圖74A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖74B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖75C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖75D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖74A至75D中所示，採取一對抗閘極空乏之措施。首先，在周邊電路部分13中之一p-MOS電晶體形成區上形成一抗蝕劑遮罩132(參見圖16)，並將一n型雜質摻雜至該n-MOS電晶體形成區中之閘極電極形成膜131中。此摻雜係藉由例如磷(P)或砷(As)之離子植入來實施。所植入離子量介於約1×1015至1×1016 cm-2之範圍內。隨後移除抗蝕劑遮罩132。接下來，儘管未顯示於該等圖式中，但在該n-MOS電晶體形成區上形成一抗蝕劑遮罩(未顯示)，並將一p型雜質摻雜至該p-MOS電晶體形成區中之閘極電極形成膜131中。此摻雜係藉由例如硼(B)、二氟化硼(BF2)或銦(In)之離子植入來實施。所植入之離子量介於約1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。可首先實施前者植入或後者植入。在上述離子植入中之每一者中，為了防止由該離子植入所引入之雜質抵達該閘極絕緣膜正下方，可組合氮(N2)之離子植入。 Next, description will be made with reference to 74A, 74B, 75C, 75D, and the like. Figure 74A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 74B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 75C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 75D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figures 74A through 75D, a measure against the lack of gates is taken. First, a resist mask 132 (see FIG. 16) is formed on one of the p-MOS transistor formation regions in the peripheral circuit portion 13, and an n-type impurity is doped into the n-MOS transistor formation region. The gate electrode is formed in the film 131. This doping is carried out by ion implantation such as phosphorus (P) or arsenic (As). The amount of implanted ions is in the range of about 1 x 10 15 to 1 x 10 16 cm -2 . The resist mask 132 is then removed. Next, although not shown in the drawings, a resist mask (not shown) is formed on the n-MOS transistor formation region, and a p-type impurity is doped to the p-MOS The gate electrode in the crystal formation region is formed in the film 131. This doping is carried out by ion implantation such as boron (B), boron difluoride (BF 2 ) or indium (In). The amount of ions implanted is in the range of about 1 x 10 15 to 1 x 10 16 cm -2 . The resist mask is then removed. The former implant or the latter implant may be performed first. In each of the above ion implantations, in order to prevent impurities introduced by the ion implantation from reaching the gate insulating film directly, ion implantation of nitrogen (N 2 ) may be combined.
接下來，將參照76A、76B、77C、77D等來進行說明。圖76A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖76B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖77C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖77D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖76A至77D中所示，在閘極電極形成膜131上形成一用於形成閘極電極之抗蝕劑遮罩(未顯示)。使用此抗蝕劑遮罩作為一蝕刻遮罩藉由反應離子蝕刻來對閘極電極形成膜131進行蝕刻處理以形成像素部分12中之MOS電晶體之閘極電極32、傳送閘TRG及周邊電路部分13中之MOS電 晶體之閘極電極52(參見圖18)。接著，氧化閘極電極32及閘極電極52(參見圖18)之表面以形成一氧化物膜133。氧化物膜133之厚度例如介於1至10 nm之範圍內。氧化物膜133不僅形成於該等側壁上而且形成於閘極電極32及52中之每一者之頂表面上。此外，在上述氧化步驟中修圓閘極電極32及52之邊緣部分具有一改善該氧化物膜之崩潰電壓之效應。另外，可藉由實施熱處理來減小蝕刻損壞。此外，在對閘極電極之上述處理中，即使移除形成於光電轉換部分21上之閘極絕緣膜，氧化物膜133亦形成於光電轉換部分21上。因此，當在下一個微影步驟中形成一抗蝕劑膜時，該抗蝕劑膜不直接形成於一矽表面上，從而防止因此抗蝕劑而引起之污染。相應地，針對像素部分12中之光電轉換部分21，此結構充當一對抗白疵點之措施。 Next, description will be made with reference to 76A, 76B, 77C, 77D, and the like. Figure 76A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 76B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 77C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 77D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 76A to 77D, a resist mask (not shown) for forming a gate electrode is formed on the gate electrode forming film 131. The gate electrode forming film 131 is etched by reactive ion etching using the resist mask as an etch mask to form the gate electrode 32, the transfer gate TRG, and the peripheral circuit of the MOS transistor in the pixel portion 12. Part MOS in MOS The gate electrode 52 of the crystal (see Figure 18). Next, the surface of the gate electrode 32 and the gate electrode 52 (see FIG. 18) is oxidized to form an oxide film 133. The thickness of the oxide film 133 is, for example, in the range of 1 to 10 nm. The oxide film 133 is formed not only on the sidewalls but also on the top surface of each of the gate electrodes 32 and 52. Further, the edge portions of the rounded gate electrodes 32 and 52 in the above oxidation step have an effect of improving the breakdown voltage of the oxide film. In addition, etching damage can be reduced by performing heat treatment. Further, in the above-described process of the gate electrode, even if the gate insulating film formed on the photoelectric conversion portion 21 is removed, the oxide film 133 is formed on the photoelectric conversion portion 21. Therefore, when a resist film is formed in the next lithography step, the resist film is not formed directly on a ruthenium surface, thereby preventing contamination caused by the resist. Accordingly, for the photoelectric conversion portion 21 in the pixel portion 12, this structure serves as a measure against the chalk point.
接下來，將參照78A、78B、79C、79D等來進行說明。圖78A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖78B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖79C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖79D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖78A至79D中所示，形成像素部分12之MOS電晶體之LDD區38、39等及周邊電路部分13之MOS電晶體之LDD區61、62、63、64等(參見圖20)。 Next, description will be made with reference to 78A, 78B, 79C, 79D and the like. Figure 78A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 78B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 79C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 79D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 78A to 79D, the LDD regions 38, 39 and the like of the MOS transistors of the pixel portion 12 and the LDD regions 61, 62, 63, 64 and the like of the MOS transistors of the peripheral circuit portion 13 are formed (see Fig. 20).
首先，至於形成於周邊電路部分13中之NMOS電晶體，在半導體基板11中之閘極電極52(52N)中之每一者之兩側處形成凹處擴散層65及66(參見圖20)。此等凹處擴散層65及66係藉由使用例如二氟化硼(BF2)、硼(B)或銦(In)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1012至1×1014 cm-2之範圍內。此外，LDD區61及62形成於半導體基板11中之閘極電極52(52N)中之每一者之兩側處。LDD區61及62係藉由使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1013至1×1015 cm-2之範圍內。 First, as for the NMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 65 and 66 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11 (see FIG. 20). . These recessed diffusion layers 65 and 66 are formed by ion implantation using, for example, boron difluoride (BF 2 ), boron (B) or indium (In) as an ion implantation species, and the dose setting thereof It is, for example, in the range of 1 × 10 12 to 1 × 10 14 cm -2 . Further, LDD regions 61 and 62 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. The LDD regions 61 and 62 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 10 13 to 1 × 10 15 cm - Within the scope of 2 .
至於形成於像素部分12中之MOS電晶體，LDD區38及39形成於半導體基板11中之閘極電極32中之每一者之兩側處。LDD區38及39係藉由使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1013至1×1015 cm-2之範圍內。另外，可形成若干凹處擴散層。至於形成於像素部分12中之MOS電晶體，從減小步驟數之觀點出發，可不形成該等LDD。另一選擇係，用於形成形成於像素部分12中之MOS電晶體之LDD區之離子植入亦可起形成於周邊電路部分13中之MOS電晶體之LDD離子植入的作用。 As for the MOS transistors formed in the pixel portion 12, LDD regions 38 and 39 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11. The LDD regions 38 and 39 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, between 1 × 10 13 and 1 × 10 15 Within the range of cm -2 . In addition, a plurality of recessed diffusion layers can be formed. As for the MOS transistor formed in the pixel portion 12, the LDD may not be formed from the viewpoint of reducing the number of steps. Alternatively, ion implantation for forming the LDD region of the MOS transistor formed in the pixel portion 12 may function as an LDD ion implantation of the MOS transistor formed in the peripheral circuit portion 13.
至於形成於周邊電路部分13中之PMOS電晶體，在半導體基板11中之閘極電極52(52P)中之每一者之兩側處形成凹處擴散層67及68(參見圖20)。此等凹處擴散層67及68係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1012至1×1014 cm-2之範圍內。此外，LDD區63及64形成於半導體基板11中之閘極電極52(52P)中之每一者之兩側處。LDD區63及64係使用例如二氟化硼(BF2)、硼(B)或銦(In)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1013至1×1015 cm-2之範圍內。 As for the PMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 67 and 68 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11 (see Fig. 20). These recessed diffusion layers 67 and 68 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 12 to 1 ×. Within the range of 10 14 cm -2 . Further, LDD regions 63 and 64 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. The LDD regions 63 and 64 are formed by ion implantation using, for example, boron difluoride (BF 2 ), boron (B), or indium (In) as an ion implantation species, and the dose thereof is set to, for example, 1 ×. 10 13 to 1 × 10 15 cm -2 .
在該周邊電路部分中之NMOS電晶體及PMOS電晶體之凹處離子植入之前，可藉由進行鍺(Ge)之離子植入來實施預非晶化作為一用於抑制植入中之通道效應之技術。此外，為了減小可造成瞬時增強擴散(TED)或諸如此類之植入瑕疵數，可在該等LDD區之形成之後添加在一介於約800℃至900℃之範圍內的溫度下之快速熱退火(RTA)。 Before the ion implantation of the NMOS transistor and the PMOS transistor in the peripheral circuit portion, pre-amorphization can be performed by performing ion implantation of germanium (Ge) as a channel for suppressing implantation. The technology of effects. Furthermore, in order to reduce the number of implant turns that can cause transient enhanced diffusion (TED) or the like, rapid thermal annealing at a temperature ranging from about 800 ° C to 900 ° C can be added after the formation of the LDD regions. (RTA).
接下來，將參照80A、80B、81C、81D等來進行說明。圖80A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖80B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖81C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖81D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖80A至81B中所示，在像素部分12之整個表面及周邊電路部分13上形成一氧 化矽(SiO2)膜134(參見圖22)。此氧化矽膜134係藉由沈積一非摻雜矽化玻璃(NSG)膜、一低壓原矽酸四乙酯(LP-TEOS)膜、一高溫氧化(HTO)膜或類似膜而形成。氧化矽膜134經形成以具有一介於例如5至20 nm之範圍內的厚度。接下來，在氧化矽膜134上形成氮化矽膜135。此氮化矽膜135係由例如一藉由LPCVD而形成之氮化矽膜組成。其厚度介於例如10至100 nm之範圍內。氮化矽膜135可係一藉由一可用以在一低溫下形成該膜之原子層沈積方法而形成之ALD氮化矽膜。在像素部分12中之光電轉換部分21上，因沈積於氮化矽膜135正下方之氧化矽膜134之厚度減小，故防止光反射，且因此光電轉換部分21之感光度變高。接下來，視需要在氮化矽膜135上沈積一係一第三層之氧化矽(SiO2)膜136。此氧化矽膜136係藉由沈積一NSG膜、一LP-TEOS膜、一HTO膜或類似膜而形成。氧化矽膜136經形成以具有一介於例如10至100 nm之範圍內的厚度。 Next, description will be made with reference to 80A, 80B, 81C, 81D, and the like. Figure 80A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 80B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 81C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 81D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 80A to 81B, a ruthenium oxide (SiO 2 ) film 134 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13 (see Fig. 22). The hafnium oxide film 134 is formed by depositing an undoped deuterated glass (NSG) film, a low pressure tetraethyl orthophthalate (LP-TEOS) film, a high temperature oxidation (HTO) film or the like. The hafnium oxide film 134 is formed to have a thickness in the range of, for example, 5 to 20 nm. Next, a tantalum nitride film 135 is formed on the hafnium oxide film 134. The tantalum nitride film 135 is composed of, for example, a tantalum nitride film formed by LPCVD. Its thickness is, for example, in the range of 10 to 100 nm. The tantalum nitride film 135 may be an ALD tantalum nitride film formed by an atomic layer deposition method which can form the film at a low temperature. In the photoelectric conversion portion 21 in the pixel portion 12, since the thickness of the ruthenium oxide film 134 deposited directly under the tantalum nitride film 135 is reduced, light reflection is prevented, and thus the sensitivity of the photoelectric conversion portion 21 becomes high. Next, a third layer of yttrium oxide (SiO 2 ) film 136 is deposited on the tantalum nitride film 135 as needed. This ruthenium oxide film 136 is formed by depositing an NSG film, an LP-TEOS film, an HTO film or the like. The hafnium oxide film 136 is formed to have a thickness ranging, for example, from 10 to 100 nm.
相應地，形成一側壁膜137作為一具有氧化矽膜136/氮化矽膜135/氧化矽膜134之結構之三層式膜。另一選擇係，側壁膜137可係一具有氮化矽膜/氧化矽膜之結構之兩層式膜。下文將闡述具有該三層式結構之側壁膜137之一情形。 Accordingly, a sidewall film 137 is formed as a three-layer film having a structure of a hafnium oxide film 136 / a tantalum nitride film 135 / a hafnium oxide film 134. Alternatively, the sidewall film 137 may be a two-layer film having a structure of a tantalum nitride film/yttria film. A case of the side wall film 137 having the three-layer structure will be explained below.
接下來，將參照82A、82B、83C、83D等來進行說明。圖82A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖82B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖83C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖83D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖82A至83B中所示，對提供作為該頂層之氧化矽膜136實施回蝕刻以使氧化矽膜136僅留在閘極電極32及52(參見圖24)中之每一者、傳送閘TRG及諸如此類之側部分上。該回蝕刻係藉由例如反應離子蝕刻(RIE)來實施。在此回蝕刻中，使用氮化矽膜135來止擋蝕刻。由於該等蝕刻由氮化矽膜135以此方式止擋，因此可減小像素部分12中之光電轉換 部分21上之蝕刻損壞，且因此可減小白疵點數。 Next, description will be made with reference to 82A, 82B, 83C, 83D, and the like. Figure 82A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 82B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 83C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 83D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 82A to 83B, etch back is provided to the ruthenium oxide film 136 provided as the top layer so that the ruthenium oxide film 136 remains only in each of the gate electrodes 32 and 52 (see Fig. 24), the transfer gate On the side of the TRG and the like. This etch back is performed by, for example, reactive ion etching (RIE). In this etch back, a tantalum nitride film 135 is used to stop the etching. Since the etching is stopped by the tantalum nitride film 135 in this manner, photoelectric conversion in the pixel portion 12 can be reduced. The etching on portion 21 is damaged, and thus the number of chalk points can be reduced.
接下來，參照84A、84B、85C、85D等來進行說明。圖84A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖84B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖85C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖85D係一沿圖51中線LIIID-LIIID剖切之剖視圖。如圖84A至85B中所示，在像素部分12中及傳送閘TRG上之光電轉換部分21之整個表面、一其中形成該浮動擴散部分之區、該重設電晶體之LDD區38及該重設電晶體之閘極電極32之一部分上形成一抗蝕劑遮罩138。接下來，對氮化矽膜135及氧化矽膜134實施回蝕刻以形成一位於閘極電極32中之每一者之側壁上之第一側壁33及一位於閘極電極52(參見圖26)中之每一者之側壁上之第二側壁53(參見圖26)，第一側壁33及第二側壁53係由氧化矽膜134、氮化矽膜135及氧化矽膜136組成。在此步驟中，光電轉換部分21、其中形成該浮動擴散區之區、以及位於一其中形成該重設電晶體之源極-汲極區之區上之氮化矽膜135及氧化矽膜134因其由抗蝕劑遮罩138覆蓋而未被蝕刻。相應地，蝕刻損壞不出現在光電轉換部分21、其中形成該浮動擴散部分之區、以及其中形成該重設電晶體之源極-汲極區之區上。 Next, description will be made with reference to 84A, 84B, 85C, 85D, and the like. Figure 84A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 84B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 85C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 85D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in FIGS. 84A to 85B, the entire surface of the photoelectric conversion portion 21 in the pixel portion 12 and the transfer gate TRG, a region in which the floating diffusion portion is formed, the LDD region 38 of the reset transistor, and the weight A resist mask 138 is formed on a portion of the gate electrode 32 of the transistor. Next, the tantalum nitride film 135 and the hafnium oxide film 134 are etched back to form a first sidewall 33 on the sidewall of each of the gate electrodes 32 and a gate electrode 52 (see FIG. 26). The second side wall 53 (see FIG. 26) on the sidewall of each of the first side wall 33 and the second side wall 53 is composed of a hafnium oxide film 134, a tantalum nitride film 135, and a hafnium oxide film 136. In this step, the photoelectric conversion portion 21, the region in which the floating diffusion region is formed, and the tantalum nitride film 135 and the yttrium oxide film 134 on a region in which the source-drain region of the reset transistor is formed are formed. It is not etched because it is covered by the resist mask 138. Accordingly, the etching damage does not occur in the photoelectric conversion portion 21, the region in which the floating diffusion portion is formed, and the region in which the source-drain region of the reset transistor is formed.
接下來，參照86A、86B、87C、87D等來進行說明。圖86A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖86B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖87C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖87D係一沿圖51中線LIIID-LIIID剖切之剖視圖。首先，如圖28中所示，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成周邊電路部分13中之NMOS電晶體之區中。使用該抗蝕劑藉由離子植入在欲形成周邊電路部分13中之NMOS電晶體之區中形成深源極-汲極區54(54N)及55(55N)。特定而言，源極-汲極區54N及55N形成於半導體基板11中之閘極電極52中之每一者之兩側處，而LDD區 61、62等位於其之間。源極-汲極區54N及55N係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。 Next, description will be made with reference to 86A, 86B, 87C, 87D, and the like. Figure 86A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 86B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 87C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 87D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in Fig. 28, a resist mask (not shown) having an opening which is provided in a region in which an NMOS transistor in the peripheral circuit portion 13 is to be formed is formed. The deep source-drain regions 54 (54N) and 55 (55N) are formed in the region of the NMOS transistor to be formed in the peripheral circuit portion 13 by ion implantation using the resist. Specifically, the source-drain regions 54N and 55N are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 61, 62 and the like interposed therebetween. The source-drain regions 54N and 55N are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 ×. Within the range of 10 16 cm -2 . The resist mask is then removed.
接下來，如圖86A至87B中所示，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成像素部分12中之NMOS電晶體之區中。使用該抗蝕劑遮罩藉由離子植入在欲形成像素部分12中之NMOS電晶體之區中形成深源極-汲極區34及35以及一浮動擴散部分FD。特定而言，源極-汲極區34及35形成於半導體基板11中之閘極電極32中之每一者之兩側處，而LDD區38、39等位於其之間。源極-汲極區34及35係使用例如砷(As)或磷(P)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。此離子植入亦可起用於形成周邊電路部分13中之NMOS電晶體之源極-汲極區54N及55N之離子植入的作用。重設電晶體RST之源極-汲極區34係藉由經由氧化矽膜134及氮化矽膜135所實施之離子植入而形成。因此，可單獨地實施此部分之離子植入。 Next, as shown in Figs. 86A to 87B, a resist mask (not shown) having an opening which is provided in a region in which the NMOS transistor in the pixel portion 12 is to be formed is formed. The deep source-drain regions 34 and 35 and a floating diffusion portion FD are formed in the region of the NMOS transistor to be formed in the pixel portion 12 by ion implantation using the resist mask. Specifically, the source-drain regions 34 and 35 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11, with the LDD regions 38, 39 and the like interposed therebetween. The source-drain regions 34 and 35 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 ×. Within the range of 10 16 cm -2 . The resist mask is then removed. This ion implantation can also function as an ion implantation for forming the source-drain regions 54N and 55N of the NMOS transistor in the peripheral circuit portion 13. The source-drain region 34 of the reset transistor RST is formed by ion implantation performed through the hafnium oxide film 134 and the tantalum nitride film 135. Therefore, ion implantation of this portion can be performed separately.
接下來，如圖28中所示，形成一具有開口之抗蝕劑遮罩(未顯示)，該等開口設置於其中欲形成周邊電路部分13中之PMOS電晶體之區中。使用該抗蝕劑遮罩藉由離子植入在欲形成周邊電路部分13中之PMOS電晶體之區中形成深源極-汲極區54(54P)及55(55P)。特定而言，源極-汲極區54P及55P形成於半導體基板11中之閘極電極52中之每一者之兩側處，而LDD區63、64等位於其之間。源極-汲極區54P及55P係使用例如硼(B)或二氟化硼(BF2)作為一離子植入種類藉由離子植入而形成，且其劑量設定為例如介於1×1015至1×1016 cm-2之範圍內。隨後移除該抗蝕劑遮罩。 Next, as shown in Fig. 28, a resist mask (not shown) having an opening which is provided in a region where the PMOS transistor in the peripheral circuit portion 13 is to be formed is formed. The deep source-drain regions 54 (54P) and 55 (55P) are formed in the region of the PMOS transistor to be formed in the peripheral circuit portion 13 by ion implantation using the resist mask. Specifically, the source-drain regions 54P and 55P are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 63, 64 and the like interposed therebetween. The source-drain regions 54P and 55P are formed by ion implantation using, for example, boron (B) or boron difluoride (BF 2 ) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 15 to 1 × 10 16 cm -2 . The resist mask is then removed.
接下來，對該等源極-汲極區實施活化退火。此活化退火係在一介於例如約800℃至1,100℃之溫度下實施。針對此活化退火，可使用 一快速熱退火(RTA)設備、一尖峰式RTA設備或類似設備。 Next, activation annealing is performed on the source-drain regions. This activation annealing is carried out at a temperature of, for example, about 800 ° C to 1,100 ° C. For this activation annealing, it can be used A rapid thermal annealing (RTA) device, a spiked RTA device, or the like.
在對該等源極-汲極區進行活化退火之前，將覆蓋光電轉換部分21之側壁膜137與由像素部分12中之MOS電晶體之閘極電極32上之側壁膜137組成之側壁33分隔開。此結構防止一因相關技術中所述之應力記憶技術(SMT)而引起之應力之退化。相應地，可抑制白疵點、隨機雜訊及諸如此類。此外，光電轉換部分21由側壁膜137覆蓋，且在用於形成該等源極-汲極區之離子植入中所使用之抗蝕劑遮罩形成於光電轉換部分21上，而側壁膜137位於其之間。換句話說，該抗蝕劑遮罩不直接形成於光電轉換部分21之表面上。因此，光電轉換部分21不被該抗蝕劑中之污染物污染，從而抑制白疵點數、暗電流及諸如此類之增大。另外，用於形成該等源極-汲極區之離子植入並非係一經由一膜之離子植入，且因此可設定該等源極-汲極區之深度同時保證該表面處之一高濃度。因此，可抑制該等源極-汲極區之串聯電阻之增大。此外，覆蓋光電轉換部分21、浮動擴散部分FD及重設電晶體之源極-汲極區34之側壁膜137在後續步驟中用作一第一矽化物阻斷膜71，源極-汲極區34經由佈線(未顯示)或諸如此類連接至浮動擴散部分FD。 The sidewall film 137 covering the photoelectric conversion portion 21 and the sidewall 33 composed of the sidewall film 137 on the gate electrode 32 of the MOS transistor in the pixel portion 12 are divided before the activation annealing of the source-drain regions. Separated. This structure prevents degradation of stress caused by stress memory technology (SMT) as described in the related art. Accordingly, chalk spots, random noise, and the like can be suppressed. Further, the photoelectric conversion portion 21 is covered by the sidewall film 137, and a resist mask used in ion implantation for forming the source-drain regions is formed on the photoelectric conversion portion 21, and the sidewall film 137 is formed. Located between them. In other words, the resist mask is not directly formed on the surface of the photoelectric conversion portion 21. Therefore, the photoelectric conversion portion 21 is not contaminated by the contaminants in the resist, thereby suppressing the number of chalk points, dark current, and the like. In addition, the ion implantation for forming the source-drain regions is not ion implantation through a film, and thus the depth of the source-drain regions can be set while ensuring that one of the surfaces is high. concentration. Therefore, an increase in the series resistance of the source-drain regions can be suppressed. In addition, the sidewall film 137 covering the photoelectric conversion portion 21, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor is used as a first germanide blocking film 71, source-drain in the subsequent step. The region 34 is connected to the floating diffusion portion FD via wiring (not shown) or the like.
接下來，將參照88A、88B、89C、89D等來進行說明。圖88A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖88B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖89C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖89D係一沿圖51中線LIIID-LIIID剖切之剖視圖。首先，如圖88A至89D中所示，在像素部分12之整個表面及周邊電路部分13上形成一第二矽化物阻斷膜72(參見圖30)。第二矽化物阻斷膜72係由一包括一氧化矽(SiO2)膜140及氮化矽膜139之堆疊膜組成。舉例而言，氧化矽膜140經形成以具有一介於例如5至40 nm之範圍內的厚度，且氮化矽膜139經形成以具有一介於例如5至60 nm之範圍內的厚度。氧化 矽膜140係由一NSG膜、一LP-TEOS膜、一HTO膜或類似膜組成。氮化矽膜139係由一ALD-SiN膜、一氮化電漿膜、一LP-SiN膜或類似膜構成。若該兩個膜之沈積溫度為高，則硼之去活化出現在PMOSFET之閘極電極中。因而，該等PMOSFET之一電流驅動能力因閘極空乏而降低。相應地，氧化矽膜140及氮化矽膜139之沈積溫度較佳低於側壁膜137之沈積溫度。該沈積溫度較佳例如處於700℃或更低下。 Next, description will be made with reference to 88A, 88B, 89C, 89D, and the like. Figure 88A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 88B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 89C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 89D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in Figs. 88A to 89D, a second vaporization blocking film 72 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13 (see Fig. 30). The second telluride blocking film 72 is composed of a stacked film including a tantalum oxide (SiO 2 ) film 140 and a tantalum nitride film 139. For example, the hafnium oxide film 140 is formed to have a thickness ranging from, for example, 5 to 40 nm, and the tantalum nitride film 139 is formed to have a thickness ranging from, for example, 5 to 60 nm. The ruthenium oxide film 140 is composed of an NSG film, an LP-TEOS film, an HTO film or the like. The tantalum nitride film 139 is composed of an ALD-SiN film, a nitride film, an LP-SiN film or the like. If the deposition temperature of the two films is high, deactivation of boron occurs in the gate electrode of the PMOSFET. Thus, one of the PMOSFETs has a current drive capability that is reduced due to gate depletion. Accordingly, the deposition temperature of the yttrium oxide film 140 and the tantalum nitride film 139 is preferably lower than the deposition temperature of the sidewall film 137. The deposition temperature is preferably, for example, at 700 ° C or lower.
接下來，將參照90A、90B、91C、91D等來進行說明。圖90A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖90B係一沿圖51中線LIIB-LIIB剖切之剖視圖，圖91C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖91D係一沿圖51中線LIIID-LIIID剖切之剖視圖。首先，如圖90A至91D中所示，形成一抗蝕劑遮罩141以大致覆蓋其中形成像素部分12中之MOS電晶體之區。使用此抗蝕劑遮罩141作為一蝕刻遮罩藉由蝕刻來移除位於像素部分12中及周邊電路部分13上之光電轉換部分21、浮動擴散部分FD、(及傳送閘TRG)、重設電晶體之源極-汲極區34、及重設電晶體之閘極電極32之一部分上之第二矽化物阻斷膜72(參見圖32)。相應地，第二矽化物阻斷膜72經形成以與第一矽化物阻斷膜71重疊於重設電晶體之閘極電極32上及圖91D中所示之隔離區14之後側處。由此，自該頂層，氮化矽膜135及氧化矽134按此次序位於光電轉換部分21上，且因此可防止光譜漣波。相反地，若未執行上述蝕刻，自該頂層，氮化矽膜139、氧化矽膜140、氮化矽膜135及氧化矽膜134按此次序位於光電轉換部分21上。在此種情況下，入射光經受多次反射，從而使光譜漣波特性退化。由於使該等漣波特性退化，因此晶片-晶片光譜變化增大。為了解決此問題，在此實施例中，故意移除光電轉換部分21上之第二矽化物阻斷膜72。 Next, description will be made with reference to 90A, 90B, 91C, 91D, and the like. Figure 90A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 90B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 91C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 91D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in FIGS. 90A to 91D, a resist mask 141 is formed to substantially cover a region in which the MOS transistors in the pixel portion 12 are formed. The resist mask 141 is used as an etch mask to remove the photoelectric conversion portion 21, the floating diffusion portion FD, (and the transfer gate TRG) located in the pixel portion 12 and the peripheral circuit portion 13 by etching, and reset The source-drain region 34 of the transistor and the second germanide blocking film 72 on a portion of the gate electrode 32 of the reset transistor (see FIG. 32). Accordingly, the second vaporization blocking film 72 is formed to overlap the first vapor blocking film 71 on the gate electrode 32 of the reset transistor and the rear side of the isolation region 14 shown in FIG. 91D. Thereby, from the top layer, the tantalum nitride film 135 and the tantalum oxide 134 are located on the photoelectric conversion portion 21 in this order, and thus spectral chopping can be prevented. On the contrary, if the above etching is not performed, the tantalum nitride film 139, the hafnium oxide film 140, the tantalum nitride film 135, and the hafnium oxide film 134 are located on the photoelectric conversion portion 21 in this order from the top layer. In this case, the incident light is subjected to multiple reflections, thereby degrading the spectral chopping characteristics. Due to the degradation of these chopping characteristics, the wafer-wafer spectral variation increases. In order to solve this problem, in this embodiment, the second vaporization blocking film 72 on the photoelectric conversion portion 21 is intentionally removed.
接下來，將參照92A、92B、93C、93D等來進行說明。圖92A係一沿圖51中線LIIA-LIIA剖切之剖視圖，圖92B係一沿圖51中線LIIB- LIIB剖切之剖視圖，圖93C係一沿圖51中線LIIIC-LIIIC剖切之剖視圖，且圖93D係一沿圖51中線LIIID-LIIID剖切之剖視圖。首先，如圖34中所示，分別在周邊電路部分13中之MOS電晶體50中之每一者之源極-汲極區54及55以及閘極電極52上形成矽化層56、57及58。矽化層56、57及58係由矽化鈷(CoSi2)、矽化鎳(NiSi)、矽化鈦(TiSi2)、矽化鉑(PtSi)、矽化鎢(WSi2)或諸如此類組成。將闡述矽化鎳之形成之一實例作為矽化層56、57及58之形成之一實例。首先，在整個表面上形成一鎳(Ni)膜。此鎳膜係使用一濺鍍設備或類似設備而形成以具有一例如10 nm之厚度。接著，在一介於約300℃至400℃之範圍內的溫度下實施一退火處理以使該鎳膜與作為該下伏層之矽起反應，從而形成一矽化鎳層。隨後藉由濕蝕刻來移除未起反應的鎳。藉由此濕蝕刻，矽化層56、57及58以一自動對準方式僅形成於矽或多晶矽表面上而不形成於該等絕緣膜上。接著，在一介於約500℃至600℃之範圍內的溫度下再次實施一退火處理以穩定該矽化鎳層。在上述矽化步驟中，如圖92A至93D中所示，由於像素部分12由第一矽化物阻斷膜71及第二矽化物阻斷膜72覆蓋，因此該矽化物不形成於像素部分12上。此結構用來防止由構成光電轉換部分21上之矽化物之金屬之擴散而引起之白疵點數及暗電流之增大。相應地，除非像素部分12中之MOS電晶體之源極-汲極區34及35之表面具有一高雜質濃度，否則接觸電阻顯著增大。此實施例係有利的，因為可相對抑制接觸電阻之增大，此乃因源極-汲極區34及35之表面可具有一高雜質濃度。 Next, description will be made with reference to 92A, 92B, 93C, 93D, and the like. Figure 92A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 92B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 93C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 93D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in FIG. 34, the deuterated layers 56, 57, and 58 are formed on the source-drain regions 54 and 55 and the gate electrode 52 of each of the MOS transistors 50 in the peripheral circuit portion 13, respectively. . The deuterated layers 56, 57, and 58 are composed of cobalt silicide (CoSi 2 ), nickel telluride (NiSi), titanium telluride (TiSi 2 ), platinum telluride (PtSi), tungsten germanium (WSi 2 ), or the like. An example of the formation of deuterated nickel will be described as an example of the formation of deuterated layers 56, 57 and 58. First, a nickel (Ni) film is formed on the entire surface. This nickel film is formed using a sputtering apparatus or the like to have a thickness of, for example, 10 nm. Next, an annealing treatment is performed at a temperature ranging from about 300 ° C to 400 ° C to react the nickel film with the ruthenium as the underlying layer, thereby forming a nickel-deposited layer. The unreacted nickel is then removed by wet etching. By this wet etching, the deuterated layers 56, 57, and 58 are formed only on the surface of the tantalum or polysilicon in an automatic alignment manner without being formed on the insulating films. Next, an annealing treatment is again performed at a temperature ranging from about 500 ° C to 600 ° C to stabilize the nickel telluride layer. In the above-described deuteration step, as shown in FIGS. 92A to 93D, since the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72, the germanide is not formed on the pixel portion 12. . This structure serves to prevent an increase in the number of white spots and dark current caused by the diffusion of the metal constituting the telluride on the photoelectric conversion portion 21. Accordingly, unless the surface of the source-drain regions 34 and 35 of the MOS transistor in the pixel portion 12 has a high impurity concentration, the contact resistance is remarkably increased. This embodiment is advantageous because the increase in contact resistance can be relatively suppressed because the surface of the source-drain regions 34 and 35 can have a high impurity concentration.
接著，如同在參照圖35及36之說明中一樣，在像素部分12之整個表面及周邊電路部分13上形成一蝕刻止擋膜74。蝕刻止擋膜74係由例如氮化矽膜組成。此氮化矽膜具有一使在用於形成接觸孔之蝕刻期間之過蝕刻最小化之效應。此外，此氮化矽膜具有一抑制因蝕刻損壞而引起之接面洩漏之增大之效應。 Next, as in the description with reference to Figs. 35 and 36, an etch stop film 74 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The etch stop film 74 is composed of, for example, a tantalum nitride film. This tantalum nitride film has an effect of minimizing overetching during etching for forming contact holes. Further, the tantalum nitride film has an effect of suppressing an increase in junction leakage due to etching damage.
接著，如同在參照圖37及38之說明中一樣，在蝕刻止擋膜74上形成一層間絕緣膜76。層間絕緣膜76係由例如氧化矽膜組成且具有一例如介於100至1,000 nm之範圍內的厚度。接下來，平坦化層間絕緣膜76之表面。此平坦化係藉由例如化學機械研磨(CMP)來實施。接下來，形成一用於形成接觸孔之抗蝕劑遮罩(未顯示)。接著，藉由例如蝕刻像素部分12中之層間絕緣膜76、蝕刻止擋膜74及第二矽化物阻斷膜72來形成接觸孔77、78及79。同樣地，在周邊電路部分13中形成接觸孔81及82。在像素部分12中，作為一實例，分別抵達傳送閘TRG、重設電晶體RST之閘極電極32及放大電晶體Amp之閘極電極32之接觸孔77、78及79顯示於圖37中。在周邊電路部分13中，作為一實施，分別抵達一N通道(Nch)低崩潰電壓電晶體之源極-汲極區55及一P通道(Pch)低崩潰電壓電晶體之源極-汲極區55之接觸孔81及82顯示於圖38中。然而，亦同時形成抵達其他電晶體之閘極電極及源極-汲極區之接觸孔，但其未顯示於該等圖式中。 Next, as in the description with reference to Figs. 37 and 38, an interlayer insulating film 76 is formed on the etching stopper film 74. The interlayer insulating film 76 is composed of, for example, a hafnium oxide film and has a thickness of, for example, in the range of 100 to 1,000 nm. Next, the surface of the interlayer insulating film 76 is planarized. This planarization is performed by, for example, chemical mechanical polishing (CMP). Next, a resist mask (not shown) for forming a contact hole is formed. Next, the contact holes 77, 78, and 79 are formed by, for example, etching the interlayer insulating film 76 in the pixel portion 12, the etching stopper film 74, and the second vaporization blocking film 72. Similarly, contact holes 81 and 82 are formed in the peripheral circuit portion 13. In the pixel portion 12, as an example, the contact holes 77, 78, and 79 which respectively reach the transfer gate TRG, the gate electrode 32 of the reset transistor RST, and the gate electrode 32 of the amplifying transistor Amp are shown in FIG. In the peripheral circuit portion 13, as an implementation, the source-drain region 55 of a N-channel (Nch) low breakdown voltage transistor and the source-drain of a P-channel (Pch) low breakdown voltage transistor are respectively reached. Contact holes 81 and 82 of the region 55 are shown in FIG. However, contact holes reaching the gate electrode and the source-drain region of the other transistors are also formed at the same time, but they are not shown in the drawings.
接下來，在接觸孔77至79、81及82中之每一者內部形成一塞柱85，而一黏著層(未顯示)及一障壁金屬層84位於其之間。作為該黏著層，例如，使用一鈦(Ti)膜或一鉭(Ta)膜。作為障壁金屬層84，例如，使用一氮化鈦膜或一氮化鉭膜。塞柱85可由例如鎢(W)、鋁(Al)或銅(Cu)組成。舉例而言，當使用銅(Cu)作為塞柱85時，例如，使用一鉭膜作為該黏著層並使用一氮化鉭膜作為障壁金屬層84。接著，儘管未顯示於該等圖式中，但形成多層佈線。若必要，可使佈線層數減至兩層、三層、四層等等。 Next, a plug 85 is formed inside each of the contact holes 77 to 79, 81 and 82, and an adhesive layer (not shown) and a barrier metal layer 84 are interposed therebetween. As the adhesive layer, for example, a titanium (Ti) film or a tantalum (Ta) film is used. As the barrier metal layer 84, for example, a titanium nitride film or a tantalum nitride film is used. The plug post 85 may be composed of, for example, tungsten (W), aluminum (Al), or copper (Cu). For example, when copper (Cu) is used as the plug 85, for example, a tantalum film is used as the adhesive layer and a tantalum nitride film is used as the barrier metal layer 84. Next, although not shown in the drawings, a multilayer wiring is formed. If necessary, the number of wiring layers can be reduced to two, three, four, and the like.
接下來，如圖39之像素部分之剖視圖中所示，可在光電轉換部分21上形成一波導23。另外，為了將入射光聚焦至光電轉換部分21，可形成一聚焦透鏡25。可在波導23與聚焦透鏡25之間形成一用於光譜分離光之濾色片27。 Next, as shown in a cross-sectional view of the pixel portion of Fig. 39, a waveguide 23 can be formed on the photoelectric conversion portion 21. In addition, in order to focus the incident light to the photoelectric conversion portion 21, a focus lens 25 can be formed. A color filter 27 for spectrally separating light may be formed between the waveguide 23 and the focus lens 25.
在製造一固態成像裝置之上述方法(第四實例)中，當形成像素電晶體部分17中之側壁33及該周邊電路部分中之側壁53時，浮動擴散部分FD亦由側壁膜137(第一矽化物阻斷膜71)覆蓋。相應地，該等側壁之形成期間之蝕刻損壞不出現在浮動擴散部分FD中。此外，可防止浮動擴散部分FD上之外擴散效應。因而，可抑制隔離區16與浮動擴散部分FD之間的一洩漏路徑之產生，從而抑制FD白疵點之產生。相應地，可製造一可實現具有高影像品質之成像之固態成像裝置。另外，像素部分12由兩層(亦即，由相同於側壁膜137之膜組成之第一矽化物阻斷膜71及由一不同於第一矽化物阻斷膜71之膜組成之第二矽化物阻斷膜72)覆蓋。相應地，像素部分12中之MOS電晶體不由一單一矽化物阻斷膜完全覆蓋。因而，可減小隨機雜訊且可減小白疵點數及暗電流。 In the above method (fourth example) of manufacturing a solid-state imaging device, when the sidewall 33 in the pixel transistor portion 17 and the sidewall 53 in the peripheral circuit portion are formed, the floating diffusion portion FD is also formed by the sidewall film 137 (first The telluride blocking film 71) is covered. Accordingly, etching damage during formation of the sidewalls does not occur in the floating diffusion portion FD. Further, the external diffusion effect on the floating diffusion portion FD can be prevented. Thus, generation of a leak path between the isolation region 16 and the floating diffusion portion FD can be suppressed, thereby suppressing the generation of the FD chalk point. Accordingly, a solid-state imaging device that can realize imaging with high image quality can be manufactured. In addition, the pixel portion 12 is composed of two layers (that is, a first telluride blocking film 71 composed of a film identical to the sidewall film 137 and a second germanium composed of a film different from the first telluride blocking film 71). The barrier film 72) is covered. Accordingly, the MOS transistor in the pixel portion 12 is not completely covered by a single telluride blocking film. Thus, random noise can be reduced and white point and dark current can be reduced.
在對上述實施例之說明中，在一n型基板中形成一p井，且光電轉換部分21之光電二極體包括自該頂層按彼次序之一P+層及一N+層。另一選擇係，可在一p型基板中形成一n井，且光電轉換部分21之光電二極體可包括自該頂層按彼次序之一N+層及一P+層。 In the description of the above embodiment, a p-well is formed in an n-type substrate, and the photodiode of the photoelectric conversion portion 21 includes a P + layer and an N + layer from the top layer. Alternatively, an n-well can be formed in a p-type substrate, and the photodiode of the photoelectric conversion portion 21 can include one of the N + layer and a P + layer from the top layer.
現將闡述該固態成像裝置之像素電晶體部分17中之重設電晶體RST、放大電晶體Amp及選擇電晶體SEL。 The reset transistor RST, the amplifying transistor Amp, and the selection transistor SEL in the pixel transistor portion 17 of the solid-state imaging device will now be explained.
在重設電晶體RST中，一汲極電極(源極-汲極區35)連接至一重設線(未顯示)，且一源極電極(源極-汲極區34)連接至浮動擴散部分FD。在信號電荷自光電轉換部分21傳送至浮動擴散部分FD之前，一重設脈衝供應至一閘極電極，且由此，重設電晶體RST將浮動擴散部分FD之電位重設至一重設電壓。 In the reset transistor RST, a drain electrode (source-drain region 35) is connected to a reset line (not shown), and a source electrode (source-drain region 34) is connected to the floating diffusion portion. FD. Before the signal charge is transferred from the photoelectric conversion portion 21 to the floating diffusion portion FD, a reset pulse is supplied to a gate electrode, and thereby, the reset transistor RST resets the potential of the floating diffusion portion FD to a reset voltage.
在放大電晶體Amp中，一閘極電極32連接至浮動擴散部分FD，且一汲極電極(源極-汲極區34)連接至一像素電力供應Vdd。放大電晶體Amp輸出在重設電晶體RST之重設之後所獲得之浮動擴散部分FD之 電位作為一重設位準，並進一步輸出一在該等信號電荷由一傳送電晶體TRG傳送之後所獲得之浮動擴散部分FD之電位作為一信號位準。 In the amplifying transistor Amp, a gate electrode 32 is connected to the floating diffusion portion FD, and a drain electrode (source-drain region 34) is connected to a pixel power supply Vdd. The floating diffusion portion FD obtained after the reset transistor Amp output is reset by resetting the transistor RST The potential is used as a reset level, and further outputs a potential of the floating diffusion portion FD obtained after the signal charges are transferred from a transfer transistor TRG as a signal level.
在選擇電晶體SEL中，例如，一汲極電極(源極-汲極區34)連接至放大電晶體Amp之一源極電極(源極-汲極區35)，且一源極電極(源極-汲極區35)連接至一輸出信號線(未顯示)。當一選擇脈衝供應至一閘極電極32時，選擇電晶體SEL轉至一導通狀態並將一自放大電晶體Amp之信號輸出輸出至輸出信號線(未顯示)同時使一像素處於一選定狀態下。選擇電晶體SEL可經組態以連接於像素電力供應Vdd與放大電晶體Amp之汲極電極之間。 In the selection transistor SEL, for example, a drain electrode (source-drain region 34) is connected to one source electrode (source-drain region 35) of the amplifying transistor Amp, and a source electrode (source) The pole-drain region 35) is connected to an output signal line (not shown). When a selection pulse is supplied to a gate electrode 32, the selection transistor SEL is turned to an on state and a signal output from the amplifying transistor Amp is output to an output signal line (not shown) while a pixel is in a selected state. under. The select transistor SEL can be configured to be coupled between the pixel power supply Vdd and the drain electrode of the amplifying transistor Amp.
接下來，將參照圖94之一方塊圖來闡述一根據本發明之一實施例之成像裝置。此成像裝置包括一根據本發明之一實施例之固態成像裝置。 Next, an image forming apparatus according to an embodiment of the present invention will be explained with reference to a block diagram of FIG. The image forming apparatus includes a solid-state imaging device according to an embodiment of the present invention.
如圖94中所示，一成像裝置200包括一提供有一固態成像裝置(未顯示)之成像單元201。一用於形成一影像之成像光學系統202提供於成像單元201之一光聚焦側處。一信號處理單元203(其包括一用於驅動成像單元201之驅動電路、一用於處理在該固態成像裝置中光電轉換至一影像之信號之信號處理電路及諸如此類)連接至成像單元201。由信號處理單元203處理之影像信號可由一影像儲存單元(未顯示)儲存。在此成像裝置200中，上述實施例中之任何一者中所述之固態成像裝置1可用作該固態成像裝置。 As shown in Fig. 94, an image forming apparatus 200 includes an image forming unit 201 provided with a solid-state imaging device (not shown). An imaging optical system 202 for forming an image is provided at one of the light focusing sides of the imaging unit 201. A signal processing unit 203 (which includes a driving circuit for driving the imaging unit 201, a signal processing circuit for processing signals photoelectrically converted to an image in the solid-state imaging device, and the like) is connected to the imaging unit 201. The image signal processed by signal processing unit 203 can be stored by an image storage unit (not shown). In the image forming apparatus 200, the solid-state imaging device 1 described in any of the above embodiments can be used as the solid-state imaging device.
由於根據本發明之一實施例之成像裝置200包括根據本發明之一實施例之固態成像裝置1，因此令人滿意地保證每一像素之光電轉換部分之感光度，如上文所述。相應地，根據本發明之一實施例之成像裝置200係有利的，因為可改善像素特性，例如，如減小白疵點數及 暗電流。 Since the image forming apparatus 200 according to an embodiment of the present invention includes the solid-state imaging device 1 according to an embodiment of the present invention, the sensitivity of the photoelectric conversion portion of each pixel is satisfactorily ensured as described above. Accordingly, the image forming apparatus 200 according to an embodiment of the present invention is advantageous in that pixel characteristics can be improved, for example, such as reducing the number of chalk points and Dark current.
根據本發明之一實施例之成像裝置200之結構不僅限於上文所述之結構。根據本發明之一實施例之成像裝置200可適用於包括固態成像裝置在內的任何成像裝置。 The structure of the image forming apparatus 200 according to an embodiment of the present invention is not limited to the structure described above. The imaging device 200 according to an embodiment of the present invention can be applied to any imaging device including a solid-state imaging device.
成像裝置200可製造呈一單晶片之形式或呈一具有一其中整體封裝一成像單元與一信號處理單元或一光學系統之成像功能組件之模組之形式。根據本發明之一實施例之固態成像裝置亦可適用於此一成像裝置。在此一情況下，可在該成像裝置中實現一高影像品質。在本文中，術語「成像裝置」係指例如一相機或一具有一成像功能組件之可攜式裝置。術語「成像」不僅係指藉助一相機之正常成像而且係指廣義上的指紋偵測等等。 The imaging device 200 can be fabricated in the form of a single wafer or in the form of a module having an imaging unit in which an imaging unit and a signal processing unit or an optical system are integrally packaged. A solid-state imaging device according to an embodiment of the present invention can also be applied to such an imaging device. In this case, a high image quality can be achieved in the image forming apparatus. As used herein, the term "imaging device" refers to, for example, a camera or a portable device having an imaging function component. The term "imaging" refers not only to normal imaging by means of a camera but also to fingerprint detection in a broad sense.
本申請案含有與以下專利申請案中所揭示之標的物相關之標的物：2008年8月1日在日本專利局提出申請之日本優先權專利申請案JP 2008-199518；2008年8月1日在日本專利局提出申請之日本優先權專利申請案JP 2008-199519；及2009年2月20日在日本專利局提出申請之日本優先權專利申請案JP 2009-037557，其全部內容以引用方式據此併入本文中。 The present application contains the subject matter related to the subject matter disclosed in the following patent application: Japanese Priority Patent Application No. JP 2008-199518 filed on Jan. 1, 2008 in the Japan Patent Office; August 1, 2008 Japanese Priority Patent Application No. JP-A-2008-199519, filed on Jan. 20, 2009, the entire contents of This is incorporated herein.
熟習此項技術者應瞭解，可視設計要求及其他因素而作出各種修改、組合、子組合及變更，只要其歸屬於隨附申請專利範圍及其等效範圍之範疇內即可。 Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made in the scope of the accompanying claims and the scope of the equivalents.
1‧‧‧固態成像裝置 1‧‧‧Solid imaging device
1A‧‧‧固態成像裝置 1A‧‧‧ Solid-state imaging device
11‧‧‧半導體基板 11‧‧‧Semiconductor substrate
12‧‧‧像素部分 12‧‧‧pixel section
14‧‧‧第一隔離區 14‧‧‧First isolation area
21‧‧‧光電轉換部分 21‧‧‧Photoelectric conversion section
32‧‧‧閘極電極 32‧‧‧gate electrode
33‧‧‧第一側壁 33‧‧‧First side wall
34‧‧‧源極-汲極區 34‧‧‧Source-Bungee Area
35‧‧‧源極-汲極區 35‧‧‧Source-bungee area
71‧‧‧第一矽化物阻斷膜 71‧‧‧First Telluride Blocking Film
72‧‧‧第二矽化物阻斷膜 72‧‧‧Second Telluride Blocking Film
FD‧‧‧浮動擴散部分 FD‧‧‧Floating diffusion part
TRG‧‧‧傳送閘 TRG‧‧‧Transmission gate
RST‧‧‧重設電晶體 RST‧‧‧Reset the transistor
Amp‧‧‧放大電晶體 Amp‧‧‧Amplified Transistor
SEL‧‧‧選擇電晶體 SEL‧‧‧Selecting a crystal
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| JP2008199519A JP5386875B2 (en) | 2008-08-01 | 2008-08-01 | Method for manufacturing solid-state imaging device |
| JP2009037557A JP5493382B2 (en) | 2008-08-01 | 2009-02-20 | Solid-state imaging device, manufacturing method thereof, and imaging device |
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