TWI399851B - Solid-state imaging device, method of producing the same, and imaging device - Google Patents

Description

Solid-state imaging device, method of manufacturing solid-state imaging device, and imaging device

The present invention relates to a solid-state imaging device, a method of manufacturing the same, and an imaging device.

A method of manufacturing a solid-state imaging device in which a sidewall having a three-layer structure is formed on a gate electrode of a MOS transistor of the solid-state imaging device, and a sensor portion is formed on one of the solid-state imaging devices a film similar to the film having the sidewall of the three-layer structure (hereinafter referred to as "sidewall film") to use the sidewall film as a germanium resist for preventing a germanide from being formed on the sensor portion Broken matter (see, for example, domestic reprint of PCT International Patent Application Publication No. WO2003/096421 (Document '421) (specifically, Figure 64 and its associated description)).

However, according to the method described in the '421, in order to form the source-drain regions of the MOS transistors, the formation of the source-drain electrodes is performed via the sidewall film having the three-layer structure. Ion implantation in the area. Therefore, it has been difficult to improve the short channel effect while suppressing the parasitic resistance. Further, in the state in which the source-drain regions are completely covered by the sidewall film having the three-layer structure, the source-drain regions are annealed, and thus the stress caused by the sidewall film is increased. (Stress Memory Technology (SMT), see, for example, K. Ota et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS (New Local Strain Channel Technology for High Efficiency 55nm CMOS)" IEDM Tech.Dig., Pp. 27-30, 2002). Further, it is assumed that the ion implantation conditions necessary for forming the source-drain region of the MOS transistor in a logic portion are different from the ion implantation for forming the source-drain region of the MOS transistor in the pixel portion. Into the conditions. The reason for this is that ion implantation for the MOS transistor in the pixel portion is performed via the sidewall film, and ion implantation for the MOS transistor in the logic portion is performed without such a film. Thus, the depth of one of the impurity diffusion layers of each of the MOS transistors in the logic portion is different from the depth of one of the impurity diffusion layers of each of the MOS transistors in the pixel portion. The gate length of the MOS transistors in the logic portion is shorter than the gate length of the MOS transistors in the pixel portion. Accordingly, it is difficult to improve the short-channel effect while suppressing the junction leakage while suppressing the increase in the parasitic resistance. Of course, ion implantation for forming the source-drain regions of the MOS transistors in the logic portion and ion implantation for forming the source-drain regions of the MOS transistors in the pixel portion The implementation is separate, but this is not stated in the literature '421.

Further, when the source-drain regions are annealed in a state in which a cover film completely covering the gate electrodes is provided, a tensile stress is applied to the cover film (SMT). This film stress can create crystal defects in one of the layers of the sensor portion, which can result in an increase in random noise and an increase in chalk points and dark current.

As described above, ion implantation for forming the source-drain regions is performed via the sidewall film. Accordingly, it is difficult to set the depth of an impurity diffusion layer to a desired value while maintaining a high ion concentration at the cerium (Si) surface. Thus, the parasitic resistance of the source-drain regions is increased, thereby reducing one of the driving forces of a pixel transistor.

A manufacturing method has also been disclosed in which the above-mentioned side wall film is not used as a telluride blocking film, but another film for telluride blocking is separately provided (see, for example, Japanese Unexamined Patent No. 2008-85104) Patent application publication). In this manufacturing method, a substrate is easily damaged by etch back of a sidewall film for forming a sidewall on each sidewall of the gate electrode. This causes a problem of an increase in dark current. Further, in this method, an oxide film disposed on a photodiode is removed prior to performing ion implantation for forming a source-drain region. Accordingly, a resist mask is directly formed on the photodiode. Thus, the photodiode is contaminated by the etchant to increase dark current. In addition, one of the surface areas of the P-type impurity is lost due to the wet etching performed on the photodiode. Thereby, the dark current is increased. During the wet etching for removing the oxide film on the photodiode, one of the isolation regions (shallow trench isolation (STI)) in one of the logic portions removed by the etching is increased the size of. Accordingly, when a germanide is formed on the source-drain region at one of the edges of the isolation region in the logic region, the junction leakage due to the germanide is increased. When the oxide film on the photodiode is removed, the problem of lifting a part of the sidewall film becomes serious. Thereby, the yield is lowered.

In a MOS transistor of a solid-state imaging device, when a sidewall having a two-layer structure is formed on each sidewall of a gate electrode, the gate electrode is formed on a germanium substrate, and a gate is formed The insulating film is located between them. Next, a ruthenium oxide film covering the gate electrode is formed on the ruthenium substrate. Further, a ruthenium oxide film is formed on the ruthenium oxide film. Next, the entire surface of the tantalum nitride film is etched back so that the tantalum nitride film continues to exist on the sidewall of the gate electrode with the tantalum oxide film therebetween. In this etch back, the ruthenium oxide film functions as an etch stop. Next, the hafnium oxide film is etched. Thereby, the upper surface of the gate electrode is exposed and the germanium substrate is also exposed. In this step, the hafnium oxide film formed on one of the photodiodes of the solid-state imaging device is also removed.

In the above method, the film thickness of the ruthenium oxide layer is also reduced by reducing the pixel size and the transistor size. Therefore, in the etch back of the tantalum nitride film, it is difficult to stop the etching without damaging the germanium substrate serving as the underlying layer. In general, when a ruthenium oxide film is used as an etch stop in etching a tantalum nitride film, it is difficult to ensure a sufficient etching selectivity.

In addition, during the removal of the hafnium oxide film, a portion of the hafnium oxide film located under the sidewall composed of the tantalum nitride film is also removed by the wet etching. Thus, the side wall is in a state of stress lift caused by a subsequent heat treatment or the like. The side wall in this state can be a cause of contamination that can lead to a decrease in yield.

When the hafnium oxide film is etched, the hafnium oxide film on one of the photodiodes of the solid-state imaging device is also removed. Next, ion implantation for forming the source and drain of an nFET and a pFET is performed. In this case, a resist mask for the ion implantation is directly formed on the photodiode. Therefore, the photodiode can be contaminated with sodium (Na) and the like contained in the anti-etching agent. These contaminants can cause an increase in the number of chalk points.

Figure 95 is a layout diagram of a CMOS sensor. As shown in FIG. 95, a photodiode PD and an active region 15 connected to the photodiode PD are provided on a substrate. A transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially disposed on the active region 15. A floating diffusion portion FD is provided between the transfer gate TRG and the reset transistor RST. Figure 96 shows an equivalent circuit of the planar arrangement described above. In the arrangement shown in FIG. 96, a pixel includes a single photodiode PD, a floating diffusion portion FD, and four transistors (ie, a transfer gate TRG, a reset transistor RST, and an amplifying transistor). Amp and a selection transistor SEL). This arrangement shows a structure in which a plurality of photodiodes are shared. Alternatively, a plurality of photodiodes PD may be shared, or a pixel may include three transistors instead of the four transistors.

It is desirable to reduce random noise, chalk points and dark current.

In accordance with an embodiment of the present invention, two different telluride blocking films are formed to partially overlap one another in one of the MOS transistors in a pixel portion, thereby reducing random noise, chalk points, and dark current.

A solid-state imaging device according to an embodiment of the present invention, comprising: a semiconductor substrate comprising: a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal; and a pixel portion disposed on the pixel a peripheral portion of the peripheral portion; a first sidewall formed by a sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the pixel portion; a second sidewall, which is the same as a film of the sidewall film is formed and disposed on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion; a first vaporization blocking film composed of a film identical to the sidewall film and disposed on a portion of the MOS transistor in the pixel portion; and a second bismuth blocking film disposed on the MOS transistors in the pixel portion to be associated with the first germanide One of the blocking films partially overlaps, wherein the MOS transistors in the pixel portion are covered by the first vapor blocking film and the second germanide blocking film.

In a solid-state imaging device according to an embodiment of the present invention, the MOS transistors in the pixel portion are composed of two films (that is, the first vapor blocking film composed of a film identical to the sidewall film) And covering by the second telluride blocking film composed of a film different from the first telluride blocking film. Therefore, the MOS transistors in the pixel portion are not completely covered by a single telluride blocking film. Thus, random noise can be reduced, and white point and dark current can be reduced.

A method of fabricating a solid-state imaging device according to an embodiment of the present invention, for forming a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal, and forming a semiconductor substrate a peripheral circuit portion at a periphery of the pixel portion, the method comprising the steps of: forming a sidewall film covering the pixel portion and the peripheral circuit portion; forming a gate electrode of the MOS transistor in the pixel portion a first sidewall of the sidewall film on a sidewall, a second sidewall formed by a sidewall film on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion, and a photocell in the pixel portion Converting a portion and a first vapor blocking film composed of a sidewall film on a portion of the MOS transistors; and forming a second germanide blocking film on the MOS transistors in the pixel portion to A telluride blocking film overlaps, wherein the MOS transistors in the pixel portion are covered by the first telluride blocking film and the second germanide blocking film.

In a method of fabricating a solid-state imaging device according to an embodiment of the present invention, the MOS transistors in the pixel portion are composed of two films (that is, the first germanide composed of a film identical to the sidewall film) The blocking film is covered by the second vapor blocking film composed of a film different from the first telluride blocking film. Therefore, the MOS transistors in the pixel portion are not completely covered by a single telluride blocking film. Thus, random noise can be reduced, and white point and dark current can be reduced.

An imaging apparatus according to an embodiment of the present invention includes: a light focusing optical unit configured to focus incident light; a solid state imaging device configured to receive light focused in the light focusing optical unit and Photoelectrically converting the light; and a signal processing unit configured to process a signal obtained by photoelectric conversion. In the image forming apparatus, the solid-state imaging device includes: a semiconductor substrate including a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal, and a peripheral portion disposed at the periphery of the pixel portion a peripheral circuit portion; a first sidewall, which is composed of a sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the pixel portion; and a second sidewall which is identical to the sidewall film a film composition and disposed on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion; a first vaporization blocking film composed of a film identical to the sidewall film and disposed in the pixel portion And the second vaporization blocking film disposed on the MOS transistors in the pixel portion to be opposite to the first germanide blocking film A portion overlaps, wherein the MOS transistors in the pixel portion are covered by the first vapor blocking film and the second germanide blocking film.

An image forming apparatus according to an embodiment of the present invention includes a solid-state image forming apparatus according to an embodiment of the present invention. Accordingly, random noise can be reduced, and white point and dark current can be reduced.

A solid-state imaging device according to an embodiment of the present invention is advantageous in that random noise can be reduced and white point and dark current can be reduced.

A method of fabricating a solid-state imaging device according to an embodiment of the present invention is advantageous because random noise can be reduced and white point and dark current can be reduced.

Since the image forming apparatus according to an embodiment of the present invention includes the solid-state image forming apparatus according to an embodiment of the present invention, random noise can be reduced, and white point and dark current can be reduced. Therefore, the image quality can be improved.

The mode for carrying out the invention (hereinafter referred to as "the embodiment") will be explained below.

1. First embodiment

A first embodiment of the present invention will be described with reference to a schematic structural cross-sectional view of one of the pixel portions of FIG. 1, a schematic structural cross-sectional view of one of the peripheral circuit portions of FIG. 2, and a planar layout of the pixel portion of FIG. 5A. A first example of the structure of a solid-state imaging device. Fig. 5A shows a case where one of the transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are connected to each other as an active region. It should be noted that the pixel portion shown in FIG. 1 and the peripheral circuit portion shown in FIG. 2 are formed on the same semiconductor substrate. Figure 1 shows a section taken along line I-I of Figure 5A. In addition, a schematic structural cross-sectional view of one of the pixel portions of FIG. 3, a schematic structural cross-sectional view of one of the peripheral circuit portions of FIG. 4, and a planar layout of the pixel portion of FIG. 5B will be described with reference to the first embodiment. A second example of the structure of a solid-state imaging device. FIG. 5B shows a case where an active region composed of a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a select transistor SEL is separated by shallow trench isolation (STI). It should be noted that the pixel portion shown in FIG. 3 and the peripheral circuit portion shown in FIG. 4 are formed on the same semiconductor substrate. Figure 3 shows a section taken along line III-III of Figure 5B. In order to reduce the pixel size in the same size of the saturated charge Qs, the arrangement shown in Fig. 5 is preferable.

[First Example of Structure of Solid-State Imaging Device]

As shown in Figs. 1, 2 and 5A, a solid-state imaging device 1 (A) includes a semiconductor substrate 11 including a pixel portion 12 having a photoelectric conversion portion 21 for photoelectrically converting incident light to obtain an electrical signal. And a peripheral circuit portion 13 disposed at the periphery of the pixel portion 12. In the pixel portion 12 of the semiconductor substrate 11, a photoelectric conversion portion 21 is provided, and a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially connected in series to be connected to the photoelectric conversion Part 21. The photoelectric conversion portion 21 is composed of, for example, a photodiode.

A first sidewall 33 composed of a sidewall film is provided to each of the gate electrodes 32 of the MOS transistor 30 (transfer gate TRG, reset transistor RST, amplifier transistor Amp, and select transistor SEL) in the pixel portion 12. On the side wall. Further, a second side wall 53 composed of a film identical to the side wall film is provided on the side wall of each of the gate electrodes 52 of the MOS transistor 50 of the peripheral circuit portion 13. Further, a first telluride blocking film 71 composed of a film identical to the film of the side wall is provided on the photoelectric conversion portion 21. Further, a second vaporization blocking film 72 partially overlapping one of the first telluride blocking films 71 is provided on each of the MOS transistors 30 in the pixel portion 12. The first telluride blocking film 71 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. The second telluride blocking film 72 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. Therefore, the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72. A portion in which the second telluride blocking film 72 overlaps with the first telluride blocking film 71 is formed in the pixel portion 12.

For each of the MOS transistors 50 in the peripheral circuit portion 13, for example, a deuterated layer 58 is provided on the gate electrode 52, and the deuterated layers 56 and 57 are provided on the source-drain regions 54 and 55, respectively. . In this manner, in order to reduce the parasitic resistance to achieve a high speed operation, each of the MOS transistors 50 in the peripheral circuit portion 13 is deuterated.

The first isolation region 14 that separates the pixel portion 12 is provided in the semiconductor substrate 11. A second isolation region 15 partitioning a region in which the MOS transistors in the peripheral circuit portion 13 are formed is provided in the semiconductor substrate 11. Each of the first isolation regions 14 and the second isolation regions 15 has an STI structure. The first isolation regions 14 are formed to be shallower than the second isolation regions 15. In addition, the first isolation regions 14 are formed such that the height of one of the portions of each of the isolation regions 14 protruding from the semiconductor substrate 11 is low.

As described above, the solid-state imaging device 1 (A) includes a region in which the sidewall film is used to form the first vapor blocking film 71, and a second vapor blocking film 72 is formed therein (by separately A region in which an insulating film for silicide blocking is formed, and a region in which the deuterated layer 56 or 57 is formed as in the MOS transistor 50 in the peripheral circuit portion 13 is formed. Further, a first telluride blocking film 71 composed of the side wall film is formed on the photoelectric conversion portion 21.

[Second example of the structure of the solid-state imaging device]

As shown in Figs. 3, 4 and 5B, a solid-state imaging device 1 (B) includes a semiconductor substrate 11 including a pixel portion 12 having a photoelectric conversion portion 21 for photoelectrically converting incident light to obtain an electrical signal. And a peripheral circuit portion 13 disposed at the periphery of the pixel portion 12. In the pixel portion 12 of the semiconductor substrate 11, a photoelectric conversion portion 21 is provided, and a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially connected in series to be connected to the photoelectric conversion Part 21. The photoelectric conversion portion 21 is composed of, for example, a photodiode.

A first sidewall 33 composed of a sidewall film is provided to each gate electrode 32 of the MOS transistor (transfer gate TRG, reset transistor RST, amplifier transistor Amp, and select transistor SEL) in the pixel portion 12. On the side wall. Further, a second side wall 53 composed of a film identical to the side wall film is provided on the side wall of each of the gate electrodes 52 of the MOS transistor 50 in the peripheral circuit portion 13. Further, a first telluride blocking film 71 composed of a film identical to the film of the side wall is provided on the photoelectric conversion portion 21. Further, a second vaporization blocking film 72 partially overlapping one of the first telluride blocking films 71 is provided on each of the MOS transistors 30 in the pixel portion 12. The first telluride blocking film 71 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. The second telluride blocking film 72 has a stacked structure including, for example, a hafnium oxide film and a tantalum nitride film. Therefore, the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72. A portion in which the second telluride blocking film 72 overlaps with the first telluride blocking film 71 is formed in the pixel portion 12.

For each of the MOS transistors 50 in the peripheral circuit portion 13, for example, a deuterated layer 58 is provided on the gate electrode 52, and the deuterated layers 56 and 57 are provided on the source-drain regions 54 and 55, respectively. . In this manner, in order to reduce the parasitic resistance to achieve a high speed operation, each of the MOS transistors 50 in the peripheral circuit portion 13 is deuterated.

A first isolation region 14 partitioning a region in which the MOS transistors in the pixel portion 12 are formed is provided in the semiconductor substrate 11. A second isolation region 15 partitioning a region in which the MOS transistors in the peripheral circuit portion 13 are formed is provided in the semiconductor substrate 11. Each of the first isolation regions 14 and the second isolation regions 15 has an STI structure. The first isolation regions 14 are formed to be shallower than the second isolation regions 15. In addition, the first isolation regions 14 are formed such that the height of one of the portions of each of the first isolation regions 14 protruding from the semiconductor substrate 11 is low.

As described above, the solid-state imaging device 1 (B) includes a region in which the sidewall film is used to form the first vapor blocking film 71, and a second vapor blocking film 72 is formed therein (by separately A region where a germanide blocking insulating film is formed, and a region where the germanium layer 56 or 57 is formed as in the MOS transistor 50 in the peripheral circuit portion 13 are formed. Further, a first telluride blocking film 71 composed of the side wall film is formed on the photoelectric conversion portion 21.

In each of the solid-state imaging devices 1 (1A and 1B), in order to prevent impurity contamination and flaw generation due to a telluride, the pixel portion 12 is preferably composed of a first telluride blocking film 71 and a second deuteration. The barrier film 72 is completely covered. The first telluride blocking film 71 and the second germanium germanium blocking film 72 may not be provided on the first and second isolation regions 14 and 15. However, it is necessary to maximize the light receiving area of the photoelectric conversion portion 21 in the same pixel size to increase the saturation charge (Qs), thereby reducing the noise effect. Accordingly, in order not to consider the overlapping margins on the isolation regions, the upper surface of the isolation regions is preferably covered by the first vapor blocking film 71 and the second vapor blocking film 72. This structure can reduce the area of the isolation regions to increase the light receiving area of the photoelectric conversion portion 21.

Thus, in the above arrangement of the solid-state imaging device 1, in order to reduce the separation width of one of the isolation regions to increase the ratio of the area of the photodiode, the second vaporization blocking film 72 and the first germanide are provided therein. The portion where the film 71 overlaps is blocked. Thereby, the level difference on each of the gate electrodes 32 in the pixel portion 12 is increased, and it is difficult to ensure the flatness of the interlayer insulating film. For example, in the separation technique described in Japanese Unexamined Patent Application Publication No. Hei No. 2005-347325, the height of one oxide film isolation portion protruding from the surface of a silicon (Si) substrate in one pixel Increased, and thus it is more difficult to ensure flatness. In this embodiment of the invention, the first isolation region 14 having a shallow trench isolation (STI) structure is used to make the height of the portion of the first isolation region 14 protruding from the semiconductor substrate 11 low. However, if the depth of the STI of the first isolation region 14 is the same as the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13, the stress and etching damage on the photodiode constituting the photoelectric conversion portion 21 are increased. This leads to an increase in the number of chalk points. Therefore, the first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. In order to achieve a high speed operation, the STI of the second isolation region 15 in the peripheral circuit portion 13 has a large depth to reduce the parasitic resistance between the wiring and the substrate.

In the solid-state imaging device 1 (1A) according to an embodiment of the present invention, the pixel portion 12 is composed of two layers (that is, a first telluride blocking film 71 composed of a film identical to a side wall film and a different one The second telluride blocking film 72) of the film composition of the first telluride blocking film 71 is covered. Accordingly, the MOS transistor 30 in the pixel portion 12 is not completely covered by a single telluride blocking film. This structure is advantageous because random noise can be reduced and white point and dark current can be reduced.

2. Second Embodiment [First Example of Method of Manufacturing Solid-State Imaging Device]

A first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention will now be described with reference to Figs. 6 to 39, which are cross-sectional views showing manufacturing steps.

As shown in FIG. 6, for example, a germanium substrate is used as a semiconductor substrate 11. A pad oxide film 111 and a tantalum nitride film 112 are formed on the semiconductor substrate 11. The pad oxide film 111 is formed by oxidizing one surface of the semiconductor substrate 11 by, for example, a thermal oxidation method. This pad oxide film 111 is formed to have a thickness of, for example, 15 nm. Next, a tantalum nitride film 112 is formed on the pad oxide film 111 by, for example, a low temperature chemical vapor deposition (LP-CVD) method. This tantalum nitride film 112 is formed to have a thickness of, for example, 160 nm. The above device has a structure of a tantalum nitride film/pad oxide film. Alternatively, the device may have a structure of a tantalum nitride film/polysilicon film or a structure of an amorphous germanium film/pad oxide film.

Next, as shown in Fig. 7, a resist mask (not shown) having an opening in a region in which an isolation region is to be formed is formed on the tantalum nitride film 112. Then, an opening 113 is formed in the tantalum nitride film 112 and the pad oxide film 111 by etching. For example, a reactive ion etching (RIE) device or an electron cyclotron resonance (ECR) etching device can be used for this etch. After the etching process, the resist mask is removed by means of an ashing device or the like.

Next, as shown in FIG. 8, a first element isolation trench 114 is formed in the semiconductor substrate 11 using the tantalum nitride film 112 as an etch mask. For example, an RIE device or an ECR etching device is used for this etching. First, a first etch is performed on the second element isolation trench 115 (and the first element isolation trench 114) of one of the peripheral circuit portions 13 (and a pixel portion 12). In this case, the depth of the first element isolation trench 114 (and the second element isolation trench 115) of the pixel portion 12 (and the peripheral circuit portion 13) is in the range of 50 to 160 nm. Next, although not shown in the drawings, a resist mask is formed on the pixel portion 12, and then a second for extending the second element isolation trench 115 in only the peripheral circuit portion 13 is implemented. Etching. Therefore, only the second element isolation trench 115 in the peripheral circuit portion 13 has a depth of, for example, 0.3 μm. The resist mask is then removed.

By forming a shallow first element isolation trench 114 in the pixel portion 12, an effect of reducing the number of white spots caused by etching damage can be achieved. By reducing the depth of the first element isolation trench 114, the area of an effective photoelectric conversion portion is increased. This is advantageous because the saturated charge (Qs) can be increased.

Next, although not shown in the drawings, a linear film is formed. The linear film is formed by, for example, thermal oxidation at a temperature ranging from about 800 ° C to 900 ° C. The linear film may be a hafnium oxide film, a hafnium oxide film containing nitrogen, or a CVD tantalum nitride film. The linear film has a thickness in the range of about 4 to 10 nm. Although not shown in the drawings, ion implantation for suppressing dark current boron (B) is performed in the pixel portion 12 using a resist mask. As an example of the conditions of the ion implantation, the implantation energy is set to about 10 keV, and the dose is set to be in the range of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ^-2 . In a region in which the isolation region of the pixel portion 12 is to be formed around the first element isolation trench 114, since the boron concentration is increased, the dark current can be more effectively suppressed to suppress the operation of a parasitic transistor. However, if the boron concentration is too high, the area of the photodiode constituting the photoelectric conversion portion is reduced, thereby reducing the saturation charge (Qs). For these reasons, the dose is specified as described above.

Next, as shown in FIG. 9, an insulating film is formed on the tantalum nitride film 112 to fill the inside of the second element isolation trench 115 (and the first element isolation trench 114). This insulating film is formed by depositing yttrium oxide, for example, by a high density plasma (CVD) method. Next, an excess portion of one of the insulating films formed on the tantalum nitride film 112 is removed by, for example, chemical mechanical polishing (CMP). Thus, the insulating film continues to exist inside the second element isolation trench 115 (first element isolation trench 114) to form the second isolation region 15 (first isolation region 14) composed of the insulating film. In this CMP, the tantalum nitride film 112 functions as a stopper for stopping CMP. The first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. However, the tantalum nitride film 112 is generally used as the blocking member, and thus the amount of protrusion of the first isolation region 14 is set to be the same as the amount of protrusion of the second isolation region 15. Herein, in the phrase "one of the first isolation regions 14 has a convex height equal to one of the convexities of the second isolation region 15," the convex heights are defined to be the same as long as the difference in the convex heights is in one. The range of process variations due to one of the processing precisions in manufacturing. In particular, when the tantalum nitride film 112 used as a mask in a trench process has a thickness of about 160 nm, the thickness of the tantalum nitride film 112 formed on a wafer is usually in a plane. The change is about ±10%. The thickness variation due to chemical mechanical polishing (CMP) is about ±20 to ±30 nm. Accordingly, even when the first isolation region 14 and the second isolation region 15 are formed such that the amount of protrusion in the pixel portion 12 is the same as the amount of protrusion in the peripheral circuit portion 13, the amount of protrusion may be about 20 It varies within the range of 30 nm. It is assumed that a wafer surface is closely observed and a pixel portion 12 is compared with a peripheral circuit portion 13 at some position on the surface. In this case, even if the protrusion heights are not completely identical values, the heights may be included in the "same height" in this embodiment of the invention as long as the pixel portion 12 and the peripheral circuit portion The difference in protrusion height between 13 does not exceed 30 nm. Finally, the center condition of one of the protrusion heights of the first isolation region 14 and the second isolation region 15 is set to be low; for example, within a range of about 0 to 20 nm from the surface of the crucible.

Next, as shown in FIG. 10, in order to adjust the height of a portion of the first isolation region 14 protruding from the surface of the semiconductor substrate 11, the oxide film is subjected to wet etching. The etching amount of the oxide film is, for example, in the range of 40 to 100 nm. In this embodiment of the invention, the first isolation region 14 having a shallow trench isolation (STI) structure is used to make the height of the portion of the first isolation region 14 protruding from the semiconductor substrate 11 low. However, if the depth of the STI of the first isolation region 14 is the same as the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13, the stress and etching damage on the photodiode constituting the photoelectric conversion portion 21 are increased. This leads to an increase in the number of chalk points. Therefore, the first isolation region 14 is formed to be shallower than the second isolation region 15 in the peripheral circuit portion 13. In order to achieve a high speed operation, the depth of the STI of the second isolation region 15 in the peripheral circuit portion 13 is increased to reduce the parasitic resistance between the wiring and the substrate. Next, the tantalum nitride 112 (see FIG. 9) is removed to expose the pad oxide film 111. The tantalum nitride film 112 is removed using, for example, wet etching using hot phosphoric acid.

Next, as shown in FIG. 11, in the case where the pad oxide film 111 is provided, a p well 121 is formed on the semiconductor substrate 11 by ion implantation using a resist mask (not shown). The resist mask has an opening in a region in which the p-well 121 is to be formed. Further implementation of channel ion implantation. The resist mask is then removed. Further, in the case where the pad oxide film 111 is provided, a n well 123 is formed on the semiconductor substrate 11 by ion implantation using a resist mask (not shown) having a resist mask Located in an opening in the area in which the n-well 123 is to be formed. Further implementation of channel ion implantation. The resist mask is then removed. Ion implantation of the p-well 121 is performed using boron (B) as an ion implantation species. In this ion implantation, the implantation energy is set to, for example, about 200 keV and the dose is set to, for example, 1 × 10 ¹³ cm ^-2 . Channel ion implantation is performed on p-well 121 using boron (B) as an ion implantation species. In this channel ion implantation, the implantation energy is set to be, for example, in the range of about 10 to 20 keV and the dose is set to be, for example, in the range of 1 × 10 ¹¹ to 1 × 10 ¹³ cm ^-2 . Ion implantation of n well 123 is performed using, for example, phosphorus (P) as an ion implantation species. In this ion implantation, the implantation energy is set to be, for example, in the range of about 200 keV and the dose is set to, for example, 1 × 10 ¹³ cm ^-2 . Channel ion implantation is performed on the n-well 123 using, for example, arsenic (As) as an ion implantation species. In this channel ion implantation, the implantation energy is set to, for example, about 100 keV and the dose is set to be, for example, in the range of 1 × 10 ¹¹ to 1 × 10 ¹³ cm ^-2 . Further, although not shown in the drawings, ion implantation for forming a photodiode in the photoelectric conversion portion is performed to form a p-type region. For example, ion implantation of boron (B) is performed on one surface of the semiconductor substrate in which the photoelectric conversion region is to be formed. Ion implantation is further carried out in a deep region using arsenic (As) or phosphorus (p) to form an n-type region which forms a junction with a lower portion of the p-type region. Therefore, a photoelectric conversion portion having a pn junction is formed.

Next, as shown in FIG. 12, the pad oxide film 111 is removed by, for example, wet etching (see FIG. 11). Next, a gate insulating film 51H having a large thickness for a high voltage is formed on the semiconductor substrate 11. The thickness of the gate insulating film 51H is about 7.5 nm in a transistor for a power supply voltage of 3.3 V, and about 5.5 nm in a transistor for a power supply voltage of 2.5 V. Next, a resist mask (not shown) is formed on the gate insulating film 51H having a large thickness for a high voltage, and is removed to have a large thickness formed on a region of the transistor for a low voltage. Gate insulating film 51H. After the resist mask is removed, a gate insulating film 51L having a small thickness is formed on the semiconductor substrate 11 for a low voltage transistor region. The thickness of the gate insulating film 51L is in the range of about 1.2 to 1.8 nm in a transistor for a power supply voltage of 1.0 V. At the same time, a gate insulating film 31 (not shown) having a small thickness is formed in the transistor formation region in the pixel portion. Each of the gate insulating films 51H, 51L, and 31 is composed of, for example, a thermal yttrium oxide film. Alternatively, each of the gate insulating films 51H, 51L, and 31 may be composed of a hafnium oxynitride film grown by rapid thermal oxidation (RTO). Alternatively, in order to further reduce a gate leakage, a high dielectric film such as an oxide film or an oxynitride film composed of hafnium (Hf), zirconium (Zr) or the like may be used. In the subsequent drawings, for the sake of convenience, a gate insulating film 51H having a large thickness and a gate insulating film 51L having a small thickness are shown as films having the same thickness.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 13 and the cross-sectional view of the peripheral circuit portion of FIG. 14, a gate electrode forming film 131 is formed on the gate insulating film 51 (51H and 51L) and the gate insulating film 31. . The gate electrode formation film 131 is formed by depositing polysilicon by, for example, an LP-CVD method. The thickness of the deposited film depends on the technology node, but is in the range of 150 to 200 nm in a 90-nm node. The film thickness tends to decrease for each node, since a gate aspect ratio is generally not increased from the viewpoint of controllability of the process. As a measure against gate depletion, germanium (SiGe) can be used instead of polysilicon. The gate depletion refers to the following problem: because the thickness of a gate oxide film is reduced, not only one effect of the physical thickness of the gate oxide film but also one of the thicknesses of one of the gate polysilicon layers It cannot be ignored, and therefore does not reduce the effective thickness of one of the gate oxide films, thereby degrading the transistor performance.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 15 and the cross-sectional view of the peripheral circuit portion of FIG. 16, a measure against the gate depletion is taken. First, a resist mask 132 is formed on a p-MOS transistor formation region, and then an n-type impurity is doped into the gate electrode formation film 131 in an n-MOS transistor formation region. This doping is carried out by ion implantation such as phosphorus (P) or arsenic (As). The amount of implanted ions is in the range of about 1 x 10 ¹⁵ to 1 x 10 ¹⁶ cm ^-2 . The resist mask 132 is then removed. Next, although not shown in the drawings, a resist mask (not shown) is formed on the n-MOS transistor formation region, and a p-type impurity is doped to the p-MOS The gate electrode in the crystal formation region is formed in the film 131. This doping is carried out by ion implantation such as boron (B), boron difluoride (BF ₂ ) or indium (In). The amount of ions implanted is in the range of 1 x 10 ¹⁵ to 1 x 10 ¹⁶ cm ^-2 . The resist mask is then removed. The former implant or the latter implant may be performed first. In each of the above ion implantations, in order to prevent impurities introduced by ion implantation from reaching directly below the gate insulating film, nitrogen (N ₂ ) ion implantation may be combined.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 17 and the cross-sectional view of the peripheral circuit portion of FIG. 18, a resist mask (not shown) for forming the gate electrode is formed on the gate electrode forming film 131. . The gate electrode forming film 131 is etched by reactive ion etching using the resist mask as an etch mask to form the gate electrode 32 of the MOS transistor in the pixel portion 12 and the peripheral circuit portion 13 The gate electrode 52 of the MOS transistor. Next, the surfaces of the gate electrodes 32 and 52 are oxidized to form an oxide film 133. The thickness of the oxide film 133 is, for example, in the range of 1 to 10 nm. The oxide film 133 is formed not only on the sidewalls but also on the top surface of each of the gate electrodes 32 and 52. Further, the edge portions of the rounded gate electrodes 32 and 52 in the above oxidation step have an effect of improving the breakdown voltage of the oxide film. In addition, etching damage can be reduced by performing heat treatment. Further, in the above-described processing of the gate electrodes, the oxide film 133 is formed on the photoelectric conversion portion 21 even if the gate insulating film formed on the photoelectric conversion portion 21 is removed. Therefore, when a resist film is formed on the photoelectric conversion portion 21 in the next lithography step, the resist film is not directly formed on a crucible surface, and thus contamination due to the resist can be prevented. Accordingly, for the photoelectric conversion portion 21 in the pixel portion 12, this structure serves as a measure against the chalk point.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 19 and the cross-sectional view of the peripheral circuit portion of FIG. 20, the LDD regions 38, 39 and the like of the MOS transistor in the pixel portion 12 and the MOS transistor in the peripheral circuit portion 13 are formed. The LDD areas 61, 62, 63, 64, and the like.

First, as for the NMOS transistors formed in the peripheral circuit portion 13, recess diffusion layers 65 and 66 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. These recessed diffusion layers 65 and 66 are formed by ion implantation using, for example, boron difluoride (BF ₂ ), boron (B) or indium (In) as an ion implantation species, and the dose thereof is set to, for example, It is in the range of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ^-2 . Further, LDD regions 61 and 62 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. The LDD regions 61 and 62 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ^- Within the scope of ² .

As for the MOS transistors formed in the pixel portion 12, LDD regions 38 and 39 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11. The LDD regions 38 and 39 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose is set to, for example, between 1 × 10 ¹³ and 1 × 10 ¹⁵ cm ^- Within the scope of ² . In addition, a plurality of recessed diffusion layers can be formed. As for the MOS transistor formed in the pixel division 12, the LDD regions may not be formed from the viewpoint of reducing the number of steps. Alternatively, ion implantation for forming the LDD region of the MOS transistor formed in the pixel portion 12 may function as an LDD ion implantation of the MOS transistor formed in the peripheral circuit portion 13.

As for the PMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 67 and 68 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. These recessed diffusion layers 67 and 68 are formed by ion implantation using, for example, arsenic (AS) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹² to 1 ×. Within the range of 10 ¹⁴ cm ^-2 . Further, LDD regions 63 and 64 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. The LDD regions 63 and 64 are formed by ion implantation using, for example, boron difluoride (BF ₂ ), boron (B), or indium (In) as an ion implantation species, and the dose thereof is set to, for example, 1 ×. 10 ¹³ to 1 × 10 ¹⁵ _c m ^-2 .

Before the ion implantation of the NMOS transistor and the PMOS transistor in the peripheral circuit portion, pre-amorphization can be performed by performing ion implantation of germanium (Ge) as a channel for suppressing implantation. The technology of effects. In addition, in order to reduce the number of implant turns that can cause transient enhanced diffusion (TED) or the like, rapid thermal annealing at a temperature ranging from about 800 ° C to 900 ° C can be added after the formation of the LDD regions. (RTA).

Next, as shown in the cross-sectional view of the pixel portion of FIG. 21 and the cross-sectional view of the peripheral circuit portion of FIG. 22, a tantalum oxide (SiO ₂ ) film 134 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The hafnium oxide film 134 is formed by depositing an undoped tellurite glass (NSG) film, a low pressure tetraethyl orthophthalate (LP-TEOS) film, a high temperature oxidation (HTO) film or the like. The hafnium oxide film 134 is formed to have a thickness ranging, for example, from 5 to 20 nm. Next, a tantalum nitride film 135 is formed on the hafnium oxide film 134. The tantalum nitride film 135 is composed of, for example, a tantalum nitride film formed by low pressure optical vapor deposition (LPCVD). Its thickness is, for example, in the range of 10 to 100 nm. The tantalum nitride film 135 may be an ALD tantalum nitride film formed by an atomic layer deposition method which can form the film at a low temperature. In the photoelectric conversion portion 21 in the pixel portion 12, since the thickness of the ruthenium oxide film 134 disposed directly under the tantalum nitride film 135 is reduced, light reflection is prevented, and thus the sensitivity of the photoelectric conversion portion 21 becomes high. Next, a third layer of yttrium oxide (SiO ₂ ) film 136 is deposited on the tantalum nitride film 135 as needed. This ruthenium oxide film 136 is formed by depositing an NSG film, an LP-TEOS film, an HTO film or the like. The hafnium oxide film 136 is formed to have a thickness ranging, for example, from 10 to 100 nm.

Accordingly, a sidewall film 137 is formed as a three-layer film having a structure of a hafnium oxide film 136 / a tantalum nitride film 135 / a hafnium oxide film 134. Alternatively, the sidewall film 137 may be a two-layer film having a structure of a tantalum nitride film/yttria film. A case of the side wall film 137 having the three-layer structure will be explained below.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 23 and the cross-sectional view of the peripheral circuit portion of FIG. 24, the ruthenium oxide film 136 provided as the top layer is etched back to leave the yttrium oxide film 136 only at the gate electrode 32. And on the side of each of 52 and so on. This etch back is performed by, for example, reactive ion etching (RIE). In this etch back, a tantalum nitride film 135 is used to stop the etching. Since the etching is stopped by the tantalum nitride film 135 in this manner, the etching damage on the photoelectric conversion portion 21 in the pixel portion 12 can be reduced, and thus the number of chalk dots can be reduced.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 25 and the cross-sectional view of the peripheral circuit portion of FIG. 26, a resist is formed on the entire surface of the photoelectric conversion portion 21 in the pixel portion 12 and a portion of the transfer gate TRG. Cover 138. Next, the tantalum nitride film 135 and the tantalum oxide film 134 are etched back to form a first sidewall 33 on the sidewall of each of the gate electrodes 32 and a gate electrode 52. The second sidewall 53 on the sidewall, the first sidewall 33 and the second sidewall 53 are composed of a hafnium oxide film 134, a tantalum nitride film 135, and a hafnium oxide film 136. In this step, the tantalum nitride film 135 and the hafnium oxide film 134 on the photoelectric conversion portion 21 are not etched because they are covered by the resist mask 138.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 27 and the cross-sectional view of the peripheral circuit portion of FIG. 28, a resist mask (not shown) having an opening in which the peripheral circuit portion is to be formed is formed. In the area of the NMOS transistor in the 13th. The deep source-drain regions 54 (54N) and 55 (55N) are formed in the region in which the NMOS transistors in the peripheral circuit portion 13 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 54N and 55N are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 61, 62 and the like interposed therebetween. The source-drain regions 54N and 55N are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 ×. Within the range of 10 ¹⁶ cm ^-2 . The resist mask is then removed.

Next, a resist mask (not shown) having an opening is formed in a region in which the NMOS transistor in the pixel portion 12 is to be formed. The deep source-drain regions 34 and 35 are formed in the region in which the NMOS transistors in the pixel portion 12 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 34 and 35 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11, with the LDD regions 38, 39 and the like interposed therebetween. Here, the source-drain region 35 adjacent to the transfer gate TRG functions as a floating diffusion. The source-drain regions 34 and 35 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 ×. Within the range of 10 ¹⁶ cm ^-2 . The resist mask is then removed. This ion implantation can also function as an ion implantation for forming the source-drain regions 54N and 55N of the NMOS transistor in the peripheral circuit portion 13. During the formation of the source-drain region in the document '421 described in the related art, one ion implantation is performed via three layers, and another ion implantation is directly performed without such layers. . Accordingly, it is difficult to implement this plasma implantation at the same time.

Next, a resist mask (not shown) having an opening is formed in a region in which the PMOS transistor in the peripheral circuit portion 13 is to be formed. The deep source-drain regions 54 (54P) and 55 (55P) are formed in the region in which the PMOS transistors in the peripheral circuit portion 13 are to be formed by ion implantation using the resist mask. Specifically, the source-drain regions 54P and 55P are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 63, 64 and the like interposed therebetween. The source-drain regions 54P and 55P are formed by ion implantation using, for example, boron (B) or boron difluoride (BF ₂ ) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2 . The resist mask is then removed. Next, activation annealing is performed on the source-drain regions. This activation anneal is carried out at a temperature ranging, for example, from about 800 ° C to 1,100 ° C. For this activation anneal, a rapid thermal annealing (RTA) device, a spiked RTA device, or the like can be used.

The sidewall film 137 covering the photoelectric conversion portion 21 and the sidewall 33 composed of the sidewall film 137 on the gate electrode 32 of the MOS transistor in the pixel portion 12 are divided before the activation annealing of the source-drain regions. Separated. This structure prevents degradation of stress caused by stress memory technology (SMT) as described in the related art. Accordingly, chalk spots, random noise, and the like can be suppressed. Further, the photoelectric conversion portion 21 is covered by the sidewall film 137, and a resist mask used in ion implantation for forming a source-drain region is formed on the photoelectric conversion portion 21, and the sidewall film 137 is located thereon between. In other words, the resist mask is not directly formed on the surface of the photoelectric conversion portion 21. Therefore, the photoelectric conversion portion 21 is not contaminated by the contaminants in the resist, thereby suppressing the increase in chalk dots, dark current, and the like. In addition, the ion implantation used to form the source-drain region is not ion implantation through a film, and thus the depth of the source-drain region can be set while ensuring a high concentration at the surface. Therefore, an increase in the series resistance of the source-drain region can be suppressed. Further, in the subsequent step, the sidewall film 137 covering the photoelectric conversion portion 21 is used as a first vaporization blocking film 71.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 29 and the cross-sectional view of the peripheral circuit portion of FIG. 30, a second germanide blocking film 72 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The second telluride blocking film 72 is composed of a stacked film including a tantalum oxide (SiO ₂ ) film 140 and a tantalum nitride film 139. For example, the hafnium oxide film 140 is formed to have a thickness ranging from, for example, 5 to 40 nm, and the tantalum nitride film 139 is formed to have a thickness ranging, for example, from 5 to 60 nm. The ruthenium oxide film 140 is composed of an NSG film, an LP-TEOS film, an HTO film or the like. The tantalum nitride film 139 is composed of an ALD-SiN film, a nitride film, an LP-SiN film or the like. If the deposition temperature of the two films is high, deactivation of boron occurs in the gate electrode of the PMOSFET. Thus, one of the PMOSFETs has a current drive capability that is reduced due to gate depletion. Accordingly, the deposition temperature of the yttrium oxide film 140 and the tantalum nitride film 139 is preferably lower than the deposition temperature of the sidewall film 137. The deposition temperature is preferably, for example, at 700 ° C or lower.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 31 and the cross-sectional view of the peripheral circuit portion of FIG. 32, a resist mask 141 is formed to substantially cover the region in which the MOS transistor in the pixel portion 12 is formed. The resist mask 141 is used as an etch mask to remove the second morphing on the photoelectric conversion portion 21 (and on one portion of the transfer gate TRG) and the peripheral circuit portion 13 in the pixel portion 12 by etching. The membrane 72 is blocked. Thereby, from the top layer, the tantalum nitride film 135 and the tantalum oxide film 134 are disposed on the photoelectric conversion portion 21 in this order, and thus spectral chopping can be prevented. On the contrary, if the etching is not performed, the tantalum nitride film 139, the hafnium oxide film 140, the tantalum nitride film 135, and the hafnium oxide film 134 are provided on the photoelectric conversion portion 21 in this order from the top layer. In this case, the incident light is subjected to multiple reflections, thereby degrading the spectral chopping characteristics. Due to the degradation of these chopping characteristics, the wafer-wafer spectral variation increases. In order to solve this problem, in this embodiment, the second vaporization blocking film 72 on the photoelectric conversion portion 21 is intentionally removed.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 33 and the cross-sectional view of the peripheral circuit portion of FIG. 34, the source-drain region 54 of each of the MOS transistors 50 in the peripheral circuit portion 13 and Deuterated layers 56, 57 and 58 are formed on 55 and gate electrode 52. The deuterated layers 56, 57 and 58 are composed of cobalt silicide (CoSi ₂ ), nickel (NiSi), titanium (TiSi ₂ ), platinum (PtSi), tungsten (WSi ₂ ) or the like. An example of the formation of deuterated nickel will be described as an example of the formation of deuterated layers 56, 57 and 58. First, a nickel (Ni) film is formed on the entire film. This nickel film is formed using a sputtering apparatus or the like to have a thickness of, for example, 10 nm. Next, an annealing treatment is performed at a temperature ranging from about 300 ° C to 400 ° C to cause the nickel film to react with the underlying layer to form a nickel-deposited layer. The unreacted nickel is then removed by wet etching. By this wet etching, the deuterated layers 56, 57 and 58 are formed on the tantalum or polysilicon surface in an automatic alignment manner instead of the insulating films. Next, an annealing treatment is again performed at a temperature ranging from about 500 ° C to 600 ° C to stabilize the nickel telluride layer. In the above-described deuteration step, the deuterated layer is not formed on the source-drain regions 34 and 35 and the gate electrode 32 of the MOS transistor in the pixel portion 12. This structure serves to prevent an increase in the number of white spots and dark current caused by the diffusion of the metal constituting the telluride on the photoelectric conversion portion 21. Accordingly, unless the surface of the source-drain regions 34 and 35 of the MOS transistor in the pixel portion 12 has a high impurity concentration, the contact resistance is remarkably increased. This embodiment is advantageous because the increase in contact resistance can be relatively suppressed because the surface of the source-drain regions 34 and 35 can have a high impurity concentration.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 35 and the cross-sectional view of the peripheral circuit portion of FIG. 36, an etch stop film 74 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The etch stop film 74 is composed of, for example, a tantalum nitride film. For example, a tantalum nitride film deposited by a reduced pressure CVD method or a tantalum nitride film deposited by a plasma CVD method is used as the tantalum nitride film. The thickness of the tantalum nitride film is, for example, in the range of 10 to 100 nm. This tantalum nitride film has an effect of minimizing overetching during etching for forming contact holes. Further, the tantalum nitride film has an effect of suppressing an increase in junction leakage due to etching damage.

Next, as shown in the cross-sectional view of the pixel portion of FIG. 37 and the cross-sectional view of the peripheral circuit portion of FIG. 38, an interlayer insulating film 76 is formed on the etching stopper film 74. The interlayer insulating film 76 is composed of, for example, a hafnium oxide film and has a thickness of, for example, in the range of 100 to 1,000 nm. The ruthenium oxide film is formed by, for example, a CVD method. As the ruthenium oxide film, a tetraethyl orthophthalate (TEOS) film, a monophosphorus phosphate glass (PSG) film, a boron borophosphate (BPSG) film or the like is used. Alternatively, a tantalum nitride film or the like may be used. Next, the surface of the interlayer insulating layer 76 is planarized. This planarization is performed by, for example, chemical mechanical polishing (CMP). Next, a resist mask (not shown) for forming a contact hole is formed, followed by, for example, etching the interlayer insulating film 76, the etch stop film 74, and the second germanide blocking film 72 in the pixel portion 12. Contact holes 77, 78, and 79 are formed. Similarly, contact holes 81 and 82 are formed in the peripheral circuit portion 13. In the pixel portion 12, as an example, the contact holes 77, 78, and 79 which respectively reach the transfer gate TRG, the gate electrode 32 of the reset transistor RST, and the gate electrode 32 of the amplifying transistor Amp are shown in FIG. In the peripheral circuit portion 13, as an example, respectively reach the source-drain region 55 of an N-channel (Nch) low breakdown voltage transistor and the source-drain of a P-channel (Pch) low breakdown voltage transistor. Contact holes 81 and 82 of the region 55 are shown in FIG. However, contact holes reaching the gate electrode and the source-drain region of other transistors are also formed, but they are not shown in the drawings. In forming the contact holes 77 to 79, 81 and 82, the interlayer insulating film 76 is etched in a first step. This etching is temporarily stopped on the etch stop film 74. Thereby, the change in the thickness of the interlayer insulating film 76, the change in the etching, and the like can be absorbed. In a second step, an etch stop film 74 composed of tantalum nitride is etched, and etching is further continued to complete the contact holes 77 to 79, 81 and 82. For example, a reactive ion etching apparatus is used to etch the contact holes.

Next, a plug 85 is formed inside each of the contact holes 77 to 79, 81 and 82, and an adhesive layer (not shown) and a barrier metal layer 84 are interposed therebetween. As the adhesive layer, for example, a titanium (Ti) film or a tantalum (Ta) film is used. As the barrier metal layer 84, for example, a titanium nitride film or a tantalum nitride film is used. These films are formed by, for example, a sputtering method or a CVD method. The plug 85 is composed of tungsten (W). For example, a tungsten film is formed on the interlayer insulating film 76 to fill the contact holes 77 to 79, 81, and 82 with the tungsten film. The tungsten film provided on the interlayer insulating film 76 is then removed. Therefore, a plug 85 composed of the tungsten film is formed in each of the contact holes 77 to 79, 81, and 82. Instead of tungsten, the plug 85 may be composed of, for example, aluminum (Al) or copper (Cu) having a resistance lower than that of tungsten. For example, when copper (Cu) is used as the plug 85, for example, a tantalum film is used as the adhesive layer and a tantalum nitride film is used as the barrier metal layer 84. Next, although not shown in the drawings, a multilayer wiring is formed. If necessary, the number of wiring layers can be increased to two, three, four, and the like.

Next, as shown in a cross-sectional view of the pixel portion of Fig. 39, a waveguide 23 can be formed on the photoelectric conversion portion 21. In addition, in order to focus the incident light to the photoelectric conversion portion 21, a focus lens 25 can be formed. A color filter 27 for spectrally separating light may be formed between the waveguide 23 and the focus lens 25.

In the above method (first example) for manufacturing a solid-state imaging device, the pixel portion 12 is composed of two layers (that is, a first telluride blocking film composed of a film identical to the sidewall film and different from the first The second telluride blocking film of the film composition of the telluride blocking film is covered. Accordingly, the MOS transistor in the pixel portion 12 is not completely covered by a single telluride blocking film. Thus, random noise can be reduced and white point and dark current can be reduced.

In the above manufacturing method, the solid-state imaging device 1 (1B) described with reference to Figs. 3, 4, and 5B is formed. In the manufacturing method, when the isolation region 14 between the transfer gate TRG, the reset transistor RST, the amplification transistor Amp, and the selection transistor SEL in the pixel portion 12 is not formed, the above-described solid-state imaging device is formed 1 (1A). In this case, the floating diffusion portion FD is shared by the source-drain region 34 which is one of the impurity diffusion layers of the reset transistor RST. In the above description of the solid-state imaging device and the method of manufacturing the solid-state imaging device, a single pixel transistor portion (including, for example, a reset transistor, an amplifying transistor, and a first pixel) is formed for the first pixel. Select the structure of the transistor). This embodiment of the present invention is applicable not only to a solid-state imaging device having such a structure of one pixel to one pixel portion but also to a solid-state imaging device having a structure in which two pixels are shared by a single pixel transistor portion. A solid-state imaging device having a structure in which four pixels are shared by a single pixel transistor portion, and a method of manufacturing such solid-state imaging devices.

[Second example of a method of manufacturing a solid-state imaging device]

The main points of the manufacturing method in the case where, for example, one pixel transistor portion shares four pixels will be described below. First, an example of a structure in which one pixel transistor portion shares four pixels will be explained with reference to a plan view of FIG.

As shown in Fig. 40, the photoelectric conversion portions 21 (21A, 21B, 21C, and 21D) of four pixels are arranged in two columns and two rows. At the center of the configuration of the photoelectric conversion portion 21, a floating diffusion portion FD is provided in an active region which is continuous with each of the photoelectric conversion portions 21. Further, transfer gates TRG (TRG-A, TRG-B, TRG-C, and TRG-D) are provided at the boundary between each of the photoelectric conversion portions 21 and the floating diffusion portion FD, and a gate insulating film (not shown) is located between them. The periphery of the photoelectric conversion portion 21 is electrically separated by the isolation region 16 (which is composed of an impurity diffusion layer) except for the region under the transfer gate TRG. . Further, a pixel transistor portion 17 is provided in a region adjacent to the photoelectric conversion portion 21 with an isolation region 14 interposed therebetween. The pixel transistor portion 17 is configured such that, for example, a reset transistor RST, an amplifying transistor Amp, and a select transistor SEL are arranged in series.

A description will be given below of a point in the case where the first example of the above-described method of manufacturing a solid-state imaging device is applied to a method of manufacturing a solid-state imaging device in which a single pixel transistor portion 17 is shared by four pixels. In the case where the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method because the floating diffusion portion FD is formed in the photovoltaic The transfer gate TRG is formed at the center of the configuration of the conversion portion 21 and is formed between each of the photoelectric conversion portions 21 and the floating diffusion portion FD. However, the manufacturing method of the solid-state imaging device operates in the same manner as in the first embodiment, except that the configurations of the photoelectric conversion portion 21, the floating diffusion portion FD, and the transfer gate TRG are different from those in the first example. Accordingly, the method of manufacturing the peripheral circuit portion is the same as the first example. A part of this method will be explained below.

First, a step of forming a side wall will be described with reference to Figs. 41, 42A, 42B, 43C, 43D and the like. Figure 41 is a plan view of a pixel portion, Figure 42A is a cross-sectional view taken along the line XLIIA-XLIIA of Figure 41, Figure 42B is a cross-sectional view taken along line XXLIB-XLIIB of Figure 41, Figure 43C is a A cross-sectional view taken along line XLIIIC-XLIIIC of Fig. 41, and Fig. 43D is a cross-sectional view taken along line XLIIID-XLIIID of Fig. 41. After forming a sidewall film 137 (first vapor blocking film 71), the sidewall film 137 is etched back to each gate electrode 32 and each of the peripheral circuit portions of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21. This is because the photoelectric conversion portion 21 is covered by a resist mask (not shown) so that the etching damage during the formation of the side walls does not enter the photoelectric conversion portion 21. An opening 137H is provided in a region of the upper sidewall film 137 in which the floating diffusion portion FD is formed to expose a region in which the floating diffusion portion FD is formed. A portion of this opening 137H is disposed on the transfer gate TRG.

Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed.

Next, a subsequent step will be explained with reference to FIGS. 44, 45A, 45B, 46C, 46D and the like. Figure 44 is a plan view of a portion of the pixel portion, Figure 45A is a cross-sectional view taken along line XLVA-XLVA of Figure 44, Figure 45B is a cross-sectional view taken along line XLVB-XLVB of Figure 44, Figure 46C is a A cross-sectional view taken along line XLVIC-XLVIC of Fig. 44, and Fig. 46D is a cross-sectional view taken along line XLVID-XLVID of Fig. 44. After forming the source-drain region of the transistor in the pixel portion and the peripheral circuit portion, a deuterated layer is formed on the source-drain region and the like in the peripheral circuit portion. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion, the photoelectric conversion portion 21, and the like. For this purpose, a second telluride blocking film 72 covering the pixel transistor portion 17 is formed prior to the formation of the germanide layer. In this step, the second telluride blocking film 72 is formed to overlap the first vapor blocking film 71 on the isolation region 14. In this step, also on the floating diffusion portion FD, a second vaporization blocking film 72 is formed to overlap the periphery of the opening 137H of the first vaporization blocking film 71. Next, as in the first example, the deuteration step and the subsequent steps of the gate electrode and the source-drain region of the MOS transistor in the peripheral circuit portion.

In the first and second examples of the above manufacturing method, when the side walls 33 and 53 are respectively formed on the sidewalls of the gate electrodes 32 and 52 in the pixel portion 12 and the peripheral circuit portion 13, the sidewalls on the floating diffusion portion FD Film 137 is not covered by a resist mask. In the case where the side walls 33 and 53 are respectively formed on the sidewalls of the gate electrodes 32 and 52 by etching, etching damage may occur in the floating diffusion portion FD.

Considerations regarding etch damage are set forth below. For example, as shown in FIG. 47, when sidewalls (not shown) are formed on the sidewalls of each of the gate electrodes (not shown) by etching, etching damage may occur in the floating diffusion portion FD. If the etching damage occurs in the floating diffusion portion FD, a leak path is generated in the p-n junction included in the floating diffusion portion FD, thereby increasing the number of FD chalk points.

The FD white point will be explained here. The electrons photoelectrically converted into the photoelectric conversion portion are transferred to the floating diffusion portion FD and converted to a voltage. In this case, in the case where there is a leak path in the floating diffusion portion FD, even if photoelectric conversion electrons are not present in the floating diffusion portion FD, the leaked electrons are output and appear as white spots. This is called "FD white point".

Sometimes, an isolating region 16 composed of a p-type diffusion layer is used to separate the photoelectric conversion portions (not shown) from the floating diffusion portion FD. When a p-type diffusion layer is used to separate pixels in this manner, in particular, the number of FD chalk points is significantly increased. For example, one of the possible causes is an impurity out-diffusion effect during heat treatment at 1,000 ° C or higher for activating the source-drain region. For example, impurities dispersed by diffusion outside the heat treatment are adhered between the floating diffusion portion FD and the isolation region 16 composed of a p-type diffusion layer. Thus, a large leak path is formed, which causes a problem of the occurrence of FD white spots. In other words, when a leakage current flows to the floating diffusion portion FD, even in a dark state, it appears as if a signal is present. Thus, a white point is produced. The reason that seems to be the existence of a signal is as follows. If the leakage mentioned above occurs during a period from the state in which one of the floating diffusion portions FD is reset to the detection of the one-to-one signal potential, the voltage fluctuation due to a leakage current is superimposed. At this reset potential.

In the above examples, the structure in which a single pixel transistor portion shares four pixels has been described. Similarly, in the case where one pixel transistor portion shares two pixels or in a case where one pixel transistor portion is formed to correspond to one pixel, etching damage may occur in the floating diffusion portion FD.

3. Third Embodiment [Example of Structure of Solid-State Imaging Device]

Hereinafter, a structure in which etching damage does not occur in the floating diffusion portion FD will be described based on the solid-state imaging device 1 which has been explained with reference to FIGS. 1 and 2 or FIGS. 3 and 4. For example, the first telluride blocking film 71 is formed to cover a portion of the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, and the gate electrode 32 of the reset transistor RST. In this case, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on the gate electrode 32 of the reset transistor RST.

By forming the first vapor blocking film 71 and the second vapor blocking film 72 to have the above structure, when the sidewalls 33 and the sidewalls (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also The first telluride blocking film 71 of a sidewall film is covered. Accordingly, during the formation of the sidewalls, the etching damage does not occur in the floating diffusion portion FD.

[Third Example of Structure of Solid-State Imaging Device]

Next, a third example of a solid-state imaging device having a structure in which one single pixel transistor portion shares four pixels will be described, which is described with reference to FIG. The solid-state imaging device will be explained with reference to FIGS. 48, 49A, 49B, 50C, 50D, and the like. Figure 48 is a plan view of a pixel portion, Figure 49A is a cross-sectional view taken along line XLIXA-XLIXA of Figure 48, Figure 49B is a cross-sectional view taken along line XLIXB-XLIXB of Figure 48, Figure 50C is a A cross-sectional view taken along line LC-LC of Fig. 48, Fig. 50D is a cross-sectional view taken along line LD-LD of Fig. 48.

A first vaporization blocking film 71 is formed to cover the photoelectric conversion portion 21, the transfer gate TRG, and the floating diffusion portion FD. In this case, a second vaporization blocking film 72 is formed to cover an upper surface without forming a second vaporization blocking film 72 overlapping the first vapor blocking film 71, for example, on the isolation region 14. The region of the first telluride blocking film 71.

Accordingly, when the side wall 33 in the pixel transistor portion 17 and the side wall (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vaporization blocking film 71 which is a side wall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving an external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Thus, this structure enables imaging with high image quality.

[Fourth Example of Structure of Solid-State Imaging Device]

Next, a fourth example of a solid-state imaging device having a structure in which one single pixel transistor portion shares four pixels will be described, which is explained with reference to FIG. The solid-state imaging device will be explained with reference to FIGS. 51, 52A, 52B, 53C, 53D, and the like. Figure 51 is a plan view of a pixel portion, Figure 52A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 52B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, Figure 53C is a A cross-sectional view taken along line LIIIC-LIIIC of Fig. 51, and Fig. 53D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51.

A first vaporization blocking film 71 is formed to cover the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor. In this case, a second vaporization blocking film 72 is formed to cover an upper surface without overlapping the first vapor blocking film 72 with the first vapor blocking film 71, for example, in the isolation region 14 and resetting the electricity. The region of the first telluride blocking film 71 is formed in such a manner as to be on the gate electrode 32 of the crystal RST.

Accordingly, the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST connected to the floating diffusion portion FD are also covered by the first vaporization blocking film 71 which is a sidewall film. Therefore, when sidewalls are formed in the pixel transistor portion and the peripheral circuit portion (not shown), etching damage to the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST can be prevented. In addition, this structure prevents the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST from receiving the external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Thus, this structure enables imaging with high image quality.

In each of the third and fourth examples of the solid-state imaging device, the peripheral circuit portion has the same structure as that shown in Fig. 2 or 4.

4. Fourth Embodiment [Third Example of Method of Manufacturing Solid-State Imaging Device]

Next, a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels will be used as an example to explain a manufacturing method for preventing etching damage to a floating diffusion portion FD. (The third example) points.

When the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method, since a floating diffusion portion is formed in the photoelectric conversion portion A transfer gate is formed at a center of a configuration between each of the photoelectric conversion portions and the floating diffusion portion. However, the manufacturing process of the solid-state imaging device operates in the same manner as the first example, except that the arrangement of the photoelectric conversion portion, the floating diffusion portion, and the transfer gates is different from the arrangement in the first example, and a side wall The pattern shape of the film and a second telluride blocking film is different from the pattern shape in the first example. A part of this method will be explained below.

First, a step of forming a side wall will be described with reference to Figs. 54, 55A, 55B, 56C, 56D and the like. Figure 54 is a plan view of a pixel portion, Figure 55A is a cross-sectional view taken along line LVA-LVA of Figure 54, and Figure 55B is a cross-sectional view taken along line LVB-LVB of Figure 54, Figure 56C is a A cross-sectional view taken along line LVIC-LVIC of Fig. 54, and Fig. 56D is a cross-sectional view taken along line LVID-LVID of Fig. 54. After forming a sidewall film 137 (the first vaporization blocking film 71), the sidewall film 137 is etched back to each of the gate electrodes 32 and a peripheral circuit portion of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21 and a floating diffusion portion FD (and the transfer gate TRG). This is because the photoelectric conversion portion 21 and the floating diffusion portion FD are covered by a resist mask (not shown) so that etching damage during formation of the sidewalls does not enter the photoelectric conversion portion 21 and the floating diffusion. Partial FD. In other words, this method is different from the first example of the manufacturing method described above only because the resist mask 138 (see FIG. 25) is formed to extend to the floating diffusion portion FD. The other steps before the formation of the resist mask 138 are the same as those of the first example. It should be noted that the floating diffusion portion FD, the source-drain region 34, and the like have not been formed in this stage. In order to facilitate understanding of the positional relationship, the floating diffusion portion FD and the source-drain region 34 are shown in the drawings.

Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed. In this step, since the floating diffusion portion FD is covered by the sidewall film 137, ion implantation is preferably performed separately from ion implantation for forming the source-drain region of the pixel portion and the transistor in the peripheral circuit portion. In.

Next, a subsequent step will be explained with reference to FIGS. 57, 58A, 58B, 59C, 59D, and the like. 57 is a plan view of a portion of the pixel portion, FIG. 58A is a cross-sectional view taken along line LVIIIA-LVIIIA of FIG. 57, and FIG. 58B is a cross-sectional view taken along line LVIIIB-LVIIIB of FIG. 57, and FIG. 59C is a cross-sectional view. A cross-sectional view taken along line LIXC-LIXC of Fig. 57, and Fig. 59D is a cross-sectional view taken along line LIDD-LIXD of Fig. 57. After forming the source-drain regions of the transistors in the pixel portion 12 and the peripheral circuit portion (not shown), a deuterated layer is formed on the source-drain regions in the peripheral circuit portion and the like. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion 17, the photoelectric conversion portion 21, and the like. For this purpose, a second telluride blocking film 72 covering the pixel transistor portion 17 is formed prior to the formation of the germanide layer. In this step, the second deuterated blocking film 72 is formed to overlap the first telluride blocking film 71. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on an isolation region 14. Next, as in the first example, the deuteration step of the gate electrode and the source-drain region in the peripheral circuit portion and the subsequent steps are performed.

Accordingly, when the sidewall 33 in the pixel transistor portion 17 and the sidewall (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vapor blocking film 71 which is the sidewall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving the external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Therefore, it is possible to manufacture a solid-state imaging device that can realize imaging with high image quality. Further, the pixel transistor portion 17 may be covered by the second vaporization blocking film 72 before the formation of the deuterated layer.

[Fourth Implementation of Method of Manufacturing Solid-State Imaging Device]

Next, a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels will be used as an example to explain a manufacturing method for preventing etching damage to a floating diffusion portion FD. (The fourth example) points.

When the pixel transistor portion is shared by four pixels, the structure of the solid-state imaging device is different from the solid-state imaging device manufactured by the above-described first example of the manufacturing method, since a floating diffusion portion is formed in the photoelectric conversion portion A transfer gate is formed at a center of a configuration between each of the photoelectric conversion portions and the floating diffusion portion. However, the manufacturing process of the solid-state imaging device operates in the same manner as the first example, except that the configurations of the photoelectric conversion portion, the floating diffusion portion, and the transfer gates are different from those in the first example, and a sidewall film And the pattern shape of a second telluride blocking film is different from the pattern shape in the first example. A part of this method will be explained below.

First, a step of forming a side wall will be described with reference to Figs. 60, 61A, 61B, 62C, 62D and the like. Figure 60 is a plan view of a pixel portion, Figure 61A is a cross-sectional view taken along line LXIA-LXIA of Figure 60, Figure 61B is a cross-sectional view taken along line LXIB-LXIB of Figure 60, Figure 62C is a A cross-sectional view taken along line LXIIC-LXIIC of Fig. 60, and Fig. 62D is a cross-sectional view taken along line LXIID-LXIID of Fig. 60. After forming a sidewall film 137 (the first vaporization blocking film 71), the sidewall film 137 is etched back to each of the gate electrodes 32 and a peripheral circuit portion of the pixel transistor portion 17. A sidewall (not shown) is formed on the sidewall of the electrode (not shown). In this case, the sidewall film 137 is left on the photoelectric conversion portion 21, a floating diffusion portion FD (and the transfer gate TRG), and one source-drain region 34 of a reset transistor RST. This is because the photoelectric conversion portion 21, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor RST are covered by a resist mask (not shown) to damage the etching during formation of the sidewalls. The photoelectric conversion portion 21, the floating diffusion portion FD (and the transfer gate TRG), and the source-drain region 34 of the reset transistor RST are not entered. In other words, this method is different from the first example of the manufacturing method described above only because the resist mask 138 (see FIG. 25) is formed to extend to the floating diffusion portion FD, resetting the source of the transistor RST The pole-drain region 34 and a portion of the gate electrode 32 of the reset transistor RST. The other steps before the formation of the resist mask 138 are the same as those of the first example. It should be noted that the floating diffusion portion FD, the source-drain region 34, and the like have not been formed in this stage. In order to facilitate understanding of the positional relationship, the floating diffusion portion FD and the source-drain region 34 are shown in the drawings.

Next, the source-drain regions 34 and 35 of the transistor in the pixel portion and the peripheral circuit portion are formed. In this step, since the floating diffusion portion FD and the source-drain region 34 of the reset transistor RST are covered by the sidewall film 137, it is preferably used for forming the pixel portion and the transistor in the peripheral circuit portion. Ion implantation is performed separately from ion implantation in the source-drain region.

Next, a subsequent step will be explained with reference to FIGS. 63, 64A, 64B, 65C, 65D, and the like. Figure 63 is a plan view of a portion of the pixel portion, Figure 64A is a cross-sectional view taken along line LXIVA-LXIVA of Figure 63, and Figure 64B is a cross-sectional view taken along line LXIVB-LXIVB of Figure 63, Figure 65C is a A cross-sectional view taken along line LXVC-LXVC of Fig. 63, and Fig. 65D is a cross-sectional view taken along line LXVD-LXVD of Fig. 63. After forming the source-drain region of the transistor in the pixel portion and the peripheral circuit portion, a deuterated layer is formed on the source-drain region and the like in the peripheral circuit portion. In this step, it is necessary that the deuterated layer is not formed on the pixel transistor portion 17, the photoelectric conversion portion 21, and the like. For this purpose, a second telluride blocking film 72 covering the pixel transistor portion 17 is formed prior to the formation of the germanide layer. In this step, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71. In this step, since the first telluride blocking film 71 is formed to extend to the portion of the gate electrode 32 of the reset transistor RST, the second telluride blocking film 72 can be formed to be the first deuterated The material blocking film 71 is overlaid on the gate electrode 32 of the reset transistor RST. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on an isolation region 14. Next, as in the first example, the deuteration step and the subsequent steps of the gate electrode and the source-drain region of the MOS transistor in the peripheral circuit portion are carried out.

Accordingly, when the side walls 33 in the pixel portion 17 and the side walls (not shown) in the peripheral circuit portion are formed, the floating diffusion portion FD is also covered by the first vapor blocking film 71 which is the side wall film. This structure prevents etching damage from occurring in the floating diffusion portion FD during the formation of the side walls. In addition, this structure prevents the floating diffusion portion FD from receiving an external diffusion effect. Accordingly, the generation of a leak path can be suppressed, thereby suppressing the generation of the FD white point. Therefore, it is possible to manufacture a solid-state imaging device that can realize imaging with high image quality. Further, the pixel transistor portion 17 may be covered by the second vaporization blocking film 72 before the formation of the deuterated layer.

[Modification of Third and Fourth Examples of Solid-State Imaging Device and Method of Manufacturing Same]

In the structures of the third and fourth examples in which four pixels are shared by a single pixel transistor portion 17, the element isolation around the photoelectric conversion portion 21 is achieved by using an impurity diffusion layer (P ⁺ -type diffusion layer). And the element isolation around the pixel transistor portion 17 is achieved by a shallow trench isolation (STI) structure. Alternatively, for example, as shown in FIG. 66, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion 17 may be composed of an impurity diffusion layer (P ⁺ -type diffusion layer). The isolation region 16 is formed. In this case, the first telluride blocking film 71 can be formed as in the third example, the fourth example, and the like. The second telluride blocking film 72 can also be formed as in the third example, the fourth example, and the like.

[Modification of the first example of the solid-state imaging device and the method of manufacturing the same]

In the structure shown in Fig. 5A, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion are achieved by a shallow trench isolation (STI) structure. Alternatively, for example, as shown in FIGS. 67 to 69B, the element isolation around the photoelectric conversion portion 21 and the element isolation around the pixel transistor portion 17 can be separated by an impurity diffusion layer (P ⁺ type diffusion layer). The composition of the isolation zone 16 is achieved. In this case, the first telluride blocking film 71 is formed in the photoelectric conversion portion 21, the transfer gate TRG, the floating diffusion portion FD, the source-drain region 34 of the reset transistor RST, and the reset transistor RST. One portion of the gate electrode 32. The second telluride blocking film 72 is formed to overlap the first telluride blocking film 71. In this case, since the first telluride blocking film 71 is formed on the portion of the gate electrode 32 of the reset transistor RST, the second telluride blocking film 72 can be formed to be combined with the first germanide The blocking film 71 is overlaid on the gate electrode 32 of the reset transistor RST. Further, in other portions, the second telluride blocking film 72 is formed to overlap the first telluride blocking film 71 on the isolation region 16. Figure 68 is a cross-sectional view taken along line LXVIII-LXVIII of Figure 67, and Figures 69A and 69B are cross-sectional views taken along line LXIX-LXIX of Figure 67.

In each of the third and fourth examples of the method of manufacturing a solid-state imaging device, the peripheral circuit portion has the same structure as the first example of the above manufacturing method.

[Detailed Example of Method of Manufacturing Solid-State Imaging Device]

Next, a detailed example of a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels will be described with reference to cross-sectional views of FIGS. 70A to 93D. This method is a method of fabricating the structure described with reference to the plan layout of one of the pixel portions of FIG. 70A, 72A, 74A, 76A, 78A, 80A, 82A, 84A, 86A, 88A, 90A, and 92A are cross-sectional views taken along line LIIA-LIIA of Fig. 51. 70B, 72B, 74B, 76B, 78B, 80B, 82B, 84B, 86B, 88B, 90B, and 92B are cross-sectional views taken along line LIIB-LIIB of Fig. 51. 71C, 73C, 75C, 77C, 79C, 81C, 83C, 85C, 87C, 89C, 91C, and 93C are cross-sectional views taken along line LIIIC-LIIIC of Fig. 51. 71D, 73D, 75D, 77D, 79D, 81D, 83D, 85D, 87D, 89D, 91D and 93D are cross-sectional views along the line LIIID-LIIID of Fig. 51.

First, the steps shown in Figs. 6 to 12 are carried out. For example, a germanium substrate is used as a semiconductor substrate 11. A first isolation region 14 is formed at a periphery of a pixel transistor portion, and a second isolation region 15 in a peripheral circuit portion 13 is formed. Next, although not shown in FIGS. 6 to 12, a p well and an n well are formed in the semiconductor substrate 11. Further implementation of channel ion implantation. Further, ion implantation for forming a photodiode in the photoelectric conversion portion is performed to form a p-type region. For example, boron (B) ion implantation is performed on the surface of the semiconductor substrate on which the photoelectric conversion portion is formed, and ion implantation is performed in the deep region using arsenic (As) or phosphorus (P) to form a plurality of n-type regions. The n-type regions form a junction with a lower portion of the p-type regions. Therefore, the photoelectric conversion portions including a p-n junction are formed.

Next, description will be made with reference to 70A, 70B, 71C, 71D, and the like. Figure 70A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 70B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 71C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 71D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. A sacrificial oxide layer 151 is formed on the semiconductor substrate 11. Next, a resist mask 152 is formed on the sacrificial oxide layer 151. The resist mask 152 has an opening 153 provided on an isolation region formed around the photoelectric conversion portion 21. Specifically, the resist mask 152 covers the photoelectric conversion portion 21 and a region where the transfer gate, a floating diffusion portion, and the pixel transistor portion are formed. Next, ion implantation is performed in the semiconductor substrate 11 using the resist mask 152 as an ion implantation mask to form the p ⁺ -type isolation region 16. In this ion implantation, for example, boron (B) is used as an ion implantation species, and the dose is set to be in the range of 1 × 10 ¹² to 1 × 10 ¹³ cm - ² . The implant energy is set to be in the range of 10 to 30 keV. The ion implantation can be performed in multiple stages depending on the depth. Thus, the photoelectric conversion portions 21 are separated from each other by the isolation regions 16, and are separated by an isolation region 14 from a pixel crystal portion forming a reset transistor, an amplifying transistor, a selection transistor, and the like. Although not shown in the figures, the peripheral circuit portions are separated by a second isolation region 15, as described above.

Next, the resist mask 152 is removed and the sacrificial oxide layer 151 is further removed. This figure shows a state just before the resist mask 152 is removed.

Next, description will be made with reference to 72A, 72B, 73C, 73D, and the like. Figure 72A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 72B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 73C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 73D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 72A to 73D, a gate insulating film 31 is formed on the semiconductor substrate 11, and a gate electrode forming film 131 is further formed on the gate insulating film 31. In this step, although not shown in the drawings, as shown in Fig. 14, a gate insulating film 51 is also formed on the semiconductor substrate 11 in the peripheral circuit portion 13, and is provided in the gate insulating film 51. A gate electrode formation film 131 is formed thereon. The gate electrode formation film 131 is formed by depositing polysilicon by an LP-CVD method. The deposited film thickness is in the range of 150 to 200 nm in a 90-nm node, but it depends on the technology node. The film thickness tends to decrease for the first node, since a gate aspect ratio is generally not increased from the viewpoint of controllability of the process. As a measure against gate depletion, germanium (SiGe) can be used instead of polysilicon. The gate depletion refers to the following problem: because the thickness of a gate oxide film is reduced, not only one effect of the physical thickness of the gate oxide film but also one of the thicknesses of one of the gate polysilicon layers It cannot be ignored, and therefore does not reduce the effective thickness of one of the gate oxide films, thereby degrading the transistor performance.

Next, description will be made with reference to 74A, 74B, 75C, 75D, and the like. Figure 74A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 74B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 75C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 75D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figures 74A through 75D, a measure against the lack of gates is taken. First, a resist mask 132 (see FIG. 16) is formed on one of the p-MOS transistor formation regions in the peripheral circuit portion 13, and an n-type impurity is doped into the n-MOS transistor formation region. The gate electrode is formed in the film 131. This doping is carried out by ion implantation such as phosphorus (P) or arsenic (As). The amount of implanted ions is in the range of about 1 x 10 ¹⁵ to 1 x 10 ¹⁶ cm ^-2 . The resist mask 132 is then removed. Next, although not shown in the drawings, a resist mask (not shown) is formed on the n-MOS transistor formation region, and a p-type impurity is doped to the p-MOS The gate electrode in the crystal formation region is formed in the film 131. This doping is carried out by ion implantation such as boron (B), boron difluoride (BF ₂ ) or indium (In). The amount of ions implanted is in the range of about 1 x 10 ¹⁵ to 1 x 10 ¹⁶ cm ^-2 . The resist mask is then removed. The former implant or the latter implant may be performed first. In each of the above ion implantations, in order to prevent impurities introduced by the ion implantation from reaching the gate insulating film directly, ion implantation of nitrogen (N ₂ ) may be combined.

Next, description will be made with reference to 76A, 76B, 77C, 77D, and the like. Figure 76A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 76B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 77C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 77D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 76A to 77D, a resist mask (not shown) for forming a gate electrode is formed on the gate electrode forming film 131. The gate electrode forming film 131 is etched by reactive ion etching using the resist mask as an etch mask to form the gate electrode 32, the transfer gate TRG, and the peripheral circuit of the MOS transistor in the pixel portion 12. The gate electrode 52 of the MOS transistor in the portion 13 (see Fig. 18). Next, the surface of the gate electrode 32 and the gate electrode 52 (see FIG. 18) is oxidized to form an oxide film 133. The thickness of the oxide film 133 is, for example, in the range of 1 to 10 nm. The oxide film 133 is formed not only on the sidewalls but also on the top surface of each of the gate electrodes 32 and 52. Further, the edge portions of the rounded gate electrodes 32 and 52 in the above oxidation step have an effect of improving the breakdown voltage of the oxide film. In addition, etching damage can be reduced by performing heat treatment. Further, in the above-described process of the gate electrode, even if the gate insulating film formed on the photoelectric conversion portion 21 is removed, the oxide film 133 is formed on the photoelectric conversion portion 21. Therefore, when a resist film is formed in the next lithography step, the resist film is not formed directly on a ruthenium surface, thereby preventing contamination caused by the resist. Accordingly, for the photoelectric conversion portion 21 in the pixel portion 12, this structure serves as a measure against the chalk point.

Next, description will be made with reference to 78A, 78B, 79C, 79D and the like. Figure 78A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 78B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 79C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 79D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 78A to 79D, the LDD regions 38, 39 and the like of the MOS transistors of the pixel portion 12 and the LDD regions 61, 62, 63, 64 and the like of the MOS transistors of the peripheral circuit portion 13 are formed (see Fig. 20).

First, as for the NMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 65 and 66 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11 (see FIG. 20). . These recessed diffusion layers 65 and 66 are formed by ion implantation using, for example, boron difluoride (BF ₂ ), boron (B) or indium (In) as an ion implantation species, and the dose setting thereof It is, for example, in the range of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ^-2 . Further, LDD regions 61 and 62 are formed at both sides of each of the gate electrodes 52 (52N) in the semiconductor substrate 11. The LDD regions 61 and 62 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 10 ¹³ to 1 × 10 ¹⁵ cm ^- Within the scope of ² .

As for the MOS transistors formed in the pixel portion 12, LDD regions 38 and 39 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11. The LDD regions 38 and 39 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, between 1 × 10 ¹³ and 1 × 10 ¹⁵ Within the range of cm ^-2 . In addition, a plurality of recessed diffusion layers can be formed. As for the MOS transistor formed in the pixel portion 12, the LDD may not be formed from the viewpoint of reducing the number of steps. Alternatively, ion implantation for forming the LDD region of the MOS transistor formed in the pixel portion 12 may function as an LDD ion implantation of the MOS transistor formed in the peripheral circuit portion 13.

As for the PMOS transistors formed in the peripheral circuit portion 13, recessed diffusion layers 67 and 68 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11 (see Fig. 20). These recessed diffusion layers 67 and 68 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹² to 1 ×. Within the range of 10 ¹⁴ cm ^-2 . Further, LDD regions 63 and 64 are formed at both sides of each of the gate electrodes 52 (52P) in the semiconductor substrate 11. The LDD regions 63 and 64 are formed by ion implantation using, for example, boron difluoride (BF ₂ ), boron (B), or indium (In) as an ion implantation species, and the dose thereof is set to, for example, 1 ×. 10 ¹³ to 1 × 10 ¹⁵ cm ^-2 .

Before the ion implantation of the NMOS transistor and the PMOS transistor in the peripheral circuit portion, pre-amorphization can be performed by performing ion implantation of germanium (Ge) as a channel for suppressing implantation. The technology of effects. Furthermore, in order to reduce the number of implant turns that can cause transient enhanced diffusion (TED) or the like, rapid thermal annealing at a temperature ranging from about 800 ° C to 900 ° C can be added after the formation of the LDD regions. (RTA).

Next, description will be made with reference to 80A, 80B, 81C, 81D, and the like. Figure 80A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 80B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 81C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 81D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 80A to 81B, a ruthenium oxide (SiO ₂ ) film 134 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13 (see Fig. 22). The hafnium oxide film 134 is formed by depositing an undoped deuterated glass (NSG) film, a low pressure tetraethyl orthophthalate (LP-TEOS) film, a high temperature oxidation (HTO) film or the like. The hafnium oxide film 134 is formed to have a thickness ranging, for example, from 5 to 20 nm. Next, a tantalum nitride film 135 is formed on the hafnium oxide film 134. The tantalum nitride film 135 is composed of, for example, a tantalum nitride film formed by LPCVD. Its thickness is, for example, in the range of 10 to 100 nm. The tantalum nitride film 135 may be an ALD tantalum nitride film formed by an atomic layer deposition method which can form the film at a low temperature. In the photoelectric conversion portion 21 in the pixel portion 12, since the thickness of the ruthenium oxide film 134 deposited directly under the tantalum nitride film 135 is reduced, light reflection is prevented, and thus the sensitivity of the photoelectric conversion portion 21 becomes high. Next, a third layer of yttrium oxide (SiO ₂ ) film 136 is deposited on the tantalum nitride film 135 as needed. This ruthenium oxide film 136 is formed by depositing an NSG film, an LP-TEOS film, an HTO film or the like. The hafnium oxide film 136 is formed to have a thickness ranging, for example, from 10 to 100 nm.

Accordingly, a sidewall film 137 is formed as a three-layer film having a structure of a hafnium oxide film 136 / a tantalum nitride film 135 / a hafnium oxide film 134. Alternatively, the sidewall film 137 may be a two-layer film having a structure of a tantalum nitride film/yttria film. A case of the side wall film 137 having the three-layer structure will be explained below.

Next, description will be made with reference to 82A, 82B, 83C, 83D, and the like. Figure 82A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 82B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 83C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 83D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in Figs. 82A to 83B, etch back is provided to the ruthenium oxide film 136 provided as the top layer so that the ruthenium oxide film 136 remains only in each of the gate electrodes 32 and 52 (see Fig. 24), the transfer gate On the side of the TRG and the like. This etch back is performed by, for example, reactive ion etching (RIE). In this etch back, a tantalum nitride film 135 is used to stop the etching. Since the etching is stopped by the tantalum nitride film 135 in this manner, the etching damage on the photoelectric conversion portion 21 in the pixel portion 12 can be reduced, and thus the number of chalk dots can be reduced.

Next, description will be made with reference to 84A, 84B, 85C, 85D, and the like. Figure 84A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 84B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 85C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 85D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. As shown in FIGS. 84A to 85B, the entire surface of the photoelectric conversion portion 21 in the pixel portion 12 and the transfer gate TRG, a region in which the floating diffusion portion is formed, the LDD region 38 of the reset transistor, and the weight A resist mask 138 is formed on a portion of the gate electrode 32 of the transistor. Next, the tantalum nitride film 135 and the hafnium oxide film 134 are etched back to form a first sidewall 33 on the sidewall of each of the gate electrodes 32 and a gate electrode 52 (see FIG. 26). The second side wall 53 (see FIG. 26) on the sidewall of each of the first side wall 33 and the second side wall 53 is composed of a hafnium oxide film 134, a tantalum nitride film 135, and a hafnium oxide film 136. In this step, the photoelectric conversion portion 21, the region in which the floating diffusion region is formed, and the tantalum nitride film 135 and the yttrium oxide film 134 on a region in which the source-drain region of the reset transistor is formed are formed. It is not etched because it is covered by the resist mask 138. Accordingly, the etching damage does not occur in the photoelectric conversion portion 21, the region in which the floating diffusion portion is formed, and the region in which the source-drain region of the reset transistor is formed.

Next, description will be made with reference to 86A, 86B, 87C, 87D, and the like. Figure 86A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 86B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 87C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 87D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in Fig. 28, a resist mask (not shown) having an opening which is provided in a region in which an NMOS transistor in the peripheral circuit portion 13 is to be formed is formed. The deep source-drain regions 54 (54N) and 55 (55N) are formed in the region of the NMOS transistor to be formed in the peripheral circuit portion 13 by ion implantation using the resist. Specifically, the source-drain regions 54N and 55N are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 61, 62 and the like interposed therebetween. The source-drain regions 54N and 55N are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 ×. Within the range of 10 ¹⁶ cm ^-2 . The resist mask is then removed.

Next, as shown in Figs. 86A to 87B, a resist mask (not shown) having an opening which is provided in a region in which the NMOS transistor in the pixel portion 12 is to be formed is formed. The deep source-drain regions 34 and 35 and a floating diffusion portion FD are formed in the region of the NMOS transistor to be formed in the pixel portion 12 by ion implantation using the resist mask. Specifically, the source-drain regions 34 and 35 are formed at both sides of each of the gate electrodes 32 in the semiconductor substrate 11, with the LDD regions 38, 39 and the like interposed therebetween. The source-drain regions 34 and 35 are formed by ion implantation using, for example, arsenic (As) or phosphorus (P) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 ×. Within the range of 10 ¹⁶ cm ^-2 . The resist mask is then removed. This ion implantation can also function as an ion implantation for forming the source-drain regions 54N and 55N of the NMOS transistor in the peripheral circuit portion 13. The source-drain region 34 of the reset transistor RST is formed by ion implantation performed through the hafnium oxide film 134 and the tantalum nitride film 135. Therefore, ion implantation of this portion can be performed separately.

Next, as shown in Fig. 28, a resist mask (not shown) having an opening which is provided in a region where the PMOS transistor in the peripheral circuit portion 13 is to be formed is formed. The deep source-drain regions 54 (54P) and 55 (55P) are formed in the region of the PMOS transistor to be formed in the peripheral circuit portion 13 by ion implantation using the resist mask. Specifically, the source-drain regions 54P and 55P are formed at both sides of each of the gate electrodes 52 in the semiconductor substrate 11, with the LDD regions 63, 64 and the like interposed therebetween. The source-drain regions 54P and 55P are formed by ion implantation using, for example, boron (B) or boron difluoride (BF ₂ ) as an ion implantation species, and the dose thereof is set to, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2 . The resist mask is then removed.

Next, activation annealing is performed on the source-drain regions. This activation annealing is carried out at a temperature of, for example, about 800 ° C to 1,100 ° C. For this activation anneal, a rapid thermal annealing (RTA) device, a spiked RTA device, or the like can be used.

The sidewall film 137 covering the photoelectric conversion portion 21 and the sidewall 33 composed of the sidewall film 137 on the gate electrode 32 of the MOS transistor in the pixel portion 12 are divided before the activation annealing of the source-drain regions. Separated. This structure prevents degradation of stress caused by stress memory technology (SMT) as described in the related art. Accordingly, chalk spots, random noise, and the like can be suppressed. Further, the photoelectric conversion portion 21 is covered by the sidewall film 137, and a resist mask used in ion implantation for forming the source-drain regions is formed on the photoelectric conversion portion 21, and the sidewall film 137 is formed. Located between them. In other words, the resist mask is not directly formed on the surface of the photoelectric conversion portion 21. Therefore, the photoelectric conversion portion 21 is not contaminated by the contaminants in the resist, thereby suppressing the number of chalk points, dark current, and the like. In addition, the ion implantation for forming the source-drain regions is not ion implantation through a film, and thus the depth of the source-drain regions can be set while ensuring that one of the surfaces is high. concentration. Therefore, an increase in the series resistance of the source-drain regions can be suppressed. In addition, the sidewall film 137 covering the photoelectric conversion portion 21, the floating diffusion portion FD, and the source-drain region 34 of the reset transistor is used as a first germanide blocking film 71, source-drain in the subsequent step. The region 34 is connected to the floating diffusion portion FD via wiring (not shown) or the like.

Next, description will be made with reference to 88A, 88B, 89C, 89D, and the like. Figure 88A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 88B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 89C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 89D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in Figs. 88A to 89D, a second vaporization blocking film 72 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13 (see Fig. 30). The second telluride blocking film 72 is composed of a stacked film including a tantalum oxide (SiO ₂ ) film 140 and a tantalum nitride film 139. For example, the hafnium oxide film 140 is formed to have a thickness ranging from, for example, 5 to 40 nm, and the tantalum nitride film 139 is formed to have a thickness ranging, for example, from 5 to 60 nm. The ruthenium oxide film 140 is composed of an NSG film, an LP-TEOS film, an HTO film or the like. The tantalum nitride film 139 is composed of an ALD-SiN film, a nitride film, an LP-SiN film or the like. If the deposition temperature of the two films is high, deactivation of boron occurs in the gate electrode of the PMOSFET. Thus, one of the PMOSFETs has a current drive capability that is reduced due to gate depletion. Accordingly, the deposition temperature of the yttrium oxide film 140 and the tantalum nitride film 139 is preferably lower than the deposition temperature of the sidewall film 137. The deposition temperature is preferably, for example, at 700 ° C or lower.

Next, description will be made with reference to 90A, 90B, 91C, 91D, and the like. Figure 90A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 90B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 91C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 91D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in FIGS. 90A to 91D, a resist mask 141 is formed to substantially cover a region in which the MOS transistors in the pixel portion 12 are formed. The resist mask 141 is used as an etch mask to remove the photoelectric conversion portion 21, the floating diffusion portion FD, (and the transfer gate TRG) located in the pixel portion 12 and the peripheral circuit portion 13 by etching, and reset The source-drain region 34 of the transistor and the second germanide blocking film 72 on a portion of the gate electrode 32 of the reset transistor (see FIG. 32). Accordingly, the second vaporization blocking film 72 is formed to overlap the first vapor blocking film 71 on the gate electrode 32 of the reset transistor and the rear side of the isolation region 14 shown in FIG. 91D. Thereby, from the top layer, the tantalum nitride film 135 and the tantalum oxide 134 are located on the photoelectric conversion portion 21 in this order, and thus spectral chopping can be prevented. On the contrary, if the above etching is not performed, the tantalum nitride film 139, the hafnium oxide film 140, the tantalum nitride film 135, and the hafnium oxide film 134 are located on the photoelectric conversion portion 21 in this order from the top layer. In this case, the incident light is subjected to multiple reflections, thereby degrading the spectral chopping characteristics. Due to the degradation of these chopping characteristics, the wafer-wafer spectral variation increases. In order to solve this problem, in this embodiment, the second vaporization blocking film 72 on the photoelectric conversion portion 21 is intentionally removed.

Next, description will be made with reference to 92A, 92B, 93C, 93D, and the like. Figure 92A is a cross-sectional view taken along line LIIA-LIIA of Figure 51, Figure 92B is a cross-sectional view taken along line LIIB-LIIB of Figure 51, and Figure 93C is a cross-sectional view taken along line LIIIC-LIIIC of Figure 51. And Fig. 93D is a cross-sectional view taken along line LIIID-LIIID of Fig. 51. First, as shown in FIG. 34, the deuterated layers 56, 57, and 58 are formed on the source-drain regions 54 and 55 and the gate electrode 52 of each of the MOS transistors 50 in the peripheral circuit portion 13, respectively. . The deuterated layers 56, 57, and 58 are composed of cobalt silicide (CoSi ₂ ), nickel telluride (NiSi), titanium telluride (TiSi ₂ ), platinum telluride (PtSi), tungsten germanium (WSi ₂ ), or the like. An example of the formation of deuterated nickel will be described as an example of the formation of deuterated layers 56, 57 and 58. First, a nickel (Ni) film is formed on the entire surface. This nickel film is formed using a sputtering apparatus or the like to have a thickness of, for example, 10 nm. Next, an annealing treatment is performed at a temperature ranging from about 300 ° C to 400 ° C to react the nickel film with the ruthenium as the underlying layer, thereby forming a nickel-deposited layer. The unreacted nickel is then removed by wet etching. By this wet etching, the deuterated layers 56, 57, and 58 are formed only on the surface of the tantalum or polysilicon in an automatic alignment manner without being formed on the insulating films. Next, an annealing treatment is again performed at a temperature ranging from about 500 ° C to 600 ° C to stabilize the nickel telluride layer. In the above-described deuteration step, as shown in FIGS. 92A to 93D, since the pixel portion 12 is covered by the first vapor blocking film 71 and the second vapor blocking film 72, the germanide is not formed on the pixel portion 12. . This structure serves to prevent an increase in the number of white spots and dark current caused by the diffusion of the metal constituting the telluride on the photoelectric conversion portion 21. Accordingly, unless the surface of the source-drain regions 34 and 35 of the MOS transistor in the pixel portion 12 has a high impurity concentration, the contact resistance is remarkably increased. This embodiment is advantageous because the increase in contact resistance can be relatively suppressed because the surface of the source-drain regions 34 and 35 can have a high impurity concentration.

Next, as in the description with reference to Figs. 35 and 36, an etch stop film 74 is formed on the entire surface of the pixel portion 12 and the peripheral circuit portion 13. The etch stop film 74 is composed of, for example, a tantalum nitride film. This tantalum nitride film has an effect of minimizing overetching during etching for forming contact holes. Further, the tantalum nitride film has an effect of suppressing an increase in junction leakage due to etching damage.

Next, as in the description with reference to Figs. 37 and 38, an interlayer insulating film 76 is formed on the etching stopper film 74. The interlayer insulating film 76 is composed of, for example, a hafnium oxide film and has a thickness of, for example, in the range of 100 to 1,000 nm. Next, the surface of the interlayer insulating film 76 is planarized. This planarization is performed by, for example, chemical mechanical polishing (CMP). Next, a resist mask (not shown) for forming a contact hole is formed. Next, the contact holes 77, 78, and 79 are formed by, for example, etching the interlayer insulating film 76 in the pixel portion 12, the etching stopper film 74, and the second vaporization blocking film 72. Similarly, contact holes 81 and 82 are formed in the peripheral circuit portion 13. In the pixel portion 12, as an example, the contact holes 77, 78, and 79 which respectively reach the transfer gate TRG, the gate electrode 32 of the reset transistor RST, and the gate electrode 32 of the amplifying transistor Amp are shown in FIG. In the peripheral circuit portion 13, as an implementation, the source-drain region 55 of a N-channel (Nch) low breakdown voltage transistor and the source-drain of a P-channel (Pch) low breakdown voltage transistor are respectively reached. Contact holes 81 and 82 of the region 55 are shown in FIG. However, contact holes reaching the gate electrode and the source-drain region of the other transistors are also formed at the same time, but they are not shown in the drawings.

Next, a plug 85 is formed inside each of the contact holes 77 to 79, 81 and 82, and an adhesive layer (not shown) and a barrier metal layer 84 are interposed therebetween. As the adhesive layer, for example, a titanium (Ti) film or a tantalum (Ta) film is used. As the barrier metal layer 84, for example, a titanium nitride film or a tantalum nitride film is used. The plug post 85 may be composed of, for example, tungsten (W), aluminum (Al), or copper (Cu). For example, when copper (Cu) is used as the plug 85, for example, a tantalum film is used as the adhesive layer and a tantalum nitride film is used as the barrier metal layer 84. Next, although not shown in the drawings, a multilayer wiring is formed. If necessary, the number of wiring layers can be reduced to two, three, four, and the like.

Next, as shown in a cross-sectional view of the pixel portion of Fig. 39, a waveguide 23 can be formed on the photoelectric conversion portion 21. In addition, in order to focus the incident light to the photoelectric conversion portion 21, a focus lens 25 can be formed. A color filter 27 for spectrally separating light may be formed between the waveguide 23 and the focus lens 25.

In the above method (fourth example) of manufacturing a solid-state imaging device, when the sidewall 33 in the pixel transistor portion 17 and the sidewall 53 in the peripheral circuit portion are formed, the floating diffusion portion FD is also formed by the sidewall film 137 (first The telluride blocking film 71) is covered. Accordingly, etching damage during formation of the sidewalls does not occur in the floating diffusion portion FD. Further, the external diffusion effect on the floating diffusion portion FD can be prevented. Thus, generation of a leak path between the isolation region 16 and the floating diffusion portion FD can be suppressed, thereby suppressing the generation of the FD chalk point. Accordingly, a solid-state imaging device that can realize imaging with high image quality can be manufactured. In addition, the pixel portion 12 is composed of two layers (that is, a first telluride blocking film 71 composed of a film identical to the sidewall film 137 and a second germanium composed of a film different from the first telluride blocking film 71). The barrier film 72) is covered. Accordingly, the MOS transistor in the pixel portion 12 is not completely covered by a single telluride blocking film. Thus, random noise can be reduced and white point and dark current can be reduced.

In the description of the above embodiment, a p-well is formed in an n-type substrate, and the photodiode of the photoelectric conversion portion 21 includes a P ⁺ layer and an N ⁺ layer from the top layer. Alternatively, an n-well can be formed in a p-type substrate, and the photodiode of the photoelectric conversion portion 21 can include one of the N ⁺ layer and a P ⁺ layer from the top layer.

The reset transistor RST, the amplifying transistor Amp, and the selection transistor SEL in the pixel transistor portion 17 of the solid-state imaging device will now be explained.

In the reset transistor RST, a drain electrode (source-drain region 35) is connected to a reset line (not shown), and a source electrode (source-drain region 34) is connected to the floating diffusion portion. FD. Before the signal charge is transferred from the photoelectric conversion portion 21 to the floating diffusion portion FD, a reset pulse is supplied to a gate electrode, and thereby, the reset transistor RST resets the potential of the floating diffusion portion FD to a reset voltage.

In the amplifying transistor Amp, a gate electrode 32 is connected to the floating diffusion portion FD, and a drain electrode (source-drain region 34) is connected to a pixel power supply Vdd. The amplified transistor Amp outputs a potential of the floating diffusion portion FD obtained after resetting the reset transistor RST as a reset level, and further outputs a signal obtained after the signal charges are transferred by a transfer transistor TRG. The potential of the floating diffusion portion FD is used as a signal level.

In the selection transistor SEL, for example, a drain electrode (source-drain region 34) is connected to one source electrode (source-drain region 35) of the amplifying transistor Amp, and a source electrode (source) The pole-drain region 35) is connected to an output signal line (not shown). When a selection pulse is supplied to a gate electrode 32, the selection transistor SEL is turned to an on state and a signal output from the amplifying transistor Amp is output to an output signal line (not shown) while a pixel is in a selected state. under. The select transistor SEL can be configured to be coupled between the pixel power supply Vdd and the drain electrode of the amplifying transistor Amp.

5. Fifth embodiment [Example of Structure of Imaging Device]

Next, an image forming apparatus according to an embodiment of the present invention will be explained with reference to a block diagram of FIG. The image forming apparatus includes a solid-state imaging device according to an embodiment of the present invention.

As shown in Fig. 94, an image forming apparatus 200 includes an image forming unit 201 provided with a solid-state imaging device (not shown). An imaging optical system 202 for forming an image is provided at one of the light focusing sides of the imaging unit 201. A signal processing unit 203 (which includes a driving circuit for driving the imaging unit 201, a signal processing circuit for processing signals photoelectrically converted to an image in the solid-state imaging device, and the like) is connected to the imaging unit 201. The image signal processed by signal processing unit 203 can be stored by an image storage unit (not shown). In the image forming apparatus 200, the solid-state imaging device 1 described in any of the above embodiments can be used as the solid-state imaging device.

Since the image forming apparatus 200 according to an embodiment of the present invention includes the solid-state imaging device 1 according to an embodiment of the present invention, the sensitivity of the photoelectric conversion portion of each pixel is satisfactorily ensured as described above. Accordingly, the image forming apparatus 200 according to an embodiment of the present invention is advantageous in that pixel characteristics such as, for example, reduction of chalk points and dark current can be improved.

The structure of the image forming apparatus 200 according to an embodiment of the present invention is not limited to the structure described above. The imaging device 200 according to an embodiment of the present invention can be applied to any imaging device including a solid-state imaging device. The imaging device 200 can be fabricated in the form of a single wafer or in the form of a module having an imaging unit in which an imaging unit and a signal processing unit or an optical system are integrally packaged. A solid-state imaging device according to an embodiment of the present invention can also be applied to such an imaging device. In this case, a high image quality can be achieved in the image forming apparatus. As used herein, the term "imaging device" refers to, for example, a camera or a portable device having an imaging function component. The term "imaging" refers not only to normal imaging by means of a camera but also to fingerprint detection in a broad sense.

The present application contains the subject matter related to the subject matter disclosed in the following patent application: Japanese Priority Patent Application No. JP 2008-199518 filed on Jan. 1, 2008 in the Japan Patent Office; August 1, 2008 Japanese Priority Patent Application No. JP-A-2008-199519, filed on Jan. 20, 2009, the entire contents of This is incorporated herein.

Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made in the scope of the accompanying claims and the scope of the equivalents.

1. . . Solid-state imaging device

1A. . . Solid-state imaging device

1B. . . Solid-state imaging device

11. . . Semiconductor substrate

12. . . Pixel portion

13. . . Peripheral circuit

14. . . First isolation zone

15. . . Second isolation zone

16. . . quarantine area

17. . . Pixel transistor part

twenty one. . . Photoelectric conversion section

21A. . . Photoelectric conversion section

21B. . . Photoelectric conversion section

21C. . . Photoelectric conversion section

21D. . . Photoelectric conversion section

twenty three. . . waveguide

25. . . Focusing lens

27. . . Color filter

31. . . Gate insulating film

32. . . Gate electrode

33. . . First side wall

34. . . Source-bungee area

35. . . Source-bungee area

38. . . LDD area

39. . . LDD area

50. . . MOS transistor

51H. . . Gate insulating film

51L. . . Gate insulating film

51. . . Gate insulating film

52. . . Gate electrode

52P. . . Gate electrode

52N. . . Gate electrode

53. . . Second side wall

54. . . Source-bungee area

54N. . . Source-bungee area

54P. . . Source-bungee area

55. . . Source-bungee area

55N. . . Source-bungee area

55P. . . Source-bungee area

56. . . Telluride layer

57. . . Telluride layer

58. . . Telluride layer

61. . . LDD area

62. . . LDD area

63. . . LDD area

64. . . LDD area

71. . . First telluride blocking membrane

72. . . Second telluride blocking membrane

74. . . Etched stop film

76. . . Interlayer insulation

77. . . Contact hole

78. . . Contact hole

79. . . Contact hole

81. . . Contact hole

82. . . Contact hole

84. . . Barrier metal layer

85. . . Stud

111. . . Mat oxide film

112. . . Tantalum nitride film

113. . . Peripheral circuit

114. . . First component isolation trench

115. . . Second component isolation trench

121. . . p well

123. . . n well

131. . . Gate electrode forming film

132. . . Resist mask

133. . . Oxide film

134. . . Cerium oxide film

135. . . Tantalum nitride film

136. . . Cerium oxide film

137. . . Sidewall membrane

137H. . . Opening

138. . . Resist mask

139. . . Tantalum nitride film

140. . . Cerium oxide film

141. . . Resist mask

151. . . Sacrificial oxide layer

152. . . Resist mask

153. . . Opening

200. . . Imaging device

201. . . Imaging unit

202. . . Imaging optical system

203. . . Signal processing unit

Amp. . . Amplifying the transistor

FD. . . Floating diffusion

N. . . aisle

N ⁺ . . . Floor

P. . . aisle

P ⁺ . . . Floor

RST. . . Reset transistor

SEL. . . Select transistor

TRG. . . Transfer gate

1 is a schematic structural cross-sectional view showing a first example of a structure of a solid-state imaging device according to an embodiment of the present invention;

Figure 2 is a schematic structural cross-sectional view showing a first example of the structure of a solid-state imaging device according to an embodiment of the present invention;

Figure 3 is a schematic structural cross-sectional view showing a second example of the structure of a solid-state imaging device according to an embodiment of the present invention;

Figure 4 is a schematic structural cross-sectional view showing a second example of the structure of a solid-state imaging device according to an embodiment of the present invention;

Figure 5A is a plan view showing a first example of a solid-state imaging device according to an embodiment of the present invention;

Figure 5B is a plan view showing a second example of a solid-state imaging device according to an embodiment of the present invention;

Figure 6 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 7 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 8 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 9 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 10 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 11 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 12 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 13 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 14 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 15 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 16 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 17 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 18 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 19 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 20 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 21 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 22 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 23 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 24 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 25 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 26 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 27 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 28 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 29 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 30 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 31 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 32 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 33 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 34 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 35 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 36 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 37 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 38 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 39 is a cross-sectional view showing a first example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 40 is a plan view showing an example of a structure in which one pixel transistor portion shares four pixels;

Figure 41 is a plan view showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

42A and 42B are partial cross-sectional views showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

43C and 43D are partial cross-sectional views showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 44 is a plan view showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

45A and 45B are partial cross-sectional views showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

46C and 46D are partial cross-sectional views showing a second example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 47 is a schematic structural cross-sectional view illustrating an etching damage effect;

Figure 48 is a plan view showing a third example of a solid-state imaging device according to an embodiment of the present invention;

49A and 49B are partial cross-sectional views showing a third example of a solid-state imaging device according to an embodiment of the present invention;

50C and 50D are partial cross-sectional views showing a third example of a solid-state imaging device according to an embodiment of the present invention;

Figure 51 is a plan view showing a fourth example of a solid-state imaging device according to an embodiment of the present invention;

52A and 52B are partial cross-sectional views showing a fourth example of a solid-state imaging device according to an embodiment of the present invention;

53C and 53D are partial cross-sectional views showing a fourth example of a solid-state imaging device according to an embodiment of the present invention;

Figure 54 is a plan view showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention,

55A and 55B are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

56C and 56D are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 57 is a plan view showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

58A and 58B are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

59C and 59D are partial cross-sectional views showing a third example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 60 is a plan view showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

61A and 61B are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

62C and 62D are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 63 is a plan view showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

64A and 64B are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

65C and 65D are partial cross-sectional views showing a fourth example of a method of manufacturing a solid-state imaging device according to an embodiment of the present invention;

Figure 66 is a plan view showing a modification of a pair of the solid-state imaging device and the third and fourth examples thereof;

Figure 67 is a plan view showing a modification of a first example of the solid-state imaging device and the method of manufacturing the same;

Figure 68 is a partial cross-sectional view showing a modification of the first example of the solid-state imaging device and the method of manufacturing the same;

69A and 69B are partial cross-sectional views showing modifications of the first example of the solid-state imaging device and the method of manufacturing the same;

70A and 70B are cross-sectional views showing a detailed example of a method of manufacturing a solid-state imaging device having a structure in which a single pixel transistor portion shares four pixels (four-pixel sharing structure);

71C and 71D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

72A and 72B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

73C and 73D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

74A and 74B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

75C and 75D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

76A and 76B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

77C and 77D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

78A and 78B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

79C and 79D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 80A and 80B are cross-sectional views showing the manufacture of a solid-state imaging device having the four-pixel sharing structure. This detailed example of the method; FIGS. 81C and 81D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 82A and 82B are cross-sectional views showing the manufacture of a four-pixel sharing This detailed example of the method of the solid-state imaging device of the structure; FIGS. 83C and 83D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 84A and 84B are cross-sectional views showing the manufacture A detailed example of a method of a solid-state imaging device having the four-pixel sharing structure; FIGS. 85C and 85D are cross-sectional views showing the detailed example of a method of fabricating a solid-state imaging device having the four-pixel sharing structure; FIGS. 86A and 86B A cross-sectional view showing the detail of a method of fabricating a solid-state imaging device having the four-pixel sharing structure 87C and 87D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; and FIGS. 88A and 88B are cross-sectional views showing the manufacture of a solid-state imaging having the four-pixel sharing structure. This detailed example of the method of the apparatus; FIGS. 89C and 89D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure; FIGS. 90A and 90B are cross-sectional views showing that the manufacturing one has the four This detailed example of the method of the solid-state imaging device of the pixel sharing structure; FIGS. 91C and 91D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

92A and 92B are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

93C and 93D are cross-sectional views showing the detailed example of a method of manufacturing a solid-state imaging device having the four-pixel sharing structure;

Figure 94 is a block diagram showing an image forming apparatus according to an embodiment of the present invention;

95 is a layout diagram of one of CMOS sensors in the related art; and

Fig. 96 is an equivalent circuit diagram of one of the planar arrangements of the CMOS sensor in the related art.

1. . . Solid-state imaging device

1A. . . Solid-state imaging device

11. . . Semiconductor substrate

12. . . Pixel portion

14. . . First isolation zone

twenty one. . . Photoelectric conversion section

32. . . Gate electrode

33. . . First side wall

34. . . Source-bungee area

35. . . Source-bungee area

71. . . First telluride blocking membrane

72. . . Second telluride blocking membrane

FD. . . Floating diffusion

TRG. . . Transfer gate

RST. . . Reset transistor

Amp. . . Amplifying the transistor

SEL. . . Select transistor

Claims (13)

A solid-state imaging device comprising: a semiconductor substrate comprising a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal; and a peripheral circuit portion disposed at a periphery of the pixel portion a first sidewall, which is composed of a sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the pixel portion; a second sidewall which is composed of a film identical to the sidewall film and is disposed On each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion; a first vaporization blocking film composed of a film identical to the sidewall film and disposed in the pixel portion And a portion of the MOS transistor; and a second vapor blocking film disposed on the MOS transistors in the pixel portion to partially overlap the one of the first vapor blocking film, wherein The MOS transistors in the pixel portion are covered by the first vapor blocking film and the second germanide blocking film. The solid-state imaging device of claim 1, wherein the semiconductor substrate further comprises a floating diffusion portion adjacent to one of the photoelectric conversion portions, and the floating diffusion portion is covered by the first vaporization blocking film. The solid-state imaging device of claim 1, wherein the semiconductor substrate further comprises a floating diffusion portion adjacent to one of the photoelectric conversion portions, wherein one of the MOS transistors in the pixel portion is a reset transistor, and the floating The diffusion portion and one of the reset transistors to which the floating diffusion portion is connected are covered by the first vapor blocking film. The solid-state imaging device of claim 1, wherein a portion of the first vapor blocking film overlapping the second vapor blocking film is disposed in the pixel portion. The solid-state imaging device of claim 1, further comprising: a first isolation region in the pixel portion of the semiconductor substrate; and a second isolation region in the peripheral circuit portion of the semiconductor substrate, wherein Each of the first isolation region and the second isolation region has a shallow trench isolation (STI) structure, the first isolation region is shallower than the second isolation region, and the first isolation region is One of the protrusions of the semiconductor substrate has a height that is the same as a height of one of the portions of the second isolation region that protrudes from the semiconductor substrate. The solid-state imaging device of claim 1, wherein the first vapor blocking film has a stacked structure including a tantalum oxide film and a tantalum nitride film, and the second germanide blocking film has a tantalum oxide film and nitrided One of the stacking structures of the diaphragm. A method of manufacturing a solid-state imaging device, comprising: forming a pixel portion having a photoelectric conversion portion configured to photoelectrically convert incident light to obtain an electrical signal on a semiconductor substrate; and forming a pixel portion formed on the pixel portion a peripheral film portion at the periphery forming a sidewall film covering the pixel portion and the peripheral circuit portion; forming a first layer of the sidewall film on each sidewall of the gate electrode of the MOS transistor in the pixel portion a sidewall, a second sidewall formed by the sidewall film on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion, and a photoelectric conversion portion in the pixel portion and the MOS transistor a portion of the sidewall film constitutes a first vapor blocking film; and a second vapor blocking film is formed on the MOS transistors in the pixel portion to form a first germanide blocking film A portion overlaps, wherein the MOS transistors in the pixel portion are covered by the first vapor blocking film and the second germanide blocking film. A method of manufacturing a solid-state imaging device according to claim 7, wherein the first vapor blocking film covers a floating diffusion portion adjacent to the photoelectric conversion portion. A method of manufacturing a solid-state imaging device according to claim 8, wherein the first vapor blocking film covers the floating diffusion portion provided adjacent to the photoelectric conversion portion, and the MOS transistors are blocked by the first germanium film The portion covered by the broken film is an impurity diffusion layer which is one of the reset transistors. A method of manufacturing a solid-state imaging device according to claim 8, wherein the portion of the first vapor blocking film overlapping the second vapor blocking film is formed in the pixel portion. The method of manufacturing a solid-state imaging device according to claim 7, further comprising the steps of: forming a first isolation region in the pixel portion of the semiconductor substrate and one of the peripheral circuit portions of the semiconductor substrate a second isolation region, wherein each of the first isolation region and the second isolation region has an STI structure, the first isolation region is shallower than the second isolation region, and the first isolation region is from the semiconductor One of the portions of the substrate protrusion is at the same height as one of the portions of the second isolation region that protrude from the semiconductor substrate. A method of manufacturing a solid-state imaging device according to claim 7, wherein the first vapor blocking film is formed to have a stacked structure including a tantalum oxide film and a tantalum nitride film, and the second germanide blocking film is subjected to It is formed to have a stacked structure including a tantalum oxide film and a tantalum nitride film. An imaging device comprising: a light focusing optical unit configured to focus incident light; an imaging unit comprising one configured to receive light focused in the light focusing optical unit and to photoelectrically convert the light a solid-state imaging device; and a signal processing unit configured to process an electrical signal output from the solid-state imaging device due to photoelectric conversion, wherein the solid-state imaging device includes a semiconductor substrate including a device configured to emit light Converting the incident light to obtain a pixel portion of the photoelectric conversion portion of an electrical signal and a peripheral circuit portion disposed at a periphery of the pixel portion, a first sidewall, which is composed of a sidewall film and is disposed in the pixel portion a second sidewall on each side wall of the gate electrode of the transistor, which is composed of a film identical to the film of the sidewall film and disposed on each sidewall of the gate electrode of the MOS transistor in the peripheral circuit portion, a first telluride blocking film composed of a film identical to the film of the sidewall film and disposed in the pixel portion and a portion of the MOS transistors And a second telluride blocking film disposed on the MOS transistors of the pixel portion to partially overlap one of the first germanide blocking films, wherein the MOS transistors in the pixel portion are The first telluride blocking film and the second telluride blocking film are covered.