TWI580252B - Line and block integrated transform method and computer-readable storage medium thereof - Google Patents

Description

Line and block integration conversion method and computer readable storage medium

The present invention relates to an image processing method, and more particularly to an integrated conversion method for rows and blocks to improve memory usage.

The rapid development of digital imaging applications, including small-scale publishing, multimedia, video conferencing, and high definition television (HDTV), has increased the need for efficient and standardized image compression techniques. Without image compression, the bandwidth used for image transmission may be unsupported by many applications. The image compression method converts the image from the 2D pixel array into a sequence of bits and transmits it through the transmission line. Each pixel represents the intensity of the image at a particular location. During the transmission of an image in a digital circuit, the pixels are generally transmitted in order from left to right and from top to bottom. When compressing a digital image, it is usually necessary to arrange the pixels in blocks. For example, JPEG is divided into 8×8 squares, and H.264 is divided into 16×16 squares. Therefore, it is necessary to use a line and a block conversion. If implemented with a digital circuit, larger memory is required to buffer the stored data.

In the prior art, digital circuits are used to implement the conversion from row to block. The common method is to use ping-pong. Assuming that the block is 16x16, the image width is W, the height is H, and each pixel is represented by 1 byte, the memory storage space required for the conversion process is 32×W. The memory of the prior art is divided into upper and lower parts, and each part can store 16 lines of pixels. First line 1~16 The primes are written to the upper half of the memory in the order of input, and then the pixels of lines 17 to 32 are written to the lower half of the memory, and the upper half of the memory is read in the order of the blocks. The data is the same as reading and writing. When the lower half of the memory is read, the data of the upper part of the memory will be read, and then the data of the 33th to 48th lines will be written to the upper part of the memory. Read the data in the lower part of the memory, and the subsequent data is repeated in this way. Therefore, the ping-pong method is used to perform row and block conversion. Although the implementation is simple, the memory utilization is not high.

An embodiment of the present invention provides an integrated conversion method for an image line and a block. The method for integrating a line and a block includes the following steps: dividing the image into M horizontal blocks and N vertical blocks; Addressing the addresses of the plurality of first pixel units of the first horizontal block of the plurality of horizontal blocks into the memory according to the order of the accumulated addresses of the memory; from the predetermined distance of each interval pixel in the memory Cyclicly reading the addresses of the plurality of first pixel units, wherein the predetermined distance of the pixels is the width of the image; and the positions of the plurality of X-1 pixel units are obtained through the double loop algorithm to sequentially read Taking the addresses of the plurality of X-1 pixel units of the X-1 horizontal block; and reading the positions of the plurality of X-1 pixel units of the memory cyclically by a predetermined distance per interval pixel At the time of address, the addresses of the plurality of Xth pixel units of the Xth horizontal block in the plurality of horizontal blocks are cyclically written to the memory by a predetermined distance per interval. The partitioning of the plurality of waterblocks and the plurality of vertical blocks forms an M×N matrix, wherein each element in the matrix is a B×B matrix, and the first pixel unit and the Xth pixel units include B Pixels, where B, M, and N are positive integers and N is the width of the image divided by B.

Another embodiment of the present invention provides a computer readable storage medium for storing a computer program. The computer program includes a plurality of code codes for loading into an electronic device and causing the electronic device to execute a line and area for an image. The integrated conversion method of the block, the integrated conversion method of the row and the block includes the following steps: dividing the image into M waters a flat block and N vertical blocks; sequentially injecting addresses of the plurality of first pixel units of the first horizontal block of the plurality of horizontal blocks into the memory according to the order of the accumulated addresses of the memory And cyclically reading addresses of the plurality of first pixel units from a predetermined distance of each of the pixels in the memory, wherein the predetermined distance of the pixels is the width of the image; and the plurality of frames are obtained by the double loop algorithm The position of the X-1 pixel unit sequentially reads the addresses of the plurality of X-1 pixel units of the X-1 horizontal block; and cyclically reads the memory when the interval is a predetermined distance per pixel When the addresses of the plurality of X-1 pixel units are located, the addresses of the plurality of Xth pixel units of the Xth horizontal block in the plurality of horizontal blocks are cyclically written by a predetermined distance per interval pixel Into the memory. The plurality of horizontal blocks and the plurality of vertical blocks form an M×N matrix, each matrix has a size of B×B, and the first pixel unit and the Xth pixel units include B pixels, wherein B, M and N are positive integers and N is the width of the image divided by B.

In summary, the method for converting the line and the block proposed by the embodiment of the present invention and the computer readable storage medium, the first pixel unit and the X pixel unit of the image are written into the memory by line conversion. And reading the first pixel unit and the X pixel unit stored in the memory by using a block conversion method, thereby increasing the usage rate of the memory, that is, compared to the ping-pong method of the prior art. The disclosure can save about half of the storage space of the memory, thereby achieving the effect of greatly reducing the implementation cost of the digital circuit.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

100‧‧‧ images

EVM‧‧‧ memory

H‧‧‧ Height

HB_0~HB_M-1‧‧‧ horizontal block

L1~LB‧‧‧

Pu1, pu2, puX‧‧‧ pixel unit

S310, S320, S330, S340, S350‧‧‧ steps

S402, S404, S406, S408, S410, S412, S414, S416, S418, S420, S422, S424, S426‧‧ steps

VB_0~VB_N-1‧‧‧ vertical block

W‧‧‧Width

FIG. 1 is a schematic diagram of a method for integrating rows and blocks according to an exemplary embodiment of the present invention.

2A and 2B are schematic diagrams of writing image line conversion to a memory according to an exemplary embodiment of the invention.

FIG. 3 is a flow chart of a method for integrating rows and blocks according to an exemplary embodiment of the present invention.

4 is a flow chart of a method for integrating rows and blocks according to an exemplary embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein.

During the transmission of an image in a digital circuit, the pixels are generally transmitted in order from left to right and from top to bottom. When compressing a digital image, it is usually necessary to arrange the pixels in blocks. For example, JPEG is divided into 8×8 squares, and H.264 is divided into 16×16 squares. Therefore, it is necessary to use a line and a block conversion. If implemented with a digital circuit, larger memory is required to buffer the stored data. The present disclosure proposes an excellent memory utilization method to reduce the storage space required in the memory, thereby improving the memory usage.

[Example of integrated conversion method of row and block]

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a method for integrating rows and blocks according to an exemplary embodiment of the present invention. Before making the following description, it must be stated that the width of the image is defined as W, and the height of the image is defined as H. As shown in FIG. 1, during image or video (sequence image) data compression, image 100 is divided into M horizontal blocks HB_0~HB_M-1 and N vertical blocks VB_0~VB_N-1, among which The horizontal blocks HB_0~HB_M-1 and the plurality of vertical blocks VB_0~VB_N-1 form an M×N matrix, and each matrix has a size of B×B. Furthermore, each matrix has B x B pixels and each pixel has one byte of data. It should be noted that in this embodiment, every 16 pixels are defined as one pixel unit, so the entire image 100 is first coordinated and the resolution of the image coordinates is a pixel. Yuan (each matrix has B pixel units). As shown in FIG. 1, the plurality of first pixel units pu1 are sequentially defined along the horizontal direction of the first horizontal block HB_0 of the plurality of horizontal blocks HB_0~HB_M-1, and so on, a plurality of Xth The pixel unit puX is sequentially defined along the horizontal direction of the Xth horizontal block HB_X(X-1) of the plurality of horizontal blocks HB_0~HB_M-1, wherein B, M and N are positive integers and N is an image The width is divided by B, and X is a positive integer between 2 and M.

Next, the conversion mechanism of the integrated conversion method of rows and blocks will be further explained. Briefly, the present disclosure writes a plurality of first pixel units pu1 and a plurality of X pixel units puX of the image 100 into the memory EVM through a line conversion method, and reads and stores the data in the block conversion mode. The plurality of first pixel units pu1 and the plurality of Xth pixel units puX of the memory EVM perform image data compression work.

Please refer to FIG. 1 to FIG. 3 simultaneously. FIG. 2A and FIG. 2B are schematic diagrams showing the conversion of image lines to a memory according to an exemplary embodiment of the present invention. FIG. 3 is a flow chart of a method for integrating rows and blocks according to an exemplary embodiment of the present invention. The row and block integration conversion method includes the steps of dividing the image 100 into M horizontal blocks and N vertical blocks (step S310). The addresses of the plurality of first pixel units pu1 of the first horizontal block HB_0 of the plurality of horizontal blocks HB_0~HB_M-1 are sequentially written into the memory EVM according to the order of the accumulated addresses of the memory EVM. (Step S320). The addresses of the plurality of first pixel units pu1 are cyclically read from a predetermined distance per interval of the memory EVM, wherein the predetermined distance of the pixels is the width W of the image (step S330). The position of the plurality of Xth pixel units is obtained by the double loop algorithm to sequentially read the addresses of the plurality of Xth pixel units of the Xth horizontal block HB_X (step S340). When the address of the plurality of Xth pixel units of the memory is cyclically read by a predetermined distance per interval, the number of the X+1 horizontal blocks HB_X of the plurality of horizontal blocks HB_0~HB_M-1 is increased. The addresses of the X+1th pixel units are cyclically written to the memory EVM every predetermined interval of the interval pixels (step S350). Here, the data of the first to the 16th lines of the image 100 (that is, the data of the horizontal block HB_0) will be described as an example to better understand the present disclosure. In this embodiment, as shown in FIG. 2A and FIG. 2B, each The first pixel units pu1 are respectively defined as 0~(B×N)-1, where 0~N-1 is defined as the first line L1; and so on, (B-1)×N~(B×N) -1 is defined as the Bth line LB, and in the present embodiment, B is equal to 16.

In step S320, the first pixel unit pu1 (ie, 0~N-1) of the first line L1 of the image 100 is sequentially written into the memory EVM according to the order of the accumulated addresses of the memory EVM to complete the line. Conversion. Then, the first pixel unit pu1 (that is, N~2N-1) of the second line L2 of the image 100 is sequentially written according to the order of the accumulated addresses of the memory EVM. Similarly, the B of the image 100 The first pixel unit pu1 of the line LB (i.e., (B-1) x N~(B x N)-1) is sequentially written to the memory EVM in accordance with the order of the accumulated addresses of the memory EVM. At this time, the overall storage space of the memory EVM is equal to the storage space of the horizontal block HB_0. In the integrated conversion method of the content and the block of the disclosure, the memory EVM only needs the storage space of the first horizontal block HB_0 to be used (that is, B×W), so compared with the prior art, the disclosure content The storage space of half of the memory can be saved, thereby increasing the usage rate of the memory, that is, the storage space of the memory of the prior art needs 32×W, but the storage space of the memory of the disclosure only needs 16×W. Next, we will more clearly explain the details of the integrated conversion method between rows and blocks.

In step S330, the address of the plurality of first pixel units pu1 in the memory EVM is cyclically read every predetermined interval of one pixel to complete the block conversion. It is worth noting that the predetermined distance of the pixels is the image. The width of 100. Further, a plurality of first pixel units pu1 (ie, 0, N, 2N, 3N~(B-1)×N) in the memory EVM are sequentially read, and then, the memory A plurality of first pixel units pu1 (ie, 1, N+1, 2N+1, 3N+1~(B-1)×N+1) in the EVM are sequentially read. By analogy, a plurality of first pixel units pu1 (i.e., N-1, 2N-1, 3N-1~B×N-1) in the memory EVM are sequentially read. It is worth mentioning that when a plurality of first pixel units pu1 (ie, 0, N, 2N, 3N~(B-1)×N) are sequentially read out to release the storage space, the second The plurality of second pixel units pu2 in the first row of the horizontal block HB_1 sequentially write the plurality of first pixel units pu1 (ie, 0, N, 2N, 3N~) (B-1) × N) The original storage space. And so on, when a plurality of first pixel units pu1 (ie, N-1, 2N-1, 3N-1~B×N-1) are sequentially read out to release the storage space, the second The plurality of second pixel units pu2 of the Bth row of the horizontal block HB_1 sequentially write the plurality of first pixel units pu1 (ie, 0, N, 2N, 3N~(B-1)×N). The original storage space for simultaneous row conversion and block conversion (from the perspective of image 100 to better understand the manner of block conversion of the present disclosure).

In step S340, the positions of the plurality of Xth pixel units puX are obtained by the double loop algorithm to sequentially read the addresses of the plurality of Xth pixel units puX of the Xth horizontal block HB_X. In this embodiment, the image 100 is first normalized by a row-to-block integration conversion method (where the coordinate units of each horizontal block are the same). For example, the coordinate positioning of the first pixel unit pu1 of the first horizontal block HB_0 (0~(B×N)-1) and the coordinate positioning of the second pixel unit pu2 of the second horizontal block HB_1 (0) ~(B×N)-1) is the same, and other horizontal blocks (such as HB_2~HB_X-1) are the same. In this embodiment, the image 100 can be regarded as being composed of a plurality of horizontal blocks HB_0~HB_M-1, and each horizontal block (for example, HB_0) is composed of the first to B lines L1 to LB, and each line ( For example, L1) is composed of a plurality of first pixel units pu1. In the disclosure, since the image 100 is converted in the order of the horizontal blocks HB_0~HB_M-1 and stored in the memory EVM, it is necessary to further calculate the coordinate position of each pixel unit of the image 100 in detail. Please select its address.

In step S350, when the plurality of second pixel units pu2 of the second horizontal block HB_1 stored in the memory EVM are sequentially read out to release the storage space, the third horizontal block in the image 100 The plurality of third pixel units pu3 of HB_2 are sequentially written into the original storage space of the plurality of second pixel units pu2 in the memory EVM. And so on, when the plurality of M-1 pixel units of the M-1 horizontal block HB_M-2 stored in the memory EVM are sequentially read out to release the storage space, the image 100 The plurality of Mth pixel units of the M horizontal block HB_M-1 are sequentially written into the original storage space of the plurality of M-1 pixel units in the memory EVM, thereby completing the transfer at the same time. Switch to block conversion work. It is worth mentioning that, when the image 100 of the present disclosure performs the integrated conversion operation of the row and the block, the read address speed is preferably greater than or equal to the write address speed to avoid overwriting to the memory EVM. Store data.

Briefly, in the disclosure, the plurality of first pixel units pu1 of the first horizontal block HB_0 in the image 100 are sequentially written into the storage space of the memory EVM, and other horizontal areas in the image 100. The order of the plurality of X-th pixel units puX of the block HB_X (for example, one of HB_1~HB_M-1) is written in the memory EVM is the same as the reading of the plurality of X-th of the horizontal block HB_X-1 from the memory EVM. The order of 1 pixel unit puX-1.

In order to explain in more detail the details of the double loop algorithm of the present invention, at least one of the various embodiments will be further described below.

In the following various embodiments, portions different from the above-described embodiments will be described, and the remaining portions that are the same as or similar to the above-described embodiments will be omitted. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Another embodiment of a method for integrating rows and blocks]

Please refer to FIG. 1 to FIG. 4 simultaneously. FIG. 4 is a flowchart of a method for integrating rows and blocks according to an exemplary embodiment of the present invention. The following will further explain the double loop algorithm to better understand the way of calculating the coordinates of the pixel unit of the image 100. Before entering the double loop algorithm, the row and block integration conversion method further includes the following steps: initializing the vertical back The circle parameter (step S402) and the initialization dynamic address function (step S404). The double loop algorithm includes the following steps: determining whether the range of the vertical block is exceeded by the vertical loop parameter (step S406). If the vertical loop parameter has not exceeded the range of the vertical block, the horizontal loop parameter and the fixed address function are initialized (steps S408 and S410). Whether or not the range of the horizontal block is exceeded is determined by the horizontal loop parameter (step S412). If the horizontal loop parameter has not exceeded the range of the horizontal block, the pixel unit address is obtained through the fixed address function and the dynamic address function (step S414), and the decision decision is entered (step S416). Next, through the decision, if the pixel unit address has not exceeded the range of the horizontal block, the pixel unit address will be The next fixed address function is stored (step S418). If the pixel unit address is outside the range of the horizontal block, the pixel unit address is subtracted from the maximum value of the horizontal block and stored in the next fixed address function (step S420). The horizontal loop parameter is incremented by one and returned to the step of determining whether the horizontal loop parameter exceeds the range of the horizontal block (step S422). If the horizontal loop parameter exceeds the range of the horizontal block, the next dynamic address function is executed (step S424). The vertical loop parameter is incremented by one and returned to the step of determining whether the vertical loop parameter exceeds the range of the vertical block (step S426). Next, the flow of each step of the embodiment of FIG. 4 will be described in detail, and when necessary, please refer to the following core code, where the symbol j represents a vertical loop parameter, the symbol i represents a horizontal loop parameter, and the fixed address function. The next fixed addressing function is reading address(i) and reading address(i+1), and the next dynamic addressing function is D(j+1)=div(D(j),B)+mod( D(j), B)×N, where div(D(j), B) is an integer operation of the dynamic addressing function with B, and mod(D(j), B) is the dynamic addressing function with B Perform the remainder operation.

[core code]

In step S402, in the embodiment, the image 100 has a plurality of horizontal blocks HB_0~HB_M-1, and the image 100 is written to the memory EVM according to the order of the horizontal blocks HB_0~HB_M-1, Initialize the vertical loop parameter to zero. Further, the horizontal block HB_0 of the image 100 is defined as a vertical loop parameter of zero; and so on, the horizontal block HB_M-1 of the image 100 is defined as a vertical loop parameter of M-1, that is, vertical back. The circle parameter is 0~M-1, where M is the height of the image (H) divided by B.

In step S404, since the address function of the present embodiment is composed of a fixed address function reading address (i) and a dynamic address function D(j), and a fixed address function and a horizontal loop parameter (ie, i) Correlation, and the dynamic addressing function is related to the vertical loop parameter (ie, j), so in this step, the dynamic address function is initialized to N, that is, D(0)=N. Furthermore, the difference between the horizontal address parameter of the fixed address function and the next fixed address function is one, and the difference between the vertical address parameter of the dynamic address function and the next dynamic address function is one, according to The order of each horizontal block is to obtain the coordinate position of the pixel unit. It is worth mentioning that the next dynamic address function is an integer operation based on the size of the dynamic address function and the matrix (ie, B), and the next dynamic address function is based on the dynamic address function and the size of the matrix ( That is, B) performs a remainder operation with the number of vertical blocks (ie, N), that is, D(j+1)=div(D(j), B)+mod(D(j), B)× N, according to which the coordinate position of each pixel unit of the image 100 is calculated to read its address to sequentially write to the memory EVM to achieve the line conversion work.

In step S406, the double loop algorithm of the present disclosure begins to enter the first loop operation, since the height of the image 100 has been coordinated into a plurality of horizontal blocks HB_0~HB_M-1 (ie, vertical loops) The parameter is 0~M-1), so the integrated conversion method of row and block will judge whether the vertical block range is exceeded by the vertical loop parameter, and the vertical loop parameter will gradually gradually decrease from 0 in this first loop operation. Increase to M-1. According to this, Through the decision of the first loop calculation, the pixel unit addresses in the image 100 are sequentially written to the memory EVM according to the order of the horizontal blocks HB_0~HB_M-1. Furthermore, if the vertical loop parameter has not exceeded the range of the vertical block, then go to step S408; if the vertical loop parameter exceeds the range of the vertical block, the double loop algorithm ends.

In step S408, at the beginning of the first loop operation, the horizontal loop parameter is first initialized to zero, that is, i=0. Since each of the plurality of horizontal blocks HB_0~HB_M-1 has the same number of pixel units (ie, B×N pixel units), and will be coordinated to 0~(B×N)-1, 2A and 2B. Therefore, when the vertical loop parameter proceeds to the beginning of each horizontal block, the horizontal loop parameter is initialized to zero.

In step S410, as described in step S408, similarly, the fixed address function also needs to be initialized, that is, reading address (0) = 0, so that each time in the horizontal block can be re-read during the second loop operation. The coordinates of a pixel unit of one line (from 0 to (B × N) -1).

In step S412, the double loop algorithm of the present disclosure begins to enter the second loop operation, where the row and block integrated conversion method has locked the horizontal block HB_0~HB_M-1 through the vertical loop parameter. One of them (for example, horizontal block HB_1), and each horizontal block (with B × N pixel units) will be coordinated to 0~(B×N)-1, as shown in Fig. 2A and Fig. 2B. Show. Therefore, the content of the disclosure is judged by a decision mechanism, that is, whether the horizontal block is beyond the range of the horizontal block (0~B×N-1), and the horizontal loop parameter is in the second loop. In the operation, it will gradually increase from 0 to B×N-1 to completely scan all the pixel units. If the horizontal loop parameter has not exceeded the range of the horizontal block, it proceeds to step S414; if the horizontal loop parameter exceeds the range of the horizontal block, it proceeds to step S424.

In step S414, the body portion of the second loop operation has been started here. If the horizontal loop parameter has not exceeded the range of the horizontal block ((0~(B×N)-1), the disclosure content will pass through Fixed address function and dynamic address function to obtain pixel list The meta-address, that is, the integer operation and the remainder operation to obtain the coordinates of each pixel unit to read the pixel unit address, please also refer to C=reading address(i)+D(j) in the core code. To better understand the contents of this disclosure. Thereafter, another decision decision is made, that is, step S416.

In step S416, a decision mechanism is entered to determine that if the pixel unit address acquired in step S414 has not exceeded the range of the horizontal block, the process proceeds to step S418; if the pixel unit address obtained in step S414 is obtained If the range of the horizontal block is exceeded, the process proceeds to step S420.

In step S418, after entering the step after the judgment of the decision mechanism, it indicates that the pixel unit address has not exceeded the range of the horizontal block, and the disclosure content stores the pixel unit address to the next fixed address function. For example, the reading address (i+1)=C in the core code is used for subsequent continuous operations.

In step S420, after the judgment of the decision mechanism, the step of entering the step indicates that the pixel unit address is beyond the range of the horizontal block, and the pixel unit address is subtracted from the maximum value of the horizontal block (0~( B×N)-1, that is, B×N pixel units) are stored to the next fixed address function, such as reading address(i+1)=C in the core code. Thereafter, the process proceeds to step S422.

In step S422, at the end of the second loop operation, the horizontal loop parameter is incremented by one (i.e., i = i + 1) and the process returns to step S412 to determine whether the horizontal loop parameter exceeds the range of the horizontal block. To gradually convert each matrix (size B×B) in the horizontal block.

In step S424, if the horizontal loop parameter exceeds the range of the horizontal block (0~B×N-1), that is, the horizontal loop parameter is equal to or greater than (B×N)-1, the second loop is ended. The operation and jump back to the body of the first loop operation to perform the operation of the next dynamic address function. Further, the next dynamic addressing function performs an integer operation according to the dynamic addressing function and the size of the matrix, and the next dynamic addressing function is based on the dynamic addressing function, the size of the matrix, and the vertical region. The number of blocks to perform a remainder operation, that is, within the core code D(j+1)=div(D(j), B)+mod(D(j), B)×N.

In step S426, at the end of the first loop operation, the vertical loop parameter is incremented by one (i.e., j = j + 1) and the process returns to step S406 to determine whether the vertical loop parameter exceeds the range of the vertical block. Thereby, each horizontal block in the image 100 is gradually converted. If the vertical loop parameter exceeds the range of the vertical block (0~M-1), the double loop algorithm ends.

The present disclosure further provides a computer readable storage medium for storing a computer program, the computer program comprising a plurality of code codes for loading into an electronic device and causing the electronic device to perform the above-mentioned FIG. 1 to FIG. 4 The integrated conversion method of the line and the block disclosed in the above embodiment is described in detail in the above embodiments, and details are not described herein again.

[Possible effects of the examples]

In summary, the method for converting the line and the block proposed by the embodiment of the present invention and the computer readable storage medium, the first pixel unit and the X pixel unit of the image are written into the memory by line conversion. And reading the first pixel unit and the X pixel unit stored in the memory through the block conversion method, thereby increasing the usage rate of the memory and greatly reducing the implementation cost of the digital circuit.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

S402, S404, S406, S408, S410, S412, S414, S416, S418, S420, S422, S424, S426‧‧ steps

Claims (8)

A row and block integration conversion method for an image, the row and block integration conversion method comprises the steps of: dividing the image into M horizontal blocks and N vertical blocks; sequentially The addresses of the plurality of first pixel units of a first horizontal block in the horizontal blocks are written into the memory according to the sequence of accumulated addresses of a memory; a pixel is reserved for each pixel from the memory. The distance is cyclically read the addresses of the first pixel units, wherein the predetermined distance of the pixels is the width of the image; and a position of the plurality of X-1 pixel units is obtained by a double loop algorithm Sequentially reading the addresses of the plurality of X-1 pixel units of the X-1 horizontal block; and cyclically reading the X-1 of the memory every predetermined interval of the pixels When the address of the pixel unit is located, the addresses of the plurality of Xth pixel units of the Xth horizontal block in the horizontal blocks are cyclically written to the memory at intervals of the predetermined distance of the pixel; Where X-1 is a positive integer between 2 and M, wherein the horizontal blocks form an M×N matrix with the vertical blocks , wherein each element of the matrix is a matrix of B×B, and the first pixel unit and the Xth pixel unit include B pixels, wherein B, M and N are positive integers and N is the The width of the image is divided by B; wherein the double loop algorithm includes the following steps: determining whether the vertical block is beyond a range by using a vertical loop parameter; if the vertical loop parameter has not exceeded the range of the vertical block, Terminating a horizontal loop parameter and a fixed address function, and if the vertical loop parameter exceeds the range of the vertical block, ending the double loop algorithm; The horizontal loop parameter is used to determine whether the range of the horizontal block is exceeded; if the horizontal loop parameter has not exceeded the range of the horizontal block, a pixel is obtained through the fixed address function and a dynamic address function. Unit address, and enter a decision judgment; through the decision, if the pixel unit address has not exceeded the range of the horizontal block, the pixel unit address is stored to the next fixed address function; Decision making, if the pixel unit address exceeds the range of the horizontal block, the pixel unit address is subtracted from the maximum value of the horizontal block and stored in the next fixed address function; The loop parameter is incremented by one, and returns to the step of determining whether the horizontal loop parameter exceeds the range of the horizontal block; if the horizontal loop parameter exceeds the range of the horizontal block, executing the next dynamic address function; Adding the horizontal loop parameter to one, and returning to the step of determining whether the horizontal loop parameter exceeds the range of the vertical block; wherein the fixed address function and the next solid The difference between the horizontal loop parameters of the address function is one, and the difference between the dynamic address function and the vertical loop parameter of the next dynamic address function is one, and wherein the next dynamic address function An integer operation is performed according to the dynamic address function and the size of the matrix, and the next dynamic address function performs a remainder operation according to the dynamic address function, the size of the matrix, and the number of the vertical blocks. The method for converting a row and a block according to claim 1, wherein the first pixel units are sequentially defined along a horizontal direction of the first horizontal block of the horizontal blocks, and the The X-th pixel unit is sequentially defined along a horizontal direction of the X-th horizontal block of the horizontal blocks, wherein the line conversion mode is adopted Writing the first pixel unit and the X pixel unit of the image into the memory, and reading the first pixel unit and the X pixel stored in the memory by using a block conversion manner unit. The method for converting a row and a block according to claim 1, wherein before entering the double loop algorithm, the method comprises the steps of: initializing the vertical loop parameter; and initializing the dynamic address function. The method for converting a row and a block according to claim 1, wherein the order of cyclically reading the addresses of the first pixel units from a predetermined distance of one pixel in the memory is equal to the The order in which the addresses of the plurality of second pixel units of a second horizontal block in the horizontal block are written into the memory. The method for converting a row and a block according to claim 1, wherein the number of bytes of the memory is equal to a product of B and a width of the image, and the read address speed is greater than or equal to a write address speed. The method for converting a row and a block according to claim 1, wherein the order of reading the addresses of the X-th pixel units from the memory is equal to writing the addresses of the X+1 pixel units The order in which the memory is entered. A computer readable storage medium for storing a computer program, the computer program comprising a plurality of code for loading into an electronic device and causing the electronic device to perform integration of a line and a block for an image The conversion method, the row and block integration conversion method comprises the steps of: dividing the image into M horizontal blocks and N vertical blocks; sequentially ordering a first horizontal block in the horizontal blocks The addresses of the plurality of first pixel units are written into the memory according to the order of the accumulated addresses of the memory; the first pixels are cyclically read from the memory by a predetermined distance of one pixel. The address of the unit, wherein the predetermined distance of the pixel is the width of the image; and the position of the plurality of X-1 pixel units is obtained by a double loop algorithm to sequentially Reading an address of a plurality of X-1 pixel units of an X-1 horizontal block; and cyclically reading the X-1 pictures of the memory every predetermined interval of the pixel When the address of the prime unit is located, the addresses of the plurality of Xth pixel units of an Xth horizontal block in the horizontal blocks are cyclically written to the memory at a predetermined distance from the pixel; wherein X-1 is a positive integer between 2 and M, wherein the horizontal blocks form an M×N matrix with the vertical blocks, wherein each element of the matrix is a matrix of B×B, and The first pixel unit and the X pixel units include B pixels, wherein B, M and N are positive integers and N is the width of the image divided by B; wherein the double loop algorithm comprises the following steps: Determining whether the range of the vertical block is exceeded by a vertical loop parameter; if the vertical loop parameter has not exceeded the range of the vertical block, initializing a horizontal loop parameter and a fixed address function, and if If the vertical loop parameter exceeds the range of the vertical block, the double loop algorithm ends; through the horizontal loop Counting whether the range of the horizontal block is exceeded; if the horizontal loop parameter has not exceeded the range of the horizontal block, obtaining a pixel unit address by using the fixed address function and a dynamic address function, and Entering a decision judgment; determining, by the decision, that if the pixel unit address has not exceeded the range of the horizontal block, storing the pixel unit address to the next fixed address function; If the pixel unit address is outside the range of the horizontal block, the pixel unit address is subtracted from the horizontal block. The maximum value is stored to the next fixed reading function; the horizontal loop parameter is incremented by one, and the step of determining whether the horizontal loop parameter exceeds the range of the horizontal block is returned; if the horizontal loop parameter exceeds the level The range of the block, the next dynamic addressing function is executed; and the horizontal loop parameter is incremented by one, and back to the step of determining whether the horizontal loop parameter exceeds the range of the vertical block; wherein the fixed address function The difference from the horizontal loop parameter of the next fixed address function is one, and the difference between the dynamic address function and the vertical loop parameter of the next dynamic address function is one, and wherein the lower A dynamic addressing function performs an integer operation according to the dynamic addressing function and the size of the matrix, and the next dynamic addressing function performs according to the dynamic addressing function, the size of the matrix, and the number of the vertical blocks. A remainder operation. The computer readable storage medium as claimed in claim 7, wherein the number of bytes of the memory is equal to a product of B and a width of the image, and the read address speed is greater than or equal to the write address speed.