TWI578706B - Apparatus with bootstrap capacitor charging circuit - Google Patents

Description

Electronic device with shoe with capacitor charging circuit

The present invention relates to an electronic device having a bootstrap capacitor charging circuit.

The first figure shows a schematic diagram of a conventional shoe with a capacitor charging circuit 10. The shoe with capacitor charging circuit 10 includes a voltage stabilizing circuit 12 and a diode DX for charging a boot band capacitor C1. As shown in the first figure, the diode DX has an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the voltage stabilizing circuit 12, and the cathode terminal is coupled to the shoe capacitor C1.

In operation, when the clock signal CLK is at the logic 0 level, the clock signal CLK turns off the upper bridge switch M1 in the output stage 19 through the drive circuit 14 and turns on the lower bridge switch M2 in the output stage 19 through the drive circuit 16, so The voltage level of the voltage switching terminal SW is the ground potential. At this time, the regulator circuit 12 starts to charge the shoe capacitor C1 through the diode DX. When the voltage level of the terminal A1 on the bootband capacitor C1 is equal to the voltage GVDD provided by the regulator circuit 12 minus the forward voltage drop Vf of the diode DX, the regulator circuit 12 stops the strap capacitor C1. Charging.

When the pulse signal CLK is at the logic 1 level, the clock signal CLK The upper bridge switch M1 in the output stage 19 is turned on by the drive circuit 14, and the lower bridge switch M2 in the output stage 19 is turned off by the drive circuit 16, so that the voltage VSW of the voltage switch terminal SW is the supply power supply voltage PVDD. At this time, the voltage level VA1 of the terminal A1 on the shoe capacitor CB is determined by the formula (1).

VA1=PVDD+GVDD-Vf (1)

It can be seen from the formula (1) that the voltage level VA1 of the terminal A1 on the bootband capacitor C1 is greater than the supply power supply voltage PVDD, so the drive circuit 14 can turn on the upper bridge drive unit M1 with a higher voltage level VA1, thereby driving the load. 18.

However, when output stage 19 is part of a class D amplifier and the load 18 is a speaker, a Class D amplifier configuration with a single-ended output stage will transmit low frequencies. When the power is output, a phenomenon of bus pumping of the power supply circuit is generated. The power supply circuit energy backflow phenomenon causes energy to be recharged from the load 18 to the supply power source, causing the amplitude of the supply power supply voltage PVDD to fluctuate. In order to solve this problem, a voltage dividing circuit 20 including a large capacitance between the power supply PVDD and the ground terminal is connected to the other side of the load 18 to absorb energy, as shown in the second figure. However, the voltage divider circuit 20 may cause the class D amplifier to require a long fade-in time when powering up.

An electronic device according to an embodiment of the invention includes a first N-type transistor, a second N-type transistor, a bootband capacitor, a first charging circuit, and a second charging circuit. The first N-type transistor is coupled to a power supply The power input is used to receive a second power source between the input terminal and a switching node. The second N-type transistor is coupled between the switching node and a ground. The shoe strap capacitor has a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The first charging circuit is coupled to the upper terminal of the bootband capacitor, and the first charging circuit charges the bootband capacitor by a first power source. The second charging circuit is coupled to the upper terminal of the bootband capacitor, and the second charging circuit charges the bootband capacitor by the second power source. The potential of the second power source is higher than the potential of the first power source.

An electronic device according to another embodiment of the present invention includes a first class D amplifier, a second class D amplifier, a first inductor, a second inductor, and a speaker. The first class D amplifier includes a first N-type transistor coupled between a power input terminal and a switching node for receiving a second power source. The first class D amplifier includes a second N-type transistor coupled between the switching node and a ground. The first class D amplifier includes a bootband capacitor having a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The first class D amplifier includes a first charging circuit coupled to the upper terminal of the shoe capacitor, the first charging circuit charging the shoe capacitor by a first power source. The first class D amplifier includes a second charging circuit coupled to the upper terminal of the boot band capacitor, and the second charging circuit charges the shoe cap capacitor with a certain current by the second power source. The second class D amplifier comprises a The first N-type transistor is coupled between a power input end and a switching node, and the power input end is configured to receive the second power source. The second class D amplifier includes a second N-type transistor coupled between the switching node and a ground. The second class D amplifier includes a bootband capacitor having a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The second class D amplifier includes a first charging circuit coupled to the upper terminal of the shoe capacitor, the first charging circuit charging the shoe capacitor by a first power source. The second class D amplifier includes a second charging circuit coupled to the upper terminal of the boot band capacitor, and the second charging circuit charges the shoe cap capacitor with a certain current by the second power source. The first inductor is coupled to the switching node of the first class D amplifier. The second inductor is coupled to the switching node of the second class D amplifier. The speaker is coupled between the first inductor and the second inductor.

10‧‧‧ Boots with capacitor charging circuit

12‧‧‧ Voltage regulator circuit

14,16‧‧‧ drive circuit

18‧‧‧load

19‧‧‧Output level

20‧‧‧voltage circuit

30‧‧‧Electronic devices

32‧‧‧Class D amplifier

322,322”‧‧‧Output

324,324"‧‧‧ boots with capacitor charging circuit

3242, 3242" ‧‧‧Low-voltage charging circuit

3244, 3244', 3244" ‧ ‧ high voltage charging circuit

326,328,326",328"‧‧‧ drive circuit

34‧‧‧Speakers

36‧‧‧voltage circuit

42‧‧‧Variable circuit

60‧‧‧Electronic devices

62,64‧‧‧D class amplifier

66‧‧‧Speakers

C1, CBT, CBT"‧‧‧ boots with capacitor

C3, C4‧‧‧ capacitor

CL, CL1, CL2‧‧‧ capacitor

D1, D2, DX‧‧‧ diode

L1, L2‧‧‧ inductance

M1, M2, MU, MD‧‧‧ transistor

N1‧‧‧O crystal

P1, P2, P3, P4, P5‧‧‧ transistors

ZD1, ZD2‧‧‧ clamp components

The first figure shows a schematic diagram of a conventional shoe with a capacitor charging circuit.

The second figure shows a schematic diagram of a conventional single-ended output class D amplifier.

The third figure shows a block diagram of an electronic device having a bootstrap capacitor charging circuit in accordance with an embodiment of the present invention.

The fourth figure shows a circuit diagram of the low voltage charging circuit and the high voltage charging circuit in combination with an embodiment of the present invention.

The fifth figure shows the low voltage charging circuit and another embodiment of the present invention. A circuit diagram of the high voltage charging circuit.

Figure 6 is a block diagram showing an electronic device having a bootstrap capacitor charging circuit in accordance with another embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" or "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The third figure shows a block diagram of an electronic device 30 having a bootstrap capacitor charging circuit in accordance with an embodiment of the present invention. In the present embodiment, the electronic device 30 includes a class D amplifier 32. The class D amplifier 32 includes an output stage 322, wherein the output stage 322 is comprised of an upper bridge switch MU and a lower bridge switch MD. The upper bridge switch MU and the lower bridge switch MD are coupled in series between a power input terminal (receiving a supply power voltage PVDD) and a ground terminal. In this embodiment, the upper bridge switch MU and the lower bridge switch MD are an N-type electric crystal. Body component.

Referring to the third figure, the electronic device 30 further includes a bootband capacitor charging circuit 324 for charging a bootband capacitor CBT. The shoe with capacitor charging circuit 324 includes a low voltage charging circuit 3242 and a high voltage charging circuit 3244. The shoe strap capacitor CBT is coupled between the shoe strap capacitor charging circuit 324 and a crossover point SW of the upper bridge switch MU and the lower bridge switch MD. The bootband capacitor CBT is charged by the bootband capacitor charging circuit 34 to produce a turn-on voltage that turns on the upper bridge switch MU.

The fourth figure shows a circuit diagram of the low voltage charging circuit 3242 and the high voltage charging circuit 3244 in connection with an embodiment of the present invention. Referring to the fourth figure, the low voltage charging circuit 342 includes a voltage stabilizing circuit 42 and a diode D1. The voltage stabilizing circuit 42 is configured to generate a stable supply voltage GVDD. In an embodiment of the invention, the supply voltage GVDD is 5V. However, the invention should not be limited thereto. The diode D1 has an anode (Anode) that receives the supply voltage GVDD and a cathode that is coupled to the upper terminal BST of the shoe capacitor CBT.

The high voltage charging circuit 3244 includes a bias current source IB1, P-type transistors P1 and P2, a diode D2, and a clamping element ZD1. In this embodiment, the clamping component ZD1 is a Zener diode. However, the invention should not be limited thereto. Any semiconductor component having a clamping voltage function, such as an avalanche diode or a transient state. A voltage regulator (Transient Voltage Suppresser, TVS) can be implemented as the clamp component. The P-type transistor P1 has a source terminal receiving the supply power voltage PVDD, and receives the bias voltage A drain terminal of current source IB1 is coupled to a gate terminal of the drain terminal. The P-type transistor P2 has a source terminal receiving the supply power voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P1. The clamping component ZD1 has a first end coupled to a terminal end of the P-type transistor P2 and a second end coupled to the crossing point SW. In the present embodiment, the clamping element ZD is a Zener diode ZD1 having a cathode coupled to a terminal of the P-type transistor P2 and an anode coupled to the crossing point SW. The diode D2 has an anode coupled to the drain terminal of the P-type transistor P2 and a cathode coupled to the upper terminal BST of the boot capacitor CBT. In an embodiment of the invention, the supply voltage PVDD is 24V, and the current value of the bias current source IB1 is 10μA. However, the invention should not be limited thereto.

The charging mode of the shoe belt capacitor CBT will be described below with reference to the circuit diagrams of the third and fourth figures. When the class D amplifier 32 is within a startup time after power is supplied, the drive circuits 326 and 328 have not supplied a drive signal to the upper bridge switch MU and the lower bridge switch MD. At this time, the upper bridge switch MU and the lower bridge switch MD are in a closed state. Since the speaker 18 is driven by the class D amplifier 32 having a single-ended output stage, in order to solve the phenomenon of energy backflow of the power supply circuit, the right side of the speaker 18 is coupled to a voltage dividing circuit 36 including large capacitors C1 and C2. To absorb energy. Because the voltage dividing circuit 36 bisects the potential difference between the supply voltage PVDD and the ground, the voltage of the left end X1 of the speaker is 1/2*PVDD, and the voltage of the crossing point SW Also 1/2*PVDD.

In this case, due to the stability in the low voltage charging circuit 3242 The supply voltage GVDD provided by the voltage circuit 42 is smaller than the voltage of the crossover point SW, and therefore, the low voltage charging circuit 3242 does not charge the shoe capacitor CBT. On the other hand, since the supply voltage PVDD used in the high voltage charging circuit 3244 is greater than the voltage of the crossover point SW, the P-type transistor P2 in the fourth figure is proportional to the bias current source. The current value of IB1 charges the shoe capacitor CBT. At this time, the diode D1 in the low voltage charging circuit 3242 can prevent current from being recharged to the voltage stabilizing circuit 42.

A selection of the diode D2 and the Zener diode ZD1 will now be described in the third and fourth figures. Considering normal operation (i.e., after the drive circuits 326 and 328 provide a drive signal), the voltage level difference (the potential difference between the node BST and the node SW) of the drive circuit 326 is preferably substantially equal to the drive. The voltage level difference of circuit 328 (the potential difference between the supply voltage GVDD and the ground), so the node BST can be selected to charge to 1/2*PVDD+GVDD. Referring to the fourth figure, in a preferred embodiment, the reverse collapse voltage value of the Zener diode ZD1 can be selected as GVDD + Vf, where Vf is equal to the forward bias value of the diode D2. In this way, when the high voltage charging circuit 3244 charges the shoe capacitor CBT, the Zener diode ZD1 operates in a reverse bias region, and the diode D2 operates in a forward bias region, so The voltage at node BST can be clamped to 1/2*PVDD+GVDD.

The fifth figure shows a circuit diagram of the high voltage charging circuit 3244' in connection with another embodiment of the present invention. Referring to the fifth figure, the low voltage charging circuit 3244' includes a bias current source IB2, P-type transistors P3, P4 and P5, an N-type transistor. N1, a diode D3, and a Zener diode ZD2. The P-type transistor P3 has a source terminal receiving the supply power voltage PVDD, receiving a drain terminal of the bias current source IB2 and a gate terminal coupled to the drain terminal. The P-type transistor P4 has a source terminal receiving the supply power supply voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P3. The P-type transistor P5 has a source terminal receiving the supply power supply voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P3. The N-type transistor N1 has a terminal end coupled to a terminal of the P-type transistor P5 and a gate terminal coupled to a terminal of the P-type transistor P4.

The Zener diode ZD2 has a cathode coupled to the drain terminal of the P-type transistor P4 and an anode coupled to the crossover point SW. The diode D3 has an anode coupled to a source terminal of the N-type transistor N1 and a cathode coupled to the upper terminal BST of the shoe capacitor CBT. In an embodiment of the invention, the supply voltage PVDD is 24V, and the current value of the bias current source IB2 is 10μA. However, the invention should not be limited thereto.

In operation, since the right side of the speaker 18 is coupled to the voltage dividing circuit 36 including the large capacitors C1 and C2 to absorb the energy of the power supply circuit energy backflow, as shown in the third figure. Therefore, the initial value of the voltage of the node SW in the fifth figure is 1/2*PVDD. The drive circuits 326 and 328 have not provided a drive signal to the upper bridge switch MU and the lower bridge switch MD during a start-up time after the class D amplifier 32 is powered. The P-type transistor P5 in the high voltage charging circuit 3244' charges the shoe capacitor CBT in proportion to the current value of the bias current source IB2. In an embodiment, the node BST may be selected to charge to 1/2*PVDD+GVDD. Therefore, the reverse collapse voltage value of the Zener diode ZD1 can be selected as V _{GS, N1} + GVDD + Vf, where V _{GS, M1 is} the gate-source voltage level difference of the N-type transistor N1, and Vf is equal to the forward bias value of the diode D3. In this way, when the high voltage charging circuit 3244' charges the shoe capacitor CBT, the Zener diode ZD2 operates in the reverse bias region, and the diode D3 operates in the forward bias region. The voltage at this node BST can be clamped to 1/2*PVDD+GVDD.

In the third figure, the speaker 34 is driven by a class D amplifier 32 having a single ended output stage. In another embodiment of the invention, the speaker can be pushed by an electronic device 60 having an H-bridge, as shown in the sixth diagram. Referring to the sixth diagram, the speaker 66 is driven by the upper bridge switch MU and the lower bridge switch MD in the output stage 322 and the upper bridge switch MU and the lower bridge switch MD in the output stage 322". The upper bridge switch in the output stage 322 The upper bridge switch MU and the lower bridge switch MD of the MU and the lower bridge switch MD and the output stage 322" form an H-bridge configuration. The Class D amplifier 62 on the left side of the speaker 66 and the Class D amplifier 64 on the right side of the speaker 66 have an approximate mode of operation. The Class D amplifier with H-bridge configuration operates in a normal mode of operation for those skilled in the art. Well known, will not repeat them here.

Referring to the sixth diagram, the output stages 322 and 322" are not yet driven by the corresponding drive circuit during a start-up time after the power supplies of the class D amplifiers 62 and 64. At this time, the bootstrap capacitors CBT and CBT 'will be charged by such high voltage The electrical circuits 3244 and 3244" are charged. The charging method can refer to the circuit diagrams shown in the fourth and fifth figures and the previous description. With the high voltage charging circuits 3244 and 3244", the bootstrap capacitors CBT and The CBT" can be charged to a sufficiently high voltage level to drive the corresponding upper bridge switch. After the bootstrap capacitors CBT and CBT" are fully charged, the output in the output stage 322 and the class D amplifier 64 in the class D amplifier 62 The stage 322" receives the signal of the corresponding drive circuit to enter the normal mode operation. Thereafter, the low voltage charging circuit 3242 in the shoe band capacitance charging circuit 324 and the low voltage charging circuit in the shoe band charging circuit 324" The 3242" will also charge the bootband capacitor CBT and the bootband capacitor CBT" respectively.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not to be construed as being limited by the scope of the invention, and

30‧‧‧Electronic devices

32‧‧‧Class D amplifier

322‧‧‧Output

324‧‧‧ Boots with capacitor charging circuit

3242‧‧‧Low voltage charging circuit

3244‧‧‧High voltage charging circuit

326,328‧‧‧ drive circuit

34‧‧‧Speakers

36‧‧‧voltage circuit

CBT‧‧‧ boots with capacitor

C3, C4, CL‧‧‧ capacitor

L1‧‧‧Inductance

MU, MD‧‧‧O crystal

Claims (7)

An electronic device includes: a first N-type transistor coupled between a power input terminal and a switching node, the power input terminal for receiving a second power source; and a second N-type transistor coupled Between the switching node and a grounding terminal; a bootband capacitor having a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor; a first charging circuit coupled to the upper terminal of the bootband capacitor, the first charging circuit charging the bootband capacitor by a first power source, and a second charging circuit comprising: a first a P-type transistor having a source terminal receiving the second power source, receiving a terminal of a bias current and a gate terminal coupled to the gate terminal of the second power supply; and a second P-type transistor having the receiving a source terminal of the second power source is coupled to a gate terminal of the gate terminal of the first P-type transistor; a clamping component having a first electrode coupled to a first terminal of the second P-type transistor a terminal and a second terminal coupled to the switching node; and a a first diode having an anode coupled to the anode terminal of the second P-type transistor and a cathode coupled to the upper terminal of the shoe capacitor; wherein the potential of the second power source is higher than The potential of the first power source. The electronic device of claim 1, wherein the second charging circuit uses a certain current to charge the bootband capacitor. The electronic device of claim 2, wherein the first charging circuit comprises: a voltage stabilizing circuit for generating the first power source; and a second diode having an anode for receiving the first power source and A cathode coupled to the upper terminal of the bootband capacitor. The electronic device of claim 3, wherein the second charging circuit further comprises: a third P-type transistor having a source terminal receiving the second power source coupled to the first P-type transistor a gate terminal of the gate terminal; and an N-type transistor having a terminal end receiving a drain of the third P-type transistor and a gate directly connected to the gate terminal of the second P-type transistor Extremely; wherein the anode of the first diode is directly connected to the 汲 terminal of the N-type transistor. The electronic device according to claim 1 or 4, further comprising: an inductor coupled to the switching node; an output capacitor coupled between the inductor and a ground; a voltage dividing circuit, a potential difference between the second power source and the ground terminal; and a speaker coupled between the inductor and the voltage dividing circuit. The electronic device of claim 5, wherein the clamping component is a Zener diode, and a reverse collapse voltage value of the Zener diode is selected as a potential of the first power source and the first diode The sum of the forward bias values. The electronic device of claim 5, wherein the clamping component is a Zener diode, and a reverse collapse voltage value of the Zener diode is selected as a potential of the first power source, the first diode The sum of the forward bias value and the gate-source potential difference of the N-type transistor in the second charging circuit.