TWI575564B - Method for manufacturing semiconductor structures - Google Patents

Description

Semiconductor structure manufacturing method

The invention relates to a method of fabricating a semiconductor structure.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a Fin Field effect transistor (FinFET) component replaces a planar transistor component.

Since the process of the FinFET device can be integrated with the conventional logic device process, it has considerable process compatibility. More importantly, since the three-dimensional structure of the FinFET element increases the contact area between the gate and the fin-shaped base body, the gate control of the gate region can be increased, thereby reducing the source-induced surface of the small-sized component. The drain induced barrier lowering (DIBL) effect and the short channel effect. In addition, since the gate of the same length in the FinFET element has a larger channel width, a doubled drain drive current can be obtained.

Although FinFET components can achieve higher drain drive currents, FinFET components still face many problems to be solved. For example, process control is extremely difficult due to the long profile characteristics of the fin structure. So how to get improved process control Degrees and the acquisition of fin structures with the desired profile have been the goal of the semiconductor industry.

Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor structure that solves the above problems.

According to the patent application scope provided by the present invention, a method for fabricating a semiconductor structure is provided. The fabrication method first provides a substrate, and the substrate includes a plurality of mandrel patterns and a plurality of dummy patterns. ). Then, a plurality of first sidewalls are formed on sidewalls of the axial patterns, and a plurality of second sidewalls are formed on sidewalls of the dummy patterns. After forming the first sidewalls and the second sidewalls, the second sidewalls are removed and the axial patterns are removed, and a plurality of sidewall sub-patterns are formed on the substrate.

According to the patent application scope provided by the present invention, a method for fabricating a semiconductor structure is provided. The fabrication method first provides a substrate comprising a plurality of axial patterns and a plurality of dummy patterns. Next, a plurality of insulating patterns are formed on the substrate, and the insulating patterns cover portions of the respective axial patterns. After the insulating patterns are to be formed, an etching process is performed to remove the insulating patterns on the top of each of the core patterns. Finally, the axial patterns are removed to form a plurality of sidewall sub-patterns on the substrate.

According to the method for fabricating a semiconductor structure provided by the present invention, a sidewall image transfer (SIT) method is used to form the sidewall sub-patterns on the substrate before forming the fin structure to define the fin structure. It is worth noting that since the sidewall sub-pattern is formed, it has been specially made to have non-continuous The sidewall pattern of the outline prevents the excessively long fin structure from collapsing during the process when the fin structure is fabricated. Briefly, the semiconductor structure fabrication method provided by the present invention can effectively improve the process control without increasing the difficulty of the process, and obtain a good profile conforming to the desired fin structure.

100‧‧‧Base

102‧‧‧hard mask layer

104‧‧‧Insulation

110‧‧‧Axis pattern

112‧‧‧First side wall

114‧‧‧ segment pattern

116‧‧‧ interval

118‧‧‧Side wall sub-pattern

120‧‧‧Dummy design

122‧‧‧Second side wall

130, 132, 134‧‧ ‧ protective layer

136‧‧‧Insulation pattern

140‧‧‧Fin structure

A-A’‧‧‧ cut line

1A to 5 are schematic views showing a first preferred embodiment of a method for fabricating a semiconductor structure according to the present invention, wherein FIG. 1B to FIG. 4B are respectively along the first A to FIG. -A' section line diagram obtained.

1A to 2B, 4A to 5, and 6A to 7 are schematic views of a second preferred embodiment of a method of fabricating a semiconductor structure provided by the present invention, wherein The figure is a schematic cross-sectional view taken along line A-A' in Figure 6A.

1A to 1B, 4A to 5, and 8A to 10B are schematic views of a third preferred embodiment of a method of fabricating a semiconductor structure provided by the present invention, wherein 8B Fig. 10B is a schematic cross-sectional view taken along line A-A' in Figs. 8A and 10A, respectively.

1A to 1B, 4A to 5, and 11A to 12B are schematic views of a fourth preferred embodiment of a method of fabricating a semiconductor structure provided by the present invention, wherein 11B Fig. 12B is a schematic cross-sectional view taken along line A-A' in Fig. 11A and Fig. 12A, respectively.

Please refer to FIG. 1A to FIG. 5 . FIG. 1A to FIG. 5 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor structure according to the present invention, wherein FIGS. 1B to 4B are respectively Obtained along the line A-A' in Figures 1A to 4A Schematic diagram of the section. As shown in FIGS. 1A and 1B, the preferred embodiment first provides a substrate 100 which may comprise a silicon-on-insulator (SOI) substrate, as is known to those skilled in the art. The SOI substrate may sequentially include a substrate, a bottom oxide (BOX) layer, and a semiconductor layer formed on the bottom oxide layer, such as a germanium layer having a single crystal structure. In addition, the substrate provided in the preferred embodiment may comprise a bulk silicon substrate. Next, a hard mask layer 102 is formed on the substrate 100. In the preferred embodiment, the hard mask layer 102 comprises a composite film layer, which may be a composite film layer of a hafnium oxide layer/tantalum nitride layer/yttria layer, but is not limited thereto.

Please continue to refer to Figures 1A and 1B. Next, a plurality of axial patterns 110 and a plurality of dummy patterns 120 are formed on the substrate 100. The axial patterns 110 and the dummy patterns 120 may include a polycrystalline germanium material, but are not limited thereto. The spacing between the axis pattern 110 and the axis pattern 110 can be used to define the distance of the fin structure to be formed; and the dummy pattern 120 is used to reduce the micro-loading effect when defining the fin structure. ). Those skilled in the art should be aware that the size, relative position and arrangement of the axis pattern 110 and the dummy pattern 120 in FIG. 1A are merely exemplary and are not limited thereto. After the axial pattern 110 and the dummy pattern 120 are formed on the substrate 100, a material layer such as an insulating layer 104 is formed on the substrate 100, such as an atomic layer deposition silicon nitride (ALD-SiN). ) layer, but is not limited to this. However, those skilled in the art will recognize that any suitable material having an etch rate different from the axial pattern 110 and the axial pattern 110 can be used as the material layer provided by the preferred embodiment. As shown in FIGS. 1A and 1B, the insulating layer 104 covers the axis pattern 110 and the dummy pattern 120.

Next, please refer to Figures 2A and 2B. Next, etch back insulation The layer 104 is, for example, subjected to a suitable dry etching process to form a plurality of first sidewalls 112 on sidewalls of the core pattern 110; and a plurality of second sidewalls 122 are formed on sidewalls of the dummy pattern 120.

Please refer to Figures 3A and 3B. After the first sidewall sub-112 and the second sidewall sub-122 are formed, a protective layer 130 is formed on the substrate 100. It should be noted that the protective layer 130 covers a portion of the axial pattern 110 and a portion of the first sidewall sub-112, but the protective layer 130 exposes all of the dummy patterns 120 and all of the second sidewalls 122. Subsequently, an etching process is performed to remove the exposed partial core pattern 110, a portion of the first sidewall spacers 112, all of the dummy patterns 120, and all of the second sidewall spacers 122. In other words, the present embodiment cuts the axis pattern 110 and the first sidewall sub 112 while removing the dummy pattern 120 and the second sidewall sub-122 to form a plurality of section patterns 114, and each part A gap 116 is further formed between the segment patterns 114, that is, the segment patterns 114 are separated from each other by the interval 116.

Please refer to Figures 4A and 4B. After the second sidewall sub-122 is removed, the dummy pattern 120 is removed, and the cutting axis pattern 110 and the first sidewall sub-112 are removed, the protective layer 130 is removed, and then all the segment patterns 114 are removed. The core pattern 110 is formed on the substrate 100 to form a plurality of sidewall sub-patterns 118, and the sidewall sub-patterns 118 are used to define the position and size of the fin structure. And as shown in FIG. 4A, after the core pattern 110 is removed, a space 116 remains between the sidewall sub-patterns 118 of the same column.

Please refer to Figure 5. After the sidewall sub-pattern 118 is formed, the hard mask layer 102 is patterned using the sidewall sub-pattern 118 as a mask to define the location and size of the fin structure. The substrate 100 is then patterned through the hard mask layer 102, and the substrate is A plurality of semiconductor structures, i.e., desired fin structures 140, are formed over 100.

According to the manufacturing method of the semiconductor structure provided by the preferred embodiment, when the unnecessary dummy pattern 120 and the second sidewall sub-122 are removed, the axis pattern 110 and the first sidewall sub-112 are simultaneously cut. Therefore, after removing the axis pattern 110 to which the first sidewall sub-112 is attached, the sidewall sub-pattern 118 is the shape of the fin structure to be formed, and the subsequently formed sidewall sub-pattern 118 and the fin structure can be avoided. 140 Because the outline is too long, it is easy to collapse. Therefore, the manufacturing method of the semiconductor structure provided by the preferred embodiment can effectively improve the process control and obtain a well-defined fin structure.

Please refer to FIGS. 1A to 2B, FIGS. 4A to 5, and FIGS. 6A to 7 . The above drawings are a second preferred embodiment of the method for fabricating the semiconductor structure provided by the present invention. A schematic diagram of a cross-sectional view taken along line A-A' in Fig. 6A is shown in Fig. 6B. It is to be noted that the constituent elements in the second preferred embodiment that are identical to the first preferred embodiment are denoted by the same reference numerals and may include the same materials, and the details are not described herein again. In addition, the steps described in the second preferred embodiment are performed in the steps shown in FIGS. 1A to 2B. That is, the preferred embodiment also provides a substrate 100 on which a hard surface is formed. Mask layer 102. Then, as shown in FIGS. 1A and 1B, a plurality of axial patterns 110 and a plurality of dummy patterns 120 are formed on the substrate 100. Next, as shown in FIGS. 2A and 2B, a plurality of first sidewall spacers 112 are formed on sidewalls of the core pattern 110, and a plurality of second sidewall spacers 122 are formed on sidewalls of the dummy pattern 120.

Please refer to Figures 6A and 6B. After the first sidewall sub-112 and the second sidewall sub-122 are formed, a protective layer 132 is formed on the substrate 100. worth taking note of That is, the protective layer 132 covers a portion of the axial pattern 110 and a portion of the first sidewall sub-112, but the protective layer 132 exposes all of the dummy patterns 120 and all of the second sidewalls 122. Subsequently, an etching process is performed to remove the exposed portion of the first sidewall 112 and all of the second sidewalls 122. In other words, the present embodiment cuts the first sidewall sub-112 while removing the second sidewall sub-122 to form a space 116 between the first sidewall sub-112s. Subsequently, the protective layer 132 is removed, and as shown in FIG. 7, the substrate 100 has a dummy pattern 120, a core pattern 110, and a first sidewall 112 separated by a space 116.

Please refer to Figures 4A and 4B again. After the protective layer 132 is removed, all the axial patterns 110 and the dummy patterns 120 on the substrate 100 are simultaneously removed, and a plurality of sidewall sub-patterns 118 are formed on the substrate 100, and the sidewall sub-patterns 118 are used to define the fins. The location and size of the structure. And as shown in FIG. 4A, after the core pattern 110 is removed, a space 116 remains between the sidewall sub-patterns 118 of the same column. Please refer to Figure 5. After the sidewall sub-pattern 118 is formed, the hard mask layer 102 is patterned using the sidewall sub-pattern 118 as a mask to define the location and size of the fin structure. The substrate 100 is then patterned through the hard mask layer 102, and a plurality of semiconductor structures, namely the desired fin structures 140, are formed on the substrate 100.

According to the method of fabricating the semiconductor structure provided by the preferred embodiment, another time for cutting the first sidewall sub-112 is provided: when the unnecessary second sidewall sub-122 is removed, the first sidewall sub-112 is simultaneously cut. Therefore, after removing the axis pattern 110 to which the first sidewall sub-112 is attached, the sidewall sub-pattern 118 is the shape of the fin structure to be formed, and the subsequently formed sidewall sub-pattern 118 and the fin structure can be avoided. 140 Because the outline is too long, it is easy to collapse. Therefore, the manufacturing method of the semiconductor structure provided by the preferred embodiment can also effectively improve the process control and obtain a good contour. Fin structure.

Please refer to FIGS. 1A to 1B, 4A to 5, and 8A to 10B. The above drawings are a third preferred embodiment of the method for fabricating the semiconductor structure provided by the present invention. FIG. 8B and FIG. 10B are schematic cross-sectional views taken along the line A-A′ in FIGS. 8A and 10A. It is to be noted that the constituent elements in the third preferred embodiment that are identical to the above-described preferred embodiments are denoted by the same reference numerals and may include the same materials, and the details are not described herein. In addition, the steps described in the third preferred embodiment are performed in the steps shown in FIG. 1A to FIG. 1B. That is, the preferred embodiment also provides a substrate 100 on which a hard surface is formed. Mask layer 102. Then, as shown in FIG. 1A and FIG. 1B, a plurality of axial patterns 110 and a plurality of dummy patterns 120 are formed on the substrate 100, and then a cover axis pattern 110 and a dummy pattern 120 are formed on the substrate 100. A layer of material such as, but not limited to, an insulating layer 104.

Please refer to Figures 8A through 9. After the insulating layer 104 is formed, a protective layer 134 is formed on the substrate 100. It should be noted that the position formed by the protective layer 134 corresponds to the axis pattern 110, and the protective layers 134 of the same column are separated from each other by the space 116. Subsequently, an etching process is performed to remove the exposed portion of the insulating layer 104 to form a plurality of insulating patterns 136 on the substrate 100. The protective layer 134 is then removed, and an insulating pattern 136 as shown in FIG. 9 is obtained on the substrate 100. The insulating pattern 136 covers a portion of each of the core patterns 110, and the insulating patterns 136 of the same column are separated from each other by the space 116.

Please refer to Figures 10A and 10B. After the insulating pattern 136 is formed, an etching process is performed to remove the insulating pattern 136 on the top of each of the core patterns 110. A plurality of first sidewalls 112 are formed on sidewalls of the respective axis patterns 110. As shown in FIG. 10A, each of the first side walls 112 in the same column is separated from each other by a space 116.

Please refer to Figures 4A and 4B again. After the first sidewall sub-112 is formed, all the axial patterns 110 and the dummy patterns 120 on the substrate 100 are simultaneously removed, and a plurality of sidewall sub-patterns 118 are formed on the substrate 100, and the sidewall sub-patterns 118 are used to define the fins. The position and size of the sheet structure. And as shown in FIG. 4A, after the core pattern 110 is removed, a space 116 remains between the sidewall sub-patterns 118 of the same column. Please refer to Figure 5. After the sidewall sub-pattern 118 is formed, the hard mask layer 102 is patterned using the sidewall sub-pattern 118 as a mask to define the location and size of the fin structure. The substrate 100 is then patterned through the hard mask layer 102, and a plurality of semiconductor structures, namely the desired fin structures 140, are formed on the substrate 100.

According to the method of fabricating the semiconductor structure provided by the preferred embodiment, another time for cutting the first sidewall 112 is provided: while the first sidewall 112 is being formed, that is, the first sidewall 112 is cut to form a space 116. Therefore, after removing the axis pattern 110 to which the first sidewall sub-112 is attached, the sidewall sub-pattern 140 is the shape of the fin structure to be formed, and the subsequently formed sidewall sub-pattern 118 and the fin structure can be avoided. 140 Because the outline is too long, it is easy to collapse. Therefore, the manufacturing method of the semiconductor structure provided by the preferred embodiment can also effectively improve the process control and obtain a well-defined fin structure.

Please refer to FIGS. 1A to 1B, 4A to 5, and 11A to 12B. The above drawings are a fourth preferred embodiment of the method for fabricating the semiconductor structure provided by the present invention. Schematic diagram of Figure 11B and Figure 12B It is a schematic cross-sectional view taken along line A-A' in the 11A and 12A drawings. It is to be noted that the constituent elements in the fourth preferred embodiment that are the same as the above-described preferred embodiments are denoted by the same reference numerals and may include the same materials, and the details are not described herein again. The steps described in the fourth preferred embodiment are continued from the steps shown in FIGS. 1A to 1B. That is, the preferred embodiment also provides a substrate 100 on which a hard surface is formed. Mask layer 102. Then, as shown in FIG. 1A and FIG. 1B, a plurality of axial patterns 110 and a plurality of dummy patterns 120 are formed on the substrate 100, and then a cover axis pattern 110 and a dummy pattern 120 are formed on the substrate 100. A layer of material such as, but not limited to, an insulating layer 104.

Please refer to Figures 11A and 11B. After the insulating layer 104 is formed, a protective layer 134 is formed on the substrate 100. It should be noted that the protective layer 134 is formed at a position corresponding to the axis pattern 110, and the protective layers 134 of the same column are separated from each other by the space 116. More importantly, in the present embodiment, the protective layer 134 exposes all of the dummy patterns 120. Subsequently, an etching process is performed to remove the exposed portion of the insulating layer 104 while removing all of the dummy patterns 120 exposed, and a plurality of insulating patterns 136 are formed on the substrate 100.

Please refer to Figures 12A and 12B. After the insulating pattern 136 is formed, an etching process is performed to remove the insulating patterns 136 on the top of each of the core patterns 110, and a plurality of first sidewalls 112 are formed on the sidewalls of the respective axis patterns 110, respectively. As shown in FIG. 12A, each of the first side walls 112 in the same column is separated from each other by a space 116.

Please refer to Figures 4A and 4B again. After forming the first sidewall sub-112, all the axial patterns 110 on the substrate 100 are removed, and the substrate 100 is formed. A plurality of sidewall sub-patterns 118 are formed, and the sidewall sub-patterns 118 are used to define the position and size of the fin structure. And as shown in FIG. 4A, after the core pattern 110 is removed, a space 116 remains between the sidewall sub-patterns 118 of the same column. Please refer to Figure 5. After the sidewall sub-pattern 118 is formed, the hard mask layer 102 is patterned using the sidewall sub-pattern 118 as a mask to define the location and size of the fin structure. The substrate 100 is then patterned through the hard mask layer 102, and a plurality of semiconductor structures, namely the desired fin structures 140, are formed on the substrate 100.

According to the method of fabricating the semiconductor structure provided by the preferred embodiment, the first sidewall spacers 112 are formed, that is, the first sidewall spacers 112 are cut to form the spaces 116 and the unnecessary dummy patterns 120 are removed.

In summary, according to the method for fabricating a semiconductor structure provided by the present invention, a sidewall image transfer (SIT) method is used to form the sidewall sub-patterns on the substrate before forming the fin structure for defining Fin structure. It should be noted that in forming the sidewall sub-pattern, the present invention provides at least three different time points: while removing the axis pattern and the dummy pattern, while removing the second sidewall, and making the first sidewall At the same time, the first sidewall is cut to create a sidewall sub-pattern with a discontinuous profile, so that the too long fin structure collapses during the process when the fin structure is fabricated. Briefly, the method for fabricating a semiconductor structure according to the present invention has great process flexibility and can effectively improve process control without increasing the difficulty of the process, and at the same time obtain a fin with good contour and desired appearance. Slice structure.

100‧‧‧Base

102‧‧‧hard mask layer

110‧‧‧Axis pattern

112‧‧‧First side wall

114‧‧‧ segment pattern

116‧‧‧ interval

130‧‧‧Protective layer

A-A’‧‧‧ cut line

Claims (19)

A method for fabricating a semiconductor structure, comprising: providing a substrate comprising a plurality of mandrel patterns and a plurality of dummy patterns; forming a plurality of sidewalls on the sidewalls of the axes a sidewall, at the same time forming a plurality of second sidewalls on sidewalls of the dummy patterns; removing the second sidewalls; and removing the axial patterns to form a plurality of sidewall sub-patterns on the substrate. The method for fabricating a semiconductor structure according to claim 1, further comprising removing the dummy patterns while removing the second sidewalls. The method for fabricating a semiconductor structure according to claim 2, further comprising: cutting the second sidewalls and the dummy patterns while cutting the axial patterns and the first sidewalls to form A plurality of section patterns. The method of fabricating a semiconductor structure according to claim 3, wherein a gap is formed between the segment patterns. The method of fabricating a semiconductor structure according to claim 4, wherein the spacers are left between the sidewall sub-patterns after removing the axial patterns. The method of fabricating a semiconductor structure according to claim 3, wherein the steps of removing the second sidewalls, removing the dummy patterns, and cutting the axial patterns and the first sidewalls are performed, The system is performed before the axis pattern is removed. The method for fabricating a semiconductor structure according to claim 1, further comprising removing the dummy patterns while removing the axial patterns. The method of fabricating the semiconductor structure of claim 7, further comprising cutting the first sidewalls while removing the second sidewalls. The method for fabricating a semiconductor structure according to claim 8 of the patent application, wherein the A space is formed between the side walls. The method of fabricating a semiconductor structure according to claim 9, wherein the spacers are disposed between the sidewall sub-patterns after removing the axial patterns and the dummy patterns. The method of fabricating a semiconductor structure according to claim 8, wherein the step of simultaneously removing the second sidewalls and cutting the axial patterns and the first sidewalls is performed to remove the equiaxes The heart pattern is preceded by the dummy pattern. The method of fabricating a semiconductor structure according to claim 1, wherein a hard mask layer is further formed between the sidewall sub-pattern and the substrate. The method of fabricating a semiconductor structure according to claim 12, further comprising patterning the hard mask layer and the substrate through the sidewall sub-patterns to form a plurality of semiconductor structures. A method for fabricating a semiconductor structure, comprising: providing a substrate on which a plurality of axial patterns and a plurality of dummy patterns are formed; forming a plurality of insulating patterns on the substrate, the insulating patterns covering portions of the axes a pattern of hearts, and a space is formed between the insulating patterns; an etching process is performed to remove the insulating patterns on top of each of the axis patterns; and the axis patterns are removed to form on the substrate a plurality of sidewall sub-patterns; and removing the dummy patterns, the spacers being retained between the sidewall sub-patterns after removing the equiaxive patterns and the dummy patterns. The method for fabricating a semiconductor structure according to claim 14, further comprising: forming an insulating layer on the substrate, wherein the insulating layer covers the axial pattern and the dummy patterns; and removing a portion of the insulating layer Layers to form the insulating patterns. The method for fabricating a semiconductor structure according to claim 15 of the patent application, wherein The insulating patterns expose the dummy patterns, and the dummy patterns and the axial patterns are simultaneously removed after the etch back process. The method of fabricating a semiconductor structure according to claim 15, wherein the step of removing the dummy patterns is performed simultaneously with the step of removing a portion of the insulating layer. The method of fabricating a semiconductor structure according to claim 14, wherein a hard mask layer is further formed between the sidewall sub-pattern and the substrate. The method of fabricating a semiconductor structure according to claim 18, further comprising patterning the hard mask layer and the substrate through the sidewall sub-patterns to form a plurality of semiconductor structures.