TWI566404B - Semiconductor integrated device - Google Patents

Description

Semiconductor integrated device

The present invention relates to a semiconductor integrated device, and more particularly to a semiconductor integrated device including a Fin Field Effect Transistor (FinFET) device and a protective structure.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a FinFET component replaces a planar transistor component.

The conventional FinFET device firstly etches a layer of a substrate surface by etching or the like to form a fin-shaped germanium film (not shown) in the substrate, and forms an insulating layer covering the germanium film on the germanium film. a layer, and then forming a gate covering a portion of the insulating layer and a portion of the germanium film, and finally forming a source in the fin-shaped germanium film not covered by the gate by an ion implantation process and a tempering process Bungee jumping. Since the process of the FinFET device can be integrated with the conventional logic device process, it has considerable process compatibility. In addition, when the FinFET element is placed on a silicon-on-insulator (SOI) substrate, conventional isolation techniques such as shallow trench isolation can be omitted. More importantly, since the three-dimensional structure of the FinFET element increases the contact area between the gate and the fin-shaped base body, the gate control of the gate region can be increased, thereby reducing the source-induced surface of the small-sized component. Energy band reduction (drain The induced barrier lowering (DIBL) effect and the short channel effect. In addition, since the gate of the same length in the FinFET element has a larger channel width, a doubled drain drive current can be obtained.

Although FinFET components can achieve higher drain drive currents, FinFET components still face many problems to be solved. For example, the fin structure of a FinFET element is very susceptible to physical or electrical external forces due to its long profile characteristics, or even damage due to the above external force. Therefore, the fin structure of the FinFET element always requires an effective protection structure.

Accordingly, it is an object of the present invention to provide an integrated device that includes a semiconductor component and that can effectively protect the semiconductor component.

According to the scope of the invention provided by the present invention, there is provided a semiconductor integrated device comprising a substrate, a plurality of active fins, and a plurality of first protective fins. At least one active area is defined on the substrate, the active fins are disposed in the active area, and the first protection fins surround the active area, and the active fins and the first protection fins Both extend in a first direction.

According to the patent application scope of the present invention, there is further provided a semiconductor integration device comprising a substrate, a plurality of active fins, and a plurality of protective fin frames. At least one active area is defined on the substrate, and the active fins are disposed in the active area, and the protection fin frames surround the active area.

According to the semiconductor integrated device of the present invention, the active fins for constructing the semiconductor component are disposed in the active region, and the first protective fins surrounding the active region are disposed outside the active region or Protect the fin frame. With the arrangement of the first protection fins and the protection fin frames, the active fins in the active region can be prevented from being affected by physical or electrical external forces.

100, 200, 300, 400‧‧‧ base

102, 202, 302, 402‧‧‧ active areas

104, 204, 304, 404‧‧‧ surrounding areas

110, 310a, 310b‧‧‧ axis pattern

112‧‧‧Side wall sub-pattern

114, 214, 216, 444 ‧ ‧ gap

140, 240, 340, 440‧‧‧ active fins

142, 242‧‧‧ first protection fins

244‧‧‧Second protection fins

342, 442‧‧‧protection fin frame

442a‧‧‧ innermost protection fin frame

444‧‧‧ gap

150, 250, 350, 450‧ ‧ reinforced structure

160, 260, 360, 460‧‧ ‧ gate layer, contact plug, or elongated contact window

D1‧‧‧ first direction

D2‧‧‧ second direction

1 to 4 are schematic views showing a first preferred embodiment of a semiconductor integrated device according to the present invention.

Figure 5 is a schematic illustration of a variation of one of the first preferred embodiments.

Figure 6 is a schematic view showing a second preferred embodiment of a semiconductor integrated device according to the present invention.

Figure 7 is a schematic illustration of a variation of one of the second preferred embodiments.

8 to 9 are schematic views showing a third preferred embodiment of a semiconductor integrated device according to the present invention.

Figure 10 is a schematic illustration of a variation of one of the third preferred embodiments.

Figure 11 is a fourth preferred embodiment of a semiconductor integrated device provided by the present invention.

Figure 12 is a schematic illustration of a variation of one of the fourth preferred embodiments.

Please refer to FIG. 1 to FIG. 4 . FIG. 1 to FIG. 4 are schematic diagrams showing a first preferred embodiment of a semiconductor integrated device according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100. The substrate 100 can comprise a silicon-on-insulator (SOI) substrate. As is known to those skilled in the art, the SOI substrate is comprised of The bottom up can include a substrate and a bottom oxide (BOX) in sequence. a layer, and a semiconductor layer formed on the bottom oxide layer, such as a germanium layer having a single crystal structure. In addition, the substrate provided in the preferred embodiment may comprise a bulk silicon substrate. An active area 102 and a peripheral area 104 surrounding the active area 102 are defined on the substrate 100. It should be understood by those skilled in the art that although the peripheral region 104 surrounds the active region 102 in the preferred embodiment, the relative relationship and size of the peripheral region 104 and the active region 102 may vary according to different product requirements, and thus are not limited thereto. this. In addition, a hard mask layer (not shown) is formed on the substrate 100. In the preferred embodiment, the hard mask layer comprises a composite film layer, which may be a composite film layer of a hafnium oxide layer/tantalum nitride layer/yttria layer, but is not limited thereto. Please continue to see Figure 1. Next, a plurality of axial patterns 110 are formed on the hard mask layer, and the axial pattern 110 may include a polycrystalline germanium material, but is not limited thereto. It should be noted that certain axial patterns 110 may extend across the peripheral region 104 and the active region 102 as shown in FIG.

Please refer to Figure 2. After the core pattern 110 is formed on the substrate 100, a material layer such as an insulating layer (not shown) is integrally formed on the substrate 100, such as but not limited to an atomic layer deposition (ALD) or A silicon nitride (SiN) layer formed by chemical vapor deposition (CVD). Those skilled in the art will appreciate that any suitable material having an etch rate other than the axial pattern 110 can be used as the material layer provided by the preferred embodiment. Next, the material layer is etched back to form a plurality of sidewall sub-patterns 112 on the sidewalls of the respective core patterns 110.

Please refer to Figure 3. After the sidewall sub-pattern 112 is formed, an etching process is performed to remove the core pattern 110. It should be noted that, in the preferred embodiment, a portion of the sidewall sub-pattern 112, particularly the sidewalls at the ends of the end of the axis pattern 110, may be removed before, during, or after the etching process. Pattern 112. more Importantly, the preferred embodiment cuts the sidewall sub-pattern 112 across the active region 102 and the peripheral region 104 before, during or after the etching process, and forms a gap between the partial sidewall sub-patterns 112. 114. As shown in FIG. 3, a void 114 is formed between the active region 102 and the peripheral region 104 for separating the sidewall sub-pattern 112 that originally spans the active region 102 and the peripheral region 104.

Please refer to Figure 4. After the sidewall sub-pattern 112 and the voids 114 are formed, the sidewall sub-pattern 112 is used as a mask to pattern the hard mask layer to define the location and size of the fin structure. A patterned hard mask is then used as an etch mask to etch the substrate 100, and a plurality of fin structures are formed on the substrate 100. After forming the fin structure, the patterned hard mask can be retained or removed as desired. It should be noted that the fin structure formed in the active region 102 can be used as the source/drain of the FinFET component, so the fin structure in the active region 102 is the active fin 140, and the active fin The sheet 140 extends in a first direction D1 as shown in FIG. More notably, the fin structures formed in the peripheral region 104 can serve as a protective structure for the FinFET component or even the active region 102, and thus the fin structures are the first protective fins 142. The first protection fin 142 surrounds the active region 102 as shown in FIG. 4, and the first protection fin 142 also extends in the first direction D1. More importantly, the voids 114 originally formed between the sidewall sub-patterns 112 are also transferred between the fin structures. Therefore, the active fins 140 and the first protective fins 142 disposed in the same column are separated from each other by the gap 114. More importantly, the gap 114 separates the active fins 140 in the active region 102 from the first protective fins 142 in the peripheral region 104 to prevent the first protective fins 142 from affecting the characteristics of the active fins 140 and the components. Actual electrical performance. After the active fins 140 and the first protective fins 142 are formed, the components in the active region 102 can be fabricated, such as a gate dielectric layer, a gate layer, a lightly doped drain, and a gate sidewall. , source/drain, etc., to form at least one FinFET Transistor element (not shown). In addition, those skilled in the art should be aware of metal gate process, selective epitaxial growth (SEG) process, metal telluride process, inner dielectric layer, contact plug, multilayer interconnect process, etc. , can be integrated into the FinFET transistor component process as needed, and will not be repeated here.

Please refer to FIG. 5, which is a schematic diagram of a variation of the preferred embodiment. According to the present variation, a plurality of reinforcing structures 150 may be further disposed on the first protective fins 142 in the peripheral region 104 while forming the constituent elements in the active region 102. As shown in FIG. 5, in the present modification, the gate layer 160 is formed in the active region 102, and the reinforcing structure 150 is formed on the first protective fin 142 in the peripheral region 104, so that the reinforcing structure 150 is formed. A semiconductor material such as polysilicon can be included. In addition, those skilled in the art should be aware that the relationship between the gate layer 160 and the active fins 140 in the active region 102 is merely an example. The gate layer 160 can span more or fewer active fins 140 depending on product requirements. And different gate layers 160 can span different active fins 140. Alternatively, in this variation, a first guard fin in the peripheral region 104 may be formed when a metal gate, a contact plug, or a long contact 160 is formed in the active region 102. The reinforcing structure 150 is formed on the sheet 142, so the reinforcing structure 150 may comprise a metallic material. Similarly, the relationship between the metal gate, the contact plug or the elongated contact window 160 and the active fins 140 may also differ from that shown in FIG. 5 depending on the product requirements. It should be noted that the reinforcing structure 150 is perpendicular to the first protection fin 142 and electrically connected to the first protection fins 142 of different columns as shown in FIG. 5, so the first protection fin 142 and the reinforcement structure 150 An orthogonal grid pattern can be formed to further strengthen the structural strength of the first protective fin 142. In addition, when the metal interconnection process in the active region 102 is performed subsequently, the metal layer connected to the body and the electrical connection is formed on the reinforcement structure 150 in the peripheral region 104 at the same time (but with the metal interconnection in the active region 102). Electrically separated) to further strengthen the structural strength of the first protective fin 142.

According to the semiconductor integrated device provided by the preferred embodiment and the variation thereof, the active fins 140 for constructing the semiconductor elements are disposed in the active region 102, and the first protection surrounding the active regions 102 is disposed outside the active region 102. Fin 142 and reinforcing structure 150. By providing the first protective fin 142 and the reinforcing structure 150 as a guard ring providing an electrical isolation or a seal ring providing stress isolation, the active fins in the active region 102 are avoided. 142 is affected by physical or electrical external forces. In addition, since the first protection fin 142 and the active fin 140 are simultaneously formed, and the reinforcement structure 150 can be formed simultaneously with other components such as a gate layer or a metal layer of the contact plug, the preferred embodiment can be The protective structure required for the active fins 140 is successfully provided without increasing the complexity of the process.

Please refer to FIG. 6. FIG. 6 is a schematic view showing a second preferred embodiment of a semiconductor integrated device according to the present invention. It should be noted that, in the second preferred embodiment, the manufacturing steps of the protective structure are the same as those of the first preferred embodiment, and the manufacturing steps are not illustrated. As shown in Fig. 6, the preferred embodiment provides a substrate 200, such as an SOI substrate or a block substrate. An active area 202 and a peripheral area 204 surrounding the active area 202 are defined on the substrate 200. As described above, although the peripheral region 204 surrounds the active region 202 in the preferred embodiment, the relative relationship between the peripheral region 204 and the active region 202 may vary according to different product requirements, and thus is not limited thereto. In addition, a hard mask layer (not shown) is formed on the substrate 200. Next, a plurality of axial patterns (not shown) are formed on the hard mask layer, and then a plurality of sidewall sub-patterns (not shown) are formed on the sidewalls of the respective axial patterns.

Please continue to see Figure 6. After the sidewall sub-pattern is formed, an etching process is performed to remove the axis pattern. It should be noted that the preferred embodiment can be etched here. Before, during or after the process, part of the sidewall sub-pattern is removed, especially the sidewall sub-pattern at the ends of the axis and the end of the axis. In addition, the preferred embodiment cuts the axial pattern and the sidewall sub-pattern across the active region 202 and the peripheral region 204 before, during or after the etching process, and forms a gap between the partial sidewall sub-patterns.

Please still refer to Figure 6. After the sidewall sub-patterns and voids are formed, the sidewall sub-pattern is used as a mask to pattern the hard mask layer to define the location and size of the fin structure. A patterned hard mask is then used as the etch mask to etch the substrate 200, and a plurality of fin structures are formed on the substrate 200. After forming the fin structure, the patterned hard mask can be retained or removed as desired. As described above, the fin structure formed in the active region 202 is the active fin 240, and the active fin 240 extends in a first direction D1 as shown in FIG. More notably, the preferred embodiment forms a plurality of first protection fins 242 and a plurality of second protection fins 244 in the peripheral region 204. The first protection fins 242 extend along the first direction D1 and are arranged along a second direction D2; and the second protection fins 244 extend along the second direction D2 and are arranged along the first direction D1. The first direction D1 is different from the second direction D2. In the preferred embodiment, the first direction D1 and the second direction D2 are perpendicular to each other, but are not limited thereto. Therefore, the first protection fins 242 are disposed on opposite sides of the active region 202 as shown in FIG. 6 , and the second protection fins 244 are disposed on the opposite sides of the active region 202 . That is to say, the first protection fin 242 and the second protection fin 244 surround the active region 202 to provide a protection function. In addition, as previously described, the voids originally formed between the sidewall sub-patterns are also transferred between the fin structures. Therefore, the active fins 240 and the first protective fins 242 disposed in the same column are separated from each other by a gap 214, respectively. In addition, the active fins 240 and the second protective fins in the active region 202 are also separated from each other by the gap 216, respectively. In other words, the void 214 and the void 216 are separated from the active fins 240 and the first protective fins 242 / the second protective fins 244 in the peripheral region 204 in the active region 202 to avoid The first protection fin 242 and the second protection fin 244 affect the characteristics of the active fin 240 and the actual electrical performance of the component. Next, fabrication of the constituent elements in the active area 202 can be performed.

Please refer to FIG. 7, which is a schematic diagram of a variation of the preferred embodiment. According to the variation, at least one reinforcing structure 250 may be further disposed on the first protection fin 242 and the second protection fin 244 in the peripheral region 204 while forming the constituent elements in the active region 202. As shown in FIG. 7, in the present variation, the gate layer 260 is formed in the active region 202, and the first protective fin 242 and the second protective fin 244 in the peripheral region 204 are formed with a reinforcing structure. 250, the reinforcement structure 250 can comprise a semiconductor material such as polysilicon. In addition, those skilled in the art will appreciate that the relationship between the gate layer 260 and the active fins 240 in the active region 202 is merely exemplary. The gate layer 260 may span more or fewer active fins 240 depending on product requirements. And different gate layers 260 can span different active fins 240. Alternatively, in the present variation, the first protection fin 242 and the second protection fin in the peripheral region 204 may be formed when the metal gate, the contact plug or the elongated contact window 260 is formed in the active region 202. The reinforcing structure 250 is formed on 244, so the reinforcing structure 250 may comprise a metallic material. Similarly, the relationship between the metal gate, the contact plug or the elongated contact window 260 and the active fin 240 may also differ from that shown in FIG. 7 depending on the product requirements. It should be noted that the reinforcing structure 250 is perpendicular to the first protection fin 242 and the second protection fin 244 as shown in FIG. 7 and all the first protection fins 242 and the second protection in the peripheral region 204. The fins 244 are all electrically connected together and further strengthen the structural strength of the first protection fin 242 and the second protection fin 244 to provide better protection of the active fins 240. In addition, in the subsequent metal interconnect process in the active region 202, a metal layer physically and electrically connected to the reinforcing structure 250 in the peripheral region 204 can be formed simultaneously (but with the metal in the active region 202). Wire electrical separation) to strengthen the first protection fin 242 and the structural strength of the second protective fin 244.

According to the semiconductor integrated device provided by the preferred embodiment and its variant, the active fin 240 for constructing the semiconductor component is disposed in the active region 202, and the first protection surrounding the active region 202 is disposed outside the active region 202. Fin 242, second protective fin 244, and reinforcing structure 250. The arrangement of the first protection fin 242, the second protection fin 244 and the reinforcing structure 250 can be used as a protective ring for providing electrical isolation or a sealing ring for providing stress isolation, so that the active fins in the active region 202 can be avoided. The sheet 240 is affected by physical or electrical external forces. As described above, since the first protection fin 242, the second protection fin 244, and the active fin 240 are simultaneously formed, the reinforcement structure 250 can be simultaneously with other components such as a gate layer or a metal layer of the contact plug. Formed, the preferred embodiment can successfully provide the protection structure required for the active fins 240 without increasing the complexity of the process.

Please refer to FIG. 8 to FIG. 9 . FIG. 8 to FIG. 9 are a third preferred embodiment of a semiconductor integrated device according to the present invention. As shown in FIG. 8, the preferred embodiment provides a substrate 300 having an active region 302 and a peripheral region 304 surrounding the active region 302. As described above, in the preferred embodiment, the peripheral area 304 surrounds the active area 302, but the relative relationship between the peripheral area 304 and the active area 302 may vary according to different product requirements, and is not limited thereto. In addition, a hard mask layer (not shown) is formed on the substrate 300. Please continue to see Figure 8. Next, a plurality of axial patterns 310a/310b are formed on the hard mask layer, and the axial patterns 310a/310b may include a polycrystalline germanium material, but are not limited thereto. It should be noted that, in the preferred embodiment, the axial pattern 310a disposed in the active region 302 is different from the axial pattern 310b disposed in the peripheral region 304: as shown in FIG. The axial pattern 310a in the region 302 can be formed according to the needs of the actual product. In the active region 302; however, the axial pattern 310b in the peripheral region 304 is disposed in the peripheral region 304 in a frame shape surrounding and sealing the active region 302.

Please refer to Figure 9. After the axis patterns 310a/310b are formed on the substrate 300, a material layer having an etching rate different from that of the axis patterns 310a/310b is formed on the substrate 300 in a comprehensive manner. Next, the material layer is etched back to form a plurality of sidewall sub-patterns (not shown) on the sidewalls of the respective axis patterns 310a/310b. And, after the sidewall sub-pattern is formed, an etching process is performed to remove the axis pattern 310a/310b. It should be noted that the preferred embodiment may remove portions of the sidewall sub-patterns, particularly the sidewall sub-patterns at the ends of the axial and vertical patterns 310a of the active region 302, before, during or after the etching process. The sidewall sub-pattern is then used as a mask to pattern the hard mask layer to define the location and size of the fin structure. A patterned hard mask is then used as an etch mask to etch the substrate 300, and a plurality of fin structures are formed on the substrate 300. And after forming the fin structure, the patterned hard mask can be retained or removed as desired by the product. It should be noted that the fin structure formed in the active region 302 is the active fin 340, and the active fin 340 extends in a first direction D1 as shown in FIG. More notably, the fin structure formed in the peripheral region 304 can serve as a protective structure for the FinFET component or even the active region 302, and these fin structures become the protection fin frame 342 along with the frame-shaped axial pattern 310a. . As shown in FIG. 9, the protective fin frame 342 surrounds and seals the active region 302, and each of the protective fin frames 342 is in a concentric arrangement. In addition, the protective fin frame 342 is physically and electrically separated from the active fins 340 to avoid affecting the characteristics of the active fins 140 in the active region 302 and the actual electrical performance of the components. Next, fabrication of the constituent elements in the active area 302 can be performed.

Please refer to FIG. 10, which is a schematic diagram of a variation of the preferred embodiment. According to the variation, while the constituent elements in the active region 302 are fabricated, A plurality of reinforcing structures 350 may also be disposed on the protective fin frame 342 in the peripheral region 304. As shown in FIG. 10, in the present variation, the gate layer 360 is formed in the active region 302, and the reinforcing structure 350 is formed on the protective fin frame 342 in the peripheral region 304. Therefore, the reinforcing structure 350 may include Semiconductor materials such as polysilicon. In addition, those skilled in the art will appreciate that the relationship between the gate layer 360 and the active fins 340 in the active region 302 is merely exemplary, and the gate layer 360 can span more or fewer active fins 340 depending on product requirements. And different gate layers 360 can span different active fins 340. Alternatively, in the present variation, when the metal gate, the contact plug or the elongated contact window 360 is formed in the active region 302, the reinforcing structure 350 is formed on the protective fin frame 342 in the peripheral region 304. The reinforcement structure 350 can comprise a metallic material. Similarly, the relationship between the metal gate, the contact plug or the elongated contact window 360 and the active fin 340 may also differ from that shown in FIG. 10 depending on the product requirements. It should be noted that the reinforcing structure 350 is perpendicular to the protection fin frame 342 as shown in FIG. 10, and all the protective fin frames 342 disposed concentrically in the peripheral region 304 are electrically connected together. The structural strength of the protection fin frame 342 is further enhanced to provide better protection of the active fins 340. In addition, when performing the metal interconnect process in the subsequent active region 302, a metal layer physically and electrically connected to the reinforcing structure 350 in the peripheral region 204 may be formed simultaneously (but with the metal in the active region 202). The wiring is electrically separated) to further strengthen the structural strength of the fin frame 342.

According to the semiconductor integrated device provided by the preferred embodiment and the variation thereof, the active fins 340 for constructing the semiconductor elements are disposed in the active region 302, and the protection of the surrounding and sealing active regions 302 is provided outside the active region 302. Fin frame 342 and reinforcing structure 350. By protecting the arrangement of the fin frame 342 and the reinforcing structure 350, it can be used as a protective ring for providing electrical isolation or a stress-isolated sealing ring to prevent the active active fins 340 in the active region 302 from being physically or electrically External force shadow ring. In addition, as described above, since the protective fin frame 342 and the active fin 340 are simultaneously formed, and the reinforcing structure 350 can be formed simultaneously with other components such as a gate layer or a metal layer of the contact plug, the present preferred embodiment The system can successfully provide the protection structure required for the active fins 340 without increasing the complexity of the process.

Please refer to FIG. 11. FIG. 11 is a schematic view showing a fourth preferred embodiment of a semiconductor integrated device according to the present invention. It should be noted that, in the fourth preferred embodiment, the manufacturing steps of the protective structure are the same as those of the third preferred embodiment, and the manufacturing steps are not illustrated. As shown in Fig. 11, the preferred embodiment provides a substrate 400, such as an SOI substrate or a block substrate. An active area 402 and a peripheral area 404 surrounding the active area 402 are defined on the substrate 400. As described above, in the preferred embodiment, the peripheral area 404 surrounds the active area 402, but the relative relationship between the peripheral area 404 and the active area 402 may vary according to different product requirements, and thus is not limited thereto. In addition, a hard mask layer (not shown) is formed on the substrate 400. Next, a plurality of axial patterns (not shown) are formed on the hard mask layer. It should be noted that in the preferred embodiment, the axial pattern disposed in the active region 402 is different from the axial pattern disposed in the peripheral region 404. The preferred embodiment is the same as the third preferred embodiment. The axial pattern in the active region 402 can be formed in the active region 402 according to actual product requirements; however, the axial pattern in the peripheral region 404 is surrounded by And the frame of the sealing active area 402 is disposed in the peripheral area 404.

Please continue to see Figure 11. After the axis pattern is formed on the substrate 400, a plurality of sidewall sub-patterns (not shown) are formed on the sidewalls of the respective axis patterns. And after forming the sidewall sub-pattern, an etching process is performed to remove the axis pattern. It should be noted that the preferred embodiment may remove portions of the sidewall sub-pattern before, during, or after the etching process, especially the sidewalls at both ends of the axis pattern in the active region 402. a pattern, and a portion of at least one sidewall sub-pattern within the perimeter region 402. The sidewall sub-pattern is then used as a mask to pattern the hard mask layer to define the location and size of the fin structure. A patterned hard mask is used as an etch mask to etch the substrate 400, and a plurality of fin structures are formed on the substrate 400. After forming the fin structure, the patterned hard mask can be retained or removed as desired.

It should be noted that the fin structure formed in the active region 402 is the active fin 440, and the active fin 440 extends in a first direction D1 as shown in FIG. More notably, the fin structure formed in the peripheral region 404 can serve as a protective structure for the FinFET component or even the active region 402, and these fin structures become the protection fin frame 442 with the frame-like axial pattern. As shown in FIG. 11, the protective fin frame 442 surrounds the active region 402, and each of the protective fin frames 442 is in a concentric arrangement. In addition, the protective fin frame 442 is physically separated from the active fins 440 to avoid affecting the active regions 402 to avoid affecting the characteristics of the active fins 440 and the actual electrical performance of the components. More importantly, in the preferred embodiment, in addition to the innermost protective fin frame 442a, the other protective fin frame 442 further includes a plurality of voids 444 formed in the protective fin frame 442 and cut. The protective fin frame 442 is broken. As shown in Fig. 11, each of the voids 444 corresponds to the side wall of the adjacent protective fin frame 442 to form a labyrinth pattern. Subsequently, fabrication of the various constituent elements in the active area 402 can be performed.

Please refer to FIG. 12, which is a schematic diagram of a variation of the preferred embodiment. According to this variation, a plurality of reinforcing structures 450 may be further disposed in the protective fin frame 442 in the peripheral region 404 while forming the constituent elements in the active region 402. As shown in FIG. 12, in the present variation, the gate layer 460 is formed in the active region 402, and a plurality of reinforcing structures 450 are formed in the protective fin frame 442 in the peripheral region 404. A semiconductor material such as polysilicon can be included. another In addition, those skilled in the art will appreciate that the relationship between the gate layer 460 and the active fins 440 in the active region 402 is merely exemplary. The gate layer 460 can span more or fewer active fins 440 depending on product requirements. And different gate layers 460 can span different active fins 440. Alternatively, in the present variation, when a metal gate, a contact plug or an elongated contact window 460 is formed in the active region 402, a plurality of reinforcing structures 450 are formed in the protective fin frame 442 in the peripheral region 404. Therefore, the reinforcing structure 450 may comprise a metal material. Similarly, the relationship between the metal gate, the contact plug or the elongated contact window 460 and the active fin 440 may also differ from that shown in FIG. 12 depending on the product requirements. It should be noted that the reinforcing structure 450 fills the gap 444 of each of the protective fin frames 442 as shown in FIG. In addition, the reinforcing structure 450 can also physically and electrically electrically connect the protective fin frames 442 disposed in the peripheral region 404 while filling the gap 444, and further strengthen the protection fin frame 442. Structural strength to provide better protection of the active fins 440. When the metal interconnect process in the active region 402 is performed, a metal layer that is physically and electrically connected to the reinforcing structure 450 in the peripheral region 404 can be formed simultaneously (but with the metal interconnect in the active region 402). Separate) to further enhance the structural strength of the fin frame 442.

According to the semiconductor integrated device provided by the preferred embodiment of the present invention, the active fins 440 for constructing the semiconductor elements are disposed in the active region 402, and the protective fins 442 surrounding the active regions 402 are disposed outside the active region 402. Reinforced structure 450. By protecting the arrangement of the fin frame 442 and the reinforcing structure 450, it can be used as a protective ring for providing electrical isolation or a stress-isolated sealing ring to prevent the active fins 440 in the active region 402 from being physically or electrically External influence. In addition, as described above, since the protective fin frame 442 and the active fin 440 are simultaneously formed, and the reinforcing structure 450 can be formed simultaneously with other components such as a gate layer or a metal layer of the contact plug, the present preferred embodiment The system can successfully provide initiative without increasing the complexity of the process. The protective structure required for the fins 440.

According to the semiconductor integrated device provided by the present invention, a active fin for constructing a semiconductor component is disposed in an active region, and a protective fin surrounding the active region or the protective fin frame is disposed outside the active region as a power supply. Separate guard ring or seal ring that provides stress isolation. In other words, by protecting the arrangement of the fins and the protection fin frame, it is possible to prevent the active fins and the functionally functional components in the active region from being affected by physical or electrical external forces.

100‧‧‧Base

102‧‧‧Active area

104‧‧‧The surrounding area

114‧‧‧ gap

140‧‧‧Active fins

142‧‧‧First protection fins

D1‧‧‧ first direction

Claims (20)

A semiconductor integration device includes: a substrate having at least one active region defined thereon; a plurality of active fins disposed in the active region, and the active fins extending along a first direction And a plurality of first protection fins surrounding the active area, and the first protection fins extend along the first direction. The semiconductor integrated device of claim 1, wherein the active fins and the first protective fins disposed in the same column are separated from each other by a gap. The semiconductor integration device of claim 1, further comprising a plurality of reinforcing structures disposed on the first protection fin. The semiconductor integrated device of claim 3, wherein the reinforcing structures are perpendicular to the first protective fins and are connected to the first protective fins. The semiconductor integrated device of claim 3, wherein the reinforcing structures comprise a semiconductor material or a metal material. The semiconductor integrated device of claim 1, further comprising a plurality of second protection fins disposed on the substrate, the second protection fins extending along a second direction, and the second direction Different from the first direction. The semiconductor integrated device according to claim 6, wherein the first A protection fin is disposed on opposite sides of the active area, and the second protection fins are disposed on opposite sides of the active area. The semiconductor integrated device of claim 6, further comprising at least one reinforcing structure disposed on the first protection fins and the second protection fins. The semiconductor integrated device of claim 8, wherein the reinforcing structure is perpendicular to the first protective fins and the second protective fins. The semiconductor integrated device of claim 8, wherein the reinforcing structure comprises a semiconductor material or a metal material. A semiconductor integration device includes: a substrate having at least one active region defined thereon; a plurality of active fins disposed in the active region; and a plurality of protective fin frames surrounding the active region . The semiconductor integrated device of claim 11, wherein the protective fin frames are in a concentric arrangement. The semiconductor integrated device of claim 11, further comprising a plurality of reinforcing structures disposed on the protective fin frames. The semiconductor integrated device of claim 13, wherein the reinforcing structures are connected to the protective fin frames. The semiconductor integrated device of claim 13, wherein the semiconductor integrated device The reinforced structure is perpendicular to the protective fin frames. The semiconductor integrated device of claim 13, wherein the reinforcing structures comprise a semiconductor material or a metal material. The semiconductor integrated device of claim 11, further comprising a plurality of voids disposed in each of the protective fin frames and cutting each of the protective fin frames. The semiconductor integrated device of claim 17, wherein each of the voids corresponds to a sidewall of the adjacent protective fin frame. The semiconductor integration device of claim 17, further comprising a plurality of reinforcing structures, and the reinforcing structures respectively fill the spaces. The semiconductor integrated device of claim 19, wherein the reinforcing structures comprise a semiconductor material or a metal material.