TWI574258B - Memory devices, systems and methods employing command/address calibration - Google Patents

Description

Memory device, system and method using command/address calibration

The inventive concept relates to a memory device, system and method, and more particularly to command/address calibration.

This application claims the US Provisional Application No. 61/468,204 filed on March 28, 2011 in the U.S. Patent and Trademark Office and the application of the Korean Intellectual Property Office on June 23, 2011. The priority of the Korean Patent Application, the entire disclosure of which is hereby incorporated by reference.

In a memory system (for example, a dynamic random access memory (DRAM) system), a signal is transmitted and received via a bus between a memory controller and a DRAM to experience propagation delay. Propagation delay can be affected by various factors, such as bus bars, a substrate, or such interconnect capacitors or parasitic capacitances. As one of the DRAM data rates increases, a variation in propagation delay and/or propagation delay degrades signal integrity. It is desirable to find an optimum signal window or signal skew between the compensation signals, such as between a data signal and a clock signal, between a command signal and a clock signal, and/or between an address signal and a clock signal.

The invention discloses a command/address calibration method and a memory device and a memory system using command/address calibration. According to one aspect of the inventive concept, a method of communicating with a memory device is provided, the method comprising transmitting a calibration command via a command/position bus; via the command/address The bus bar transmits a sequence of n first test signals, wherein n is equal to one integer greater than 2 or greater; and a clock signal is transmitted via a first clock line together with each of the n first test signals Each of the n first test signals is transmitted with respect to each of the first to nth phases of the one of the clock signals, each of the first to nth phases being different from each other Receiving, via a data bus, n second test signals from a sequence of n first test signals respectively transmitted through the sequence of the command/address bus; comparing the n first test signals with the n second test signals; and in response to the comparing the n first test signals and the received n second test signals, determining a signal to be transmitted via the command/address bus relative to the clock signal One of the preferred phases.

Each of the n first test signals includes a first plurality of bits transmitted in parallel via the command/address bus, the first plurality of bits may be followed by a parallel arrangement via the command/address bus The second plurality of bits sent.

Each of the first plurality of bits and the second plurality of bits may include a packet.

For each of the n first test signals, the first plurality of bits may be transmitted at one of a rising edge of the clock signal and one of the falling edges of the clock signal, and may be The second plurality of bits are transmitted by the rising edge of the clock signal and the falling edge of the clock signal.

At least a portion of the n second test signals of the sequence may be received via a data strobe line or via a line dedicated to calibration during at least one calibration mode.

The method can further include whether each of the second test signals is identical to a corresponding first test signal.

The preferred phase may be determined to correspond to one of the first through nth phases.

Determining the preferred phase may be derived from determining a phase sequence of one of the first to nth phases, each phase of the phase sequence corresponding to a second test signal determined to be valid.

According to another aspect, an interface training method can include: transmitting a first calibration signal to a semiconductor device via a command/address bus; transmitting a clock signal to the first calibration signal together with the transmission a semiconductor device, the clock signal providing a timing to the semiconductor device to latch a logic level of the first calibration signal; receiving a second calibration signal from the semiconductor device via a data bus, the second calibration signal being Deriving a latched logic level of the first calibration signal; transmitting the command and address signals to the first semiconductor device via the command/address bus with the transmission of the clock signal, the commands and bits A phase between the address signal and the clock signal is responsive to the second calibration signal.

The method can further include transmitting a read request signal to the semiconductor device via one of the first lines separated from the command/address bus while transmitting the first calibration signal.

The first line can be a clock enable line.

The first calibration signal can include a data packet of a sequence transmitted at a rate that is at least twice the rate of the period of the clock signal.

Transmitting a first calibration signal to the semiconductor device may include A training pattern is sent for each of a plurality of lines of the order/address bus.

The training pattern may be the same for each of the plurality of lines of the command/address bus.

The phase between the command and the address signal and the clock signal can be individually adjusted for each of the plurality of lines of the command/address bus.

A first signal may be transmitted via the first line of the command/address bus to transmit a first signal with respect to one of the clock signals, and may be via the command/address address of the second line of the bus bar relative to One of the clock signals transmits a second signal in a second phase.

When the semiconductor device is a first semiconductor device, the method can include transmitting a third calibration signal to a second semiconductor device via the command/address bus; along with the transmitting of the third calibration signal Transmitting a clock signal to the second semiconductor device, the clock signal providing a timing to the second semiconductor device to latch a logic level of the third calibration signal; receiving, via the data bus, a second semiconductor device a fourth calibration signal derived from the latched logic level of the third calibration signal; the command and the address signal are transmitted via the command/address bus with the transmission of the clock signal To the second semiconductor device, a phase between the command and the address signal and the clock signal is responsive to the fourth calibration signal.

According to another aspect, a method of calibrating communication via a command/address bus of a memory device can include receiving a clock signal via a clock signal line; receiving a calibration command via the command/address bus One of the rising edge of one of the clock signals and one of the falling edges of the clock signal Receiving, by the command/address bus, a first test data packet to generate first information; and transmitting the command at the other of the rising edge of the clock signal and the falling edge of the clock signal And the address bus receives a second test data packet to generate the second information; and transmits the first information and the second information via a data bus.

The method can include receiving a command and an address via the command/address bus at the rising and falling edges of the clock signal.

The invention also encompasses systems and devices. For example, a semiconductor device can include: a clock generator configured to generate a clock signal; a clock output terminal coupled to the clock generator and configured to output the clock signal; a command generator circuit configured to generate a command; an address generator circuit configured to generate an address; a plurality of command/address terminals; a command/address buffer having a connection to the And outputting one of the command/address terminals, the command/address buffer being coupled to the command generator circuit and the address generator circuit for transmitting commands and addresses from outside the semiconductor device via the command/address terminals a signal; a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the command/address bus, n being greater than one of two integers, the phase control The device is configured to adjust a phase of at least some of the n training patterns relative to one of the clock signals; a data terminal; and a data buffer coupled to the data terminals, wherein the phase Controller group In response to the adjustment command and address signal received via the first information of such information by the terminal in the data buffer with respect to the phase of one of the clock signal. The system can include such devices and/or implement such methods. The invention is not limited The features set forth in this summary, and the scope and applicability thereof will be apparent by reference to the following detailed description.

Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description of the invention.

Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings in which: FIG. The exemplary embodiments of the present invention are provided to more fully explain the inventive concepts to those skilled in the art. However, the invention may be embodied in different forms and should not be construed as being limited to the example embodiments set forth herein. That is, the exemplary embodiments are merely examples of their existence: numerous embodiments and variations that do not require the various details disclosed herein. Various changes can be made to the inventive concept, and the inventive concept can have various forms. However, the embodiments are not intended to limit the invention to the specific embodiments disclosed, and all such changes, equivalents and substitutions are included in the spirit and scope of the present invention. In all the figures, the same component symbols refer to the same components. In the accompanying drawings, the structure may have been exaggerated for clarity.

The terminology used herein is for the purpose of describing the embodiments, As used herein, the singular forms " It will be further understood that the phrase "comprising", "including" and / or "having" (and <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Other features, numbers, steps, exercises The presence or addition of a component, component, component or combination thereof unless otherwise stated.

It will be understood that when an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or the intervening element can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element is not present. As used herein, the phrase "and/or" includes any and all combinations of one or more of the associated listed items and can be abbreviated as "/".

It will be understood that, although the first, second, etc. may be used herein to describe various elements, such elements are not limited to such terms. These terms are only used to distinguish one element from another. For example, a first signal may be referred to as a second signal, and similarly, a second signal may be referred to as a first signal without departing from the teachings of the present disclosure.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the <RTIgt; It will be further understood that the wording (such as the term defined in a common dictionary) should be interpreted as having one meaning consistent with its meaning in the relevant technical context, and will not be interpreted in the sense of an idealized or overly formalized form. Unless explicitly stated otherwise in this document.

A high speed operation and low power consumption are desired from a semiconductor memory device. For example, one of the low power double data rate (LPDDR) specifications can be expected to satisfy dynamic random access memory (DRAM). An LPDDR DRAM system transmits and receives data bidirectionally between a DRAM and an external device (e.g., a memory controller) at both the rising and falling edges of a clock signal.

As one of the methods of accelerating memory operation, the command and address can be transmitted to a memory device (for example, a memory chip, for example, a DRAM non-NAND flash) at both the rising and falling edges of a clock signal. Memory chip). The memory device is configured to latch command and/or address information at both the rising and falling edges of the clock signal. A common signal for transmitting a command signal and an address signal is referred to as a command/address signal CMD/ADDR or CA. Pins, terminals, bus bars, internal conductors, or other signal paths for transmitting command/address signals may also be referred to herein using the acronym CA.

Figures 1 and 2 are timing diagrams illustrating one example of command/address calibration.

Referring to FIG. 1, the relative timing of a pair of clock signals (clock signal pair CK and CKB) and a plurality of command/address signals CMD/ADDR can be adjusted (together or individually) such that each command/address is made. The middle of the CMD/ADDR window is positioned to optimally clock an input operation of the memory device (eg, a latch operation). Figure 1 shows that the center portion of each command/address CMD/ADDR window has been adjusted to intersect the falling edge of the clock signal CK with the falling edge of the clock signal CK (or vice versa, ie, the pulse signal) The command/address signal CMD/ADDR of one of the timings when one of the rising edges of the CKB intersects the falling edge of the clock signal CK. The intersection may correspond to one of the time when the clock signals CK and CKB are equal to each other (eg, having the same voltage level 凖). Although Figure 1 shows only the command/address CMD/ADDR window for a command/address CMD/ADDR signal (eg, one of the conductors on a plurality of conductor CMD/ADDR bus bars), multiple commands/addresses CMD/ADDR Signals (eg, multiple command/address CMD/ADDR signals received on separate different command/address CMD/ADDR signal paths) may each be aligned as shown in FIG. 1, and are discussed below with each such Command/address CMD/ADDR signal correlation. The command/address signal timing is adjusted or matched to the rising/falling edges of the clock signals CK and CKB. Since the middle of the command/address CMD/ADDR window is at one of the intersections between the rising and falling edges of the clock signals CK and CKB, the command/address CMD can be maximized or otherwise improved. One of the /ADDR timing margins. Figure 1 illustrates the relative timing of one of the clock signals CK and CKB and the command/address signal CMD/ADDR as seen by the memory device receiving one of these signals. The clock signals CK and CKB and the command/address signals CMD/ADDR can be generated by an external source (for example, a memory controller, a CPU, a host computer, etc.), and the clock signal CK generated by the external source and The relative timing between the CKB and the command/address signal CMD/ADDR can be changed during transmission, and thus, the relative timing produced can be different from the relative timing experienced by the memory device (eg, relative timing generated by an external source) It can be different from the relative timing shown in Figure 1.

Due to changes between signal paths (eg, changes in layout, signal drive capability, etc.), during transmission of clock signals CK and CKB and command/address signals CMD/ADDR from an external source to a memory device, A propagation time difference is generated between the clock signals CK and CKB and the command/address signal CMD/ADDR. As shown in FIG. 2, the middle of the command/address CMD/ADDR window can be before or after the rising and falling edges of the clock signals CK and CKB, thereby reducing the timing margin of the command/address CMD/ADDR. .

In the four command/address signals CMD/ADDR (CA1, CA2, CA3, and CA4) shown in FIG. 2, for the first command/address signal CMD/ADDR CA1 and the second command/address signal CMD/ ADDR CA2, the timing of the clock signals CK and CKB can lag behind the window of the CA1 and CA2 signals. If the timing of the first command/address signal CMD/ADDR CA1 and the second command/address signal CMD/ADDR CA2 is postponed by calibration, the middle portion of each command/address CMD/ADDR window of CA1 and CA2 can be Positioned to correspond to an intersection between the rising and falling edges of the clock signals CK and CKB. When received by the memory device after this delay, the middle portion of each command/address CMD/ADDR window of CA1 and CA2 can occur on the rising/falling edges of CK and CKB. For the fourth command/address signal CMD/ADDR CA4, the timing of the delayed clock signals CK and CKB can be delayed by calibration or the timing of the fourth command/address signal CMD/ADDR CA4 can be advanced to make each command/ The middle of the address CMD/ADDR window is at a position corresponding to an intersection between the rising edge and the falling edge of the clock signals CK and CKB.

3 is a block diagram of one exemplary memory system 10 that performs command/address calibration.

Referring to FIG. 3, the memory system 10 includes a memory controller 20 and a memory device 30 with a clock signal line 11, a command/address bus 12 and a DQ bus 13 connected thereto. A clock signal CK generated by the memory controller 20 is supplied to the memory device 30 through the clock signal line 11. The clock signal CK can be provided as a continuous alternating inverted signal together with an inverted clock signal CKB. Inverted clock signal CKB can be connected to the clock signal The CK is provided together, that is, generated by the memory controller 20 and provided to the memory device 30 (not shown in Figure 3). The rising and falling edges of the clock signals CK and CKB can be detected based on the intersection between a pair of clock signals CK and CKB, thereby improving timing accuracy.

A single clock signal CK (non-transmission clock signal CKB) may also be supplied to the clock signal line 11 as a continuous alternating inverted signal. This embodiment reduces the signal lines (and terminals) between the memory device 30 and the memory controller 20. In this case, to identify the rising edge and the falling edge of the clock signal CK, the clock signal CK and a reference voltage Vref can be compared with each other. If noise fluctuation occurs in the reference voltage Vref, a shift occurs in the detection of the clock signal CK, thereby degrading the timing accuracy compared to using the clock signal pair CK and CKB. Therefore, it may be desirable to transmit complementary alternating inverted signals that are complementary to one another by using the clock signals pair CK and CKB. In this case, the clock signal line 11 may include two signal lines that transmit the clock signal CK and the pulse signal CKB. The clock signal CK set forth in the embodiment of the inventive concept can be described as a clock signal pair CK and CKB. For the sake of simplicity, the clock signals CK and CKB are described as the clock signal CK.

The command/address signal CA generated by the memory controller 20 is supplied to the memory device 30 through the command/address bus. The command/address bus 12 can carry a command signal or an address signal to the memory device 30 (exclusively at any time) and/or the command/address bus 12 can simultaneously transmit a command signal and a The address signal is carried to the memory device 30. The memory controller 20 can transmit a mode register register (MRS) command indicating a command/address calibration mode via the command/address bus. The MRS command can include a school The quasi-mode entry command and a calibration mode exit command. A calibration start signal may be transmitted through the command/address bus 12 indicating one of the calibration mode entry commands or one of the calibration mode exit commands.

When the command/address bus 12 is composed of command/address signals CA of n signal lines (for example, conductors) (where n is a natural number), and is input at the rising and falling edges of the clock signal CK. When the command/address signal CA (for example, the command/address signal CA is transmitted at a double data rate (DDR)), each clock cycle can be commanded by the command/address bus 12 by 2n bits/ The address CA information is supplied from the memory controller 20 to the memory device 30. Inputting one of the command/address signals CA at the rising edge of the clock signal CK and inputting one of the command/address signals CA at the falling edge of the clock signal CK may each constitute a command/address having n bits. Different groups of CA information.

In normal operation, the DQ bus 13 transmits a data signal DQ between the memory controller 20 and the memory device 30 (eg, in a write operation, the data signal DQ is transmitted from the controller to the memory device 30, And in a read operation, the data signal DQ is transmitted from the memory device 30 to the memory controller 20). Information regarding command/address calibration (described in further detail below) may be output on the DQ bus 13 for supply to the memory controller 20. The DQ bus 13 is connected to the DQ pads (and/or other device terminals, such as solder bumps) of both the memory controller 20 and the memory device 30. The mapping of the calibration command/address information signal and the DQ pad can be set in various ways.

For example, when the bit structure of the data signal DQ of the memory device 30 is x32 (DQ[31:0]), the number of DQ bus bars is 32. When the command/address bus is composed of 10 conductors and the command/address signal CA is in the clock When 10 bits are transmitted at both the rising edge and the falling edge of the number CK, the memory device 30 can receive the 20-bit command/address signal CA every clock cycle of the clock CK. Since the number 32 of DQ bus bars is greater than the number 20 of command/address signals, each DQ bus bar can correspond to a single bit in the command/address signal bit CA, thereby providing a single command/ Information of the address signal bits (eg, two DQ bus lines can transmit command/address information for command/address calibration of a single line in the command/address bus 12). Therefore, the mapping can be performed such that for each cycle of the clock signal CK, one of the command/address signals input at the rising edge of the clock signal CK is output to 10 DQ pads [9:0] and One value of the 10-bit command/address signal input at the falling edge of the clock signal CK is output to the other 10 DQ pads [19:10]. Therefore, although the command/address CA signal can be transmitted to the memory device 30 at a double data rate (DDR) (two sets of bits for each cycle of the clock CK), a single data rate (SDR) can be used. Information about command/address calibration is transmitted back to the memory controller 20 from the memory device 30 (for a set of bits for each cycle of the clock CK). Note that the DQ bus can transmit data relative to a clock different from the clock CK. Figure 5, discussed further below, shows one embodiment in which data is transmitted relative to a data strobe clock DQS.

When the bit signal organization of the data signal DQ of the memory device 30 is x16 (DQ[15:0]), the number of DQ bus bars is 16. Since the number 16 of DQ bus bars is less than the number 20 of command/address signal bits (received according to clock cycle CK), the DQ bus bar may not be sufficient for a command/bit during one cycle of clock CK. Address calibration information is transmitted as a set of bits lose. Therefore, the DQ bus 13 can transmit information about command/address calibration in sequence. For example, the DQ bus can transmit command/address calibration information about a 10-bit command/address signal input to the memory device 30 at the rising edge of the clock signal CK at a time (eg, in a DQ bus) Line DQ[0:9]), and later, transmit command/address calibration information about the 10-bit command/address signal input at the falling edge of the clock signal CK (eg, in the DQ bus Line DQ[0:9]).

4A and 4B are diagrams for illustrating command/address calibration that may be performed by the memory system 10 shown in FIG.

Referring to FIG. 4A and FIG. 4B, the memory controller 20 detects that the command/address signal CA window received by the memory device 30 is opposite to the edge of the clock signal CK (provided from the memory controller 20). Whether the location (or timing) is so such that the memory device 30 successfully interprets the command/address signal. 4A and 4B show several successful interpretations of the command/position signal as a pass (or P) and an unsuccessful interpretation of the command/address signal as a failure (F). 4A shows a plurality of cycles of transmission of a command/address signal along a single command/address line of a command/address bus. Each cycle of transmitting a calibration test pattern is adjusted by the controller to change the relative phase of the clock CK and the command/address signal compared to the previous transmission cycle. The examples of Figures 4A and 4B show that for each subsequent transmission cycle, this relative phase changes by 1/20 (e.g., 18 degrees) of a clock CK cycle. The relative phase of each transmission cycle can be changed more or less depending on the desired accuracy. Note that the relative phase of the clock CK and the command/address signal received by the memory device 30 for a particular transmission cycle can be correlated with the clock CK and the command/address signal transmitted by the controller. Different phases. Due to the different characteristics of the transmission of the clock signal CK and the signal line of the command address bus 12, the time from the transmission (from the controller 20) to the reception (by the memory device 30) may be different. These different characteristics may include differences in signal path length, conductivity of the signal path (eg, due to conductor size), parasitic capacitance of the signal path (eg, from adjacent lines), temperature, and the like. The memory controller 20 transmits the clock signal CK to the memory device 30 through the clock signal line 11 and transmits the command/address signal CA to the memory device 30 through one of the signal lines of the command/address bus. After receiving the phase adjusted command/address signal CA, the memory device 30 transmits the command/position signal CA interpreted by the memory device 30 to the memory controller 20 through the DQ bus 13 . The memory controller 20 detects which of the command/address signals have successfully transmitted their information to the memory device 30 (via or P) and which transmission cycles were unsuccessful (failed or F).

4A shows a clock signal (CK@Memory) and a plurality of command/address signals received by the memory device 30 via one of the command/address busses (received via several transmission cycles). In order to simplify and better emphasize the shifting of the relative phase of the command/address signal and the clock CK, the command/address signals are shown as vertical stacking in Figure 4A instead of in a continuous timing diagram. It should be noted that in this example, each of the CA@Memory signals shown in Figure 4A is received in chronological order (e.g., via the same signal line of the command/address bus bar CA). In FIG. 4B, when the edge of the clock signal CK is present at one of the positions S1 or S2 of the command/address signal CA, the memory device 30 may not be able to successfully interpret the command/address signal CA (eg, cannot be in the window) At the appropriate logic high or logic low of the latch command/address signal CA), and The memory controller 20 may determine that the transmission cycle associated with S1 and S2 is a failure F. When the edge of the pulse signal CK exists at a position S3, S4, S5, S6, S7, S8, S9, S10 or S11, the memory device can successfully interpret the command/address signal CA (for example, successfully locked) The appropriate logic high or logic low state of the command/address signal CA is stored, and the memory controller 20 may determine that the transmission cycle associated with S3, S4, S5, S6, S7, S8, S9, S10 or S11 is Pass P. When the edge of the clock signal CK is present at one of the positions S12 or S13 of the command/address signal CA, the memory controller 20 may determine that the transmission cycle associated with S12 or S13 is a failure F.

4A and 4B show that one of the timings of the clock CK (CK@Memory) received by the memory device 30 should have a timing such that one of the clock signals CK must be associated with the command/address to be latched. The logic of signal CA occurs simultaneously (eg, at the correct logic window of command/address signal CA). However, this representation is intended to be simple and not necessary. The timing of the edge of the clock signal CK may not need to be at the same time as the logic to be latched, but may, for example, be shifted in time. For example, one of the clocks other than CK may be responsible for triggering latching of the command/address signal CA by the memory device 30. For example, an internal clock ICK can be generated by the memory device 30 in response to the clock signal CK, and the internal clock ICK can be used by a buffer of the memory device 30 (eg, the CA receiver 304 in FIG. 5). The logic of the command/address signal CA on the CA bus 12 is latched at one of the rising edges or one falling edge of the ICK. Even if the externally received clock CK and the internally generated clock ICK have the same frequency and duty cycle (which may not be the case), CK and ICK may also shift in time. Therefore, the edge of the external clock CK may not be the command/bit to be latched. The logic of the address signal CA occurs simultaneously (e.g., alongside the window (before or after) of the logic high state 1 of the command/address signal CA that can be latched at the memory device 30. As another example, even when the edge of the clock CK is directly input to a buffer of the memory device 30 to trigger the latching of the signal input to the memory device, before the latching action is sufficient to latch the logic of the input signal There can be some delay.

The memory device 30 can transmit information about the command/address calibration to the controller 20 on the data bus DQ as described above. For example, the memory device 30 can transmit a signal interpreted (eg, latched) by the memory device 30 on the command/address signal line of the CA command/address bus. Therefore, during a calibration transmission cycle, if the memory controller transmits a 1 (eg, a logic high state) to the memory device on one of the signal lines of the command/address bus 12, the clock CK is opposite to the transmission. The phase causes the memory device 30 to trigger to latch the signal on the signal line outside of the appropriate signal window, and the memory device can inaccurately interpret the transmitted signal as a zero. However, the memory device can transmit a value of 0 via one of the signal lines of the DQ data bus. The memory controller 20 can determine that the transmission associated with the transmission cycle is unsuccessful and determines that the transmission is a failure F. In one subsequent transmission cycle during command/address calibration, the relative phase of the transmission of the clock CK and the command/address calibration signal (eg, 1) may be shifted such that the memory device 30 is triggered to indicate The signal line is latched in the signal window and this value 1 can be transferred to the memory controller 20 (as command/address calibration information). The memory controller 20 can therefore compare the command/address calibration signal transmitted to the memory device 30 with the command/address calibration information (value 1) received from the memory device 30 and determine The subsequent transmission cycle is successful (through P).

The memory controller 20 can analyze the transmission cycle group of command/address calibration to determine the clock CK and the command sent on the command/address signal line of the command/address CA signal during normal operation of the memory system 10 / A relative phase between the address signals. This optimal relative phase can be implemented by the memory controller 20 transmitting command and address information to the memory device 30 during normal operation. For example, the optimal relative phase can be determined by aggregating a determination of one of the transmission cycles through P and selecting one of the relative phases of the transmission cycle at the center of the group. For example, since the transmission cycles associated with S3, S4, S5, S6, S7, S8, S9, S10, and S11 are successful (via P) in FIGS. 4A and 4B, the memory controller 20 can The relative phase of the transmission cycle associated with S7 (between clock CK and command/address calibration signal) is selected as the optimum phase. Alternatively, memory controller 20 may select the optimum phase as one of the relative phases associated with the first and last successful transmission cycles (when the relative phase of each transmission cycle is ordered) (eg, 0 degrees, 15 degrees, 30 degrees, etc.)) - In the example of Figures 4A and 4B, this will be the average of the relative phases of the transmission cycles associated with S3 and S11. Alternatively, the memory controller 20 may select the optimum phase as one of the relative phases associated with the last and first unsuccessful transmission cycles sandwiching the successful transmission cycle (when each transmission cycle) When the relative phases are in order) - in the example of Figures 4A and 4B, this will be the average of the relative phases of the transmission cycles associated with S2 and S12. In this way, command/address calibration can be performed.

Although a single command/address signal CA has been set forth in the current embodiment Calibration of (on a single line of command/address CA bus 12), but this command/address calibration can be performed for multiple command/address signals CA transmitted over command/address bus 12. This calibration can be performed for all signal lines of the command/address bus 12 at the same time. The memory controller 20 can determine the best relative phase of each of the signal lines of the command/address bus 20 (eg, as explained above) and individually adjust the signal lines of the command/address bus 20 The relative phase of each of them.

Alternatively, the memory controller 20 can determine the best relative phase of one of the entire set of signal lines and select the same best phase for all of the signal line groups of the command/address bus. In selecting the same best relative phase for the entire signal line group, the memory controller 20 can determine a successful transmission cycle (via P) as all of the bits of the command/address calibration signal are from the memory device 30. One cycle of successful interpretation is performed and an unsuccessful transmission cycle (failure F) is determined as one of the cycles in which at least one of the bits of the command/address calibration signal is not successfully interpreted by the memory device 30. The optimal relative phase of the entire set of signal lines can be determined by analyzing the pass P of the transmission cycle and the F-Fail flag in a manner similar to that described above with respect to a single signal line of the command/address bus 12 .

In another alternative, the memory controller 20 can determine the best relative phase of one of the plurality of signal line groups that make up the command/address bus. The optimal relative phase of each of the plurality of signal line groups can be determined as set forth herein for determining the best relative phase of one of the entire set of signal lines constituting the command/address bus. The signal line group of the command/address bus 12 may include a group of adjacent signal lines (eg, where no command/address is placed) Other signal lines of the flow row 12).

In another alternative, the optimal relative phase can be determined only for a subset of the signal lines of the command/address bus 12 as explained above. That is, the command/address calibration signal may be transmitted by the controller only on a subset of the signal lines of the command/address bus 12 and/or the memory device 30 may transmit signal lines only for the command/address bus Command/address calibration information for one of the subgroups. The best relative phase can be determined for this subgroup of signal lines of the command/address bus. The remaining lines of the signal line of the command/address bus 12 may have one of the best phases determined based on the optimal relative phase for the signal line sub-group decision. This can be done, for example, by interpolating (and/or extrapolating) the optimal relative phase of the immediately adjacent signal lines (of the subset of signal lines) as an optimal relative phase. For example, if the command/address bus includes 10 signal lines (capable of transmitting 10 parallel information bits at a time), the odd lines (where the signal lines are positioned in the order of 1 to 10) may have as described with respect to FIG. 4A And one of the determined optimal relative phases as illustrated in FIG. 4B (a plurality of transmission cycles of the command/address calibration signal from the controller 20 to the memory device 30 and the command/address calibration information from the memory device 30 Send to memory controller 20). The even lines of the command/address bus 12 may have their best relative phase determined by the previously determined optimum relative phase of the adjacent odd lines of the interpolated command/address bus. Therefore, the signal line 2 of the command/address bus 12 can have an optimum relative phase which is determined as the average of the optimum relative phases of the signal lines 1 and 3. In addition to averaging the neighbors, other interpolations may be performed (eg, if signal lines 1, 2, and 3 are unevenly spaced or have some known length difference and/or the interpolation may include two Optimal relative phase determination of more than one odd signal line). class Similarly, signal line 4 may have its optimum relative phase as determined by averaging the optimum relative phase determined for signal lines 3 and 5 or interpolating the optimum relative phase for signal lines 3 and 5. Since the signal line 10 will not have two adjacent signal lines in this example, its optimum relative phase may be selected to be the same as the optimal relative phase of the signal line 9, or may be extrapolated from multiple odd signal lines ( For example, extrapolation from signal lines 7 and 9).

5 is a block diagram of one example of a memory system 10 that can be used to perform any of the command/address calibration embodiments set forth.

Referring to FIG. 5, the memory system 10 includes a memory controller 20 and a memory device 30. The memory controller 20 can include a clock generator 201, a command/address generator 202, a command/address transmitter 203 (which may be referred to as a CA transmitter hereinafter), a register 204, A comparator 206, a phase/timing controller 208 and an input/output unit 210.

The memory controller 20 supplies the clock signal CK generated from the clock generator 201 to the memory device 30 through the clock signal line 11. The command/address generator 202 generates an initial command/address signal CA0 and provides it to the CA transmitter 203.

CA 203 receives a transmission having a first phase p1 one initial command / address signal CA _sp1, and in response to a control signal CTRL 208 one phase / timing controller to adjust the initial command / address signal CA or one phase _sp1 The timing is to generate a command/address signal CA _sp2 having a phase adjustment of one of the second phases p2. The CA transmitter 203 can also be controlled by the control signal CTRL to substantially maintain the phase of the initial command/address signal CA such that the first phase p1 is substantially the same as the second phase p2 (for ease of interpretation, even in certain situations) Next, the initial command/address CA _sp1 signal may not have a phase adjustment, and the signal CA _{sp2 is} also referred to as a phase-adjusted command/address signal CA). The phase adjusted command/address signal CA _{sp2 is} sent to the register 204, and the information represented by the phase adjusted command/address signal CA _sp2 is stored in the register 204 as CA _s . The phase adjusted command/address signal CA _{sp2 is} provided to the memory device 30 via the command/address bus. The phase adjusted command/address signal CA _sp2 is provided to the memory device 30 along with the clock signal CK.

The register 204 stores the information of the phase adjusted command/address signal CA _sp2 as the transmitted command/address information CA _s . Comparing comparator 206 is stored in the register 204 by sending a command / address information CA _s command from the output of the input / output unit 210 of the received / calibrated address information CA _r (as set forth herein, by a memory The body device 30 receives and sends back to the memory controller 20). Comparator 204 compares information CA _s with information CA _r to generate a pass or fail signal P or F.

The phase/timing controller 208 generates a control signal CTRL indicating a phase shift of one of the initial command/address signals CA _sp1 based on the pass or fail information P or F generated by the comparator 206. The control signal CTRL is provided to the CA transmitter 203 and the phase or timing of the initial command/address signal CA _sp1 is adjusted to produce a phase adjusted command/address signal CA _sp2 .

In a normal operation mode, the data input/output unit 210 receives the read data R_Data1 transmitted from the memory device 30 through the DQ bus 13 or transmits the write data W_Data1 to be written to the memory device 30 through the DQ bus 13. . In addition, in the command/address (CA) calibration mode, the data input/output unit 210 can receive the phase-adjusted command/address corresponding to the phase received by the memory device 30 from the memory controller 20 via the DQ bus 13 Command/address calibration information CA _{r of} signal CA _sp2 . Command / address CA _r calibration information may be based upon a clock in the memory device 30 via the phase adjustment of the command / address signal CA _sp2 being transmitted to the memory device 30 in response to CK (e.g., when the clock signal CK Information that is latched in the case of rising edges and/or falling edges. When the timing of CK is such that the phase-adjusted command/address signal CA _sp2 is properly interpreted (or latched), CA _r may be the same information as CA _s or when memory device 30 incorrectly resolves The CA _r may be different from CA _s when translating the phase-adjusted command/address signal CA _sp2 . Data input / output unit 210 outputs the command / address signal CA _r information to the comparator 206.

The input/output unit 210 can include an input buffer 212, a selection unit 214, and an output buffer 216. Input buffer 212 and output buffer 216 may include latches and/or amplifiers to respectively latch and/or amplify the received signals. Input buffer 212 is connected to receive via DQ bus 13 from the data memory device 30 and transmit the command / address information calibrating CA _r. The selecting unit 214 transmits the data received by the input buffer 212 as the read data R_Data1 to the internal circuit block (not shown) of the memory controller 20 in response to a first selection signal SEL1 in the normal operation mode, and CA calibration mode in response to the first selection signal SEL1 and from the input buffer 212 receives the command / address CA _{R & lt} calibration information transmitted to the comparator 206. The selection unit 214 can be a multiplexer. Input buffer 212 can properly interpret the command / address information calibrating CA _r, DQ bus DQ 13 has been in a calibration mode before CA calibration calibration mode and / or the command / address information CA _{R & lt} calibration on the DQ bus The row 13 is transferred to the input buffer 212 at a slower rate to ensure that the information on the DQ bus 13 is latched at the correct window (eg, when the command/address calibration is at a double data rate (DDR) The slower transmission rate is at a single data rate (SDR). In this instances, the reception of the 13 DQ bus command / address CA _{R & lt} calibration information by the transmission data input / output unit 210 to the command comparator CA 206 / _{R & lt} same address CA calibration information. The output buffer 216 transmits the write data W_Data1 to be written to the memory device 30 through the DQ bus 13 .

The memory device 30 includes a clock buffer 302, a command/address receiver 304 (which will hereinafter be referred to as a CA receiver 304), and a data input/output unit 310. The clock buffer 302 receives the clock signal CK transmitted through the clock signal line 11 to generate an internal clock signal ICK. The phase adjusted command/address signal CA _{sp2 is} transmitted to the memory device 30 via the command/address bus. CA receiver 304 generates response command / address CA _{R & lt} calibration information in the internal clock signal ICK, which may occur when the signal CKE to be enabled by a chip select signal / CS and a clock enable. The wafer select signal /CS time pulse enable signal CKE may be provided separately from the command/address signal line 12, as in FIG. 5, or may be carried on the command/address signal line 12 for transmission to the memory 30, unlike Shown in Figure 5.

The clock enable signal CKE can be used as a pseudo command that acts as a read command for one of the phase adjusted commands/address signals CA _sp2 transmitted through the command/address bus 12 in the CA calibration mode. The CA receiver 304 is in accordance with a timing (e.g., a rising edge and/or a falling edge) of the ICK received based on the clock enable signal CKE in an active state and when the memory device 30 is enabled by the chip select signal /CS. The phase-tuned command/address signal CA _sp2 is latched to generate command/address calibration information CA _r . The command/address calibration information CA _{r is} supplied to the data input/output unit 310.

Data input / output unit 310 is connected to receive the command / address information CA _r and the internal calibration circuit block 30 from one of the memory device (e.g., coupled to read the data stored R_Data2 one data read path of memory array Circuitry (not shown) transmitting the read data R_Data2 and transmitting the received read data R_Data2 to the DQ bus 13 in response to a second select signal SEL2 in a normal read mode of operation, or in a calibration mode The second command/address signal CA2 is transmitted to the DQ bus 13 in response to the second selection signal SEL2. In a normal write mode, the data input/output unit 310 receives the write data W_Data1 to be written to the memory device 30 through the DQ bus 13 and transmits the received write data W_Data1 to the internal memory device 30. Circuit block. The data input/output unit 310 includes a selection unit 312, an output buffer 314, and an input buffer 316. According to the normal operation mode or the calibration mode, the selection unit 312 selects the second command/address signal CA2 output from the command/address receiver 304 and the internal circuit block provided from the memory device 30 in response to the second selection signal SEL2. One of the data R_Data2 is read and the selected signal or data is transmitted to the output buffer 314. The selection unit 312 can be a multiplexer.

Output from the buffer 314 to the selection unit 312 outputs the command / address CA _r calibration information transmitted to or read data DQ bus 13 R_Data2. The input buffer 316 receives the data transmitted through the DQ bus 13 and transmits the received data as the write data W_Data2 to the internal circuit block of the memory device 30. For example, the write data W_Data2 can be transferred to a memory array via the data write path circuit for writing into the memory array. The data write path circuit and the data read path circuit can share the circuit.

In the current embodiment, the command/address calibration information CA _r output from the output buffer 314 of the memory device 30 is supplied to the memory controller 20 through the DQ bus 13 . In addition, the command/address calibration information CA _r output from the output buffer 314 of the memory device 30 can be supplied to the memory controller 20 through a data strobe (DQS) line and a DQ bus 13 . The data input/output unit 210 of the memory controller 20 and the data input/output unit 310 of the memory device 30 can be connected to each other through the DQS line and the DQ bus bar 13.

The CA calibration in the memory system 10 can be performed as follows. The CA transmitter 203 of the memory controller 20 generates a command/address signal CA _sp2 by adjusting the phase or timing of the initial command/address signal CA _sp1 in response to the control signal CTRL of the phase/timing controller 208. The control signal CTRL can also have a value that maintains the phase of the command/address signal as previously described. The CA receiver 304 of the memory device 30 receives the phase adjusted command/address signal CA _sp2 to generate command/address calibration information according to one of the internal clock signals ICK and when enabled by the clock enable signal CKE. CA _r . The command/address calibration information CA _{r of the} memory device 30 is transmitted to the DQ bus 13 in response to the second selection signal SEL2. Prior to calibrating the command/address signal, one of the phase adjusted command/address signal CA _sp2 transmitted from the memory controller 20 and the command/address interpreted (eg, latched) by the memory device 30 One of the values of the calibration information CA _r may be different from each other, for example, due to noise generated during signal transmission and/or signal transmission timing changes between the clock CK and the signal transmitted by the CA bus 12 . The calibration command/address signal solves this problem.

In the command / address calibration mode, the memory controller 20 in response to the first selection signal SEL1 206 via the DQ bus 13 receives the command / address CA _r calibration information transmitted to the comparator. When the DQ bus DQ 13 calibrated in a calibration mode before CA calibration mode, the memory controller 20 incorrectly interpret the command / address CA _{R & lt} calibration information (e.g., interpreted by the input buffer 212) The chance is reduced. The comparator 206 compares one of the command/address signals CA _sp2 transmitted by the memory controller 20 to the memory device 30 and stored in the register 204 with the command/address calibration information CA received by the memory controller. _A value of _r , and a pass signal P is generated when the two values are identical to each other and a failure signal F is generated when the two values are different. The phase/timing controller 208 generates a new phase shift indicating one of the initial command/address signals CA _sp1 (to obtain a command/address signal CA _{sp2 having a} new phase adjustment of one of the new relative phase differences from the clock CK) The control signal CTRL is repeated and the process is repeated for a new initial command/address signal CA _sp1 having a different relative phase with respect to the clock CK. After multiple cycles of this process (each cycle having a different phase shift of one of the initial command/address signals CA _sp1 caused by the CA transmitter 203), the controller analyzes the group of P and failed F signals to determine normal The optimal relative phase of the operational CA signal line (or several lines or bus bars). Although not shown in FIG. 5, the control signal CTRL may be transmitted to the clock generator 201 to adjust the timing or phase of the clock signal CK to adjust the relative phase of the command/address signal and the clock signal CK.

By repeating the previous CA calibration, the phase/timing controller 208 of the memory controller 20 determines the input (eg, latch) for the command/address signal. The optimal timing of the middle portion of the command/address signal CA window (eg, through the middle of the P position) and a command/address signal CA is generated such that the middle of the command/address signal CA window corresponds to the memory The input of the body device 30 (which may correspond to one edge of the clock signal CK), and the generated command/address signal CA is pulsed with the optimal relative phase between the command/address signal CA and the clock CK. CK is supplied to the memory device 30. Therefore, when the timing of the input (e.g., latch) of the command/address signal corresponds to the edge of the clock signal CK received by the memory device 30, the memory device 30 receives the middle of the corresponding one for the effective window. The rising and falling edges of the pulse signal CK (strictly speaking) the command/address signal CA of the rising and falling edges of the clock signals CK and CKB.

Although calibration of a single command/address signal on a single line of command/address bus 12 has been illustrated, this calibration can be performed for a plurality or all of the command/address bus bars as previously described.

Figure 6 is a diagram for illustrating one example of an exemplary command/address calibration method. 6 is a timing diagram for explaining one of the command/address calibration methods that can be implemented in the memory system 10, wherein the bit structure of the data device DQ of the memory device 30 is x32 (the DQ bus is connected to the memory by the DQ bus system) 32 DQ terminals (eg, pads, bumps, etc.) of the body device 30 and 32 DQ signal lines of 32 DQ terminals of the memory controller 20 are included).

Referring to FIG. 6 in conjunction with FIG. 5, the memory controller 20 generates a clock signal CK for the memory device 30. The memory controller 20 sends an incoming command/address calibration mode command to the memory device 30. The memory controller 20 transmits an incoming command/address calibration mode command via the command/address bus. Entering the Command/Address Calibration Mode command can use a Mode Register Setting (MRS) The command format stylized memory device, one of the mode registers, is input to indicate a command/address calibration mode. The memory device 30 can enter the command/address calibration mode in response to the mode register setting information in response to the command/address calibration mode indication. The memory controller 20 can transmit a command/address end signal via the command/address bus. The command/address end signal can be entered using one of the MRS commands indicating that the self-calibration mode exits.

At time t ₀ , a command/address alignment start signal is received at the memory device via the command/address bus 12 together with the activation of one of the wafer low signal levels of the wafer select signal /CS. A rising edge of one of the clock signals CK received by the memory device 20 triggers a latch into the command/address calibration mode command. For example, a first mode register command (MRW#41) is transmitted as an incoming command/address calibration mode command. When a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#41 command may include a command to indicate that the command is a mode register setting command. The address signal CA[3:0] and the command/address signal CA[9:4] for instructing the mode register setting command to enter one of the command/address calibration modes.

In this example, the MRW #41 command is input at both the rising and falling edges of the clock signal CK; in Figure 6, the MRW #41 command is first remembered at time t0 in response to the rising edge of the clock CK. The body device latches and is latched a second time by the memory device 30 in response to the subsequent clock CK followed by the subsequent falling edge. That is, the same MRW #41 command is input at the rising edge and the falling edge of the clock signal CK corresponding to the start of the clock signal CK at time t ₀ . That is, since an MRS command is input at a double data rate (DDR) through a command/address signal line, an error can be generated such that one of the memory devices having a high operating frequency misses the MRS command. In addition, a different command can be erroneously interpreted as an incoming command/address calibration mode command. In order to reduce the possibility of error, the same MRW #41 command is input at the rising edge and the falling edge of the clock signal CK corresponding to the time t ₀ of the clock signal CK. That is, since the same command/address signal is input at the rising edge and the falling edge of the clock signal CK, a result similar to that transmitted at a single data rate (SDR) can be obtained, and can be reduced, especially yet. One of the entry calibration modes caused by the calibration command/address signal line failed (or, one of the calibration modes was not intentionally entered).

After a predetermined time elapses from time t ₀ when the MRW #41 command is first input, the clock enable signal CKE is started together with the start of the logic low state of the wafer select signal /CS (in Figure 6 at address/command) The calibration period is valid at a logic low level). At time t ₁ , the command/address address CAxR is transmitted by the memory controller 20 and received by the memory device 30, followed by transmission in the second half of the clock cycle (here the clock CK is followed by the subsequent edge) and Receive CAxF. The command/address signals CAxR and CAxF are transmitted from the memory controller 20 to the memory device 30 via the command/address bus. The time tMRW may be a mode register setting write cycle time to provide sufficient time for the memory device 30 to write the indication data to the mode register settings of the memory device 30.

In this example, the command/address signal CAxR constitutes a plurality of signals transmitted on all lines of the command/address bus 12 input at the rising edge of the clock signal CK, and the command/address signal CAxF is formed at the time. A plurality of signals transmitted on all lines of the command/address bus 12 input at the falling edge of the pulse signal CK. The pair of CAxR and CAxF may constitute a command/address test pattern signal that is transmitted to the memory device during command/address calibration to determine whether the memory device is properly interpreted by The information of the test pattern signal. In the example of FIG. 6, the test pattern (transmitted for each relative phase sequence) includes a sequence of two bits of each command/address signal line of the command/address bus 12 (command/address) Two logic windows for the calibration signal). However, the test pattern may include a sequence of one or more bits, or may include one bit (the description of FIGS. 4A and 4B may imply the transmission of the phase-adjusted command/address signal CA _sp2 ) One bit test pattern, however, the phase adjusted command/address signal CA _sp2 may be sent via one of each of the lines of the command/address bus 12 (or some) A bit, two bits, or a sequence of more than two bits). The command/address signal CAxR and the command/address signal CAxF input to the memory device 30 through the command/address bus 12 can represent different signals of different byte groups. For example, when the command/address bus 12 is composed of a 10-bit command/address signal CA[9:0], a 10-bit command/address signal CAxR and 10 bits can be used. The meta command/address signal CAxF is divided into different signals. Therefore, the command/address terminal (pin, pad, solder bump, etc.) (not shown) of the memory device 30 connected to the 10-bit command/address bus 12 can be 20 bits. The command/address calibration signal CA[9:0] is input to the memory device 30. The memory device 30 can input (eg, latch) a command/address from one of the timings of the edge of the clock CK (eg, simultaneously or at a predetermined or fixed time before or after the appropriate trigger edge of the clock CK). Calibration signal. The memory device 30 can transmit the input command calibration signal (as interpreted by the memory device - which can be interpreted correctly or incorrectly) to the memory controller 30, as described above (for example) 4A, FIG. 4B and/or FIG. 5.

Since the memory device 30 is required to have a large capacity, the degree of integration and the number of memory cells are increased. As the number of memory cells increases, the number of address bits used to address the memory cells also increases. An increase in the number of address pins results in an increase in the size of the wafer. Therefore, a need exists for a method for suppressing an increase in the number of address pins required in most memory chips. Since the command/address signal is input at both the rising and falling edges of a clock signal in this example, the number of command/address pins of the memory device 30 can be reduced.

In this example, during the calibration mode of the command/address bus, a read command cannot be transmitted from the memory controller 20 via the command/address signal line. Therefore, in the calibration mode of the command/address signal bus, the clock enable signal CKE serves as one of the command/address signals CAxR and CAxF read commands. When the clock enable signal CKE is activated at a logic low state, the command/address signals CAxR and CAxF are input at a timing determined by the edge of the clock CK, and the result is output to the memory through the data bus DQ13. Body controller 20. Thus, the clock enable signal CKE acts as a dummy command and enables the memory device to input command/address calibration test patterns (eg, signals CAxR and CAxF). The phase adjusted command/address signal CA _sp2 transmitted from the memory controller 20 in the embodiment illustrated in relation to FIG. 5 corresponds to the command/address signal CAxR or CAxF in FIG. . . The values of CAyR and CAyF (hereinafter, collectively referred to as CAnR and CAnF). Each of the CANR and CAFF cycles is transmitted in response to one of the phase-adjusted command/address signals CA _sp2 , and each of the cyclic transmissions has a new relative phase difference with respect to the clock CK compared to the previous CAnR and CAnF signals. Command/address signals CAnR and CAnF signal pairs. For ease of explanation, the adjusted phase difference for each of the CannR and CAnF signal pairs is not shown in Figure 6 (see Figures 4A and 4B and related descriptions). Therefore, n (n is an integer equal to 2 or greater) test command/address test pattern signals (eg, n CARR and CANF signal pairs) can be transmitted along with a clock signal via a command/address bus. , wherein each of the n test pattern signals is transmitted in a 1st to nth phase that is different from one of the clock signals.

At time t ₃ of the delay time tADR from the time t _{1 of the} clock signal CK at which the clock enable signal CKE is started, the DQ bus bar 13 will be in the command/address signal CAxR or CAxF by the memory device. 30 interpreted (e.g., a latch) input 30 of a memory device command / address of the calibration test pattern and CAxF of CAxR (corresponding to the command / address information calibrating CA _r) output from the memory device 30 to memory Body controller 20. The time tADR can be predetermined and the timing is known based on one of the operations of the memory device. (Note that in Figure 6, and illustrates the time t ₃ represented by the dashed vertical alignment of the CK, the portion of the timing sequence of FIG. CA, CS, and CKE at the time t ₃ nights of truncation symbols represented by a ratio of these time series At a time.) As shown in FIG. 6, during a period of a plurality of clock edges of the clock CK, the even-numbered DQ lines (DQ0, DQ2, etc.) of the DQ bus 13 are outputted by the clock CK. The rising edge triggers the value of the command/address signal CAxR input by the memory device 30 (eg, command/address calibration information associated with CAxR). In this example, the time of command/address calibration information output to the memory controller 20 may occur during a plurality of cycles of the clock CK. As shown in FIG. 6, the command/address signal input by the memory device is output on the DQ bus 13 at the same time as the value of the command/address signal CAxR input by the memory device 30 and in the same manner as it is. The value of CAxF (e.g., command/address calibration information associated with CAxF), except that the value of the command/address signal CAxF is output on the odd DQ line of the DQ bus 13 . The DQ bus bar may (but need not) extend substantially in the same direction between the memory device 30 and the controller 20 when viewed from a top-down perspective, and numbered from 0 to m, where m+1 The number of bus lines that are DQ bus bars.

If the relative phase of the clock CK and the address/command calibration test pattern signals CAxR and CAxF trigger input (eg, latch) address/command calibration test pattern signals CAxR and CAxF at the correct logic window, then the memory device The calibration test pattern signal should be interpreted correctly. In this example, memory controller 20 will determine a pass P (the relative phase of the test pattern signals CAxR and CAxF test pattern signals for clock CK and position/command calibration). If the relative phase of the CK and CAxR and CAxF signals results in an incorrect interpretation of the information represented by the address/command calibration test pattern signals CAxR and CAxF, the memory controller 20 will determine a failure F.

The DQ pad can be set in a variety of ways to transfer the value of the second command/address signal CA2 received by the memory device 30 through the DQ line to the calibrated command/address signals CAxR and CAxF of the memory controller 20. Mapping. An example of a map is shown in Figure 8, where the command/position signal CAxR (bits) input by the memory device 30 at the rising edge of the clock signal CK can be used. The values of CA0 to CA9) are output to the memory device 30 DQ pad DQ[9:0], and the value of the command/address signal CAxF input by the memory device 30 at the falling edge of the clock signal CK can be output to the memory. Body device DQ pad DQ [19:10]. Another example of mapping is shown in FIG. 9, in which one of the command/address signals CA9 of the command/address signal CAxR input at the rising edge of the clock signal CK can be output to the memory device 30. A DQS pad DQS0, and the value of the command/address signal CA[8:0] can be output to the memory device 30 DQ pad DQ[8:0]. One value of the command/address signal CA9 among the command/address signals CAxF input at the falling edge of the clock signal CK can be output to one of the DQS pads DQS1 of the memory device and the command/address signal CA can be used. The value of 8:0] is output to the memory device DQ pad DQ[17:9].

At the memory controller 20, the relative phase between the clock CK and the phase adjusted command/address signals (e.g., CAyR and CAyF) sent to the memory device 30 is changed, and command/address calibration is performed. A new cycle. Shown in Figure 6, which is based on the command / address bus 12 on command / position calibration signal CAyR (at time t ₄₎ and CAyF (at the immediately subsequent clock edge of CK) to the memory Apparatus 30, and the memory device 30 transmits a value interpreted by the memory device to one of an intermediate loop of the memory controller 20 in a manner similar to that described above with respect to CAxR and CAxF, and thus It is not necessary to repeat the explanation.

Just prior to time t _5, the wafer selection enable signal / CS of a logic level of the low state together, when the clock enable signal CKE to start. This can occur when the command/address calibration signals CAnR and CAnF (the last of the n command/address calibration information sets transmitted from the memory device 30 to the controller 20 during the command/address calibration session) When the command/address bus 12 is transmitted from the memory controller 20 to the memory device 30. The command/address calibration information CAnR and CAnF can be transmitted in the same manner as the transmission of the command/address calibration information CAxR and CAxF.

At a time t _5, the wafer selection signal / CS of a logic low state level of activated together, the bus bars 12 via the command transmission / end address command / address calibration mode command. (Note that the timing of the vertical alignment with time t ₅ for the even DQ and odd DQ diagrams in Figure 6 occurs before time t ₅ - see the truncation marks in the even DQ and odd DQ timings.) For example, transmit one The second mode register (MRW#42) command is used as the end command/address calibration mode command. If a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#42 command may include a command to identify the command as a mode register setting command. The command/address signal CA[3:0] and the command/address signal CA[9:4] for identifying the mode register setting command as an end command/address calibration mode command.

The MRW #42 command is input at both the rising edge and the falling edge of the clock signal CK corresponding to time t ₅ . That is, the rising edge of the clock signal CK at time t ₅ is followed by the same MRW #42 command twice at the subsequent pulse edge CK followed by the subsequent falling edge. When an MRS command is input using a command signal under a DDR, an error can be generated such that one of the memory devices having a high operating frequency misses the MRS command. To reduce the chance of this error, enter the same MRW#42 command twice at the rising and falling edges of the clock signal CK.

Existence causes the memory device to determine when to latch the exit command/address calibration mode Many ways of the command (here, MRW#42). In one embodiment, the memory device can be configured to latch at the edge of the clock signal CK with a predetermined relationship (eg, timing) with respect to the transition from the low state active to the high state of the clock enable signal CKE. Information provided on bus bar 12. For example, as shown in FIG. 6, the memory device can be configured to latch at the CA busbar 12 at both edges of the clock CK following the transition from the low state active to the high state of the clock enable signal CKE. Information provided on. When the CKE is high, the memory device 30 treats the information on the command address bus 12 as a command (to be processed, for example, by one of the memory devices 30) rather than a calibration test pattern. It should also be noted that the clock enable signal CKE may be considered to be active low only during certain operations, such as during the CA calibration mode, and at other times, to interpret it as a high active signal.

After the predetermined time tMRZ is delayed from the time t _{5 at which the} MRW #42 command is input, the command/address signals CAnR and CAnF are terminated to the output of the memory device DQ pad. The time t _{0 of the} clock signal CK from the MRW #41 command (which is the command/address calibration start signal) is input to the time t ₅ of the clock signal CK at which the MRW #42 command is input at that time. The upper time tMRZ can be a CA calibration cycle.

Figure 7 is a diagram showing a true value of an exemplary mode register command setting method.

Referring to FIG. 7, the MRW #41 command and the MRW #42 command can be set by the clock enable signal CKE, the wafer select signal /CS, and the command/address signal CA[9:0]. When the pulse enable signal CKE is at a logic high state (H) level, the chip select signal /CS is at a logic low state (L) level, and the command/address signal is When CA[3:0] is at a logic low (L) level and the command/address signal CA[9:4] is at the logic level HLHLLH, the MRW#41 command can be used to set the MRS of the memory device 30. A scratchpad (for example, written to the MRS register). That is, the MRW #41 command may include the command/address signal CA[9:0] 29H. The same MRW #41 command can be sent to the memory device on the command/address bus 12 at both the rising and falling edges of the clock signal CK. The memory device 30 can be configured to set the mode register to indicate memory when properly interpreting at least one of the two MRW #41 commands sent to the memory device 30 when input by the memory device 30 The body device 30 is in a command/address calibration command. (Note that sending two MRW #41 commands to the memory device 30 may include maintaining the command sent on the command/address bus without changing the two logical windows of the command/address signal - the two logic windows It can include one complete clock cycle of the clock CK.)

When the pulse enable signal CKE is at a logic high state level, the chip select signal /CS is at a logic low state level, the command/address signal CA[3:0] is at a logic low state level, and the command When the address signal CA[9:4] is under the logic level HLHLHL, the MRW#42 command can be used to set the MRS register of the memory device 30. That is, the MRW #42 command may include the command/address signal CA[9:0] 2AH. The same MRW #42 command can be sent to the memory device twice on the command/address bus 12 at both the rising and falling edges of the clock signal CK. In this paper, the command/address signal CA[9:4] can be used as the mode register setting address MA[5:0].

8 is a diagram showing one example of a mapping between a command/address signal and a DQ pad, in accordance with an embodiment. Since in the current embodiment, The command/address signal CA[9:0] is input to both the rising and falling edges of the clock signal CK, so the command/address signal CA[9:0] can be composed of 20 bits. In this regard, the bit structure of the data DQ of the memory device 30 is x32 and, therefore, the number of DQ pads is 32. The number of DQ pads is greater than the number of command/address signals such that the DQ pads can correspond one-to-one to the command/address signals.

Referring to Figure 8, the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be mapped to be output to the DQ pad DQ[9:0]. The value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK can be mapped to be output to the DQ pad DQ[19:10]. For example, in FIG. 6, the output value corresponding to the time of the command input at the rising edge of the clock signal CK of ₁ / t to the address signal CAxR DQ pads DQ [9: 0], and the corresponding The value of the command/address signal CAxF input at the falling edge of the clock signal CK at time t ₁ is output to the DQ pad DQ[19:10]. The value of the command/address signal CAxR input at the rising edge of the clock signal CK corresponding to the time t ₄ is output to the DQ pad DQ[9:0], and the clock signal CK corresponding to the time t ₄ will be The value of the command/address signal CAxF input at the falling edge is output to the DQ pad DQ[19:10].

9 is a diagram showing one example of another example for illustrating a mapping between a command/address signal and a DQ and DQS pad, in accordance with another embodiment.

Referring to FIG. 9, the value of the command/address signal CA[9:0] (eg, CAxR) input to the memory device 30 at the rising edge of the clock signal CK can be mapped to be output to the DQS pads DQS0 and DQS1, and Even DQ pads DQ [0, 2, 4, 6, 8, 10, 12 and 14]. That is, the input value of the command/address signal CA9 is output to the DQS pad DQS1, the input value of the command/address signal CA4 is output to DQS0, and the input values of the command/address signal CA[3:0] are respectively output. to The DQ pads DQ[6, 4, 2, 0] and the input values of the command/address signals CA[8:5] are output to the DQ pads DQ[14, 12, 10, 8], respectively.

The value of the command/address signal CA[9:0] (eg, CAxF) input to the memory device 30 at the falling edge of the clock signal CK can be mapped to output to the DQS pad/DQS0 and /DQS1 and the DQ pad. DQ [17:9]. That is, the input value of the command/address signal CA9 can be output to the DQS pad/DQS1, and the input value of CA4 can be output to the DQS pad/DQS0, and the input value of the command/address signal CA[3:0] can be input. They are respectively output to the DQ pad DQ[7, 5, 3, 1] and the input values of the command/address signals CA[8:5] are output to the DQ pads DQ[15, 13, 11 and 9], respectively.

Figure 10 is a diagram for illustrating one of the command/address alignment methods in accordance with another embodiment.

FIG. 10 is a timing diagram for explaining one of the command/address calibration methods in the memory device 30, wherein the bit structure of the data DQ of the memory device 30 is x32.

Referring to FIG. 10 in conjunction with FIG. 5, the memory controller 20 generates a clock signal CK for the memory device 30. The memory controller 20 issues an incoming command/address calibration mode command (or command) to the memory device 30 via the command/address bus. The entry command/address calibration mode command can be entered using a special case of the MRS commands set forth herein with respect to other embodiments. The memory controller 20 transmits an exit command/address calibration mode command (or command) through the command/address bus. The exit command/address calibration mode command may be entered using a special case of the MRS commands set forth herein with respect to other embodiments.

At time t ₀ of the clock signal CK, together with the activation of one of the logic low level of the wafer select signal /CS, the MRW#41 command is transmitted through the command/address bus 12 to enter the command/address calibration command. . For example, the MRW #41 command is input at both the rising edge and the falling edge of the clock signal CK starting at time t ₀ . That is, the same MRW #41 command can be input at the rising edge and the falling edge of the clock signal CK starting at time t ₀ .

At time t ₁ after the delay time tMRW of the t _{0 of the} clock signal CK inputting the MRW #41 command at that time, together with the activation of the logic low state of the wafer selection signal /CS, for the clock signal CK One cycle starts the clock enable signal CKE with a predetermined pulse width, and sequentially transmits the command/address signals CAxR and CAxF through the command/address bus.

At the rising edge of the clock signal CK at time t ₁ , the command/address signal CAxR is input, and at the falling edge of the clock signal CK (before the time t ₁ , the clock CK is followed by the subsequent falling edge) Enter the command/address signal CAxF. The command/address signal CAxR and the command/address signal CAxF input through the command/address bus 12 can represent different signals of different information (for example, different test pattern information).

In the calibration mode, the clock enable signal CKE acts as one of the command/address signals CAxR and CAxF corresponding to the value of the second command/address signal CA2 received by the memory device 30 in FIG. During the command/address calibration mode (and when the wafer select/CS is active (logic low)), the memory device initiates the interpretation of one of the clock enable signals CKE at a logic low level to An instruction of one of the signals on the command/address signal bus is input to the subsequent edge of the clock signal CK, and thus, for example, as shown in FIG. 10, the command/address signal CAxR received by the memory device 30 is input or CAxF value.

T ₃ since the beginning of the delay times t ₁ tADR time, the command / address signal and the value CAxF of CAxR (interpreted by the memory device / input) to the DQ pads. At time t _3, the command / address signal is outputted to the even-numbered DQ CAxR pad, and the clock CK during the immediately subsequent clock edge, the command / address signal is output to the odd-numbered DQ pad CAxF.

The mapping between the command/address signals CAxR and CAxF and the DQ pad can be set in various ways. An example of mapping is illustrated in FIG. 11 in which the value of the command/address signal CAxR input at the rising edge of the clock signal CK can be output as an even DQ pad DQ[2n], where n is 0 to 9, and The value of the command/address signal CAxF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where n is 0 to 9.

As another mapping example, the result of the calibration of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK can be output to the even DQ pad DQ [ 2n], where n is 0 to 3, a value of a command/address signal CA4 can be output to the DQS pad DQS0, and the value of the command/address signal CA[8:5] can be output to the even DQ pad DQ [ 2n], where n is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad DQS1. The value of the command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where n is 0. Up to 3, a value of the command/address signal CA4 can be output to the DQS pad/DQS0, and the value of the command/address signal CA[8:5] can be output to the odd DQ pad DQ[2n+1], where n The system is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad/DQS1.

At time t ₄ , together with the activation of the logic low state of the crystal moon selection signal /CS, the clock enable signal CKE is activated for a cycle of the clock signal CK with a predetermined pulse width, and is input by the memory device 30. Command/address bus 12 transmits command/address signals CAyR and CAyF.

In that the time t ₄ at the rising edge of the clock signal CK of the command / address signal CAyR, and at a falling edge of the clock signal CK (time t after the clock _{CK. 4} of the immediately subsequent clock edge ) Enter the command/address signal CAyF. The command/address signal CAyR and the command/address signal CAyF input through the command/address bus 12 can be different signals (eg, different bytes of the test pattern).

In the calibration mode, the clock enable signal CKE acts as one of the command/address signals CAyR and CAyF read commands, and therefore, when the pulse enable signal CKE is enabled at a logic low level, it will be received by the memory device 30. The values of the command/address signals CAyR and CAyF are output to the even DQ pads and the odd DQ pads are input by the memory device 30 in response to a timing of the clock CK.

After the self-clock signal CK of a predetermined delay time t ₄ time tADR, the command / address signal and CAyR CAyF (such as at time t ₄ at the beginning of the memory means as input) the value output to DQ pads. That is, the command/address signal CAyR input by the memory device 30 is output to the even DQ pad and the command/address signal CAyF input by the memory device 30 is output to the odd DQ pad.

When the memory device 30 transmits the command/address signals CAyR and CAyF to the memory controller 20, the mapping to the DQ pad can be set in various ways. As an example of mapping, the input can be entered at the rising edge of the clock signal CK. The value of the address/address signal CAyR is output to the even DQ pad DQ[2n], where n is 0 to 9, and the value of the command/address signal CAyF input at the falling edge of the clock signal CK can be output to an odd number. DQ pad DQ[2n+1], where n is 0 to 9.

As another mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAyR input at the rising edge of the clock signal CK can be output to the even DQ pad DQ[2n], Where n is 0 to 3, a value of a command/address signal CA4 can be output to the DQS pad DQS0, and the value of the command/address signal CA[8:5] can be output to the even DQ pad DQ[2n], Where n is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad DQS1. The value of the command/address signal CA[3:0] among the command/address signals CAyF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where n is 0. Up to 3, a value of the command/address signal CA4 can be output to the DQS pad/DQS0, and the value of the command/address signal CA[8:5] can be output to the odd DQ pad DQ[2n+1], where n The system is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad/DQS1.

At time t _5, the wafer selection signal / CS of low logic level state to start with, the transmission line bus 12 via the command / address a command to quit / calibration mode command address of MRW # 42 command. In this example, corresponding to the time t at both rising and falling edges of the clock signal CK ₅ MRW # 42 of the input command. That is, the same MRW #42 command is input at the rising edge and the falling edge of the clock signal CK corresponding to the time t ₅ .

There are numerous ways for the memory device 30 to recognize the signal on the command/address bus 12 as a command (rather than another set of test pattern calibration information for a new cycle). For example, there may be a predetermined number of cycles in which the memory device 30 is expected to receive a command sent to the memory device for a predetermined number of cycles; the memory device 30 may count the number of cycles of the test pattern information and When the count reaches a predetermined number (or, for example, the previous count or the next count), it is expected to receive a command. Alternatively, the memory device 30 can monitor all information (eg, monitoring command/address calibration information CA _r ) input via the command/address bus 12 to detect a predetermined code (eg, a command code). And exit the calibration mode when a predetermined code is detected (and/or the predetermined code is recognized as an exit command/address calibration command code), or otherwise the input information is considered to be tested during one of the calibration modes. Calibration information generated by the pattern transmission.

After the predetermined time tMRZ is delayed from the time t ₅ at which the MRW #42 command is input, the output of the calibrated command/address signal CAyR to the DQ pad is terminated. From the time t ₀ (in the case of the input system enters the command / address calibration mode command MRW #41 command) to the time t ₅ (in the case of the input system exit command / address calibration mode command MRW #42 command) The period plus time tMRZ may correspond to a CA calibration mode period.

Although FIG. 10 only shows two sets of test patterns (for CAxR and CAxF and for CAyR and CAyF) transmitted during the calibration mode period, more than two test patterns can be transmitted during one calibration period. In addition, FIG. 10 illustrates a logic window that is positioned such that its logic window center corresponds to a command/address calibration signal for a corresponding clock edge of clock CK. However, this is for illustrative purposes only; it is expected that the controller 20 will change the relative phase of each of the command/address calibration signals (representing the calibration test pattern) such that the clock edge CK is for the command/address The timing of many command/address calibration signals in the calibration signal will be in time Up shifting (and may be center shifted (eg, on the outside) relative to the command/address alignment signal logic window such that the memory device 30 incorrectly interprets one of the command/address calibration signal logic timings) .

11 is a table showing one example of a mapping between a command/address signal and a DQ pad in accordance with another embodiment.

Referring to Figure 11, the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be mapped to output to the even DQ pad DQ[2n], where n is 0 to 9. The value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK can be mapped to output to the odd DQ pad DQ[2n+1], where n is 0 to 9. For example, in FIG. 10, the value of the command/address address CAxR input at the rising edge of the clock signal CK corresponding to the time t ₁ can be output to the even DQ pad DQ[2n], where n is 0. Up to 9, and the value of the command/address signal CAxF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where n is 0 to 9. The value of the command/address signal CAxR input at the rising edge of the clock signal CK at time t ₄ can be output to the even DQ pad DQ[2n], where n is 0 to 9, and the clock signal can be The value of the command/address signal CAxF input at the falling edge of CK is output to the odd DQ pad DQ[2n+1], where n is 0 to 9.

12 is a table showing another example of a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment. Referring to Figure 12, the value of the command/address signal CA[9:0] (e.g., CAxR) input to the memory device 30 at the rising edge of the clock signal CK can be mapped for output to the DQS pad DQS0 and DQ pads. DQ[8:0]. That is, the value of the command/address signal CA9 can be output to the DQS pad DQS0, and the command/address address can be The value of the number CA[8:0] is output to the DQ pad DQ[8:0].

The value of the command/address signal CA[9:0] (eg, CAxF) input to the memory device 30 at the falling edge of the clock signal CK can be mapped to output to the DQS pad DQS1 and the DQ pad DQ [17: 9]. That is, the value of the command/address signal CA9 can be output to the DQS pad DQS1, and the value of the command/address signal CA[8:0] can be output to the DQ pad DQ[17:9].

FIG. 13 is a timing diagram illustrating one of the command/address alignment methods in the memory device 30 in accordance with another embodiment. The bit structure of the data DQ of the memory device 30 is 16X. In the current embodiment, the command/address signal CA[9:0] is input at both the rising and falling edges of the clock signal CK, and therefore, each command/address test pattern CA[9:0 ] can be composed of 20 bits. In this regard, since the bit structure of the data DQ of the memory device 30 is x16, the number of DQ pads is 16. The number of command/address test pattern bits for a particular relative phase transmission generated by memory controller 20 is greater than the number of DQ pads such that the DQ pad does not uniquely correspond to the command/address signal. Thus, the DQ pads can be assigned to command/address signals received on different signal lines of the command/address bus 12 at predetermined time intervals.

Referring to FIG. 13 in conjunction with FIG. 5, the memory controller 20 generates a clock signal CK for the memory device 30. The memory controller 20 sends an incoming command/address calibration mode command (or command) to the memory device 30 via the command/address bus. The Enter Command/Address Calibration Mode command can use the specific MRS command format described elsewhere in this document. The memory controller 20 transmits an exit command/address calibration mode command via the command/address bus. The Exit Command/Address Calibration Mode command can be used elsewhere in this article. Specific MRS command format.

At time t ₀ , the command/address alignment mode command is transmitted through the command/address bus 12 along with the activation of one of the logic select states of the wafer select signal /CS. For example, a third mode register (MRW#43) command is transmitted as a command/address calibration start signal. When a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#43 command may include a command indicating that the command is a mode register setting command/ The address signal CA[3:0] and the mode register setting command indicating that the mode register setting command is one of the command/address signals CA[9:4] entering the calibration mode command.

The MRW #43 command is input at both the rising and falling edges of the clock signal CK starting at time t ₀ . That is, the same MRW #43 command is input at the rising edge of the clock signal CK at time t ₀ and again at the subsequent falling edge of the clock signal CK. This is due to the possibility of generating an error such that one of the memory devices with a high operating frequency (eg, during a DDR operation) misses or misinterprets the MRS command. To reduce the chance of this error, the same MRW #43 command is entered at the rising and falling edges of the clock signal CK corresponding to time t ₀ .

Since that time the clock signal 43 to the command input MRW # CK of a predetermined delay time t ₀ of time tMRW at t _1, starting with the wafer select signal / CS of a logic level of the low state, CK clock signal for One of the cycles starts the clock enable signal CKE with a predetermined pulse width, and the command/address signals CAxR and CAxF are transmitted through the command/level bus 12. The time tMRW can be set by a mode register to set the write cycle time.

The command/address signal CAxR is input at the rising edge of the clock signal CK at time t ₁ and at the falling edge of the clock signal CK (below the subsequent falling edge of the clock signal CK after t ₁ ) Enter the command/address signal CAxF. The command/address signal CAxR and the command/address signal CAxF input through the command/address bus 12 can be different signals. For example, when the command/address bus 12 is composed of a 10-bit command/address signal CA[9:0], a 10-bit command/address signal CAxR and 10 bits can be used. The meta command/address signal CAxF is divided into different signals. Thus, the command/address terminal (eg, pad, pin or bump - not shown) of the memory device 30 connected to the 10-bit command/address bus 12 can be commanded by 20 bits. The address signal CA[9:0] is input to the memory device 30.

Since the memory device 30 is required to have a large capacity, the degree of integration and the number of memory cells are increased. As the number of memory cells increases, the number of address bits used to address the memory cells also increases. An increase in the number of address pins results in an increase in the size of the wafer. Accordingly, a method for suppressing an increase in the number of address pins required in most memory chips is desired. Since the command/address signals are input at both the rising and falling edges of a clock signal in the current embodiment, the number of command/address pins of the memory device 30 can be reduced.

During the command/address calibration mode, the clock enable signal CKE acts as one of the command/address signals CAxR and CAxF read commands. When the clock enable signal CKE is activated at a logic low state, the command/address signals CAxR and CAxF are input in response to a timing of the clock CK, and the result is output as a data signal DQ. Therefore, the clock enable signal CKE is used as a pseudo command.

Since the times t ₁ after a predetermined delay time tADR, output from the memory device 30 as an input of the command / address signal and CAxF CAxR as a data signal DQ. The time tADR can be set from the start of the clock enable signal CKE to the data output to one of the DQ pads to set the delay time.

At time t _3, the output device 30 via the DQ pad memory of the memory device 30 as an input the calibrated command / address signal CAxR. For a predetermined time in a calibrated command / address signal is output to the DQ pad CAxR time after the tADD t _4, the output device 30 via the DQ pad memory 30 by the memory device calibrated as a command / address signal input of CAxF .

The mapping between the calibrated command/address signals CAxR and CAxF and the DQ pad can be set in various ways. As a mapping example, the value of the command/address signal CAxR input at the rising edge of the clock signal CK can be output to the DQ pad DQ[9:0], and then can be at the falling edge of the clock signal CK. The value of the input command/address signal CAxF is output to the DQ pad DQ[9:0].

As another mapping example, the value of the command/address signal CA[4:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[4:0], The result of the calibration of the command/address signal CA[9:5] is then also output to the DQ pad DQ[4:0]. The value of the command/address signal CA[4:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[9:5], and then, will also be The result of the calibration of the command/address signal CA[9:5] is output to the DQ pad DQ[9:5].

As a further mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[3:0], Output a value of a command/address signal CA4 To a DQS pad DQS0, the value of the command/address signal CA[8:5] is output to the DQ pad DQ[4:0], and a value of a command/address signal CA9 is output to a DQS pad DQS1. The value of the command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[7:4], and the command/address signal is output. One value of CA4 is output to a DQS pad/DQS0, the value of the command/address signal CA[8:5] is output to the DQ pad DQ[7:4], and a value of the command/address signal CA9 is output to A DQS pad / DQS1.

Starting at time t ₄ , together with the activation of the logic low level of the wafer select signal /CS, the clock enable signal CKE is initiated with a predetermined pulse width for one cycle of the clock signal CK, and the command/address bus is transmitted through the command/address bus The command/address signals CAyR and CAyF are transmitted from the memory controller 20 to the memory device 30.

The command/address signal CAyR is input at the rising edge of the clock signal CK at time t ₄ , and the command/address signal CAyF is input immediately after the subsequent falling edge of the clock signal CK. The command/address signal CAyR and the command/address signal CAyF input through the command/address bus 12 can be different signals.

After a predetermined delay time since the time t ₄ tADR, via DQ pads by the memory device 30 as an input of the command / address signal and CAyF CAyR DQ bus 13 to the output. After outputting the calibrated command/address signal CAyR (as input from the memory device 30) to the DQ pad, the calibrated command/address signal CAyF (as input by the memory device 30) is output.

The mapping between the calibrated command/address signals CAyR and CAyF and the DQ pad can be set in various ways. As a mapping example, the clock signal CK can be The value of the command/address signal CAyR input at the rising edge is output to the DQ pad DQ[9:0], and then the value of the command/address signal CAyF input at the falling edge of the clock signal CK can be output to DQ pad DQ[9:0].

As another mapping example, the value of the command/address signal CA[4:0] among the command/address signals CAxR input at the rising edge of the clock signal CK can be output to the DQ pad DQ[4:0]. And then, the result of the calibration of the command/address signal CA[9:5] is also output to the DQ pad DQ[4:0]. The value of the command/address signal CA[4:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[9:5], and then, will also be The result of the calibration of the command/address signal CA[9:5] is output to the DQ pad DQ[9:5].

As a further mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[3:0], Output a value of the command/address signal CA4 to the DQS pad DQS0, output the value of the command/address signal CA[8:5] to the DQ pad DQ[4:0], and place the command/address signal CA9 One value is output to the DQS pad DQS1. The value of the command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[7:4], and the command/address signal is output. One value of CA4 is output to DQS pad/DQS0, the value of command/address signal CA[8:5] is output to DQ pad DQ[7:4], and one value of command/address signal CA9 is output to DQS Pad / DQS1.

At time t _5, the wafer selection signal / CS of low logic level state to start with, from the command / address bus 12 transfer to exit the calibration / calibration mode command here. For example, a fourth mode register (MRW#44) command is transmitted as a command/address calibration end signal. When a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#44 command can be set by a mode register setting command, and the mode is temporarily stored. The device setting command may include a CA[3:0] for indicating that the command is a mode register setting command, and a command/bit for indicating the mode register setting command is an exit command/address calibration mode command. Address signal CA[9:4].

The MRW #44 command can be input at both the rising and falling edges of the clock signal CK corresponding to time t ₅ . That is, the same MRW #44 command is input at both the rising edge and the falling edge of the clock signal CK starting at time t ₅ . After the predetermined time tMRZ is delayed from the time t ₅ at which the clock signal CK of the MRW #44 command is input, the output of the calibrated command/address signal CAyR via the DQ pad is terminated. The period from the time t _{0 of} inputting the MR _W #41 command to the time t ₅ CK at which the MRW #44 command is input at that time plus tMRZ may be a CA calibration period.

Although FIG. 13 only shows two sets of test patterns (for CAxR and CAxF and for CAyR and CAyF) transmitted during the calibration mode period, more than two test patterns can be transmitted during one calibration period. In addition, FIG. 13 illustrates a logic window that is positioned such that its logic window center corresponds to a command/address calibration signal for a corresponding clock edge of clock CK. However, this is for illustrative purposes only; it is expected that the controller 20 will change the relative phase of each of the command/address calibration signals (representing the calibration test pattern) such that the clock edge CK is for the command/address The timing of the numerous command/address calibration signals in the calibration signal will be shifted in time (and may be center shifted relative to the command/address calibration signal logic window) The bit is (eg, on its outside) such that the memory device 30 incorrectly interprets one of the command/address alignment signal logic timings).

Figure 14 is a table for explaining one of the mode register command setting methods according to another embodiment.

Referring to FIG. 14, the MRW #43 command and the MRW #44 command can be set by the clock enable signal CKE, the wafer select signal /CS, and the command/address signal CA[9:0]. When the pulse enable signal CKE is in a logic high state, the chip select signal /CS is in a logic low state, the command/address signal CA[3:0] is in a logic low state, and the command When the address signals CA[9:4] are respectively under a logic level HLHLHH, the MRW#43 command can be set. That is, the MRW #43 command can be represented by a command/address signal CA[9:0] value of 2BH. As described above, the MRW #43 command may be the same at both the rising and falling edges of the clock signal CK, however, a different value (eg, the inverse of 2BH) may alternatively be sent to the memory device. 30.

When the clock enable signal CKE is in a logic high state, the chip select signal /CS is in a logic low state, the command/address signal CA[3:0] is in a logic low state, and the command The MRW#44 command can be set when the address signals CA[9:4] are respectively under the logic level HLHHLL. That is, the MRW #44 command can be set identically at both the rising edge and the falling edge of the clock signal CK. In this paper, the command/address signal CA[9:4] can be used as the mode register setting address MA[5:0].

15 is a diagram for illustrating one example of a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment.

Referring to Figure 15, the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be mapped for output to the DQ pad DQ[9:0] of the memory device 30. Thereafter, the result of the calibration of the command/address signal CA[9:0] input at the falling edge of the clock signal CK can be mapped to be output to the DQ pad DQ[9:0]. For example, in FIG. 13, the value of the command/address signal CAxR input at the rising edge of the clock signal CK corresponding to time t ₁ can be mapped to be output to the DQ pad DQ[9:0], and The value of the command/address signal CAxF input at the falling edge of the clock signal CK corresponding to time t ₁ can then be mapped for output to the DQ pad DQ[9:0]. Corresponding to time t ₄ of a rising edge of the clock signal at the input CK of the command / address signal value of CAyR may be mapped to output to the DQ pad DQ [9: 0], and then, at time t ₄ corresponds to the The value of the command/address signal CAyF input at the falling edge of the clock signal CK can be mapped to be output to the DQ pad DQ[9:0].

16 is a diagram showing one example of another example for illustrating a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment.

Referring to Fig. 16, a portion of the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK may be sequentially mapped to the DQ pad DQ[4:0] at predetermined time intervals. A portion of the value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK may be sequentially mapped to the DQ pad DQ[5:9] at predetermined time intervals.

For example, in FIG. 13, in that the rising and falling edges at t time clock signal at each of ₁ CK of the command / address signal and CAxF CAxR the command / address signal CA [9: 0] value of Thereafter, the value CAxR of CA[4:0] (as an input) can be respectively output via the DQ pad DQ[4:0], and the value CAxR of the CAxR is output via the DQ pad DQ[4:0] at a subsequent time. :5] (as input) one of the outputs. However, the value of the command/address signal CA[4:0] of CAxF is output via DQ pad DQ[9:5] (as an input), followed by the command/address signal outputting CAxF via DQ pad DQ[9:5] The value of CA[9:5] (as input).

17 is a diagram showing one example of another example of mapping between a command/address signal and a DQ pad in accordance with another embodiment.

Referring to FIG. 17, a portion of the input value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be sequentially output to the DQS pads DQS0 and DQS1 and the DQ pad DQ[3:0]. . For example, the value of the command/address signal CA[3:0] of CAxR is output via the DQ pad DQ[3:0], wherein the value of the command/address signal CA4 of CAxR is output via the DQS pad DQS0. Then, the value of the command/address signal CA[8:5] of CAxR is output via the DQ pad DQ[3:0], wherein the value of the command/address signal CA9 is output via the DQS pad DQS1.

The portion of the input value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK may be sequentially output to the DQS pad/DQS0 and /DQS1 and the DQ pad DQ[7:4]. For example, after outputting the portion of CAxR as described above, the value of the command/address signal CA[3:0] of CAxF is output via the DQ pad DQ[7:4], and the command of CAxF is output via the DQS pad/DQS0. / The value of the address signal CA4, the value of the command/address signal CA[8:5] of the CAxF is output via the DQ pad DQ[7:4], and the command/address signal CA9 of the CAxF is output via the DQS pad/DQS1. value.

Figure 18 is a diagram of one example of an exemplary command/address calibration method in accordance with another embodiment. 18 is a timing diagram illustrating one of the command/address calibration methods in the memory device 30 shown in FIG. 5, wherein the memory device 30 The data DQ is organized in 16X. The method represented by FIG. 18 can be the same as the method set forth above with respect to FIG. 10 or an alternative thereto, except that the method shown in FIG. 18 can be used to control the command/address calibration information from the memory device 30 to the memory control. The output of the device 20 is different. In addition, FIG. 18 illustrates the use of a specific instance of MRW #43 as an incoming command/address calibration mode command and using a particular instance of MRW #44 as one of the exit command/address calibration mode commands. Since the timing and operation of the memory system 10 of the embodiment of FIG. 10 and its alternatives have been described above, it is not necessary to repeat one of the common features of the embodiments of FIGS. 10 and 18 herein. The mapping between the input command/address signals CAxR and CAxF and the DQ pad can be set in various ways. As a mapping example, a portion of the value of the command/address signal CAxR input at the rising edge of the clock signal CK may be sequentially output to the even DQ pad DQ[2n] at predetermined time intervals, and may be at a predetermined time interval. The portion of the value of the command/address signal CAxF input at the falling edge of the pulse signal CK is sequentially output to the odd DQ pad DQ[2n+1], where n is 0 to 4. An example of this is explained further with respect to FIG.

As another mapping example, the values of the command/address signals CA[3:0] of the CAxR input at the rising edge of the clock signal CK are respectively output to the even DQ pad DQ[2n], where n is 3 to 0. At the same time, the value of CAxR command/address signal CA4 is output to DQS pad DQS0, and the value of CAxR command/address signal CA[8:5] is output to even DQ pad DQ[2n], where n is 8 to 5, and simultaneously output the value of the CAxR command/address signal CA9 to the DQS pad DQS1. At the same time, the value of the CAxF command/address signal CA[3:0] is output to the odd DQ pad DQ[2n+1], where n is 3 to 0, and The value of CAxF command/address signal CA4 is output to DQS pad/DQS0, and the value of CAxF command/address signal CA[8:5] is output to odd DQ pad DQ[2n+1], where n is 8 to 5, and simultaneously output the value of the command/address signal CA9 to the DQS pad/DQS1. In this embodiment and all other embodiments set forth herein, the command/address signals corresponding to later calibration cycles may be performed in one of the manners set forth above with respect to CAxR and CAxF (eg, other CARR and CANF, eg, The mapping of other values of CAyR and CAyF) to the output of the memory device, but this is not required. Additionally, although the mapping and output have been described with respect to terminals (eg, pads, pins, bumps, etc.) of the memory device 30, for all of the embodiments set forth herein, such statements are equally applicable to memory devices. 30 provides an associated bus and signal line for communication with the memory controller 20 and terminals (pads, pins, bumps, etc.) of the memory controller. For example, in one embodiment, one of the command address information (or values) to one of the even DQ pads of the memory device 30 is output to cover the command address information (or value) via the DQ bus. The transmission of the even DQ line of 13 is received by the memory controller 20 through the corresponding even DQ terminal.

19 is a diagram showing one example of a mapping between a command/address signal and a DQ pad, in accordance with an embodiment.

Referring to FIG. 19, a portion of the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK may be sequentially output to the even DQ pad DQ[2n], where n is 0 to 4. The portion of the value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK may be sequentially output to the odd DQ pad DQ[2n+1], where n is 0 to 4. For example, in FIG. 10 may be corresponding to the time t CAxR input of _a rising edge of the clock signal CK of the command / address signal CA [0: 4] is outputted to the even values of DQ pads DQ [ 2n], at the same time, the value of the command/address signal CA[0:4] of the CAxF input at the falling edge of the clock signal CK is output to the odd DQ pad DQ[2n+1], where n is 0 to 4. At a subsequent time (which can be immediately after this output), the value of the CAxR command/address signal CA[5:9] can be output to the even DQ pad DQ[2n], and the CAxF command can be/ The value of the address signal CA[5:9] is output to the odd DQ pad DQ[2n+1], where n is 0 to 4. At a later time, calibration information associated with other calibration cycles may be output in a similar manner, such as CAyF and CAyR as illustrated with respect to FIG.

20 is a diagram showing one example of another example for illustrating a mapping between a command/address signal and a DQ pad in accordance with an embodiment.

Referring to FIG. 20, the value of the command/address signal CA[9:0] (eg, CAxR) input at the rising edge of the clock signal CK can be mapped to be output to the DQS pads DQS0 and DQS1 and the even DQ pad DQ [ 2n], where n is 0 to 3. For example, the value of the CAxR command/address signal CA[0:3] is output to the even DQ pad DQ[2n], and the value of the CAxR command/address signal CA4 is output to the DQS pad DQS0 (where n Lines 0 to 3). Then, the value of the CAxR command/address signal CA[5:8] is output to the even DQ pad DQ[2n], and the value of the CAxR command/address signal CA9 is output to the DQS pad DQS1 (where n is 0) To 3).

The value of the command/address signal CA[9:0] (eg, CAxF) input at the falling edge of the clock signal CK can be mapped to output to the DQS pad/DQS0 and /DQS1 and the odd DQ pad DQ[2n+ 1], where n is 0 to 3. For example That is, the value of the command/address signal CA[0:3] of the CAxF is output to the odd DQ pad DQ[2n+1], and the value of the command/address signal CA4 of the CAxF is output to the DQS pad/DQS0. Then, the value of the CAxF command/address signal CA[5:8] is output to the odd DQ pad DQ[2n+1], and the value of the CAxF command/address signal CA9 is output to the DQS pad/DQS1. The output of CA[4:0] of CAxR and CA[4:0] of CAxF can occur simultaneously. The output of CA[5:9] of CAxR and CA[5:9] of CAxF can occur simultaneously. At a later time, calibration information associated with other calibration cycles may be output in a similar manner, such as CAyF and CAyR as illustrated with respect to FIG.

21 is a block diagram showing another example of a memory system that can be used to implement one of the one or more CA calibration embodiments set forth herein.

Referring to Figure 21, memory system 40 differs from the memory system shown in FIG. 5 of 10, which was due to the command / address information calibrating CA _r (as interpreted by the memory device 60 from the controller 50 of the phase The adjusted calibration signal CA _sp2 ) is provided to the memory controller 50 via a separate calibration bus CA_Cal 15 instead of the DQ bus 13 . The calibration bus CA_Cal 15 can be dedicated to transmitting the received command/address information CA _r during the calibration mode. When not in the calibration mode (during normal operation), the calibration bus CA_Cal 15 may be used for another function or may not be used. For example, the calibration bus bar CA_Cal 15 can be used to transmit DQ calibration information from the memory device 60 to the memory controller 50 during a DQ bus calibration mode. The DQ calibration may be the same as the CA calibration described herein with respect to any of the CA calibration embodiments, and the DQ calibration information may be the same as the CA calibration information, except that the DQ calibration is transmitted over the DQ bus via the calibration signal. In the case of the implementation, and therefore, a repetitive statement is not required here. Therefore, during the calibration of the command/address signal, other signals can be transmitted through one of the additional signal lines DQ signal lines and one DQS signal line, thereby improving efficiency. To avoid a repetitive statement, one of the same components as in Figure 5 will not be provided in detail.

In the memory controller 50, the clock generator 201 generates a clock signal CK to supply the clock signal CK to the memory device 60 through the clock signal line 11. The CA transmitter 203 adjusts the phase or timing of the initial command/address signal CA _sp1 in response to the control signal CTRL of the phase/timing controller 208 to produce a phase adjusted command/address signal CS _sp2 .

In the memory device 60, the CA receiver 304 receives the phase-adjusted command/address signal CA in response to a timing of the internal clock signal ICK and when enabled by the clock enable signal CKE and the wafer select signal /CS. _Sp2 to generate command/address calibration information CA _r . Command / address information CA _r calibration system bus through calibration CA_Cal 15 provided to the memory device 60 by the memory controller 50. The command/address calibration information CA _{r is} supplied to the comparator 206 of the memory controller 50 through the calibration bus CA_Cal 15.

The comparator 206 of the memory controller 50 compares the transmitted command/address information CA _s (which may be the information of the phase-adjusted command/address signal CA _sp2 - which may be associated with the initial command/address signal CA The information of _{sp1 is} the same) and the received command/address calibration information CA _{r is used} to generate the pass signal P or the fail signal F. The phase/timing controller 208 generates a control signal CTRL indicative of a phase shift of one of the phase adjusted commands/address signals CA _sp2 based on the pass signal P or the fail signal F generated by the comparator 206. The CA transmitter 203 generates a phase adjusted command/address signal CA _sp2 based on the control signal CTRL. During the calibration of one of the command/address communications between the memory device 60 and the memory controller 50, multiple cycles of transmitting the phase adjusted command/address signal _{CAsp2 may} be performed (each cycle having a relative time) One of the pulses CK is differently adjusted relative phase), and the most between the clock CK and the command/address signal transmitted from the memory controller 50 to the memory device 60 can be selected based on a plurality of P and F failure F decisions. The preferred phase is as described herein with respect to other embodiments (e.g., the embodiment of memory controller 20 and memory device 30 of FIG. 5 is illustrated). For example, by repeating the CA calibration loop, the phase/timing controller 208 of the memory controller 50 determines to trigger the memory device 60 to input it (eg, latch) in the middle of the command/address signal CA window. The clock CK is optimally phased with one of a plurality of or all of the command/address signals. Therefore, the memory device 60 receives a command/address corresponding to the rising edge and the falling edge of the clock signal CK (which can be the rising and falling edges of the clock signals CK and CKB) in the middle of a valid window thereof. Signal CA.

As with the other embodiments set forth herein, a single command/address signal line CA (which can be used to determine a single optimal relative phase of all of the signal lines of a command/address bus 12), for commands Some but not all command/address signal lines of the address bus 12 or all command/address signal lines of the command/address bus 12 (individually or as a group) perform calibration. The results can be used to determine and control the relative phase between the clock CK and the signal line of the command/address bus 12, the signal line of the command/address bus 12 or as a single group (eg, command address) All signal lines of the bus are sent with the same optimal phase relative to the clock CK Number), that is, each of the signal line groups of the command/address bus 12 has one of the best relative phases determined by the memory controller 50 and can be shared during normal operation. The circuit is operative to determine the best relative phase - for example, the CA phase/timing controller 208) or individually (eg, each of the signal lines of the command/address bus 12 has a decision by the memory controller 50) A corresponding optimal phase and may have dedicated (non-shared) circuitry during normal operation to achieve this determined optimal relative phase, such as a dedicated CA phase/timing controller 208).

22 is a block diagram showing another example of a memory system that can be used to implement one or more of the command/address alignment embodiments set forth herein.

Referring to FIG. 22, a memory system 70 can include a memory controller 80 and a memory device 90. The memory controller 80 can include a clock generator 801, a command/address (CA) generator 802, a CA generation reference unit 803, a register unit 804, a comparator 806, and a phase/timing controller. 808 and data input/output units 810 and 812. The memory controller 80 supplies the clock signal CK generated by the clock generator 801 to the memory device 90 through the clock signal line 11.

The memory system 70 additionally includes a CA reference signal line CA_Ref 16. The CA reference signal line CA_Ref 16 transmits a signal CA_Ref _s and receives a CA reference calibration information CA_Ref _{r in} the CA calibration mode of command/address CA communication between the memory controller 80 and the memory device 70. The CA reference calibration information CA_Ref _{r is} provided to the CA_Ref comparator 806 to determine one of the results of one of the CA calibration cycles (eg, by P or F), which is provided to the phase/timing controller 808 to provide a control Signal CTRL to CA generator 802 adjusts the relative phase or timing of command/address signal CA relative to clock CK. Since the CA reference signal line CA_Ref 16 is provided, the calibration of the command/address CA communication can be performed simultaneously with the transmission of the command/address signal CA via the command/address bus.

The CA generator 802 generates a CA signal having one of the phases or timings that have been determined (possibly adjusted) in response to the control signal CTRL, and transmitted to the memory device 90 via the command/address bus. The CA generation reference unit 803 can be configured identically to the CA generator 802 (e.g., can use the same circuit configuration from the same unit memory bank of a memory bank library) and generate a transmitted command/address reference signal CA_Ref _s . By sending a command / address lines may be CA_Ref _s reference signal with a command generated by the CA of the same or generator 802 is completely independent of the command / address signal / address signal CA the CA. Can be determined by one of the phase control signal CTRL generate transmission command / address reference signal CA_Ref _s, the system may provide a control signal CTRL (or Freedom of Information CA phase timing controller 808 provides the derived) by the CA phase timing controller 808. The control by the control signal CTRL transmitted via the command / address signal of reference phase CA_Ref _s may be generated by the CA system and the same phase of an output 802 of the CA signal.

The transmitted command/address reference signal CA_Ref _{s is} provided to the scratchpad unit 804 to store the information represented by the transmitted command/address reference signal CA_Ref _s . The transmitted command/address reference signal CA_Ref _{s is} supplied to the CA reference signal line CA_ref 16 that transmits the transmitted command/address reference signal CA_Ref _s to the memory device 90.

The register unit 804 stores information represented by the transmitted command/address reference signal CA_Ref _s . The comparator 806 compares the information of the transmitted command/address reference signal CA_Ref _s stored in the register unit 804 with the received command/bit received from the memory device 90 via the data input unit 810 of the memory controller 80. The address references the calibration information CA_Ref _r . The comparator 806 compares the information of the transmitted command/address reference signal CA_Ref _s stored in the CA_Ref register 804 with the received command/address reference calibration information CA_Ref _r to generate a pass signal P or a fail signal F. The lines in the same manner with respect to other embodiments described herein set forth the manner, for each cycle of the command / address calibration of a communication (transmission in each cycle corresponding to a particular one of the one CA_Ref _s phase) performed by the signal The generation of P or fail signal F, and the group of pass and fail F signals generated during the command/address communication calibration mode can be used to determine the command/address signal transmitted between the CA bus 12 and the clock CK. An optimal relative phase.

For example, phase/timing controller 808 generates a control signal CTRL that indicates a phase shift of one of command/address signals CA based on a set of pass or fail signals P or F generated by comparator 808 during the calibration mode. The control signal CTRL is used to determine (eg, adjust or maintain) the relative phase or timing of the command/address signal CA and the clock CK, and generate a phase adjusted command/address signal transmitted via the command/address bus 12 CA.

The data input unit 810, which can be an input buffer and/or amplifier, receives the received command/address reference calibration information CA_Ref _r from the memory device 90 via the CA reference signal line CA_ref 16, and receives the received command/address The reference calibration information CA_Ref _{r is} delivered to the comparator 806. A data output unit 812, which may be an output buffer and/or amplifier, receives the transmitted command/address reference signal CA_Ref _s generated by the CA generation reference unit 803 and transmits the transmitted command/address reference signal CA_Ref _s to the CA. Reference signal line CA_ref 16.

The memory device 90 includes a clock buffer 902, a CA receiver 904, a CA reference receiver 906, and input/output units 908 and 910 (which may be input and output buffers and/or amplifiers, respectively). The clock buffer 902 receives the clock signal CK transmitted through the clock signal line 11 to generate an internal clock signal ICK. The internal clock signal ICK may have the same timing (eg, phase and duty cycle) as the external clock signal CK, or it may be different (eg, in terms of phase and/or duty cycle). The CA receiver 904 receives the wafer select signal /CS time pulse enable signal CKE and the command/address signal CA transmitted through the command/address bus 12 . The clock enable signal CKE can be used as a pseudo-command as one of the commands/address signals CA that are transmitted through the command/address bus 12 as explained elsewhere herein. When the clock enable signal CKE is in an active state, the CA receiver 304 can receive the command/address signal CA.

The input unit 908 receives the transmission via a transmission 80 with reference to the CA bus CA_ref 16 from the memory controller via the command / address reference signal CA_Ref _s, and be transmitted to the CA receiver 906. The reference receiver. The CA Receive Reference Receiver 906 can be configured the same as the CA Receiver 904. The CA receive reference receiver 906 receives the wafer select signal /CS, the clock enable signal CKE, and the transmitted command/address reference signal CA_Ref _s transmitted through the CA reference bus CA_ref 16, and is on a rising edge of the clock ICK and / The transmitted command/address reference signal CA_Ref _s is latched at either the falling edge (which may be the same time as the edge of the external clock CK or the time dependent on the edge of the external clock CK). The information transmitted by the CA_Ref receiver 906 and transmitted by the command/address reference signal CA_Ref _s is received by the command/address reference calibration information CA_Ref _r , and the received command/address reference calibration information CA_Ref _r can be The information represented by the transmit command/address reference signal CA_Ref _s is the same or different (for example, based on the relative phase of the clock CK and the transmitted command/address reference signal CA_Ref _s during this cycle of command/address calibration) The timing of the latch).

The received command/address reference calibration information CA_Ref _r may be the same as the information obtained from one of the signals received via the CA bus 12, and the information is output from the CA receiver 904 to a source within the memory device 70 (at When the CA receiver 904 receives the wafer selection signal /CS, the clock enable signal CKE, and the command/address signal CA transmitted through the command/address bus 12, the information is input to the CA receiver in response to the internal clock signal ICK. After 904). The received command / address reference calibration information transmission system CA_Ref _r CA CA_ref 16 and the reference signal line 910 via the output unit 80 to the memory controller.

The memory system 70 can perform a plurality of cycles of CA calibration, an exemplary single cycle being set forth below. The CA generator 802 of the memory controller 80 adjusts the phase or timing of the command/address signal CA in response to the control signal CTRL of the phase/timing controller 808. CA generating unit 803 generates a reference can be tied to the command / address signal CA sent by the same command / address reference signal CA_Ref _s, CA and the reference signal line a reference signal CA_ref 16 CA_Ref _s transmitted to the memory via the transmission via command / address Body device 90. The CA reference receiver 906 of the memory device 90 inputs the transmitted command/address reference signal CA_Ref _s at a time according to the internal clock signal ICK and enabled by the clock enable signal CKE, and generates the received command/bit. The address references the calibration information CA_Ref _r . The command/address reference calibration information CA_Ref _r received by the memory device 90 is transmitted to the memory controller 80 via the CA reference signal line CA_ref16.

The received command/address reference calibration information CA_Ref _{r is} provided to comparator 806. Comparator 806 compares the transmitted command/address reference signal CA_Ref _s with the received command/address reference calibration information CA_Ref _r to generate a pass signal P or a fail signal F for this cycle of command/address calibration. Through the repetition of the aforementioned CA calibration cycle, the phase/timing controller 808 of the memory controller 80 determines an optimum relative phase between the CA signal transmitted by the CA generator 802 via the CA bus 12 and the clock CK. This optimal relative phase may be selected as set forth elsewhere herein and may facilitate the CA receiver 904 to input (eg, latch) the timing input corresponding to the middle portion of the command/address signal CA logic window in normal operation. The command/address signal transmitted by the CA bus 12 during the period (eg, such that the middle of the command/address signal logic window corresponds to one of the clock signal CK and/or the internal clock signal ICK).

Although the calibration of a single command/address signal CA for one of the CA busses 12 has been set forth in the current embodiment, the calibration illustrated can be used to adjust the phase of the signal transmitted over all of the signal lines of the command/address busbar 12. . This can be done using only a single CA_ref signal line 16 (applying its calibration results to all signal lines of the command/address bus 12). Alternatively, the CA_ref signal line 16 may be one of a plurality of CA_ref signal lines, each of the plurality of CA_ref signal lines being used to adjust one of the CA bus bars 12. Corresponding to signal lines or signal line groups. Additionally, each of the plurality of CA_ref signal lines 16 may be adjacent to one of the signal lines of the CA bus 12 for calibration thereof (eg, immediately adjacent to 2 or 3 signal lines or at 2 or 3 signals) Inline). This may include a plurality of CA_ref signal lines interposed between the signal lines of the CA bus 12. Moreover, in an alternate embodiment, the CA_ref line 16 may be used for other purposes (eg, transmission of power or other information signals) during modes other than CA calibration (eg, normal operation).

The memory controller and memory device described herein can take a wide variety of forms. For example, the memory controller can include a semiconductor wafer or can be a package (eg, one or more wafers encapsulated in a protective casing (eg, resin)). The memory device can include a semiconductor wafer or can be a package (eg, one or more semiconductor memory wafers encapsulated in a protective casing (eg, a resin)). The memory device can be a NAND flash memory (including 3D NAND flash memory), DRAM, PRAM, RRAM, and/or MRAM. The memory controller and memory device can be packaged in the same semiconductor package (eg, a memory controller chip and one or more memory chips stacked together and encapsulated in a package). The controller/device package can be a package overlay (POP).

The controller may include a portion of a master memory chip that acts as one of the master devices of one or more slave memory chips, the calibration being performed for one of the master memory chip and the slave memory chip or Command/address communication between multiples is performed. The master memory chip and the one or more slave wafers can be stacked and communicated through a through substrate via (TSV) (eg, via via) of each of the wafers connected to each other (where the clock signal is described herein) 11, command / bit The address bus 12, the DQ bus 13, the chip enable signal line / CS, the clock enable CKE, and the data strobe line DQS are all formed by one or more of the through holes. The memory controller and memory device can be a component of a memory card (embedded or removable).

The memory controller and the memory device can be mounted on a plurality of circuit boards that can include the same printed circuit board or a single computing system: a printed circuit board including components of a memory module, A motherboard or other printed circuit board (for example, in a mobile phone, personal information assistant (PDA) or tablet) of a computing device (for example, a personal computer).

For some applications, the controller and memory device can be integrally formed by the same single piece of semiconductor substrate (eg, portions of the same semiconductor wafer). For example, the memory can be a microprocessor, a communication chip, or an embedded memory in a digital signal processor.

Moreover, although the above embodiments have been described as being associated with a memory system, the present invention can also be used to calibrate other command/address communications external to the memory system (eg, one of the motherboard interconnects in a server, computer, etc.) Between the nodes) to facilitate communication between devices attached to the motherboard.

Moreover, while these embodiments illustrate one example of command/address calibration information transmitted from a memory device to a memory controller, the interpretation of a command/address calibration signal sent from the memory controller to the memory device ( For example, the memory device is used as an input), however, other types of information can also be sent. For example, if the test pattern is predetermined (whether programmed or at the time of command/address calibration), the memory device is The body can determine whether the information it has entered is input without error in response to providing a P or F failure indication to the memory controller. Alternatively, the memory device can contain between a plurality of bits of the test pattern that are expected to be formed during a calibration cycle and/or between the bits of the bit that are received side by side as part of the test pattern. The logic of a relationship (and thus a pass or fail signal sent to one of the memory controllers).

In addition, calibration of command/address communication has been illustrated to calibrate timing for inputting command/address signals into one of the memory devices, however, other types of calibration of command/address communications may be performed. For example, for each cycle of command/address communication calibration, the controller can change a signal power, a terminal impedance of the controller and/or the memory device (eg, an adjustable die termination (pull-up and pull-up) / or series)) and / or command / address calibration signal one of the load cycle.

It should be noted that this description illustrates the calibration of a command/address communication by means of a calibration test pattern signal transmitted via a command/address bus. It is contemplated that certain embodiments will allow some but not all of the signal lines of a command/address bus to be shared for both command and address information during normal operation. For example, a design may require 22 address bits and 10 command bits, which may result in one or more of the signal lines of the command/address bus that are not used to transmit a command bit (eg, If the command/address bus 12 is composed of eleven signal lines transmitting twenty-two (22) address bits (two groups of eleven (11) bits in sequence), the communication may be Only ten (10) bits of one of the eleven (11) signal lines are required, leaving one of the signal lines unused for command communication). As another example, the command/address bus is located There are signal lines available for command communication, but some of these signal lines may not be used for address communication (for example, eleven bits of a command message and twenty (20) bits of address information) One of the signal lines that can leave one eleven signal line commands/address bus bars is not used for address communication).

Although the present invention has been particularly shown and described with reference to the exemplary embodiments of the present inventive concepts, which are provided for illustrative purposes, and those skilled in the art will appreciate that various modifications can be made in accordance with the inventive concepts. And equivalent to other embodiments. Therefore, the scope of the inventive concept should be defined by the scope of the accompanying claims.

10‧‧‧ memory system

11‧‧‧clock signal line

12‧‧‧Command/Address Bus

13‧‧‧Information signal bus

15‧‧‧Single calibration bus/calibration busbar

20‧‧‧ memory controller

30‧‧‧ memory device

40‧‧‧ memory system

50‧‧‧ memory controller

60‧‧‧ memory device

70‧‧‧ memory system

80‧‧‧ memory controller

90‧‧‧ memory device

201‧‧‧ clock generator

202‧‧‧Command/Address Generator

203‧‧‧Command/Address Transmitter/

204‧‧‧Storage register

206‧‧‧ comparator

208‧‧‧ Phase/Timing Controller

210‧‧‧Input/output unit

212‧‧‧Input buffer

214‧‧‧Selection unit

216‧‧‧Output buffer

302‧‧‧clock buffer

304‧‧‧Command/Address Receiver

310‧‧‧Data input/output unit

312‧‧‧Selection unit

314‧‧‧Output buffer

316‧‧‧Input buffer

801‧‧‧ clock generator

802‧‧‧Command/Address (CA) Generator

803‧‧‧Command/address generation reference unit

804‧‧‧ register unit

806‧‧‧ Comparator

808‧‧‧ Phase/Timing Controller

810‧‧‧Data input unit

812‧‧‧ data output unit

902‧‧‧clock buffer

904‧‧‧Command/Address Receiver

906‧‧‧Command/Address Reference Receiver

908‧‧‧Input unit

910‧‧‧Output unit

CA‧‧‧Command/Address Signal

CA_Cal‧‧‧Single calibration bus/calibration busbar

Command/address reference calibration information received by CA_Refr‧‧‧

CA_Refs‧‧‧ sends command/address reference signal

CA1‧‧‧First Command/Address Signal

CA2‧‧‧First Command/Address Signal

CA3‧‧‧ Command/Address Signal

CA4‧‧‧ Command/Address Signal

CAnF‧‧‧ Command/Address Signal

CAnR‧‧‧ Command/Address Signal

Command/address calibration information received by CA _r ‧‧‧

CA _s ‧‧‧Send command/address information

CA _sp1 ‧‧‧ initial command/address signal

CA _sp2 ‧‧‧ phase-adjusted command/address signal

CAxF‧‧‧ Command/Address Signal

CAxR‧‧‧ Command/Address Signal

CAyF‧‧‧Command/Address Signal

CAyR‧‧‧ Command/Address Signal

CK‧‧‧ clock signal

CKB‧‧‧ clock signal

CKE‧‧‧ clock enable signal

CMD/ADDR‧‧‧ command/address signal

/CS‧‧‧Wafer selection signal

CTRL‧‧‧ control signal

DQ‧‧‧ data signal

DQS‧‧‧ data strobe clock

ICK‧‧‧Internal clock signal

MRW#41‧‧‧First Mode Register Command

MRW#42‧‧‧Second Mode Register Command

MRW#43‧‧‧ Third Mode Register Command

MRW#44‧‧‧4th Mode Register Command

R_DATA1‧‧‧Reading data

R_DATA2‧‧‧Reading data

SEL1‧‧‧first selection signal

SEL2‧‧‧Second selection signal

W_DATA1‧‧‧Write data

W_DATA2‧‧‧Write information

1 and 2 are timing diagrams for explaining the concept of command/address calibration; FIG. 3 is a block diagram for explaining one of memory systems for performing command/address calibration; FIG. 4A and FIG. 4B are for A diagram illustrating, for example, command/address calibration performed by the memory system shown in FIG. 3; FIG. 5 is a memory that can be used to implement one or more of the command/address calibration embodiments set forth herein a block diagram of a first example of a body system; FIG. 6 is a table for explaining a command/address calibration method according to a first embodiment; FIG. 7 is for explaining one of the first embodiment according to a first embodiment A schematic diagram of a mode register command setting method; FIG. 8 is a diagram showing one example of a mapping between a command/address signal and a DQ pad according to an embodiment; FIG. 9 is a diagram for Declaring a command/address signal and DQ according to an embodiment FIG. 10 is a diagram for explaining one of the command/address calibration methods according to another embodiment; FIG. 11 is a diagram for explaining another embodiment according to another embodiment. FIG. One example of an example of a mapping between a command/address signal and a DQ pad; Figure 12 shows another example for illustrating a mapping between a command/address signal and a DQ pad in accordance with another embodiment FIG. 13 is a diagram for explaining one of command/address calibration methods according to another embodiment; FIG. 14 is for explaining a mode register command setting method according to another embodiment. FIG. 15 is a diagram showing one example of a mapping between a command/address signal and a DQ pad according to another embodiment; FIG. 16 is a diagram for explaining another embodiment according to another embodiment. Another example of another example of a mapping between a command/address signal and a DQ pad; FIG. 17 shows another example for illustrating a mapping between a command/address signal and a DQ pad in accordance with another embodiment One of the drawings; FIG. 18 is a diagram of a command/address calibration method for another embodiment; 19 shows a diagram for illustrating one of the examples of mapping between a command/address signal and a DQ pad in accordance with another embodiment; FIG. 20 is a diagram showing a command/address signal for illustrating another embodiment. One of the other examples of mappings with DQ pads; Figure 21 is a diagram showing one or more of the commands that may be used to implement the ones described herein / Block diagram of another example of a memory system of one of the address alignment embodiments; and FIG. 22 is a diagram showing another memory system that can be used to implement one or more of the command/address alignment embodiments set forth herein. A block diagram of an example.

CA‧‧‧Command/Address Signal

CAxF‧‧‧ Command/Address Signal

CAxR‧‧‧ Command/Address Signal

CAyF‧‧‧Command/Address Signal

CAyR‧‧‧ Command/Address Signal

CK‧‧‧ clock signal

CKE‧‧‧ clock enable signal

/CS‧‧‧Wafer selection signal

MRW#41‧‧‧First Mode Register Command

MRW#42‧‧‧Second Mode Register Command

Claims (48)

A method of communicating with a memory device, comprising: transmitting a calibration command via a command/address bus; transmitting a sequence of n first test signals via the command/address bus, wherein n is equal to 2 Or a larger integer; transmitting, together with each of the n first test signals, a clock signal via a first clock line, each of the n first test signals being relative to the One of the first to nth phases is transmitted by one of the clock signals, each of the first to nth phases being different from each other; receiving via the data bus via the command/address bus Transmitting the n first test signals of the sequence to derive a sequence of n second test signals; comparing the n first test signals with the n second test signals; and responding to the comparing the n first The test signal and the received n second test signals determine a preferred phase of the third signal to be transmitted via the command/address bus with respect to one of the clock signals. The method of claim 1, wherein each of the n first test signals comprises juxtaposed via the command/address bus followed by a second plurality of bits transmitted in parallel via the command/address bus The first plurality of bits sent. The method of claim 2, wherein each of the first plurality of bits and the second plurality of bits comprises a packet. The method of claim 2, wherein for each of the n first test signals, one of the rising edges of the clock signal and one of the clock signals is decreased The first plurality of bits are transmitted along one of the edges, and the second plurality of bits are transmitted at the other of the rising edge of the clock signal and the falling edge of the clock signal. The method of claim 1, wherein at least a portion of the n second test signals of the sequence are received via a data strobe line. The method of claim 1, wherein at least a portion of the n second test signals of the sequence are received via a line dedicated to calibration during at least one calibration mode. The method of claim 1, wherein the comparing the n first test signals with the n second test signals comprises: determining whether each of the n second test signals is the same as a corresponding first test signal . The method of claim 1, wherein the preferred phase is determined to correspond to one of the first to nth phases. The method of claim 8, wherein determining the preferred phase comprises: determining a phase sequence of the first to nth phases, each phase of the phase sequence corresponding to the n seconds that have been determined to be valid One of the test signals. An interface training method, comprising: transmitting a first calibration signal to a semiconductor device via a command/address bus; transmitting a clock signal to the semiconductor device together with the transmitting of the first calibration signal, The clock signal provides a timing to the semiconductor device to latch a logic level of the first calibration signal; receiving a second school from the semiconductor device via a data bus a quasi-signal, the second calibration signal being derived from a latched logic level of the first calibration signal; and the transmitting of the clock signal, along with the command/address bus, transmitting a command and an address signal to the quasi-signal The semiconductor device, the phase between the command and the address signal and the clock signal is responsive to the second calibration signal. The method of claim 10, further comprising transmitting a read request signal to the semiconductor device via one of the first lines separated from the command/address bus while transmitting the first calibration signal. The method of claim 11, wherein the first line is a clock enable line. The method of claim 10, wherein the first calibration signal comprises transmitting a data packet sequence at a rate that is at least twice a rate of a period of the clock signal. The method of claim 10, wherein the transmitting of the first calibration signal to the semiconductor device comprises transmitting a training pattern via each of the plurality of lines of the command/address bus. The method of claim 14, wherein the training pattern is the same for each of the plurality of lines of the command/address bus. The method of claim 14, wherein the transmitting of the command and address signals via the command/address bus includes: individually adjusting each of the plurality of lines of the command/address bus The phase between the command and the address signal and the clock signal. The method of claim 14, wherein the transmitting of the command and the address signal via the command/address bus includes: via the command/address bus One of the first lines transmits a first signal relative to a first phase of the clock signal and a second line via the command/address bus bar to transmit a second phase relative to one of the clock signals The second signal. The method of claim 10, wherein transmitting the command/address signal comprises transmitting both address information and command information via each of a majority of the command/address bus. The method of claim 10, wherein the semiconductor device is a first semiconductor device, and wherein the method further comprises: transmitting a third calibration signal to the second semiconductor device via the command/address bus; The transmitting of the three calibration signals sends the clock signal to the second semiconductor device, the clock signal providing a timing to the second semiconductor device to latch the logic level of the third calibration signal; Receiving a fourth calibration signal from the second semiconductor device, the fourth calibration signal being derived from a latched logic level of the third calibration signal; via the command/address along with the transmission of the clock signal The bus sends a command and address signal to the second semiconductor device, and a phase between the command and the address signal and the clock signal is responsive to the fourth calibration signal. A method of calibrating communication via a command/address bus of a memory device, comprising: receiving a clock signal via a clock signal line; Receiving, by the command/address bus, a calibration command; receiving, by the command/address bus, a first test data packet to generate the first information; and one of the clock signals The falling edge receives a second test data packet via the command/address bus to generate the second information; and transmits the first information and the second information via a data bus. The method of claim 20, further comprising receiving a command and an address via the command/address bus at the rising and falling edges of the clock signal. A semiconductor device comprising: a clock generator configured to generate a clock signal; a clock output terminal coupled to the clock generator and configured to output the clock signal; a command generator a circuit configured to generate a command; an address generator circuit configured to generate an address; a plurality of command/address terminals; a command/address buffer having a plurality of connections to the plurality of One of a command/address terminal output coupled to the command generator circuit and the address generator circuit for transmitting commands/bits from outside the semiconductor device via the plurality of command/address terminals An address controller; a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the plurality of command/address terminals, n being greater than one integer of two, The phase controller is configured to adjust a phase of at least some of the n training patterns relative to one of the clock signals; a read enable circuit configured to generate a read enable signal; a first terminal coupled to the read enable circuit to transmit the one of the n training samples when the sequence is transmitted Reading an enable signal; a data terminal; and a data buffer coupled to the data terminals, wherein the phase controller is configured to adjust in response to the first information received by the data buffer via the data terminals The command and address signals are phased relative to one of the clock signals. The semiconductor device of claim 22, wherein the phase controller is configured to control the command/address buffer to transmit an incoming calibration mode command via the command/address terminals. The semiconductor device of claim 22, wherein the first information received by the data buffer via the data terminals is responsive to the n training patterns. The semiconductor device of claim 24, wherein the first information received by the data buffer via the data terminals is derived from latched logic levels of the n training patterns. The semiconductor device of claim 22, further comprising: a clock enable circuit coupled to the first terminal and configured to generate a clock enable signal during one of the time when the n training patterns of the sequence are not transmitted. The semiconductor device of claim 22, wherein the phase controller is configured to individually adjust the commands and bits for each of the command/address terminals The address signal is phased relative to one of the clock signals. A semiconductor device comprising: a clock generator configured to generate a clock signal; a clock output terminal coupled to the clock generator and configured to output the clock signal; a command generator a circuit configured to generate a command; an address generator circuit configured to generate an address; a plurality of command/address terminals; a command/address buffer having a plurality of connections to the plurality of One of a command/address terminal output coupled to the command generator circuit and the address generator circuit for transmitting commands/bits from outside the semiconductor device via the plurality of command/address terminals An address controller; a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the plurality of command/address terminals, n being greater than one integer of two, The phase controller is configured to adjust a phase of at least some of the n training patterns relative to one of the clock signals; a data terminal; and a data buffer coupled to the data terminals, Where the phase control The device is configured to adjust a phase of the command and the address signal relative to the clock signal in response to the first information received by the data buffer via the data terminals, wherein the phase controller is configured to control the The command/address buffer transmits an enter calibration mode command via the command/address terminals, and Wherein the phase controller is configured to control the command/address buffer to transmit each of the n training patterns at a rate that is at least twice the rate of the period of the clock signal as one of the modified Sequence side by side data. The semiconductor device of claim 28, wherein each of the n training patterns is of the same type. The semiconductor device of claim 28, wherein at least some of the n training patterns are different from each other. An electronic system comprising: the semiconductor device of claim 22; a printed circuit board having mounted thereon a semiconductor device as claimed in claim 22, the printed circuit board comprising the commands connected to the semiconductor device of claim 22 / One of the address terminals command/address bus; and a second device mounted on the printed circuit board to be connected to the command/address bus. The system of claim 31, wherein the second device is a semiconductor memory device. A communication method, comprising: receiving a training signal via a command/address bus; receiving a latch signal together with the receiving of the training signal; and latching the training signal in response to at least one edge of the latch signal Generating training signal information; transmitting the training signal information; receiving a command signal and an address signal via the command/address bus; Receiving the latch signal together with the command signal and the receiving of the address signals, the latch signal responding to the transmitted training signal information with respect to one of the command signals and one of the address signals; And latching the command signals and the address signals in response to at least one edge of the latch signal. The method of claim 33, wherein latching the training signal and latching the command signals and the address signals comprises: latching in response to rising and falling edges of the latch signal. The method of claim 34, further comprising: receiving an incoming calibration mode command on the command/address bus; and entering a calibration mode in response to the entering the calibration mode command. The method of claim 35, wherein the entering the calibration mode command is a mode register setting (MRS) command, and wherein the step of entering a calibration mode comprises programming a mode register setting. The method of claim 35, further comprising: receiving an exit calibration mode command on the command/address bus; and exiting a calibration mode in response to the exit calibration mode command. The method of claim 35, further comprising: monitoring the training signal information; detecting the training signal information to include an exit calibration mode command; and exiting the calibration in response to detecting that the training signal information includes an exit calibration mode command mode. The method of claim 33, further comprising: receiving a signal on a first input while receiving a training signal; and enabling latching of the training signal in response to the signal received on the first input. The method of claim 39, wherein the first input is a clock enable input. The method of claim 33, wherein transmitting the training signal information comprises transmitting the training signal information via the command/address bus. The method of claim 33, wherein transmitting the training signal information comprises transmitting the training signal information via one of the pins dedicated to training during at least one calibration mode. A semiconductor device comprising: a command/address terminal; a first terminal; a command/address buffer coupled to the command/address terminal for receiving a command information, address information, and calibration information a command, the command/address buffer is responsive to receiving a clock via the first terminal to receive information received via the command/address terminals; a command circuit coupled to the command/address buffer Providing an internal command to receive the command information and responding to the command information; a decoder coupled to the command/address buffer to receive and decode the address information; and a calibration control circuit coupled to the Command/address buffer, group State to receive the calibration information and transmit the calibration information to an external source. The semiconductor device of claim 43, further comprising: a data terminal; and a data buffer coupled to the data terminals, wherein the calibration control circuit is coupled to the data buffer to calibrate the data via the data terminals Information is transferred to the external source. The apparatus of claim 43, further comprising: a mode register setting, wherein the command circuit is configured to receive an enter calibration mode command, and to program the first code with the first code in response to the enter calibration mode command The mode register is configured to cause the device to enter a calibration mode, wherein the calibration control circuit transmits the calibration information to an external source in response to the first code. The apparatus of claim 45, wherein the calibration control circuit is configured to detect that one of the calibration information received during the calibration mode exits the calibration mode and is configured to cause the mode register setting to be modified thereby causing The device exits the calibration mode. The device of claim 43, wherein the device comprises a dynamic random access memory semiconductor device of a dynamic random access memory array, wherein the decoder is configured to access the dynamic in response to the address information The location within the random access memory array. The device of claim 43, wherein the device comprises one of a NAND flash memory array A NAND flash memory semiconductor device, wherein the decoder is configured to access a location within the NAND flash memory array in response to the address information.