TW201246211A - Memory devices, systems and methods employing command/address calibration - Google Patents

Abstract

During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Description

201246211 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a memory device, system and method, and more particularly to command/address calibration. This application claims the first application of the US Provisional Application No. 61/468,204, filed on March 28, 2011, at the US Patent and Trademark Office, and filed at the Korean Intellectual Property Office on June 23, 2011. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; [Prior Art] In a 5 memory system (for example, a dynamic random access memory (DRAM) system), a signal is transmitted and received via a bus between a memory controller and a DRAM 2 Propagation delay. Propagation delay can be affected by various factors, such as busbars, substrates, or interconnected capacitors or parasitic capacitors such as these. As one of the DRAM data rates increases, a variation in propagation delay and/or propagation delay degrades signal integrity. It is desirable to find a signal skew between the best signal window or the compensation signal, such as between a command signal and a clock signal between the data signal and a clock signal and/or between the address signal and a clock signal. SUMMARY OF THE INVENTION The present invention discloses a command/address calibration method and a memory device and a memory system using command/address alignment. According to one aspect of the inventive concept, a method of communicating with a memory device is provided, the method comprising transmitting a calibration command via a command/location bus; via the command/address I63456.doc -4- 201246211 The row transmits a sequence of 1! first test signals, wherein n is equal to an integer of 2 or greater; together with each of the n first test signals, a clock signal is transmitted via a first clock line 'Then each of the n first test signals is 'the first to the first' transmitted with respect to the first to nth phases of the clock signal; Each of the phases is different from each other; receiving a second test nickname from a sequence of n first test signals respectively derived from the sequence transmitted via the command/address bus via a data bus Comparing the n first test signals with the n second test signals; and comparing the n first test signals with the received second test signals in response to determining the via/bits The signal transmitted by the address bus is preferably phased with respect to one of the clock signals. Each of the n first test signals includes a first-plural number of bits transmitted in parallel via the command/address bus, the first plurality of bits may be followed by the command/address bus The second plurality of bits sent in parallel. Each of the first plurality of bits and the second plurality of bits may include a packet. For each of the n first test signals, the first plurality of bits may be transmitted at one of a rising edge of the clock signal and one of the falling edges of the clock signal and may be The second plurality of bits are transmitted by the rising edge of the clock signal and the falling edge of the clock signal. At least a portion of the n second test signals of the sequence may be received via a data strobe line or via a line dedicated to calibration during at least one calibration mode. 163456.doc 201246211 The method can further include the same as the first corresponding first test signal. Whether each of the first to nth phases of the two test signals is judged to correspond to the one. Determining the preferred phase may be derived from a phase sequence of one of the first to the nth phases, and the helmet &lt; parent phase in the phase sequence corresponds to a second test signal determined to be valid. According to another aspect, the interface training method may include: transmitting a -first calibration signal to a semiconductor device via a command/address bus; and transmitting the same to the first calibration signal (four) Sending to the semiconductor device 'the clock signal provides - timing to the semiconductor device to latch the first calibration signal logic level; receiving - the second calibration signal via the data sink (four) self-conductor device, the second calibration Transmitting a signal from the latched logic level of the first calibration signal; transmitting the command and address signals to the first semiconductor device via the command/address bus with the transmission of the clock signal Command and Health (4) (4) A phase between the clock signals is responsive to the second calibration signal. The method can further include transmitting a read request signal to the semiconductor device via one of the first lines separated from the command/address bus while transmitting the first calibration signal. The first line can be a clock enable line. The first calibration signal can include a data packet of a sequence transmitted at a rate that is at least twice the rate of the period of the clock signal. Transmitting a first calibration signal to the semiconductor device can include transmitting a training pattern via each of a plurality of lines of the command line address block/block address bus. The training pattern may be the same for each of the plurality of lines of the command/address bus. The phase between the command and the address signal and the clock signal can be individually adjusted for each of the plurality of lines of the command/address bus. A first signal may be transmitted via the first line of the command/address bus to transmit a first signal with respect to one of the clock signals, and may be via the command/address address of the second line of the bus bar relative to One of the clock signals transmits a second signal in a second phase. When the semiconductor device is a first semiconductor device, the method can include transmitting a third calibration signal to a second semiconductor device via the command/address bus; along with the transmitting of the third calibration signal Sending a clock signal to the second semiconductor device 'the clock signal number provides a timing to the second semiconductor device to latch a logic level of the third calibration signal; and the data is busted from the second semiconductor device Receiving a fourth calibration signal derived from the latched logic level of the third calibration signal, along with the transmission of the clock signal, via the command/address bus, the command and the address A signal is sent to the second semiconductor device, and a phase between the command and the address signal and the clock signal is responsive to the fourth calibration signal. According to another aspect, a method of calibrating communication via a command/address bus of a memory device can include receiving a clock signal via a clock signal line; receiving a calibration command via the command/address bus One of the rising edge of the clock k and one of the falling edges of the clock signal 163456.doc 201246211 receives a first test data packet via the command/address bus to meet the first Receiving, by the command/address bus, the first measurement type 5 data packet to generate the second information; and the other of the rising edge of the clock signal and the falling edge of the clock signal; And transmitting the first information and the second information via a data bus. The method can include receiving a command and an address via the command/address bus at the rising and falling edges of the clock signal. The invention also encompasses systems and devices. For example, a semiconductor device can include: a clock generator configured to generate a clock signal; a clock output terminal 'connected to the clock generator and configured to output the clock signal a command generator circuit 'which is configured to generate commands; an address generator circuit 'which is configured to generate an address; a plurality of command/address terminals; a command/address buffer with a connection Outputting to one of the command/address terminals, the command/address buffer being coupled to the command generator circuit and the address generator circuit for transmitting commands from outside the semiconductor device via the command/address terminals and a bit signal; a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the command/address bus, the η system being greater than an integer of 2, The phase controller is configured to adjust a phase of at least some of the n training patterns relative to the one of the clock signals; a data terminal; and a data buffer coupled to the data terminals, wherein The phase Is prepared by adjusting the set state in response to the command and address signal via a first terminal receiving the data information such that data from the buffer to the one with respect to the phase of the clock signal. The system can include such devices and/or implement such methods. The present invention is not limited to the features of the present invention, and the scope and applicability thereof will be apparent from the following detailed description. [Embodiment] An exemplary embodiment of the inventive concept will be more clearly understood from the following detailed description. The embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings in which: FIG. The exemplary embodiments of the present invention are provided to more fully explain the inventive concepts to those skilled in the art. However, the invention may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. That is, the exemplary embodiments are merely examples of their existence: numerous embodiments and variations that do not require the various details disclosed herein. Various changes can be made to the inventive concept, and the inventive concept can have various forms. However, the embodiments are not intended to limit the invention to the specific embodiments disclosed, and all such modifications, equivalents and substitutions are included in the spirit and scope of the invention. In all the figures, the same component symbols refer to the same components. In the accompanying drawings, the structure may have been exaggerated for clarity. The terminology used herein is for the purpose of describing the embodiments and is not intended to As used herein, the singular forms " It will be further understood that the word "comprising", "including" and / or "having" (and the associated wording) stipulates the existence of the stated features, number, steps, operations, components, components, or a combination thereof, but does not exclude one or more The existence or addition of other features, numbers, steps, operations, components, components, or combinations thereof, unless otherwise stated. It will be understood that when a component is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or a device can be present. In contrast, when a component is referred to as being "directly connected" or "directly connected to another component," there is no intervening component. As used herein, the phrase "and/or" includes the recited. Any and all combinations of one or more of them may be abbreviated as "/". It will be understood that 'the various elements may be used in the context of the first, __le, and the like, but such elements should not be limited to such terms. These terms are only used to distinguish one element from another. For example, a first signal can be referred to as a second signal, and similarly, a second signal can be referred to as a first k number without departing from the teachings of the present disclosure. All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the <RTIgt; It will be understood that the wording (such as the term defined in a commonly used dictionary) should be interpreted as having one meaning consistent with its meaning in the relevant technical context, without the meaning of being idealized or overly formalized. To explain, unless explicitly stated in this article. A high speed operation and low power consumption are desired from a semiconductor memory device. For example, it can be expected to meet low power double data rate (LPDDR)

Specification of Dynamic Random Access Memory (DRAM). An LPDDR DRAM system transmits and receives data bidirectionally between a DRAM and an external device (e.g., a memory controller) on both the rising and falling edges of a clock signal. 163456.doc 201246211 As one of the methods of accelerating memory operation, commands and addresses can be transmitted to a memory device (for example, a memory chip, for example, a DRAM) at both the rising and falling edges of a clock signal. Non-NAND flash memory chip). The memory device is configured to latch command and/or address information at both the rising and falling edges of the clock signal. A common signal for transmitting a command signal and an address signal is referred to as a command/address signal CMD/ADDR or CA. Pins, terminals, bus bars, internal conductors, or other signal paths for transmitting command/address signals may also be referred to herein using the acronym CA. Figures 1 and 2 are timing diagrams illustrating one example of command/address calibration.

Referring to FIG. 1, the relative timing of a pair of clock signals (clock signal pair CK and CKB) and a plurality of command/bit-address signals CMD/ADDR can be adjusted (either together or individually) such that each command/bit The middle of the address CMD/ADDR window is positioned to optimally clock an input operation of the memory device (e.g., a latch operation). Figure 1 shows that the center portion of each command/address CMD/ADDR window has been adjusted to intersect the falling edge of the clock signal CK with the falling edge of the clock signal CK (or vice versa, ie, the pulse signal) The command/address signal CMD/ADDR of one of the timings when one of the rising edges of the CKB intersects the falling edge of the clock signal CK. The intersection may correspond to one of the time when the clock signals CK and CKB are equal to each other (e.g., have the same voltage level). Although Figure 1 shows only the command/address CMD/ADDR window for a command/address CMD/ADDR signal (eg, one of the conductors on a plurality of conductor CMD/ADDR bus bars), multiple commands/addresses CMD/ADDR 163456.doc •11 · 201246211 Signals (eg, multiple command/address CMD/ADDR signals received on separate CMD/ADDR signal paths) may each be as shown in Figure 1. The following discussion is related to each such command/address CMD/ADDR signal. The command/address signal timing is adjusted or matched to the rising/falling edges of the clock signals CK and CKB. Since the middle of the command/address CMD/ADDR window is at one of the intersections between the rising and falling edges of the clock signals CK and CKB, the command/address CMD can be maximized or otherwise improved. One of the /ADDR timing margins. Figure 1 shows the relative timing of one of the clock signals CK and CKB and the command/address signal CMD/ADDR, as seen by the memory device receiving one of these signals. The clock signals CK and CKB and the command/address signals CMD/ADDR can be generated by an external source (for example, a memory controller, a CPU, a host computer, etc.) and the clock signal CK generated by the external source and The relative timing between the CKB and the command/address signal CMD/ADDR can be changed during transmission, and thus, the relative timing produced can be different from the relative timing experienced by the memory device (eg, relative timing generated by an external source) It can be different from the relative timing shown in Figure 1. Due to changes between signal paths (eg, changes in layout, signal drive capability, etc.), during transmission of clock signals CK and CKB and command/address signals CMD/ADDR from an external source to a memory device, A propagation time difference is generated between the clock signals CK and CKB and the command/address signal CMD/ADDR. As shown in FIG. 2, the middle of the command/address CMD/ADDR window can be used to reduce the timing margin of the command/address CMD/ADDR before or after the rising and falling edges of the clock signals CK and CKB. . 163456.doc •12- 201246211 In the four command/address signals CMD/ADDR (CA1, CA2, CA3 and CA4) shown in Figure 2, for the first command/address signal CMD/ADDR CA1 and second The command/address signal CMD/ADDR CA2, the timing of the clock signals CK and CKB can lag between the windows of the CA1 and CA2 signals. If the timing of the first command/address signal CMD/ADDR CA1 and the second command/address signal CMD/ADDRCA2 is postponed by calibration, the middle portion of each command/address CMD/ADDR window of CA1 and CA2 can be located. Corresponding to an intersection between the rising edge and the falling edge of the clock signals CK and CKB. When received by the memory device after this delay, the middle portion of each command/address CMD/ADDR window of CA1 and CA2 can occur on the rising/falling edges of CK and CKB. For the fourth command/address signal CMD/ADDR CA4, the timing of the delayed clock signals CK and CKB can be delayed by calibration or the timing of the fourth command/address signal CMD/ADD-R CA4 can be advanced to make each The middle of the command/address CMD/ADDR window is at a position corresponding to an intersection between the rising edge and the falling edge of the clock signals CK and CKB. 3 is a block diagram of an exemplary memory system 10 for performing command/address calibration. Referring to FIG. 3, the memory system 10 includes a memory controller 20 and a memory device 30, a clock signal line 11, A command/address bus 12 and a DQ bus 13 are connected therebetween. A clock signal CK generated by the memory controller 20 is supplied to the memory device 3 through the clock signal line 11. The clock signal CK can be provided as a continuous alternating inverted signal together with an inverted clock signal CKB. The inverted clock signal CKB may be provided with the clock signal 163456.doc •13·201246211 ck, that is, generated by the memory controller 20 and provided to the memory device 30 (not shown in FIG. 3). The intersection between the pair of clock signals CK and CKB detects the rising and falling edges of the clock signals ck and CKB, thereby improving the timing accuracy. A single clock signal CK (non-transmission clock signal cKB) may also be supplied to the clock signal line i as a continuous alternate inverted signal. This embodiment reduces the signal lines (and terminals) between the stealth device 30 and the § memory controller 20. In this case, to identify the rising and falling edges of the clock signal CK, the clock signal ck and a reference voltage Vref can be compared with each other. If noise fluctuation occurs in the reference voltage Vref, a shift occurs in the detection of the clock signal CK, thereby degrading the timing accuracy compared to the use of the clock signal pair CK and CKB. Therefore, it is desirable to transmit successive alternating inverted signals complementary to each other by using the clock signals CK and CKB. In this case, the clock signal line 11 may include two signal lines for transmitting the clock signal CK and the pulse signal CKB. The clock signal ck as set forth in the embodiment of the inventive concept can be described as a clock signal pair CK and CKB. For the sake of simplicity; the clock signal is described as CK and CKB as the clock signal CK. The command/address signal CA generated by the memory controller 2 is supplied to the memory device 3 via the command/address bus. The command/address bus 12 can carry a command signal or an address signal to the memory device 3 (except at any time) and/or the command/address bus 12 can simultaneously output a command signal and The address signal is transmitted to the memory device 3〇. The memory controller 2 can transmit a command mode/address calibration mode via a command/address bus 12 to transmit a mode register setting (MRS) command. The MRS command can include a 163456.doc is 201246211 quasi-mode entry command and a calibration mode exit command. A calibration start signal or a calibration end signal indicating one of the calibration mode exit commands may be transmitted through the command/address bus 12 to indicate a calibration mode entry command. When the command/address bus 12 is composed of command/address signals CA of n signal lines (for example, conductors) (where η is a natural number), and is input at the rising and falling edges of the clock signal CK When the command/address signal (: eight (for example, in a double: data rate (10) R) transmits the command/address signal CA), each clock ring can transmit 2n bits through the command/address bus 12 The command/address ca information is supplied from the memory controller 20 to the memory device 3A. Entering at the rising edge of the clock signal ck - the command/address signal ca and one of the command/address signals ca input at the falling edge of the clock signal ck can each constitute a command/bit containing n bits Different groups of address CA information. In normal operation, the -DQ bus 13 transmits a data signal DQ between the memory controller 2 and the memory device 30 (for example, in the write-to-write operation, the data signal DQ is transmitted from the controller to the memory. The body device 3〇, and transmits the data signal Dq from the memory device 3〇 to the memory controller 2G in a reading # 〇 information about the command/address calibration (described in detail below) It can be output on the DQ bus 13 to be supplied to the memory controller. The Q bus 13 is connected to the DQ pads (and/or other device terminals, such as solder bumps) of both the memory controller 2 and the memory device. The mapping of the calibration command/address information signal and DQ塾 can be set in various ways. For example, when the memory device 3's data signal DQ has a bit structure x32 (DQ[31:0]), the number of DQ bus lines is 32. When the command / & it U consists of 1 conductor and the command/address signal is transmitted at the rising and falling edges of the clock signal 163456.doc •15· 201246211 ck, the time is transmitted. Each clock cycle of the pulse, the memory device 30 can receive a command/address signal CA of 2 bits. Since 0 (the number of bus bars 32 is greater than the number of command/address signals 20), each DQ bus bar can correspond to a single bit in the command/address signal bit CA, thereby providing a single bit. Command/address signal bit information (for example, two DQ bus lines can transmit command/address information about command/address calibration of one of the command/address bus bars 12). Performing a mapping such that for each cycle of the clock signal CK, one of the command/address signals rounded at the rising edge of the clock signal CK is output to one DQ pad [9:0] and will One value of the 10-bit command/address signal input at the falling edge of the clock signal $CK is output to another 1 DQ塾[19:10]. Therefore, although it is possible to double the data rate (10) Each cycle of the pulse CK is transmitted to the memory device 30' but can be - single data rate (SDR) (for each cycle of the clock CK) Information about command/address calibration is transmitted back from the S-memory device 30 to the memory controller 2A. Note that the bus can transmit data relative to one of the clocks different from the clock CK. The following discussion of @5 shows an embodiment in which the pulse trainer transmits data relative to the -f material. When the bit structure of the data signal DQ of the memory device 30 is _ (DQ[15:〇]), the number of DQ bus bars is 16. Since the number 16 of dq bus bars is less than the number of commands / (four) (four) bits (received by the loop CK) 20, the DQ bus bars may not be sufficient for the command/address calibration during one cycle of the clock. The information is transmitted as a group of bits 163456.doc •16·201246211. Therefore, the DQ bus 13 can transmit the information about the command/address calibration in sequence. For example, the DQ bus can be transmitted at one time. The command/address calibration information of the bit command/address apostrophe input to the memory device 3〇 at the rising edge of the pulse signal CK (for example, on the Dq bus line DQ[〇:9]), And later, transmit command/address calibration information about the 10-bit command/address signal input at the falling edge of the clock signal (for example, again on the DQ bus line DQ[0:9] 4A and 4B are diagrams for explaining command/address calibration that can be performed by the memory system 10 shown in Fig. 3. Referring to Fig. 3 with reference to Figs. 4A and 4B, the memory controller 2 detects Measure the edge of the command/address signal CA window and the clock signal ck received by the memory device 30 (from the memory of s The controller 20 provides) whether the relative position (or timing) is such that the memory device 30 successfully interprets the command/address signals. Figures 4A and 4B present several successful interpretations of the command/position signals as Passing (or P) and presenting the unsuccessful interpretation of the command/address signal as a failure (F). Figure 4A shows a command/address signal along a single command/bit of the command/address bus Multiple cycles of transmission of the address line. Each cycle of transmitting a calibration test pattern is adjusted by the controller to change the relative phase of the clock ck and the command/address signal compared to the pre-transmission cycle. The example of Figure 4b shows that for each subsequent transmission cycle, this relative phase changes by 1 / 20 (e.g., 18 degrees) of a clock CK cycle. Depending on the desired accuracy, each transmission cycle can be changed more or more. Relative phase. Note that the relative phase of the clock c κ and command/address signals received by the memory device for a specific transmission cycle can be compared with the clock CK and command/address signals transmitted by the controller. 163456.doc 201246211 Different phase, due to clock The different characteristics of the signal transmission and the signal line of the command address bus 12 may vary from transmission (from controller 2〇) to reception (by memory device 30). These different characteristics may include signals. One of the path lengths is different, the conductivity of the signal path (eg, due to the size of the conductor), the parasitic capacitance of the signal path (eg, from an adjacent line), temperature, etc. The memory controller 20 transmits the clock signal line. The clock signal CK is transmitted to the memory device 30 and the command/address signal CA is transmitted to the memory device 3 through one of the signal lines of the command/address bus bar 2 (^ in receiving the phase adjusted command / After the address signal CA, the memory device 3 transmits the command/position signal ca interpreted by the 5 memory device 3 to the 5 memory controller 20 through the Dq bus 13 . § Recalling the controller 2 〇&gt; (Which of the transmission commands/address signals have successfully transmitted their information to the memory device 3 (pass or pass) and which transmission cycles were unsuccessful (failed or F) Figure 4A shows a clock signal (CK@Memory) and a plurality of command/address signals received by the memory device 3 via one of the command/address busses (received via several transmission cycles). In order to simplify and better emphasize the shifting of the relative phase of the command/address statement with the clock CK, the command/address signal is shown as a vertical stack in Figure 4a instead of in a continuous timing diagram, however It should be noted that each of the ca@memory signals shown in 'in this example' is shown in chronological order (eg, via the same signal line of the command/address bus CA). Figure 4B In the case where the edge of the clock signal ck exists at one of the positions S1 or S2 of the command/address signal CA, the memory device 30 cannot successfully interpret the command/address signal cA (for example, cannot be latched at the window) Appropriate logic high or logic low of command/address signal CA And 163456.doc • 18· 201246211 The memory controller 20 may determine that the transmission cycle associated with S1 and S2 is a failure F. The edge of the current pulse signal CK exists at a position S3, S4, S5, S6, S7, S8 At time S9, S10 or S11, the memory device can successfully interpret the command/address signal CA (eg, successfully latch the appropriate logic high or logic low of the command/address signal c A) and remember The body controller 2〇 may determine that the transmission cycle associated with S3, S4, S5, S6, S7, S8, S9, S10 or S11 is through P. The edge of the current pulse signal CK is present in one of the command/address signals CA At position s 12 or S13, the memory controller 20 may determine that the transmission cycle associated with S 12 or S 13 is a failure f. The illustration of Figures 4A and 4B shows the clock CK received by the memory device 3 ck (ck One of the @memory timings should have a timing such that one of the clock signals ck must coincide with the logic of the command/address signal CA to be latched (eg, the correct logic occurring at the command/address signal CA) At the window. However, this representation is for making the explanation simple and not necessary, the clock signal CK The timing along the edge may not need to be at the same time as the logic to be latched, and (for example) may be shifted in time. For example, one of the clocks other than CK may be responsible for triggering the memory device 3 to the command / The address signal CA is latched. For example, the internal clock ICK can be generated by the memory device 3 in response to the clock signal CK, and the internal clock ICK can be buffered by one of the memory devices 30 (for example, FIG. 5 The CA receiver 304) is used to latch the logic of the command/address signal CA on the CA bus 12 at one rising edge or one falling time of ICK, even if the externally received clock CK and internal generation time Pulse ICK has the same frequency and duty cycle (which may not be the case), and CK and ICK can also shift in time. Therefore, the edge of the external clock CK may not coincide with the logic of the command/bit I63456.doc 201246211 address signal CA to be latched (eg, along the logic high of the command/address signal CA that can be latched in the memory device 30) Outside the window of State 1 (before or after). As another example, even when the edge of the clock CK is directly input to one of the buffers of the memory device 30 to trigger the latching of the signal input to the memory device, 'before the latching action is sufficient to latch the logic of the input signal There can be some delay. The memory device 30 can transmit information about the command/address calibration to the controller 2 on the data bus Dq as described above. For example, the memory device 30 can transmit a signal interpreted (e.g., latched) by the memory device 30 on the command/address signal line of the CA command/address bus. Therefore, during a calibration transmission cycle, if the memory controller transmits a 〗 〖 (eg, logic high state) to the memory device on the □s line of the command/address hop/claw row 12, but the clock ck The relative phase with the transmission causes the memory device 3 to be triggered to latch the signal on the signal line outside the appropriate signal window, and the memory device can inaccurately interpret the transmitted signal as a memory. The device can transmit the value 〇 via the __ signal line of the DQ data g stream 13. The memory controller 20 can determine that the transmission associated with the transmission ring is unsuccessful and depends on the transmission, - F. The subsequent transmission of the loop during command/address calibration may shift the relative phase of the transmission of the clock CK to the command/address calibration signal (eg, '1) such that the memory device 3G is triggered to indicate The signal line is latched in the signal window, and this value i can be transmitted to the memory controller 20 (as a command/address calibration information, the Bu Keon controller can be compared to the memory device memory device 30 for comparison. The command/bit 30 command/address calibration signal is the same as the self-address calibration information (value 1) and is judged to be 163456.doc 201246211 The subsequent transmission cycle is successful (via P). The memory controller 20 can analyze the command/address The calibrated transmission cycle group determines a relative phase between the clock CK and the command/address signal transmitted on the command/address signal line of the command/address CA signal during normal operation of the memory system 1 。. The optimal relative phase may be implemented by the memory controller 2 to transmit command and address information to the memory device during normal operation. For example, it may be determined by aggregation as a transmission cycle through p and Selecting one of the relative phases of the transmission cycle at the center of the group to determine the optimal relative phase. For example, because of S3, S4, S5, S6, S7, S8, S9 'S10 and FIG. 4B and FIG. The transmission cycle associated with S11 is successful (via P), so the memory controller 2 can select the relative phase of the associated transmission cycle (between clock CK and command/address calibration signals) as the best Phase __ select, remember (4) the controller selects the optimum phase as the average of the relative phases associated with the first and last successful transmission cycles (when the relative phase of the parent-transmission cycle is ordered) (eg , 0 degrees, 15 degrees, 30 degrees, etc.)) _ In the example of FIG. 4A and FIG. 4B, the average of the relative phases of the transmission cycles associated with s 3 and s 11 is selected as 'memory control (four) The optimum phase may be selected as an average of the relative phases associated with the last and the first unsuccessful transmission cycles % of the successful transmission cycle (when the relative phase of each transmission cycle is ordered) )_ In the example of Figure 4 and the figure, this will be related to The average of the relative phases of the transmission cycles associated with S12. The command/address calibration can be performed in this manner.

Although the calibration of a single command/address signal CA I63456.doc -21 - 201246211 (on a single line of command/address CA bus 12) has been described in the current embodiment, it can be directed to the pass command/bit The command/address calibration is performed by a plurality of command/address signals CA transmitted by the address bus 12. This calibration can be performed for all signal lines of the command/address bus 2 at the same time. The memory controller 2 can determine the best relative phase of each of the signal lines of the command/address bus 20 (eg, as set forth above) and individually adjust the command/address bus 2 The relative phase of each of the signal lines. Alternatively, memory controller 20 can determine an optimal relative phase of the entire set of signal lines and select the same best phase for all of the signal line groups of command/address bus 12. In selecting the same optimal relative phase for the entire signal line group, the memory controller 2 can determine a successful transmission cycle (via P) as all of the bits of the command/address calibration signal are from the memory device. 30 successfully interprets one of the loops and determines an unsuccessful transmission loop (failure F) as one of the loops in which at least one of the bits of the command/address calibration signal is not successfully interpreted by the memory device 30. The optimal relative phase of the entire set of signal lines can be determined by analyzing the pass P of the transmission cycle and the F-Fail flag in a manner similar to that described above with respect to a single signal line of the command/address bus 12 . In another alternative, the memory controller 20 can determine the best relative phase of one of the plurality of signal line groups that make up the command/address bus. The optimal relative phase of each of the plurality of signal line groups can be determined as set forth herein for determining the best relative phase of one of the entire set of signal lines constituting the command/address bus. The signal line group of the command/address bus 12 may include a group of adjacent signal lines (for example, other signal lines with no command/address address 163456.doc • 22· 201246211 stream 12). In another alternative, the best relative phase can be determined only for a subset of the signal lines of the command/address busbar 12 as explained above. That is, the command/address calibration signal may be transmitted by the controller only on a subset of the signal lines of the command/address bus 2 and/or the memory device 30 may transmit signals only regarding the command/address bus Command/address calibration information for one of the lines. The best relative phase can be determined for this subgroup of signal lines of the command/address bus. The remaining lines of the signal line of the command/address bus 12 may have an optimum phase determined based on the optimum relative phase for the signal line sub-group decision. This can be done, for example, by interpolating (and/or extrapolating) the optimal relative phase of the immediately adjacent signal lines (of the subset of signal lines) as an optimal relative phase. For example, if the command/address bus includes 10 signal lines (capable of transmitting 10 parallel information bits at a time), the odd lines (where the signal lines are clamped in the order of 1 to 1) may have 4A and 4B determine one of the best relative phases (by the controller 20 to the memory device 30 command / address calibration L number of multiple transmission cycles and command / address calibration information from The memory device 30 is sent to the memory controller 2). The even line of the command/address bus 12 may have its optimum relative phase determined by the previously determined optimum relative phase of the adjacent odd line of the interpolated command/address bus. Therefore, the signal line 2 of the command/address bus 12 can have an optimum relative phase which is determined as the average of the optimum relative phases of the signal lines 1 and 3. In addition to averaging the neighbors, other interpolations may be performed (eg, if signal lines 1, 2, and 3 are unevenly spaced or have some known length difference and/or the interpolation may include two Optimal relative phase determination of more than one odd signal line). Class 163456.doc • 23· 201246211 t ground 'signal line 4 may have its most determined by respect to signal lines 3 and 5: relative phase: averaging or interpolation is determined for the optimal relative phase of the signal line... The best relative phase. _ _ , Tian Yu in this example signal line 10 will: have two adjacent signal lines 'so the best relative phase can be chosen as: the best relative phase of the wide 9 is the same, or can be from multiple odd signals Line extrapolation (for example, extrapolation from signal lines 7 and 9). Figure 5 is a block diagram of one example of a memory system 10 that can be used to perform the four-command/command/address calibration embodiment of (d). Referring to FIG. 5, the memory system 1 includes a memory controller 2 and a memory device 30. The memory controller 2 can include a clock generator 2, a command/address generator 202, and a command/ The address transmitter 2〇3 (which may be referred to as a CA transmitter hereinafter), the register 2〇4, the comparator package, a phase/timing controller 208, and an input/output unit 21A. The memory controller 20 supplies the clock signal CK generated from the clock generator 2〇1 to the memory device 3 through the clock signal line. The command/address generator 202 generates an initial command/address signal CA〇 and provides it to the ca transmitter 203. The CA transmitter 203 receives an initial command/address apostrophe CAspl' having a first phase pl and The phase or timing of one of the initial command/address signals CAsp is adjusted in response to one of the phase/timing controllers 2〇8 control signal CTRL to produce a phase-adjusted command/address signal CASP2 having a second phase P2. The CA transmitter 203 can also be controlled by the control signal CTRL to substantially maintain the phase of the initial command/address signal CA such that the first phase pl is substantially the same as the second phase p2 (for ease of interpretation, even in certain situations) •24· 163456.doc

The 201246211 lower 'initial command/address CAspl signal may not have a phase adjustment, and the signal CASP2 is also referred to as a phase adjusted command/address signal ca). The phase adjusted command/address signal CASP2 is sent to the register 2〇4, and the information represented by the phase adjusted command/address signal CASP2 is stored in the temporary memory 204 as a CAS. The phase adjusted command/address signal CASP2 is provided to the memory device 3 via the command/address bus. The phase-adjusted command/address signal CASP2 is provided to the memory device 30 in conjunction with the clock signal CK. The register 204 stores the information of the phase adjusted command/address signal CAsp2 as the transmitted command/address information CAS. The comparator 206 compares the transmitted command/address information cAs stored in the register 204 with the received command/address calibration information CAr output from the input/output unit 210 (as described herein) The body device 30 receives and sends back to the memory controller 2). The comparator 204 compares the information CAS with the information CAr to generate a pass or fail signal P or F. The phase/timing controller 2〇8 generates a control signal CTRL indicating a phase shift of one of the initial command/address signals c1 based on the pass or fail information P or F generated by the comparator 206. The control signal CTRL is supplied to the CA transmitter 2〇3, and the initial command/address signal Ά phase or timing is adjusted to produce a phase-adjusted command/address signal CAsp2. In a normal operation mode, the data input/output unit 210 receives the read data transmitted from the memory device 3G through the DQ bus 13 or transmits the write to the memory device through the DQ bus 13 Enter the data W a Datal. In addition, in the command/address (CA) calibration mode, the data input / I63456.doc -25 - 201246211 output unit 210 can be received through the DQ bus 13 corresponding to the memory device 3 received from the memory controller 20 The phase-adjusted command/address signal CASP2 command/address calibration information CAr » command/address calibration information 『8 can be sent by the memory device 30 to the phase-adjusted command/address signal casp2 to The memory device 30 then latches the information in response to the clock CK (eg, in the case of a rising edge and/or a falling edge of the clock signal CK). When the timing of CK is such that the phase-adjusted command/address k number CAsp2 is properly interpreted (or latched), the CAr can be the same information as the CAS, or when the memory device 30 incorrectly interprets the The CAr can be different from the CAS when the phase adjustment command/address signal cAsp2. The data input/output unit 21 outputs the command/address signal information CAr to the comparator 206. Input/output unit 210 can include an input buffer 212, a selection unit 214, and an output buffer 216. Input buffer 212 and output buffer 216 may include latches and/or amplifiers to latch and/or amplify the received signals, respectively. The input buffer 212 is coupled to receive data and command/address calibration information cAr transmitted through the Dq bus 13 from the hidden device 30. The selecting unit 214 transmits the data received by the input buffer 212 as the read data R_DaU1 to the internal circuit block (not shown) of the memory controller 20 in response to a first selection signal SEU in the normal operation mode, and The command/address calibration information CAr received by the input buffer 212 is transmitted to the comparator 2〇6 in response to the first selection signal being smeared in the CA calibration mode. Selection unit 214 can be a multiplexer. The input buffer 212 can correctly interpret the command/address calibration information CAr. The DQ bus 13 has been calibrated in a DQ calibration mode prior to the CA calibration mode and/or the command/address calibration information CAr is at 163456.doc • 26 - 201246211 The bus 13 is transmitted to the input buffer 212 at a slower rate to ensure that the information on the DQ bus 13 is latched at the correct window (for example, when the command/address calibration is doubled) At rate (DDR), the slower transfer rate is at - Single Data Rate (SDR). In this example, the command/address calibration information CAr received on the Dq bus 13 is the same as the command/address calibration information CAr transmitted from the data input/output unit 2 to the CA comparator 206. The output buffer 216 transmits the write data W_Data1 to be written to the memory device 3 through the DQ bus 13. The memory device 30 includes a clock buffer 3, a command/address receiver 304 (which will hereinafter be referred to as a ca receiver 304), and a data input/output unit 310. The clock buffer 3〇2 receives the clock signal CK transmitted through the clock signal line u to generate an internal clock signal ICK^ transmits the command/address bus. 12. The phase-adjusted command/address signal CAsp2 is transmitted. To the memory device 30. The CA receiver 304 generates command/address calibration information CAr in response to the internal clock signal ick, which may occur when enabled by a wafer select signal /CS and a clock enable signal CKE. The chip select signal /cs clock enable signal CKE may be provided separately from the command/address signal line 12, as in FIG. 5 or may be carried on the command/address signal line 12 for transmission to the memory 30, unlike Shown in Figure 5. The clock enable signal CKE can be used as a pseudo command that acts as a read command for one of the phase adjusted commands/address signals CAsp2 transmitted through the command/address bus 12 in the CA calibration mode. The CA receiver 304 is based on one of the ICKs received when the clock enable signal CKE is in an active state and is enabled when the memory device 3 is enabled by the chip select signal /CS (eg 163456.doc • 27-201246211 as rising edge) And/or falling edge) the phase-adjusted command/address signal casp2 is latched to generate command/address calibration information CA to provide command/address calibration information to the data input/output unit 31. The data input/output unit 310 is connected to receive command/address calibration information CAr and an internal circuit block from the memory device 3 (for example, a data read path connected to one of the memory arrays storing the read data R_Data2) The circuit (not shown) transmits the read resource #R_Data2, and transmits the received read data R_Data2 to the DQ bus 13 in response to a second selection signal SEL2 in the __ normal read mode of operation. In a calibration mode, the second command/address signal (5) is transmitted to the calling bank 13 in response to the selection signal SEL2. In a normal write mode, the data input/output unit receives the write data 1 to be written to the memory device 3 through the DQ bus 13 and transmits the received write data W_Data1 to the memory device 3〇. Internal circuit block. The data input/output unit 310 includes a selection unit 312, an output buffer 314, and an input buffer 316. According to the normal operation mode or the calibration mode, the selection unit 312 selects the second command/address signal CA2 output from the command/address receiver 3〇4 and the internal circuit area from the memory device 3〇 in response to the second selection signal SEL2. The block provides one of the readings #R_Data2 and transmits the selected signal or data to the output buffer 314. The selection unit 312 can be a multiplexer. The output buffer 314 transmits the command/address calibration information CAr or the read data R_Data2 output from the selection unit 312 to the DQ bus 13. The input buffer 3 16 receives the data transmitted through the DQ bus 13 and transmits the received data as the write data W-Data2 to the internal circuit area of the memory device 3 163456.doc • 28· 201246211. For example, the write data W-Data2 can be transferred to a memory array via a data write path circuit for writing to the memory array. The data write path circuit and the data read path circuit can share the circuit. In the present embodiment, the command/address alignment information cAr output from the output buffer 314 of the memory device 3A is supplied to the memory controller 20 through the DQ bus 13 . In addition, the command/address calibration information CAr output from the output buffer 314 of the memory device 30 can be supplied to the memory controller 2 via a data strobe (DqS) line and a Dq bus 13. The data input/output unit 210 of the memory controller 2 and the data input/output unit 310 of the memory device 30 can be connected to each other through the DQS line and the DQ bus 13. The CA calibration in the memory system 10 can be performed as follows. The CA transmitter 203 of the memory controller 20 generates the command/address signal CASP2 by adjusting the phase or timing of the initial command/address signal CAspi in response to the control signal CTRL of the phase/timing controller 2〇8. The control signal CTRL can also have a value that maintains the phase of the command/address signal as previously described. The CA device 304 of the memory device 3 receives the phase-adjusted command/address signal CASf&gt;2 according to one of the internal clock signals ICK and when enabled by the clock enable signal CKE to generate a command/address Calibration information CAf. The command/address calibration information CAr of the memory device 30 is transmitted to the DQ bus 13 in response to the second selection signal SEL2. The value of one of the phase adjusted command/address signal CAsp2 transmitted from the memory controller 20 and the command/bit interpreted (eg, latched) by the delta memory device 30 prior to the calibration command/address signal Address calibration information 之一, one value can be, for example, due to noise generated during signal transmission and/or signal transmission timing change between clock CK and signal transmitted by CA bus 12 163456.doc • 29- 201246211 Can be different from each other. The calibration command/address signal solves this problem. In the command/address calibration mode, the memory controller 20 transmits the command/address calibration information CAr received via the DQ bus 13 to the comparator 2〇6 in response to the first selection signal SEL1. If the Dq bus 13 is calibrated in the DQ calibration mode prior to the CA calibration mode, the memory controller incorrectly interprets the command 7 address calibration information (eg, interpreted by the input buffer 212). small. The comparator 2〇6 compares one value of the command/address signal CASP2 transmitted from the memory controller 2 to the memory device 30 and stored in the register 2〇4 with the command/bit received by the memory controller. The address calibration information CAr has a value, and when the two values are identical to each other, a pass signal p is generated and a failure signal F is generated when the two values are different. The phase/timing controller 208 generates a command/address signal indicating the initial command/address signal (: one of the new phase shifts of the gossip (to obtain a new phase adjustment with one of the new relative phase differences from the clock CK) The control signal CTRL of CASP2) repeats the process for a new initial command/address signal cAsy having a different relative phase with respect to the clock CK. Multiple cycles in this process (each cycle has a CA transmitter 203 After the initial command/address signal CAspi has a different phase shift), the controller analyzes the group of P and failed F signals to determine the best operation of the CA彳§ line (or several lines or hidden rows). Relative phase. Although not shown in FIG. 5, the control signal CTR1 can be transmitted to the clock generator 2〇1 to adjust the timing or phase of the clock signal CK to adjust the relative phase of the command/address signal and the clock signal CK. By repeating the previous CA calibration, the phase/timing controller 208 of the memory controller 20 determines that the command/address signal is input (eg, latched) by 163456.doc -30-201246211 to the command/bit Address signal CA window The optimum timing of the intermediate portion (eg, through the middle of the P position) and a command/address signal CA is generated such that the middle of the command/address signal CA window corresponds to the input of the memory device 30 (which corresponds to On the edge of the clock signal CK, and the optimal relative phase between the command/address signal 〇8 and the clock ck is supplied to the memory device 3 with the generated command/address signal 八八脉脉 CK. Therefore, 'when the timing of the input (for example, latch) of the command/address signal corresponds to the edge of the clock signal CK received by the memory device 3', the memory device 30 receives the intermediate corresponding to a valid window thereof. The command/address signal c A at the rising and falling edges of the clock signal CK (strictly speaking) the rising and falling edges of the clock heart numbers CK and CKB. Although the command/address bus 12 has been explained Calibration of a single command/address signal on a single line, but this calibration can be performed for multiple or all command/address bus bars as previously described. Figure 6 is a diagram illustrating an example command/address calibration method One of the diagrams. Figure 6 is used to illustrate A timing diagram of one of the command/address calibration methods implemented in the memory system, wherein the data structure DQ of the memory device 30 is x32 (the DQ bus is connected to 32 of the memory device 3) Dq terminals (for example, pads, bumps, etc.) and 32 memory ports of the memory controller 2 (composed of 32 DQ signal lines of the ^ terminal). Referring to FIG. 6 with reference to FIG. 6, the memory controller 2 is generated for use. The clock signal CK of the memory device 3. The memory controller 2 sends an incoming command/address calibration mode command to the memory device 3, and the memory control (4) transmits the incoming command through the command/address bus 12 / Address calibration mode command. Enter p 7 address; k-mode command can be used - mode register setting 163456.doc • 31- 201246211 Command format One of the program memory devices mode register is input to indicate a command / address calibration mode . The memory device 30 can enter the command/address calibration mode in response to the mode register setting information in response to the command/address calibration mode indication. The memory controller 20 can transmit a command/address end signal via the command/address bus. The command/address end signal can be entered using one of the MRS commands that indicate self-calibration mode exit. At time t, the command/address alignment start signal is received at the memory device via the command/address bus 12 together with the activation of one of the wafer select signals /CS logic low level. A rising edge of one of the clock signals CK received by the memory device 20 triggers a latch into the command/address calibration mode command. For example, a first mode register command (MRW#41) is transmitted as an entry command/address calibration mode command. When a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#41 command may include a command to indicate that the command is a mode register setting command. The address signal CA[3:0] and the command/address signal CA[9:4] for instructing the mode register setting command to enter one of the command/address calibration modes. In this example, the MRW#41 command is input at both the rising and falling edges of the clock signal CK; in Figure 6, the MRW#41 command is first responded to the rising edge of the clock CK at time t〇. The memory device is latched and is secondarily latched by the memory device 30 in response to the subsequent lapse of the clock CK. That is, the same MRW #41 command is input at the rising edge and the falling edge of the clock signal CK corresponding to the start at the time tG of the clock signal CK. That is, since an MRS command is input at a double data rate (DDR) through a command/address signal line, an error can be generated to have a high operating frequency of -32-163456.doc 201246211 one S The memory device missed the]y[RS command. In addition, a different command can be erroneously interpreted as an incoming command/address calibration mode command. To reduce the error

The error can be entered as the same MRW #41 command at the rising edge and the falling edge of the clock signal CK corresponding to the time tQ of the clock signal CK, that is, due to the rising edge and the falling edge of the clock signal CK. Entering the same command/address signal 'so you can get one of the results similar to a single data rate (SDR) transmission' and can reduce one of the incoming calibration modes resulting especially when the command/address signal line has not been calibrated Failed (or, one of the calibration modes was not intentionally entered). The clock enable signal CKE is started together with the start of the logic low state of the wafer select signal /CS after the time t〇 after the first input of the MRW#41 command is delayed by a predetermined time (in Figure 6 at address/command) The calibration period is valid at a logic low level. At time t1, the command/address signal CAxR is transmitted by the memory controller 20 and received by the memory device 30, followed by transmission and reception following the second half of the clock cycle (here the clock CK is followed by the subsequent edge) CAxF. The command/address signals cAxR and CAxF are transmitted from the memory controller 2 to the memory device 3 via the command/address bus. The time tMRW can be set by a mode register to set the write cycle time to provide sufficient time for the memory device 30 to write the indication data to the mode register settings of the memory device 3. In this example, the 'command/address signal CAxR constitutes a plurality of signals transmitted on all lines of the command/address bus 12 input at the rising edge of the clock signal CK, and the command/address signal CAxF is formed at the time. 163456.doc 33· 201246211 A plurality of signals transmitted on all lines of the command/address bus 12 input at the falling edge of the pulse signal CK. The pair of C AxR and C AxF may constitute a command/address test pattern signal that is transmitted to the memory device during command/address calibration to determine whether the memory device is properly resolved. Translate the information represented by the test pattern signal. In the example of Figure 6, the test pattern (sent for each relative phase sequence) includes a sequence of two bits of each command/address signal line of the command/address bus 丨2 (command/bit Two logical windows of the address calibration signal). However, the test pattern may include a sequence of one or more bits, or may include one bit (in the transmission of the phase-adjusted command/address signal CAsp2, the description of FIG. 4A and FIG. 4B may be implied) – a bit test pattern, however, the phase adjusted command/address signal CAsp2 may be one bit transmitted by each of the lines of the command/address bus 12 (or some) , two bits or a sequence of more than two bits). The command/address signal CAxR and the command/address signal CAxF input to the memory device through the command/address bus 12 can represent different signals of different bytes. For example, when the command/address bus 12 is composed of one or more command/address signals CA[9:〇], one-bit command/address signals CAxR and 10 can be used. The bit command/address signal CAxF is divided into different signals. Therefore, the command of the memory device 3〇 connected to the command/address bus 12 of 10 bits/address solder bumps, etc. (not shown) will be the command of the continent 2 = quasi = CA [9 :〇] input to the memory device 3〇β memory device% can be determined by one of the timings of the edge of the clock CK (for example, at the same time or at a predetermined or fixed time before or after the appropriate trigger edge of the time (10)) A person (eg, latch) command/address calibration signal. The memory device 3 can transmit the input command to the memory controller 30, 163456.doc • 34 - 201246211 (as interpreted by the memory device - which can be correctly interpreted or incorrectly interpreted), As described above, for example, with respect to Figures 4A, 4B, and/or 5 . Since the memory device 30 is required to have a large capacity, the degree of integration and the number of memory cells are increased. As the number of memory cells increases, the number of address bits used to address the memory cells also increases. The increase in the number of address pins results in an increase in the size of the wafer. Therefore, there is a need for a method for suppressing the increase in the number of address pins required in most memory chips. Since the command/address signal is input at both the rising and falling edges of a clock signal in this example, the number of command/address pins of the memory device 30 can be reduced. In this example, a read command cannot be transmitted from the memory controller 20 through the command/address signal line during the calibration mode of the command/address bus. Therefore, in the calibration mode of the command/address signal bus, the clock enable signal CKE acts as one of the command/address signals CAxR and CAxF read commands. When the clock enable signal CKE is activated at a logic low state, the command/address signals CAxR and CAxF are input at a timing determined by the edge of the clock CK, and the result is output to the memory through the data bus DQ13. Body controller 20. Thus, the clock enable signal CKE acts as a dummy command and enables the memory device to input command/address calibration test patterns (e.g., signals CAxR and CAxF). The phase adjusted command/address signal CAsp2 transmitted from the memory controller 20 in the embodiment illustrated with respect to FIG. 5 corresponds to the command/address signal CAxR or CAxF in FIG. 6 . . . CAyR and CAyF (in In the following text, the values are collectively referred to as CAnR and CAF. Each of the CANR and CAF pairs 163456.doc -35- 201246211 shall be transmitted in one of the phase-adjusted commands/address signals CAsp2, each of which is transmitted relative to the previous CAnR and CAF signals relative to the clock CK Command/address signals cAnR and CAnF signal pairs with a new relative phase difference. For ease of explanation, the adjusted phase difference for each CAnR and CAnF signal pair is not shown in Figure 6 (see Figures 4A and 4B and related descriptions). Therefore, n (n is an integer equal to 2 or greater) test command/address test pattern signals (eg, n CARR and CAnF signal pairs) can be transmitted along with a clock signal via a command/address bus. , wherein each of the n test pattern signals is transmitted in a first to nth phase different from one of the clock signals. At the time η from the time ti delay time tADR at which the clock enable signal CKE of the clock enable signal CKE is started, the DQ bus bar 13 will be solved by the memory device 30 in the command/address signal CAxR or CAxF. The value of the command/address calibration test patterns caxR and CAxF (corresponding to the command/address calibration information CAr) input by the memory device 30 at the time of translation (for example, latching) is output from the memory device 30 to the memory control. 20. The time tADR can be predetermined and based on one of the operations of the memory device known timing. (Note that in Figure 6, the portion of the timing diagram illustrating the timing of CK, CA, CS, and CKE that are vertically aligned with the dashed line representing time h is one of the times h that is represented by the wear symbol in these timings. At the time.) As shown in FIG. 6, during the period of the plurality of clocks of the clock CK, the even-numbered Dq lines (DQ0, DQ2, etc.) of the Dq bus bar 3 are outputted by the clock. The value of the command/address signal CAxR input by the memory device 30 triggered by the rising edge of CK (eg, command/address calibration information associated with CAxR). In this example, the time to turn to the note • 36-163456.doc is 201246211 The command/address calibration information of the body controller 20 can occur within a plurality of cycles of the clock ck. As shown in FIG. 6, the command/address signal input by the memory device is output on the DQ bus 13 at the same time as the value of the command/address signal CAxR input by the memory device and in the same manner as it is. The value of CAxF (e.g., command/address calibration information associated with CAxF), except that the value of the command/address signal CAxF is output on the odd DQ line of the bus bar 13. When viewed from a top-down perspective, the dq bus bar can (but need not) extend substantially in the same direction between the memory device 3 and the controller 20' and self-numbering, where the state dq bus Number of bus lines" If the relative phase of the clock CK and the address/command calibration test pattern signal CAxR&amp; cAxF triggers input (eg, latch) address/command calibration test pattern signal at the correct logic window, The memory device should correctly resolve the calibration test pattern signal. In this example, the memory controller 2〇 will determine a pass p (for the clock CK and the position/command calibration test pattern signal CAxR and CAxF test pattern signal relative phase) ^ if and R and CAxF number The relative phase results in an incorrect interpretation of the information represented by the address/command calibration test pattern No. 5 CAxR and CAxF, and the memory controller 20 will determine a failure f. The DQ pad can be set in an evening manner to transfer the value of the second command/address signal CA2 received by the memory device 30 through the dq line to the calibrated command/address signals CAxR and CAxF of the memory controller 20. Mapping. An example of a map is shown in Figure 8, where the command/position signal c AxR (bits 163456.doc • 37 - 201246211 CA0 to CA9) input by the memory device 3 at the rising edge of the 4th CK can be used. The value is output to the memory device 30 dq pad Dq[9:〇], and the value of the command/address signal CAxF input by the memory device 30 at the falling edge of the clock signal Ck can be output to the memory device dq pad dq. Another example of [19:1〇;^ mapping is shown in Figure 9, where one of the command/address signals CA9, which is one of the command/address signals CAxR input at the rising edge of the clock signal CK, can be used. It is output to one of the DQS pads DQS0 of the memory device 3, and the value of the command/address signal CA[8:0] can be output to the memory device 3〇Dq塾Dq[8:0]. One value of the command/address signal CA9 among the command/address signals CAxF input at the falling edge of the clock signal CK can be output to one of the DQS pads DQS1 of the memory device and the command/address signal CA can be used. The value of 8:0] is output to the memory device DQ pad DQ[17:9]. At the memory controller 20, the relative phase between the clock CK and the phase adjusted command/address signals (e.g., cAyR and CAyF) sent to the memory device 30 is changed, and command/address calibration is performed. A new cycle. As shown in FIG. ,, it transmits command/position calibration signals CAyR (at time u) and CAyF (at the CK followed by subsequent clock edges) to the memory device on the command/address bus 12 30, and the memory device 30 transmits a value interpreted by the memory device to one of an intermediate loop of one of the memory controllers 20 in a manner similar to that described above with respect to C AxR and C AxF, and thus A repeated explanation here is not necessary. The clock enable signal CKE is activated just before the time 'together with the start of the logic low state of the wafer select signal /CS'. This can occur when the command/address calibration signals CAnR and CAnF (nine commands/address calibrations transmitted from the memory device 30 to the controller 20 during the command/address calibration session are 163456.doc • 38 - 201246211 The last group in the group is transmitted from the memory controller 20 to the memory device 30 through the command/address bus. Command/Address Calibration Information CAnR and CAnF can be transmitted in the same way as command/address calibration information CAxR and CAxF. At a time t5, an end command/address calibration mode command is transmitted through the command/address bus 12, together with the activation of the logic low state of the wafer select signal /CS. (Note that the timing of vertical alignment with time 15 illustrated in Figure 6 for even DQ and odd DQ occurs before time 15 sees truncation marks in even DQ and odd DQ timings.) For example, transmitting a second mode The register (MRW#42) command is used as the end command/address calibration mode command. If a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#42 command may include a command to identify the command as a mode register setting command. The command/address signal CA[3:0] and the command/address signal CA[9:4] for identifying the mode register setting command as an end command/address calibration mode command. The MRW #42 command is input at both the rising edge and the falling edge of the clock signal CK corresponding to time t5. That is, the same MRW #42 command is input twice at the time pulse signal CK at the time t5 and immediately after the time pulse signal CK followed by the subsequent falling edge. When a MRS command is input using a command signal under a DDR, an error can be generated to cause the memory device to miss the MRS command with one of the high operating frequencies. To reduce the chance of this error, enter the same MRW#42 command twice at the rising and falling edges of the clock signal CK. There are numerous ways in which the memory device can determine when to latch the exit command/address calibration mode 163456.doc -39 - 201246211 (here, MRW #42). In one embodiment, the memory device can be configured to latch at the edge of the clock signal CK with a predetermined relationship (eg, timing) with respect to the transition from the low state active to the high state of the clock enable signal CKE. Information provided on bus bar 12. For example, as shown in FIG. 6, the memory device can be configured to latch at the CA busbar 12 at both edges of the clock CK following the transition from the low state active to the high state of the clock enable signal CKE. Information provided on. When the CKE is high, the memory device 30 treats the information on the command address bus CA 12 as a command (to be processed, for example, by the command decoder of one of the memory devices 30) rather than a calibration test pattern. It should also be noted that the clock enable signal CKE may be considered to be active low only during certain operations, such as during the CA calibration mode, and at other times, as a high active signal. After the predetermined time tMRZ is delayed from the time t5 at which the MRW #42 command is input, the command/address signals CAnR and CAnF are terminated to the output of the memory device DQ pad. The period from the time when the clock signal CK of the MRW#41 command (which is the command/address calibration start signal) is input to the time t5 when the clock signal CK of the MRW#42 command is input at that time plus the time tMRZ Can be CA calibration cycle. Figure 7 is a diagram showing a true value of an exemplary mode register command setting method. Referring to Figure 7, the MRW #41 command and the MRW #42 command can be set by the clock enable signal CKE, the chip select signal /CS, and the command/address signal CA[9:0]. When the pulse enable signal CKE is at a logic high state (H) level, the chip select signal /CS is at a logic low state (L) level, and the command/address signal 163456.doc -40· 201246211 CA[3: 0] At a logic low (L) level and the command/address signal CA[9:4] is at the logic level HLHLLH, the MRW#41 command can be used to set the MRS register of the memory device 30 ( For example, write to the MRS register). That is, the MRW #41 command can include the command/address signal CA[9:0] 29H. The same MRW #41 command can be sent to the memory device on the command/address bus 12 at both the rising and falling edges of the clock signal CK. The memory device 30 can be configured to set the mode register to indicate when the at least one of the two MRW #4 1 commands sent to the memory device 30 is properly interpreted when input by the memory device 30 The memory device 30 is in a command/address calibration command. (Note that sending two MRW #41 commands to the memory device 30 may include maintaining the command sent on the command/address bus without changing the two logical windows of the command/address signal - the two logic windows It may include - one of the clocks CK and the whole clock period.) The clock enable signal CKE is at a logic high level, the wafer select signal /CS is at a logic low level, and the command/address signal is When CA[3:0] is in a logic low state and the command/address signal CA[9:4] is under the logic level HLHLHL, the MRW#42 command can be used to set the MRS temporary storage of the memory device 30. Device. That is, the MRW #42 command may include the command/address signal CA[9:0] 2AH. The same MRW #42 command can be sent to the memory device twice on the command/address bus 12 at both the rising and falling edges of the clock signal CK. In this paper, the command/address signal CA[9:4] can be used as the mode register setting address MA[5:0]. Figure 8 is a diagram showing one example of a mapping between a command/address signal and a DQ pad, in accordance with an embodiment. Since in the current embodiment, the command/address apostrophe CA[9:0] is input at both the rising edge and the falling edge of the clock signal ck of 163456.doc 201246211, the command/address signal CA[9:0 ] can be composed of 20 bits. In this regard, the bit structure of the data DQ of the memory device 30 is 2 and the number of DQ pads is 32. The number of DQ pads is greater than the number of command/address signals so that DQ padding corresponds one-to-one to the command/address apostrophe&gt; Referring to Figure 8, the input of the clock signal CK is at the rising edge of 7^ The value of the number CA[9:0] can be mapped to output to the DQ pad DQ[9:〇]. The value of the command/address signal CA[t〇] input at the falling edge of the clock signal ck is red ii4r jti is output to E) Q pad [Q[19:1〇]. For example, in FIG. 6, the value of the input 7 Μ signal CAxR corresponding to the input of the rising edge of the clock signal CK at time t! is output to the DQ pad DQ[9:0], and will correspond to time 11 The output of the command/address signal cAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[19:10]. The value of the command/address signal CAxR input at the rising edge of the pulse &amp; CK corresponding to the time U is output to the direct DQ &amp; DQ[9:0], and will be at the clock signal corresponding to the time t4. CK drop / σ input command / address signal CAxF value output to DQ pad DQ [19: 1G] ° Figure 9 is shown according to another embodiment for illustrating the command / address signal and DQ and DQS pad One of the other examples of mappings, with reference to Figure 9, the value of the command/address signal CA[9:0] (e.g., CAxR) input to the memory device 30 at the rising edge of the clock signal CK can be It is mapped to output to DQS pads DQS0 and DQS1 and even DQ pads DQ [0, 2, 4, 6, 8, 10, 12 and 14]. That is, the input value of the command/address signal CA9 is output to the DQS pad DQS1, and the input value of the command/address signal CA4 is output to the DQS0'. The input values of the command/address signal CA[3:0] are respectively output. To 1634S6.doc • 42· 201246211 DQ pad DQ[6, 4, 2, 〇] and output the command/address signal CA[8:5]2 input values to DQ pad DQ[14, 12, 10, 8J respectively . The value of the command/address signal CA[9:0] (eg, CAxF) input to the memory device 3 at the falling edge of the clock signal CK can be mapped to be output to the DQS pad/DQS0 and /DQS1 and DQ. Pad DQ [17:9]. That is, the input value of the command/address signal CA9 can be output to the DQS pad/DQS1, and the input value of ca4 can be output to the DQS pad/DQS0, and the input value of the command/address signal CA[3:0] can be input. The output values are respectively output to the DQ pad DQ[7, 5, 3, 1] and the input values of the command 7 / address apostrophe CA [8:5] are respectively output to the Dq pad Dq [15, 13, 11 and 9]. Figure 10 is a diagram for illustrating one of the command/address calibration methods in accordance with another embodiment. Figure 10 is a timing diagram for explaining one of the command/address calibration methods in the memory device 30. The memory device 3 has a bit structure d32 of the data dq. 5, the memory controller 2 generates a clock for the memory device 30. The address calibration mode command (or instruction) is to the memory device 30. The entry command/address calibration mode command can be entered using a special case of the MRS commands described herein with respect to other embodiments. The memory controller 20 transmits an exit command/address calibration mode command (or command) through the command/address bus. The Exit Command/Address Calibration Mode command can be entered using a special case of the MRS commands described herein with respect to other embodiments. At the time t〇 of the clock signal CK', together with the start of the low-level level of the chip select signal /cs, the command/address bus 12 transmits the command/bit through the command/address bus 12 The MRW#41 command for the address calibration command. For example, the MRW#41 command is input at both the rising edge and the falling edge of the clock signal CK starting at time t〇. That is, the same MRW #41 command can be input at the rising edge and the falling edge of the clock signal CK starting at time t〇. At a time q after the tQ delay time tMRW of the clock signal CK inputting the MRW#41 command at that time, together with the activation of the logic low state of the wafer selection signal /CS, one cycle for the clock signal CK The clock enable signal CKE is activated with a predetermined pulse width, and the command/address signals CAxR and CAxF are sequentially transmitted through the command/address bus. The command/address signal CAxR is input at the rising edge of the clock signal CK at time t!, and is input at the falling edge of the clock signal CK (which is followed by the subsequent falling edge of the clock CK after the time ti) Command/address signal C AxF. The command/address signal CAxR and the command/address signal CAxF input through the command/address bus 12 can represent different signals of different information (for example, different test type information). In the calibration mode, the clock enable signal CKE acts as one of the command/address signals CAxR and CAxF corresponding to the value of the second command/address signal CA2 received by the memory device 30 in FIG. During the command/address calibration mode (and when the wafer select/CS is active (logic low)), the memory device initiates the interpretation of one of the clock enable signals CKE at a logic low level to An instruction of one of the signals on the command/address signal bus is input to the subsequent edge of the clock signal CK, and thus, for example, as shown in FIG. 10, the command/address signal CAxR received by the memory device 30 is input or CAxF 163456.doc .44- 201246211 value. The value of the command/address signals CAxR and CAxF (interpreted/input by the memory device) is output to the DQ pad starting at time t3 of the time h delay time tADR. At time t3, the input command/address signal CAxR is output to the even DQ pad, and during the subsequent clock edge of the clock CK, the round command/address signal CAxF is output to the odd DQ. The mapping between the command/address signals CAxR and CAxF and the DQ pad can be set in various ways. An example of mapping is illustrated in FIG. 11, in which the value of the command/address signal CAxR input at the rising edge of the clock signal CK can be output to the even DQ pad DQ[2n], where η is 0 to 9, and The value of the command/address signal CAxF input at the falling edge of the clock signal CK can be output to the odd DQ 塾 DQ [2n + 1], where η is 0 to 9. As another mapping example, the result of the calibration of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK can be output to the even DQ pad DQ [ 2n], where η is 0 to 3, one value of a command/address signal CA4 can be output to the DQS pad DQS0, and the value of the command/address signal CA[8:5] can be output to the even DQ pad DQ [ 2n], where η is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad DQS 1. The value of the command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+l], where η is 0 Up to 3, a value of the command/address signal CA4 can be output to the DQS pad/DQSO, and the value of the command/address signal CA[8:5] can be output to the odd DQ pad DQ[2n+l], where η The system is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad/DQS1. 163456.doc •45· 201246211 At time t4, together with the activation of the logic low state of the chip select signal /cs, the clock enable signal CKE is started with a predetermined pulse width for one cycle of the clock signal CK, and is remembered by the memory. The body device 30 inputs the command/address signals CAyR and CAyF transmitted through the command/address bus. The command/address signal CAyR is input at the rising edge of the clock signal CK at time t4, and is input at the falling edge of the clock signal CK (the clock CK immediately after the time t4 is followed by the subsequent clock edge) Command/address signal CAyF. The command/address signal CAyR and the command/address signal CAyF input through the command/address bus 12 can be different signals (e.g., different bytes of the test pattern). In the calibration mode, the clock enable signal CKE acts as one of the command/address signals CAyR and CAyF read commands, and therefore, when the pulse enable signal CKE is enabled at a logic low level, it will be received by the memory device 30. The values of the command/address signals CAyR and CAyF are output to the even DQ pads and the odd DQ pads are input by the memory device 30 in response to a timing of the clock CK. After a predetermined time tADR is delayed from time t4 of the clock signal CK, the values of the command/address signals CAyR and CAyF (as started by the memory device as input at time t4) are output to the DQ pad. That is, the command/address signal CAyR input by the memory device 30 is output to the even DQ pad and the command/address signal CAyF input by the memory device 30 is output to the odd DQ 塾0 when the memory device 30 will command When the address signals CAyR and CAyF are transmitted to the memory controller 20, the mapping to the DQ pad can be set in various ways. As a mapping example, the value of the input 163456.doc -46 - 201246211 command / address signal CAyR input to the rising edge of the clock signal CK can be output to the even Dq pad DQ[2n], where η is 0 to 9 And the value of the command/address signal CAyF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where η is 0 to 9. As another mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAyR input at the rising edge of the clock signal CK can be output to the even DQ pad DQ[2n], Where n is 〇 to 3, a value of a command/address signal CA4 can be output to the DQS pad DQS0, and the value of the command/address signal CA[8:5] can be output to the even DQ pad DQ[2n], 11 is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad DQS1. The value of the command/address signal CA[3:0] in the command/address signal CAyF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+l], where η is 0 Up to 3, a value of the command/address signal CA4 can be output to the DQS pad/DQS0, and the value of the command/address signal CA[8:5] can be output to the odd DQ pad DQ[2n+l], wherein η is 4 to 7, and a value of the command/address signal CA9 can be output to the DQS pad/DQS1. At time t5, together with the activation of the logic low state of the wafer select signal /CS, the MRW #42 command of the exit command/address alignment mode command is transmitted through the command/address bus 12 . In this example, the MRW #42 command is input at both the rising and falling edges of the clock signal CK corresponding to time t5. That is, the same MRW #42 command is input at the rising edge and the falling edge of the clock signal CK corresponding to time t5. There are numerous ways for memory device 30 to recognize the signal on command/address bus 12 as a command (rather than another set of test pattern calibration information for a new cycle). For example, the memory device device 30 can receive the pre-existing number of the test type information sent to the memory device by the memory device 30, 163456.doc -47 - 201246211, and the memory device 3G can The number of cycles of the test pattern information is counted and when the count reaches a predetermined number (or, for example, the first count or the last tenth), the command is expected to be received. Another_select 4 device 30 can monitor all information (eg, monitoring command/address calibration information CAr) input via the command/address bus 12 to test a predetermined code (eg, a command code), and when Exit the calibration mode when the predetermined code is detected (and/or the predetermined code is recognized as the exit command/address calibration command code), or otherwise the input information is considered to be the calibration mode - the test pattern during the cycle The calibration information generated by the transmission. The output of the calibrated command/address signal CAyR^DQ pad is terminated after the predetermined time tMRZ is delayed from the time ts at which the MRW #42 command is input. From the time t〇 (in the case of the input system enters the command/address calibration mode command MRW#4 1 command) to the time ts (in the case of the input system exit command / address calibration mode command MRW #42 command) The period plus time tMRZ may correspond to a CA calibration mode period. Although Figure 10 shows only two sets of test patterns (for CAxR and CAxF and for CAyR and CAyF) sent during the calibration mode period, more than two test patterns can be sent during a calibration cycle. In addition, Figure 1 illustrates a logic window that is positioned such that its logic window center corresponds to the command/address calibration signal for the corresponding clock edge of clock CK. However, this is for illustrative purposes only; it is contemplated that controller 20 will change the relative phase of each of the command/address calibration signals (representing the calibration test pattern) such that clock edge CK is for command/address The timing of the numerous command/address calibration signals in the calibration signal will shift at time 163456.doc • 48· 201246211 (and may be shifted relative to the center of the command/address calibration signal logic window (eg, on the outside) In order for the memory device 3 to incorrectly interpret the timing of the command/address calibration signal logic). Figure 11 is a table showing one example of a mapping between a command/address signal and a DQ pad in accordance with another embodiment. Referring to Figure 11, the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be mapped to output to the even DQ pad DQ[2n], where η is 0 to 9. The value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK can be mapped to be output to the odd DQ pad DQ[2n+l], where η is 0 to 9. For example, in FIG. 1A, the value of the command/address address CAxR input at the rising edge of the clock signal CK corresponding to the time ^ can be output to the even DQ pad DQ[2n] 'where η is 0 Up to 9, and the value of the command/address address CAxF input at the falling edge of the clock signal CK can be output to the odd DQ pad DQ[2n+1], where η is 0 to 9. The value of the command/address signal CAxR input at the rising edge of the clock signal CK at time t4 can be output to the even DQ pad DQ[2n] 'where η is 0 to 9, and can be in the clock signal CK The value of the command/address signal CAxF input at the falling edge is output to the odd DQ pad DQ[2n+l], where η is 0 to 9. Figure 12 is a table showing another example of a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment. Referring to FIG. 12, the value of the command/address signal ca[9:0] (eg, 'CAxR) input to the memory device 30 at the rising edge of the clock signal CK can be mapped to be output to DQS, DQS0, and DQ. DQ[8:0]. That is, the value of the command/address signal CA9 can be output to dqs^dqso, and the value of the command/address address 163456.doc -49-201246211 CA[8:0] can be output to the DQ pad DQ[8 :0]. The value of the command/address signal CA[9:0] (eg, CAxF) input to the memory device 3 at the falling edge of the clock signal CK can be mapped to the DQS pad DQS1 and the DQ pad DQ[17 :9]. That is, the value of the command/address signal CA9 can be output to the DQS pad DQS1, and the value of the command/address signal CA[8:0] can be output to the DQ pad DQ[17:9]. Figure 13 is a timing diagram illustrating one of the command/address calibration methods in a memory device 3 in accordance with another embodiment. The memory device 3's data Dq is located in the 16X organization. In the current embodiment, the command/address signal CA[9:〇] is input at both the rising and falling edges of the clock signal CK, and therefore, each command/address test pattern CA[9:〇 ] can be composed of 2 units. In this connection, since the bit structure of the data DQ of the memory device 30 is χ16, the number of DQ塾 is 16. The number of command/address test pattern bits transmitted by a particular relative phase generated by the memory controller 20 is greater than the number of Dq pads' such that the DQ pad does not uniquely correspond to the command/address signal. Therefore, the DQ pads can be assigned to command/address signals received on different signal lines of the command/address bus 12 at predetermined time intervals. Referring to Figure 13 in conjunction with Figure 5, the memory controller 2 generates a clock signal CK for the memory device 30. The memory controller 2 sends an incoming command/address calibration mode command (or command) to the memory device via the command/address bus 12. The 30° entry command/address calibration mode command can be used elsewhere in this document. The specific MRS command format. The memory controller 20 transmits an exit command/address calibration mode command through the command/address bus 12 . Exit Command/Address Calibration Mode commands can be used as described elsewhere in this article 163456.doc

-50- 201246211 Specific MRS command format. At time t, the command/address alignment mode command is transmitted through the command/address bus 12 along with the activation of one of the logic select signals /CS. For example, a third mode register (MRW#43) command is transmitted as a command/address calibration start signal. When a command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#43 command may include a command indicating that the command is a mode register setting command/ The address signal CA[3:0] and the mode register setting command indicating that the mode register setting command is one of the command/address signals CA[9:4] entering the calibration mode command. The MRW#43 command is input at both the rising and falling edges of the clock signal CK starting at time t〇. That is, at the rising edge of the clock signal CK at time to - and again - at the subsequent pulse edge of the clock signal CK - the same MRW #43 command is input. This is due to the possibility of generating an error such that one of the memory devices with a high operating frequency (e.g., during a DDR operation) misses or misinterprets the MRS command. To reduce the chance of this error, the same MRW #43 command is entered at the rising and falling edges of the clock signal CK corresponding to time t〇. The time t〇 of the clock signal CK from which the MRW#43 command is input is delayed by a predetermined time tMRW, together with the activation of the logic low state of the wafer selection signal /CS, for the clock signal CK One cycle starts the clock enable signal CKE with a predetermined pulse width and transmits the command/address signals CAxR and CAxF through the command/level bus 12. The time tMRW can be set by a mode register to set the write cycle time. 163456.doc •51 - 201246211 At the time t, the command/address signal CAxR is input at the rising edge of the clock signal CK, and at the falling edge of the clock signal CK (the clock k after the CK is tight) The command/address signal CAxF is then input at the subsequent falling edge. The command/address signal CAxR and the command/address signal CAxF input through the command/address bus 12 can be different signals. For example, when the command/address bus 12 is composed of a command/address signal CA[9:〇] of one bit, 'a command/address signal of one bit can be CAxr&amp;10 The bit command/address signal CAxF is divided into different signals. Therefore, the command/address terminal (for example, pad, pin or bump-not shown) of the memory device 3 connected to the 10-bit command/address bus 12 can be 2 bits. The command/address signal CA[9:0] is input to the memory device 30. Since the suffix device 30 is required to have a large capacity, the degree of integration and the number of memory cells are increased. As the number of memory cells increases, the number of address bits used to address memory cells also increases. An increase in the number of address pins results in an increase in the size of the wafer. Therefore, a method for suppressing an increase in the number of address pins required in most memory chips is desired. Since the command/address signal is input at both the rising and falling edges of a clock signal in the present embodiment, the number of command/address pins of the memory device 3 can be reduced. During the command/address calibration mode, the clock enable signal CKE acts as one of the command/address signals CAxR and CAxF read commands. When the clock enable signal CKE is activated at a logic low state, the command/address signals CAxR and CAxF are input in response to one of the clocks CK, and the result is output as a data signal DQ. Therefore, the clock enable signal CKE is used as a pseudo command. 163456.doc • 52- 201246211 After delaying the predetermined time tADR from time q, the command/address signals CAxR and CAxF input by the memory device 30 are output as a data signal DQ. The time tADR can be set from the start of the clock enable signal CKE to the data output to one of the DQ pads to set the delay time. At time t3, the calibrated command/address signal CAxR, which is input by the memory device 30, is output via the DQ pad of the memory device 30. At time 14 after the calibration command/address signal CAxR is output to the DQ pad for a predetermined time tADD, the calibrated command/address signal CAxF input by the memory device 30 is output via the DQ pad of the memory device 30. The mapping between the calibrated command/address signals CAxR and CAxF and the DQ pad can be set in various ways. As a mapping example, the value of the command/address signal CAxR input at the rising edge of the clock signal CK can be output to the DQ pad -DQ[9:0], and then the falling edge of the clock signal CK can be The value of the command/address signal CAxF input is output to the DQ pad DQ[9:0]. As another mapping example, the value of the command/address signal CA[4:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[4:0], The result of the calibration of the command/address signal CA [9:5] is then also output to the DQ pad DQ[4:0]. The value of the command/address signal CA[4:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[9:5], and then, will also be The result of the calibration of the command/address signal CA[9:5] is output to the DQ pad DQ[9:5]. As a further mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[3:0], Output a value of a command/address signal CA4 to 163456.doc -53-201246211 to a DQS pad DQSO, and output the value of the command/address signal CA[8:5] to the DQ pad DQ[4:0], And outputting a value of a command/address signal CA9 to a DQS pad DQS1, a command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK. The value is output to the DQ pad DQ[7:4], one value of the command/address signal CA4 is output to a DQS pad/DQS0, and the value of the command/address signal CA[8:5] is output to the DQ pad DQ. [7:4], and output a value of the command/address signal CA9 to a DQS pad / DQS1. Starting at time t4, together with the activation of the logic low state of the wafer select signal /CS, the clock enable signal CKE is initiated with a predetermined pulse width for one cycle of the clock signal CK, and through the command/address bus 12 Transmitting the command/address signals CAyR and CAyF from the memory controller 20 to the memory device 30° at the rising edge of the clock signal CK at time t4, inputting the command/address signal CAyR, and at the clock signal CK The command/address signal CAyF is entered immediately after the subsequent falling edge. The command/address signal CAyR and the command/address signal CAyF input through the command/address bus 12 can be different signals. After the predetermined time tADR is delayed from time t4, the command/address signals CAyR and CAyF which are input by the memory device 30 are output to the DQ bus 13 via the DQ pad. After outputting the calibrated command/address signal CAyR (as input from the memory device 30) to the DQ pad, the calibrated command/address signal CAyF (as input by the memory device 30) is output.

The mapping between the calibrated command/address signals CAyR and CAyF and the DQ pad can be set in various ways. As a mapping example, the value of the command/address signal CAyR input at the rising edge of the clock signal CK 163456.doc • 54· 201246211 can be output to the DQ pad DQ[9:0], and then the time can be The value of the command/address signal CAyF input at the falling edge of the pulse signal CK is output to the DQ pad DQ[9:0]. As another mapping example, the value of the command/address signal CA[4:0] among the command/address signals CAxR input at the rising edge of the clock signal CK can be output to the DQ pad DQ[4:0]. And then, the result of the calibration of the command/address signal CA[9:5] is also output to the DQ pad DQ[4:0]. The value of the command/address signal CA[4:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[9:5], and then, will also be The result of the calibration of the command/address signal CA[9:5] is output to the DQ pad DQ[9:5]. As a further mapping example, the value of the command/address signal CA[3:0] among the command/address signals CAxR input at the rising edge of the clock signal CK is output to the DQ pad DQ[3:0], Output a value of the command/address signal CA4 to the DQS pad DQS0, output the value of the command/address signal CA[8:5] to the DQ pad DQ[4:0], and place the command/address signal CA9 One value is output to the DQS pad DQS 1. The value of the command/address signal CA[3:0] among the command/address signals CAxF input at the falling edge of the clock signal CK is output to the DQ pad DQ[7:4], and the command/address signal is output. One value of CA4 is output to DQS pad/DQS0, and the value of command/address signal CA[8:5] is output to I) Q pad DQ[7:4], and one value of command/address signal CA9 is output. To DQS pad / DQS1. At time t5, along with the activation of the logic low state of the wafer select signal /CS, the command/address bus 12 is transmitted through the exit calibration/address calibration mode 163456.doc -55·201246211. For example, a fourth mode register (MRW#44) command is transmitted as a command/address calibration end signal. When the command/address signal CA[9:0] of 10 bits is uploaded in the command/address bus 12, the MRW#44 command can be set by a mode register setting command, and the mode is temporarily stored. The device setting command may include a CA[3:0] for indicating that the command is a mode register setting command and a command/bit for indicating the mode register setting command is an exit command/address calibration mode command. Address signal CA[9:4]. The MRW #44 command can be input at both the rising and falling edges of the clock signal CK corresponding to time t5. That is, the same MRW #44 command is input at both the rising edge and the falling edge of the clock signal CK starting at time t5. After the predetermined time tMRZ is delayed from the time t5 at which the clock signal CK of the MRW #44 command is input, the output of the calibrated command/address signal CAyR via the DQ pad is terminated. The period from the time t0 when the MRW #41 command is input to the time t5 CK at which the MRW #44 command is input at that time plus tMRZ can be a CA calibration period. Although Figure 13 shows only two sets of test patterns (for CAxR and CAxF and for CAyR and CAyF) sent during the calibration mode period, more than two test patterns can be sent during a calibration cycle. In addition, Figure 13 illustrates a logic window that is positioned such that its logic window center corresponds to the command/address calibration signal for the corresponding clock edge of clock CK. However, this is for illustrative purposes only; it is contemplated that controller 20 will change the relative phase of each of the command/address calibration signals (representing the calibration test pattern) such that clock edge CK is for command/address The timing of the numerous command/address calibration signals in the calibration signal will be shifted in time (and may be center shifted relative to the command/address calibration signal logic window)

163456.doc 56 - S 201246211 bits (eg, on the outside thereof) such that memory device 30 incorrectly interprets one of the command/address alignment signal logic timings). Figure 14 is a table for explaining one of the mode register command setting methods according to another embodiment. Referring to FIG. 14, the MRW #43 command and the MRW #44 command can be set by the clock enable signal CKE, the wafer select signal /CS, and the command/address signal CA[9:0]. When the clock enable signal CKE is in a logic high state, the chip select signal /CS is in a logic low state, the command/address signal CA[3:0] is in a logic low state, and the command When the address signals CA[9:4] are respectively under a logic level HLHLHH, the MRW#43 command can be set. That is, the MRW #43 command can be represented by a command/address signal CA[9:0] value of 2BH. As described above, the MRW #43 command may be the same at both the rising and falling edges of the clock signal CK, however, a different value (eg, the inverse of 2BH) may alternatively be sent to the memory device. 30. When the pulse enable signal CKE is in a logic high state, the chip select signal /CS is in a logic low state, the command/address signal CA[3:0] is in a logic low state, and the command The MRW#44 command can be set when the address signals CA[9:4] are respectively under the logic level HLHHLL. That is, the MRW #44 command can be set identically at both the rising edge and the falling edge of the clock signal CK. In this paper, the command/address signal CA[9:4] can be used as the mode register location address MA[5:0]. Figure 15 is a diagram for illustrating one example of a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment. Referring to FIG. 15, the command/address 163456.doc -57-201246211 signal CA[9:0] input at the rising edge of the clock signal CK can be mapped to be output to the DQ pad DQ of the memory device 30 [ 9:0]. Thereafter, the result of the calibration of the command/address signal CA[9:0] input at the falling edge of the clock signal CK can be mapped to be output to the DQ pad DQ[9:0]. For example, in FIG. 13, the value of the command/address signal CAxR input at the rising edge of the clock signal CK corresponding to the time ^ can be mapped to be output to the DQ pad DQ[9:0], and then The value of the command/address signal CAxF input at the falling edge of the clock signal CK corresponding to the time ti can be mapped to be output to the DQ pad DQ[9:0]. The value of the command/address signal CAyR input at the rising edge of the clock signal CK corresponding to time t4 can be mapped to be output to the DQ pad DQ[9:0], and then, at time corresponding to time t4 The value of the command/address signal CAyF input at the falling edge of signal CK can be mapped to output to DQ pad DQ[9:0]. Figure 16 is a diagram showing one example of another example for illustrating a mapping between a command/address signal and a DQ pad of a memory device 30 in accordance with another embodiment. Referring to Fig. 16, a portion of the value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be sequentially mapped to the DQ pad DQ[4:0] at predetermined time intervals. A portion of the value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK may be sequentially mapped to the DQ pad DQ[5:9] at predetermined time intervals. For example, in FIG. 13, after the values of the command/address signals CA[9:0] of the command/address signals CAxR and CAxF are respectively input at the rising edge and the falling edge of the clock signal CK at time q, respectively. The value of CAxR CA[4:0] (as input) can be output via DQ pad DQ[4:0], respectively, followed by 163456.doc -58 - 201246211 by DQ pad DQ[4:0] The output CAxR is output as one of the values CA[9:5] (as input). However, the value of the command/address signal CA[4:0] of CAxF is output via DQ pad DQ[9:5] (as an input), followed by the command/address signal outputting CAxF via DQ pad DQ[9:5] The value of CA[9:5] (as input). Figure 17 is a diagram showing one example of another example of mapping between a command/address signal and a DQ pad in accordance with another embodiment. Referring to FIG. 17, a portion of the input value of the command/address signal CA[9:0] input at the rising edge of the clock signal CK can be sequentially output to the DQS pads DQS0 and DQS1 and the DQ pad DQ[3:0]. . For example, the value of the command/address signal CA[3:0] of CAxR is output via DQ塾DQ[3:0], where the value of the command/address signal CA4 of CAxR is output via the DQS pad DQS0. Then, the value of the command/address signal CA[8:5] of CAxR is output via the DQ pad DQ[3:0], wherein the value of the command/address signal CA9 is output via the DQS pad DQS1 q - can be in the clock The portion of the input value of the command/address signal CA[9:0] input at the falling edge of the signal CK is sequentially output to the DQS pad/DQS0 and /DQS1 and the DQ pad DQ[7:4]. For example, after outputting the portion of CAxR as described above, the value of the command/address signal CA[3:0] of CAxF is output via the DQ pad DQ[7:4], and the command of CAxF is output via the DQS pad/DQSO. / The value of the address signal CA4, the value of the command/address signal CA[8:5] of the CAxF is output via the DQ pad DQ[7:4], and the command/address signal CA9 of the CAxF is output via the DQS pad/DQS1. value. Figure 18 is a diagram of an exemplary command/address calibration method in accordance with another embodiment. FIG. 18 is a timing diagram illustrating a command/address calibration method in the memory device 30 shown in FIG. 5, wherein the memory device 30 is 163456.doc-59·201246211. . The method represented by FIG. 18 may be the same as the method described above with respect to FIG. 1G or its #代代方案, &amp; the method represented by FIG. a may be used to calibrate information from the memory device at command/address. The output to memory controller 20 differs. In addition, _ illustrates the use of a specific instance of Μ 43 43 as an entry command/address calibration mode command and uses a specific instance of MR 4 4 as the quit command summary calibration mode command One of the options. Since the timing and operation of the memory system 10 of the embodiment of FIG. 1 and its alternatives have been described above, there is no need to repeat one of the common features of the embodiment of FIG. 10 and FIG. (4) The input command/address signal can be set in various ways (: eight\11 and (:in\17 and ]〇(the mapping between the 5 pads. As a mapping example, the time interval can be scheduled at the clock signal CK The portion of the command/address signal CAxRi value input at the rising edge is sequentially output to the even DQ pad DQ[2n], and the command/address signal CAxF input at the falling edge of the clock k number CK can be input at predetermined time intervals. Partial sequential output of values To the odd DQ pad DQ[2n+1], to to 4. An example of this is further explained with respect to Fig. 19. As another mapping example, the command/address signal CA of the CAxR input at the rising edge of the clock signal CK2 will be CA. The value of [3:〇] is output to the even dq pad DQ[2n], where η is 3 to 0, and the value of CAxR command/address signal CA4 is output to 〇(^〇(^〇, meanwhile CAxR) The values of the command/address signals CA[8:5] are output to the even DQ pads DQ[2n], where n is 8 to 5, and the value of the command/address signal cA9 of CAxR is simultaneously output to 塾DQS1 ° At the same time, the value of CAxF command/address signal ca[3:〇] is output to the odd DQ pad DQ[2n+1], where 11 is 3 to 〇, and 163456.doc 201246211 CAxF is commanded / The value of the address signal CA4 is output to the DQS pad/DQS0, and the values of the CAxF command/address signals CA[8:5] are respectively output to the odd DQ pads DQ[2n+l], where the η is 8 to 5, And simultaneously outputting the value of the command/address signal CA9 to the DQS pad/DQS1. In this embodiment and all other embodiments set forth herein, the method may be performed as described above with respect to CAxR and CAxF. The mapping and output of the command/address signals of the loop (eg, 'other CAnR and CAnF, eg CAyR and CAyF) to the output of the memory device are later calibrated, but this is not required. Also 'although already related to memory The terminals (eg, pads, pins, bumps, etc.) of the body device 30 illustrate the mapping and output, but for all of the embodiments described herein, the same applies to the memory device 3 and the memory controller. 20 provides communication between the associated bus and signal lines and the memory controller - terminals (pads, pins, bumps, etc.). For example, in one embodiment, some command address information (or value) is output to one of the even DQ pads of the memory device 3, and the command address information (or value) is included via DQ. The transmission of the even DQ lines of the bus bar 13 and the reception by the memory controller 2() through the corresponding even DQ terminals. Figure 19 is a diagram showing one example of a mapping between a command/address signal and a Dq pad, in accordance with an embodiment. Referring to FIG. 19, a portion of the value of the command/address signal CA[9:0] input at the rising edge of the clock signal (:1&lt;: may be sequentially output to the even DQ pad dq [2η], where n is 〇 to 4. The part of the value of the command/address signal CA[9:0] input at the falling edge of the clock signal CK2 can be sequentially output to the odd 〇9 pad DQ[2n+1], where To 4. For example, in Figure 〇, the command/address signal CA[0:4 of cAxR input at the rising edge of the clock signal CK corresponding to the time t! at 163456.doc • 61 * 201246211 can be entered. The value is output to the even dq pad DQ[2n], and the value of the CAxF command/address signal CA[0:4] input at the falling edge of the clock signal CK is output to the odd DQ pad DQ[2n+ l], where η is 0 to 4. At a subsequent time (which can be immediately after this output), the value of the CAxR command/address signal CA[5:9] can be output to the even DQ pad DQ [ 2n], and the value of the CAxF command/address signal CA[5:9] can be output to the odd DQ pad DQ[2n+l], where η is 0 to 4. At a later time, it can be similar Mode outputs calibration information associated with other calibration cycles, for example, Regarding CAyF and CAyR as illustrated in Figure 10. Figure 20 is a diagram showing one example of another example for illustrating the mapping between a command/address signal and a DQ pad in accordance with an embodiment. The value of the command/address signal CA[9:0] (eg, 'CAxR) input at the rising edge of signal CK can be mapped to output to DQS pads DQS0 and DQS1 and even DQ pads DQ[2n], where η is 0 To 3 » For example, the value of the CAxR command/address signal CA[0:3] is output to the even DQ pad DQ[2n], and the value of the CAxR command/address signal CA4 is output to the DQS pad DQS0. (where n is 〇 to 3.) Then, the value of the CAxR command/address signal CA[5:8] is output to the even DQ pad DQ[2n], and the value of the CAxR command/address signal cA9 is output. To DQS pad DQS1 (where η is 0 to 3.) The value of the command/address signal CA[9:0] (for example, CAxF) input at the falling edge of the clock signal CK can be mapped to output to the dqs pad. /Dqs〇 and /DQS1 and odd Dq pad DQ[2n+l], where n is 〇 to 3. For example, 丨63456.doc 善s 201246211, the CAxF command/address signal CA[0:3] The value is output to the odd DQ pad DQ[2n+l], The value of the CAxF command/address signal CA4 is output to the DQS pad/DQS0. Then, the value of the CAxF command/address signal CA[5:8] is output to the odd DQ pad DQ[2n+l], The value of the CAxF command/address signal CA9 is output to the DQS pad/DQS1. The output of CA[4:0] of CAxR and CA[4:0] of CAxF can occur simultaneously. The output of CA[5:9] of cAxR and CA[5:9] of CAxF can occur simultaneously. At a later time, calibration information associated with other calibration cycles can be output in a similar manner, such as CAyF and CAyR as illustrated with respect to FIG. 21 is a block diagram showing another example of a memory system that can be used to implement one or more of the ca calibration embodiments set forth herein. Referring to FIG. 2, the delta recall system 4 is different from the memory system shown in FIG. 5, because of the command/address calibration information CAr (as interpreted by the memory device 60 from the controller 5). The phase-adjusted calibration signal cAsp2) is provided to the memory controller 50 via a separate calibration bus CA_Cal 15 instead of the bus bar. The calibration bus CA-(5) 15 can be dedicated to transmitting the received command/address information CAr during the calibration mode. When not in the calibration mode (during normal operation of JL), the calibration m stream cA_Cal丨5 can be used for another function or not. For example, the calibration busbar ca-Μ 15 can be used to transfer calibration information from the memory device to the memory controller 50 during the -Dq bus calibration mode. The DQ calibration can be the same as the ca calibration described in any of the CA calibration embodiments herein, and the DQf quasi-information can be transmitted and the CA calibration information is the same. 1 The DQ calibration system is in the calibration system. Executed in the case of a passing wheel, and because of 163456.doc -63- 201246211, there is no need for a repetitive statement here. Therefore, during the calibration of the command/address signal, 'the other signal can be transmitted through one of the additional signal lines DQ signal line and one DQS signal line', thereby improving efficiency. To avoid a repetitive statement, a detailed description of one of the components in Fig. 5 will not be provided. In the memory controller 50, the clock generator 201 generates a clock signal CK to supply the clock signal CIC to the memory device 60 through the clock signal line 11. The CA transmitter 203 adjusts the phase or timing of the initial command/address signal CAspi in response to the control signal CTRL of the phase/timing controller 208 to produce a phase adjusted command/address signal C Asp2 » in the 5 memory device 60 The CA receiver 308 receives the phase-adjusted command/address signal casp2 in response to a timing of the internal clock signal ICK and when the clock enable signal cke and the wafer select signal /CS are enabled to generate a command. / Address calibration information CAr. The command/address calibration information CAr is supplied from the memory device 60 to the memory controller 50 through the calibration bus CA-Cal 15. The command/address calibration information CAr is supplied to the comparator 206 of the memory controller 50 through the calibration bus cA_Cal 15.

The comparator 206 of the suffix controller 50 compares the transmitted command/address information CAS (which may be the information of the phase-adjusted command/address signal CAsp2 - which may be associated with the initial command/address signal CAspl The information is the same) and the received command/address calibration information CAr is used to generate the pass signal p or the fail signal F. The phase/timing controller 208 generates a control signal CTRL indicating a phase shift of one of the phase adjusted commands/address signals c A ^ P ^ based on the pass signal P or the fail signal F generated by the comparator 2〇6. The CA transmitter 203 generates a phase adjusted command/address signal ~ according to the control signal 163456.doc • 64· 201246211 CTRL. During the calibration of one of the command/address communications between the memory device 60 and the memory controller 5, a plurality of loops of the phase-adjusted command/address signal can be executed (each cycle has a relative The clock CK - different adjusted relative phase) and may select between the clock CK and the command/address signal transmitted from the memory controller 50 to the memory device 6 based on a plurality of P and F failure decisions. The preferred relative phase is as exemplified herein with respect to other embodiments (eg, the memory controller 2 and the memory device 3 of FIG. 5) and a 'by repeating the CA calibration cycle, the memory The phase/timing controller 2〇8 of the controller % determines the clock used to trigger the memory device 6 to input (for example, latch) the command/address L number CA from the middle thereof with one or more clocks. Or one of the best relative phases of any command/address signal. Therefore, the memory device 6 receives a command/bit corresponding to the rising edge and the falling edge of the clock signal CK (which can be the rising and falling edges of the clock signals CK and CKB) for the middle of one of the effective windows. Address signal ca. As with the other embodiments set forth herein, a single command/address signal line CA can be used (this calibration can be used to determine a single optimal relative phase of one of all ## lines of a command/address bus 丨2), Calibration is performed for some but not all command/address signal lines of the command/address bus 12 or for all command/address signal lines of the command/address bus 12 (individually or as a group). The results can be used to determine and control the relative phase between the clock CK and the apostrophe line of the command/address busbar 12, the signal line of the command/address bus 丄2 or as a single group (eg, command) All signal lines of the address bus are sent with the same best relative phase as the clock CK 163456.doc -65- 201246211), a plurality of groups (ie, the signal of the command/address bus 丨2) Each of the line groups has one of the best relative phases determined by the memory controller 50 and can share circuitry during normal operation to achieve the determined optimal relative phase - for example, the CA phase/timing controller 208) Or individually (eg, each of the signal lines of the command/address bus 12 has one of the best relative phases determined by the memory controller 5 且 and may have a dedicated (non-shared) circuit during normal operation) To achieve this determined optimal relative phase, such as a dedicated CA phase/timing controller 208). 22 is a block diagram showing another example of a memory system that can be used to implement one or more of the command/address alignment embodiments set forth herein. Referring to Figure 22, a memory system 70 can include a memory controller 8A and a memory device 90. The memory controller 80 can include a clock generator 801, a command/address (CA) generator 8〇2, a ca generating reference unit 8〇3, a register unit 8〇4, and a comparator 8〇. 6. A phase/timing controller 808 and data input/output units 81 and 812. The memory controller rib supplies the clock signal generated by the clock generator 8〇1 to the memory device 90 via the clock signal line 11. The memory system 70 additionally includes a CA reference signal line CA_Ref 16. The CA reference signal line CA_Ref 16 communicates with the command/address CA between the memory controller 8 and the memory device 70 (a signal CA-Refj is transmitted in the eight-calibration mode to receive a CA reference calibration information CA_Refr. CA The reference calibration information CA_Refr is provided to the CA_Ref comparator 8〇6 to determine one of the results of one of the CA calibration cycles (eg, by P or F), which is provided to the phase/timing controller 808 to provide a control signal 〇1111^至〇八产163456.doc -66· 201246211 The generator 802 adjusts the relative phase or timing of the command/address signal CA with respect to the clock CK. Since a CA reference signal line CA_Ref 16 is provided, The command/address signal CA is simultaneously transmitted via the command/address bus 12 to perform the calibration of the command/address CA communication. The CA generator 802 generates one phase that has been determined (possibly adjusted) in response to the control signal CTRL or One of the timing CA signals is transmitted to the memory device 90 via the command/address bus 12. The CA generation reference unit 803 can be configured identically to the CA generator 802 (eg, can be used from a memory cell) Library The same circuit memory cell has the same circuit configuration, and generates a transmitted command/address reference signal CA_Refs. The transmitted command/address reference signal CA_Refs may be the same as the command/address signal CA generated by the CA generator 802. Or completely independent of the command/address signal CA. The transmitted cold/address reference signal CA_Refs may be generated by one of the control signals CTRL, which may be provided by the CA phase timing controller 808 (or free CA) The information provided by the phase timing controller 808 is derived. The transmitted command/address reference signal CA_Refsi phase controlled by the control signal CTRL can be the same as the phase of the CA signal output by the CA generator 802. The /address reference signal CA_Refs is provided to the register unit 804 to store the information indicated by the transmitted command/address reference signal. The transmitted command/address reference signal CA_Refs is provided to the transmit command/address reference signal CA_Refs The CA reference signal line CA_ref 16 is transmitted to the memory device 90. The register unit 804 stores the transmitted command/address reference signal 163456.doc -67·2012462 11 - s indicates that the comparator 806 compares the information of the throughput command/address reference letter A_Refs stored in the register unit m with the data input unit 81 via the 隐 隐 hidden controller 8G ( The received command/address reference calibration information received from the memory device 9 以 compares the information and the transmitted command/address reference signal CA_Refs stored in the CA_Ref temporary (4) 4 with the comparator comparator 〇6 The received command/address references the calibration information CA_Refr to generate a pass signal p or a fail signal f. Each pass of the command/address communication calibration (each cycle corresponds to one of the transmissions of a certain phase of A-Refs) performs a pass signal in the same manner as described herein with respect to the other embodiments. The generation of p or failure signal f, and the group of pass and fail F signals generated during the command/address communication calibration mode can be used to determine the command/address signal and clock CK transmitted via the bus bus 2 An optimal relative phase between. For example, the phase/timing controller 8〇8 generates control of the phase shift of one of the command/address signals CA based on the pass or fail signal 5&gt; or group of F generated by the comparator 8〇8 during the calibration mode. Signal CTRL. The control signal CTRL is used to determine (eg, 'adjust or maintain" the relative phase or timing of the command/address signal ca and the clock ck, and generate a phase adjusted command/address signal transmitted via the command/address bus 12 CA. The data input unit 81, which can be an input buffer and/or an amplifier, receives the received command/address reference calibration information CA_Refr from the memory device 90 through the CA reference signal line CA_ref 16, and receives the received command/address The calibration information CA-Refr is delivered to the comparator 8〇6. A data output unit 812, which may be an output buffer and/or amplifier, receives the transmitted command/address reference signal CA_Refs generated by the CA generation reference unit 163456.doc $-68 - 201246211 803 and will send the command/address The reference signal CA_Refs is transmitted to the CA reference signal line CA_ref. The memory device 90 includes a clock buffer 902, a CA receiver 904, a CA reference receiver 906, and input/output units 908 and 910 (which can be input and Output buffer and / or amplifier). The clock buffer 902 receives the clock signal CK transmitted through the clock signal line 11 to generate an internal clock signal ICK. The internal clock signal ICK may have the same timing (e.g., phase and duty cycle) as the external clock signal CK, or it may be different (e.g., in terms of phase and/or duty cycle). The CA receiver 904 receives the wafer select signal /CS time pulse enable signal CKE and the command/address signal CA transmitted through the command/address bus bank 12. The clock enable signal CKE can be used as a pseudo-command as one of the commands/address signals CA that are transmitted through the command/address bus 12 as explained elsewhere herein. The CA receiver 304 can receive the command/address signal CA when the clock enable signal CKE is in an active state.

The input unit 908 receives the transmitted command/address reference signal CA_Refs transmitted from the memory controller 80 through the CA reference bus CA_ref 16 and transmits it to the CA receive reference receiver 906. The CA Receive Reference Receiver 906 can be configured the same as the CA Receiver 904. The CA receive reference receiver 906 receives the wafer select signal /CS, the clock enable signal CKE, and the transmitted command/address reference signal CA_Refs transmitted through the CA reference bus CA_ref 16, and is on a rising edge of the clock ICK and/or The transmit command/address reference signal CA_Refs is latched at the falling edge (which may be the same time as the edge of the external clock CK or dependent on the time of the external clock CK 163456.doc -69 - 201246211). The command/address reference calibration information CA_Refr received by the message/address reference signal CA_Refs latched by the CA_Ref receiver 906 can be transmitted with the command/address reference calibration information cA_Refr The information indicated by the command/address reference signal CA_Refs is the same or different (for example, 'based on the latch generated by the relative phase of the clock CK and the transmitted command/address reference signal cA_Refs during this cycle of command/address calibration) The received command/address reference calibration information CA_Refr may be the same as the information obtained from one of the signals received via the CA bus 12, and the information is output from the CA receiver 904 to one of the internals of the memory device 70. The source (in response to the internal clock signal ICK inputting the information to the CA receiver 904 when receiving the wafer select signal /cs, the clock enable signal CKE, and the command/address signal CA transmitted through the command/address bus 12 After the CA receiver 904). The received command/address reference calibration information CA_Refr is transmitted to the memory controller 80 via the CA reference signal line CA_ref 16 and the output unit 910. The memory system 70 can perform a plurality of cycles of CA calibration, an exemplary single cycle being set forth below. The CA generator 802 of the memory controller 80 adjusts the phase or timing of the command/address signal CA in response to the control signal CTRL of the phase/timing controller 808. The CA generation reference unit 803 generates a commandable/address/address signal CA. The same command/address reference signal CA__Refs is transmitted, and the transmitted command/address reference signal CA_Refs is transmitted to the memory device 90 via the CA reference signal line CA_ref16. The CA reference receiver 906 of the memory device 90 inputs the transmitted command/address reference signal CA_Refs at the time according to the internal clock signal ICK and is enabled by the time 163456.doc • 70· 201246211 pulse enable signal CKE enabled, and generates The received command/address reference calibration information CA_Refr, "transceives the command/address reference calibration received by the memory device 9 from the CA reference k line ca ref 16 to the memory controller 80 The received command/address reference calibration information CA_Refr is provided to the comparator_. &amp; 806 compares the transmitted command/address reference signal CA with the received information and the received command/address reference calibration The information CA_Refr is generated by the loop for the command/address alignment to generate a pass signal p or a fail signal F^ through the aforementioned CA calibration loop, and the phase/timing controller 808 of the memory controller 8 determines the CA generator 802 via the CA. An optimal relative phase between the CA signal transmitted by the bus 12 and the clock CK. This optimal relative phase may be selected as described herein, and may facilitate the CA receiver 904 to correspond to the command. / The timing input (eg, latch) of the middle portion of the address signal ca logic window is a command/address signal transmitted by the CA bus 12 during normal operation (eg, such that the middle of the command/address signal logic window corresponds to One of the clock signal CK and/or the internal clock signal ick.) Although the calibration of a single command/address signal CA of the CA bus 12 has been described in the current embodiment, the calibration described can be used for Adjust the phase of the signal transmitted on all signal lines of the command/address bus 12. This can be done using only a single CA_ref signal line 16 (applying its calibration results to all signal lines of the command/address bus 12) Alternatively, the CA_ref signal line 16 may be one of the C A_ref signal lines, and each of the plurality of CA_ref signal lines is used to adjust one of the ca bus bars 12 163456.doc • 71 · 201246211 corresponds to a signal line or group of signal lines. In addition, each of the plurality of signal lines 16 may be adjacent to one of the signal lines of the CA bus 12 for calibration (eg, immediately adjacent to 2 or 3 signals) Line or in 2 or 3 letters In-line) This may include a plurality of CA-ref signal lines interposed between the signal lines of the CA bus 12. In addition, in an alternative embodiment, the CA-ref line 16 may be in a mode other than CA calibration ( For example, during normal operation) for other purposes (such as 'transmission of power or other information signals). The memory controller and memory device described herein may take many forms. For example, the memory controller may include a The semiconductor wafer may be a package (eg, one or more wafers encapsulated in a protective casing (eg, a resin)). The memory device may comprise a semiconductor wafer or may be a package (eg, one or more semiconductor memory chips encapsulated in a protective case (eg, resin)). The memory device may be a NAND flash memory. Body (including 3D NAND flash memory), DRAM, pRAM, RRAM &amp; / or MRAM. The memory controller and memory device can be packaged in the same semiconductor package (e.g., a memory controller chip and one or more memory chips stacked together and encapsulated in a package). The controller/device package can be a package overlay (POP). The controller can include a portion of a master memory chip that acts as one of the master devices of one or more slave memory chips, the calibration being performed for the master memory chip and the slave memory chip - or Command/address communication between multiples is performed. The master memory chip and the one or more slave wafers can be stacked and communicated via a through-substrate via (TSV) (eg, through-via via) of each of the wafers connected to each other (wherein the clock is described herein) Signal u 'command/bit 163456.doc •72· 201246211 Address bus 12, DQ bus 13, chip selection signal line / cs, clock enable CKE and data strobe line DQS all or some of - or more of the through holes are formed). The memory controller and memory device can be a component of a memory card (either enemy or removable). • The memory controller and memory device can be mounted on a number of boards that can include the following - the same printed circuit board or in a single computing system. Includes a component of the memory module "Printed Circuitry a computing device (for example, a - personal computer) or other printed circuit board (for example, in a mobile phone, personal data assistant (pD sentence or tablet). For some applications, the controller and The memory device can be integrally formed by the same single semiconductor substrate (eg, a portion of the same semiconductor wafer). For example, the memory can be embedded in a microprocessor, a communication chip, or a digital signal processor. Furthermore, although the above embodiments have been described as being associated with a memory system, the present invention can also be used to calibrate other command/address communications external to the memory system (eg, on a motherboard such as a server, computer, etc.) Between the interconnected nodes) to facilitate communication between devices attached to the motherboard. Further, although the embodiments illustrate the transfer from the memory device to the memory An example of a command/address calibration information of a controller is an interpretation of a command/address calibration signal sent from a memory controller to a memory device (eg, by a hidden device as an input), However, 'other types of assets may also be sent. For example, if the test pattern is predetermined (whether it is programmed or will be programmed when command/address calibration is performed), then the memory device is 163456.doc • 73· 201246211::: Determine whether the information it has entered is entered without error in response to this, indicated to the memory controller by P or F. Another option is that the memory device can contain a box of m 4 (d) for the purpose of having a relationship between the series of bits that constitute the test transmitted during the parent quasi-cycle and/or as part of the test pattern: a bit between the bits of the bit (and thus sent to memory) The logic of one of the controller's pass or fail signals. In addition, the calibration of the command/address communication has been explained to calibrate the timing used to input the command/address signal into the memory device, however, the executable command: Address communication Type calibration. For example, for each cycle of command/address communication calibration, the controller can change - terminal power of one of the signal power, controller, and/or memory device (eg, an adjustable die termination) One of the load cycles (up and/or in series) and/or command/address calibration signals. It should be noted that this description illustrates a command/bit by means of a calibration test pattern signal sent via a command/address bus. Calibration of address communications. It is contemplated that certain embodiments will allow some but not all of the signal lines of a command/address bus to be shared between command and address information during normal operation. A design may require 22 address bits and 1 command bit, which may result in one or more of the signal lines of the command/address bus that are not used to transmit a command bit (eg, if commanded) / address bus 2 is composed of eleven signal lines transmitting twenty-two (22) address bits (in groups of two groups of - (11) bits), then communication can only Requires ten of ten (1) signal lines (10) Bits, leaving one of these signal lines are not used for command communication). As another example, the command/address bus bar 163456.doc •74· 201246211 has signal lines available for command communication 'but some of these signal lines may not be used for address communication (eg, one command) Twenty (20) bits of the information's eleven bits and address information may be left—one of the eleven signal line commands/address bus lines is not used for address communication). Although the present invention has been particularly shown and described with reference to the exemplary embodiments of the present inventive concepts, which are provided for illustrative purposes, and those skilled in the art will appreciate that various modifications can be made in accordance with the inventive concepts. And equivalent to other embodiments. Therefore, the scope of the inventive concept should be defined by the scope of the accompanying application patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are timing diagrams for explaining the concept of command/address calibration; FIG. 3 is a block diagram for explaining one of memory systems for executing command/address calibration; 4 and FIG. 4 are diagrams illustrating, for example, a command/address calibration performed by the memory system shown in FIG. 3; FIG. 5 is used to implement one or more of the commands set forth herein/ One of the first examples of one of the memory systems of the address calibration embodiment; FIG. 6 is a table for explaining one of the command/address calibration methods according to a first embodiment; FIG. 7 is for explaining Figure 1 is a diagram showing one example of a mapping between a command/address signal and a DQ pad according to an embodiment. formula;

9 is a diagram showing another example of a mapping between a command/address signal and a DQ 163456.doc -75 - 201246211 pad according to an embodiment; FIG. 1 is used to illustrate another One of the commands/address calibration methods of one embodiment; FIG. 11 is a diagram showing one example of a mapping between a command/address signal and a DQ pad according to another embodiment; 12 is a diagram showing one example of another example for describing a mapping between a command/address signal and a DQ pad according to another embodiment; FIG. 13 is for explaining a command/bit according to another embodiment. Figure 14 is a diagram for explaining one of the mode register command setting methods according to another embodiment; Figure 15 is a diagram for explaining a command/address according to another embodiment Figure 1 is a diagram showing one example of another example of a mapping between a command/address signal and a DQ pad in accordance with another embodiment; 17 is a diagram for explaining between a command/address signal and a DQ pad according to another embodiment. Figure 1 is a diagram of one of the command/address calibration methods for another embodiment; Figure 19 is a diagram for illustrating a command/address signal in accordance with another embodiment. One of the examples of mapping between a DQ pad and FIG. 20 is a diagram showing another example of a mapping between a command/address signal and a DQ pad according to another embodiment; The 21 Series display can be used to implement one or more of the commands described in this article / 163456.doc

S 76. 201246211 Address Calibration Example One block diagram of another example of a memory system; and FIG. 22 shows one of the embodiments of one or more command/address alignments that may be used to implement the ones described herein. A block diagram of another example of a memory system. [Main component symbol description] 10 Memory system 11 Clock signal line 12 Command/address bus 13 Data signal bus 15 Separate calibration bus/calibration bus 20 Memory controller 30 Memory device 40 Memory system 50 Memory Controller 60 Memory Device 70 Memory System 80 Memory Controller 90 Memory Device 201 Clock Generator 202 Command/Address Generator 203 Command/Address Transmitter / 204 Register 206 Comparator 208 Phase /Sequence Controller 163456.doc •77· 201246211 210 Input/Output Unit 212 Input Buffer 214 Selection Unit 216 Output Buffer 302 Clock Buffer 304 Command/Address Receiver 310 Data Input/Output Unit 312 Selection Unit 314 Output Buffer 316 Input Buffer 801 Clock Generator 802 Command/Address (CA) Generator 803 Command/Address Generation Reference Unit 804 Register Unit 806 Comparator 808 Phase/Timing Controller 810 Data Input Unit 812 Data Output Unit 902 Clock Buffer 904 Command/Address Receiver 906 Command/Address Reference Receiver 908 Input Unit 910 Output Unit CA Command/Address Signal 163456.doc 78. [s 201246211

CA_Cal CA_Refr CA_Refs CA1 CA2 CA3 CA4 CAnF CAnR CAr CAS C ASp i CAsp2 CAxF CAxR CAyF CAyR CK CKB CKE CMD/ADDR /cs CTRL DQ Individually calibrated bus/calibration bus received command/address reference calibration information sent command /address reference signal first command / address signal first command / address signal command / address signal command / address signal command / address signal command / address signal received command / address calibration information is sent Command/address information initial command/address signal phase-adjusted command/address signal command/address signal command/address signal command/address signal command/address signal clock signal clock signal clock enable signal Command/address signal chip select signal control signal data signal 163456.doc •79· 201246211 DQS data strobe clock ICK internal clock signal MRW#41 first mode register command MRW#42 second mode register command MRW#43 Third Mode Register Command - MRW#44 Fourth Mode Register Command. R_DATA1 Read Data R_DATA2 Read Data SEL1 First Select Signal SEL2 Second Optional signal W_DATA1 write data W DATA2 written information I63456.doc • 80-

Claims (1)

201246211 VII. Patent application scope: 1. A method for communicating with a memory device, which comprises: transmitting a calibration command via a command/address bus; sending a sequence of η via the command/address bus First test signals, wherein η is equal to one integer greater than 2 or greater; together with each of the n first test signals, transmitting a clock signal via a first clock line, the n first test Each of the signals is transmitted with a respective first to nth phase relative to one of the clock signals, 'each of the first to nth phases being different from each other; via a data bus Receiving, by each of the n first test signals sent from the sequence of the command/address bus, a rl second test signal; and comparing the n first test signals with the n second test signals And determining, in response to the comparing the n first test signals and the received n first measurement signals, that the signal to be transmitted via the command/address bus is relative to one of the clock signals Phase. 2. The method of claim 1, wherein each of the n first test signals. The first plurality of bits followed by the second plurality of bits transmitted in parallel via the command/address bus are serially transmitted by the command/address bus. 3. The method of claim 2, wherein the force includes a packet in the first plurality of bits and each of the second plurality of bits. 4. As in the case of claim 2, the force is "to" one of the rising edges of one of the n first test signals and one of the clock signals is decreased by 163456.doc 201246211 a plurality of bits And transmitting the first rising edge and the clock signal to the first plurality of bits at one of the other ones of the falling edges of the clock signal number. 5. The method of claim 1, wherein at least a portion of the n second test signals of the sequence are received via a data gating line. 6. The method of claim 1 wherein at least a portion of the n second test signals of the sequence are received via a line dedicated to calibration during at least one calibration mode. 7. If you ask for it! The method of comparing the n first test signals with the same. The step of the second test signal includes determining whether each of the second test signals is identical to a corresponding first test signal. 8. The method of claim 1, wherein the preferred phase is determined to correspond to one of the first to nth phases. 9. The method of claim 8, wherein determining the preferred phase comprises determining a phase sequence of the first to the eleventh phases, each phase of the phase sequence corresponding to the second test signal determined to be valid. An interface training method, comprising: transmitting a first calibration signal to a semiconductor device via a command/address bus; transmitting a clock signal to the semiconductor device together with the transmitting of the first calibration signal The clock signal provides a timing to the semiconductor device to latch the logic level of the first calibration signal; receiving a second calibration signal from the semiconductor device via a data bus. The first calibration signal is latched logic 163456.doc 201246211 level derived; along with the transmission of the clock signal, the command and address signals are sent to the semiconductor device via the command/address bus, the commands and A phase between the address signal and the clock signal is responsive to the second calibration signal. 11. The method of claim 10, further comprising transmitting a read request signal to the semiconductor device via one of the first lines separated from the command/address bus while transmitting the first calibration signal. The method of claim 11, wherein the first line is a clock enable line. 13. The method of claim 10, wherein the first calibration signal comprises transmitting a data packet sequence at a rate that is at least twice a rate of a period of the clock signal. 14. The method of claim 10, wherein the transmitting of the first calibration signal to the semiconductor device comprises transmitting a training pattern via each of the plurality of lines of the command/address bus. 15. The method of claim 14, wherein the training pattern is the same for each of the plurality of lines of the command/address bus. The method of claim 14, wherein the transmitting of the command and address signals via the command/address bus includes: individually adjusting each of the plurality of lines of the command/address bus The phase between the command and the address signal and the clock signal. 17. The method of claim 14, wherein the transmitting of the command and address signals via the command/address bus comprises: passing the first line of the command/address bus to be relative to the One of the first signals of the clock signal transmits a signal 163456.doc 201246211 and a second line via one of the command/address bus bars to transmit a second signal with respect to one of the second phase of the clock signal. 18. The method of claim 10, wherein transmitting the command/address signal comprises transmitting both address information and command information via each of a plurality of lines of the command/address bus. 19. The method of claim 1, wherein the semiconductor device is a first semiconductor device, and wherein the method further comprises: transmitting a third calibration signal to a second semiconductor device via the command/address bus; Transmitting the clock signal to the second semiconductor device together with the transmitting of the third calibration signal, the clock signal providing a timing to the second semiconductor device to latch a logic level of the third calibration signal; Receiving, via the data bus, a fourth calibration signal from the second semiconductor device, the fourth calibration signal being derived from a latched logic level of the third calibration signal; via the transmission of the clock signal The command/address bus sends a command and an address signal to the second semiconductor device, and a phase between the command and the address signal and the clock signal is responsive to the fourth calibration signal. 20. A method of calibrating communication via a command/address bus of a memory device, comprising: receiving a clock signal via a clock signal line; receiving a calibration command via the command/address bus; 4 - 163456.doc 201246211 receiving, by one of the rising edge of the clock signal and one of the falling edges of the clock signal, a first test data packet via the command/address bus to generate the first information; Receiving, by the other of the rising edges and the falling edge of the clock signal, a second test data packet via the command/address bus to generate second information; and transmitting the first via a data bus Information and the second information. 21. The method of claim 20, further comprising receiving a command and an address via the command/address bus at the rising/falling and falling edges of the clock signal. 22. A semiconductor device, comprising: a clock generator configured to generate a clock signal; a clock output terminal coupled to the clock generator and configured to output the clock signal; a command generator circuit configured to generate a command; an address generator circuit 'configured to generate an address; a plurality of command/address terminals; a command/address buffer having a connection to the One of a command/address terminal output coupled to the command generator circuit and the address generator circuit for transmitting a command/address signal from outside the semiconductor device via the command/address terminals a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the command/address bus, the η system being greater than one integer of 2, the phase controller Configuring to adjust one of the n training samples to J/some training patterns relative to one of the clock signals 163456.doc 201246211 bits; a data terminal; and a data buffer connected to the data Promoter, wherein the phase controller is configured to adjust the response via the command and address signals received from the first terminal of the information data such that data from the buffer to the one with respect to the phase of the clock signal. 23. The device of claim 22, wherein the phase controller is configured to control the command/address buffer to transmit an enter calibration mode command via the command/address terminals. 24. The apparatus of claim 23, wherein the phase controller is configured to control the command/address buffer to transmit the n training patterns at a rate that is at least twice the rate of the period of the clock signal Each is a side-by-side sequence of one of the modified sequences. 25. The device of claim 24, wherein each of the n training patterns is of the same type. 26. The device of claim 24, wherein at least some of the n training patterns are different from one another. 27. The device of claim 22, wherein the first information received by the data buffer via the data terminals is responsive to the n training patterns. 28. The device of claim 27, wherein the first information received by the data buffer via the data terminals is derived from latched logic levels of the n training patterns. The device of claim 22, further comprising: a read enable circuit; and 163456.doc S 201246211 a first terminal connected to the read enable sequence - (four) «hour-time period (four) input (four) The circuit generates one of the read enable signals. 30. The apparatus of claim 29, further comprising: - a clock enable circuit coupled to the (four)-terminal to generate a "clock enable signal" from time to time when the sequence of the sequence is not transmitted. 31. The device of claim 22, wherein the phase controller is configured to individually adjust the command and address signals for each of the plurality of lines of the command/address bus relative to the clock One phase of the signal. 32. A system comprising: the apparatus of claim 22, wherein the printed circuit board has a device as claimed in claim 22, the printed circuit board including the command/address terminal connected to the device of claim 22 a command/address bus; and a second device mounted on the printed circuit board, connected to the command/address bus. 33. The system of claim 32, wherein the second device is Semiconductor memory device. 34. A communication method, comprising: receiving a training signal via a command/address bus; receiving - latching a number with the receiving of the training signal; locking in response to at least one edge of the latch signal Storing the training signal to generate training signal information; 163456.doc 201246211 transmitting the training signal information; receiving the command signal and the address signal via the command/address bus; and receiving the special command signal and the address signals Receiving the latch signal together, the latch signal is responsive to the transmitted training signal information with respect to one of the command signals and the address signals; and latching in response to at least one edge of the latch signal The command signals and the address signals. 35. The method of claim 34, wherein latching the training signal and latching the command signals and the address signals comprises latching in response to rising and falling edges of the latch signal. 36. The method of claim 35, further comprising: receiving an incoming calibration mode command on the command/address bus; entering a calibration mode in response to the entering the calibration mode command. 3. The method of claim 3, wherein the incoming calibration mode command is a 'mode register setting (MRS) command, and wherein the step of entering the calibration mode comprises a stylized-mode register setting. 38. The method of claim 36, wherein the step of: receiving: exiting the calibration mode command on the command/address stream; and exiting a calibration mode in response to the exiting the calibration mode command. 39. The method of claim 36, further comprising: monitoring the training signal information; detecting the training signal information containing an exit calibration mode command; and 163456.doc 201246211 responding to detecting that the training signal information includes an exit calibration Exit the calibration mode by mode command. 40. The method of claim 34, further comprising: receiving a signal on a first input while receiving a training signal; and enabling latching of the training signal in response to a signal received on the first input . 41. The method of claim 40, wherein the first input is a clock enable input 0 42. The method of claim 34, wherein transmitting the training signal information comprises: transmitting the training signal via the command/address bus News. 43. The method of claim 34 wherein transmitting the training signal information comprises transmitting the training signal information via one of the training sessions dedicated to training during at least one calibration mode. 44. A semiconductor device comprising: a command/address terminal; a first terminal; a command/address buffer coupled to the command/address terminal for receiving command information, address information, and calibration information a first information, the command/address buffer is responsive to receiving a signal received via the command/address terminal via a clock received by the first terminal; a command circuit coupled to the command/bit The address buffer provides internal commands in response to the command information and in response to the command information; a decoder 'connects to the command/address buffer to receive and decode the address information of 163456.doc 201246211; A control circuit coupled to the command/address buffer is configured to receive the prioritized information and transmit the prioritized information to an external source. 45. The semiconductor device of claim 44, further comprising: a data terminal; and a data buffer coupled to the data terminal, wherein the calibration control circuit is coupled to the data buffer to communicate via the data terminal The calibration information is transmitted to the external source. 46. The apparatus of claim 44, further comprising: a mode register setting, wherein the command circuit is configured to receive an incoming calibration mode command and to respond to the incoming calibration mode command with a first __ program The code stylizes the mode register settings to cause the device to enter a calibration mode, wherein the calibration control circuit transmits the calibration information to an external source in response to the first code. 47. The apparatus of claim 46, wherein the calibration control circuit is configured to detect the calibration information received during the calibration mode, exiting the calibration mode and configured to cause the mode register setting to be modified This causes the device to exit the calibration mode. 48. The apparatus of claim 44, wherein the apparatus comprises a dynamic random access memory semiconductor device of a dynamic random access memory array, wherein the decoder is configured to store in response to the address information Take the location within the array of dynamic random access memory. 163. The device of claim 44, wherein the device comprises a NAND flash memory semiconductor device, wherein the decoder is configured to respond to the Address information accesses the location within the NAND flash memory array. 163456.doc