TWI570729B - Memory device and reading method thereof - Google Patents

Description

Memory device and its reading method

This case is related to a memory device and its reading method.

During the memory reading process, a read disturbance error may occur. The read interference error means that the gate voltage of the memory crystal transistor is too high, so that the electrons/holes in the electron or source/drain of the channel are attracted into the floating gate, causing the stored data to be changed (by 1 becomes 0). For example, when the selected page is being read, if the voltage applied to the unread page transistor gate is too high, it may cause read disturb errors to other unread pages. If the number of reads is thousands or millions of times, the read interference error may become more severe.

Therefore, the present invention proposes a memory device and a reading method thereof, which can reduce read interference errors.

The present invention relates to a memory device comprising an even source line (coupled to a complex even bit line) and an odd source line (coupled to a plurality of odd bit lines), but the even source line and the odd number The source lines are electrically insulated from each other.

This case is about another memory device, including an even grounding option. The line selection (coupled to the complex even bit line) and the odd ground selection line (coupled to the complex odd bit line), but the even ground selection line and the odd ground selection line are electrically insulated from each other.

The present invention relates to a method for reading a memory device, which uses forced bias or self-boost to reduce the gate-source voltage across unread/unselected memory cells during reading. To reduce the occurrence of read interference errors.

According to an embodiment of the present invention, a memory device is provided, including: a plurality of conductive stack structures including at least one string of select lines, complex digital lines, and at least one ground select line; and a plurality of memory cells formed on the conductive stack structures And a plurality of bit lines formed on the conductive stack structures; and at least one odd common source line and at least one even source line formed on the conductive stack structures. The odd common source line is coupled to the plurality of odd bit lines of the bit lines, and the even common source lines are coupled to the complex even bit lines of the bit lines.

According to another embodiment of the present invention, a memory device is provided, comprising: a plurality of conductive stack structures including at least one string of select lines, complex digital element lines, at least one odd ground selection line, and at least one even ground selection line; a plurality of memory crystals Forming cells within the conductive stack structure; complex bit lines formed over the conductive stack structures; and at least one common source line formed over the conductive stack structures. The odd ground selection line is coupled to the plurality of odd bit lines of the bit lines, and the even ground selection lines are coupled to the complex even bit lines of the bit lines.

According to still another embodiment of the present invention, a method of reading a memory device is proposed. The memory device includes a plurality of first bit lines, a plurality of second bit lines coupled to the at least one first common source line of the first bit lines, and coupled to the At least one second common source line of the two bit lines. When reading the first bit lines of a selected page: applying a reference voltage to the first common source line of the selected page; applying a bit line voltage to the selected page a bit line; and applying any one of the bit line voltage and a further reference voltage to the second bit line of the selected page and the second common source line, the bit line The voltage is higher than the reference voltage, and the other reference voltage is higher than the reference voltage, such that one of the plurality of memory cells on the first bit lines of the selected page has a first voltage across the selected page. One of the plurality of memory cells on the second bit line is second across the voltage. For a unselected page: applying the reference voltage to the first common source line of the unselected page; applying the bit line voltage to the first bit lines of the unselected page; and applying the bit line And any one of the voltage and the another reference voltage to the second bit line of the unselected page and the second common source line, such that the plurality of first bit lines of the unselected page The first voltage across the memory cell is higher than the second voltage of the plurality of memory cells on the second bit lines of the unselected page.

According to a further embodiment of the present invention, a method of reading a memory device is proposed. The memory device includes a plurality of first bit lines, and a plurality of second bit lines coupled to the first bit lines and at least one common source line of the second bit lines to control the first One of the channels is a first ground selection line that controls one of the second channels and a second ground selection line. Applying a reference voltage to the common source line of the selected page when reading the first bit lines of a selected page; applying a bit line voltage to the first bits of the selected page And applying any one of the bit line voltage and a further reference voltage to the second bit lines of the selected page, the bit line voltage being higher than The reference voltage, the other reference voltage is higher than the reference voltage, applying the another reference voltage to the first ground selection line to turn on the plurality of ground selection switches on the first bit lines, and applying a shutdown voltage to the first Two ground selection lines to turn off the plurality of ground selection switches on the second bit lines such that one of the plurality of memory cells on the first bit lines of the selected page has a first voltage across the selected page One of the plurality of memory cells on the second bit line is second across the voltage. For a unselected page: applying the reference voltage to the common source line of the unselected page; applying the bit line voltage to the first bit lines of the unselected page; and applying the bit line voltage and And applying any one of the other reference voltages to the second bit lines of the unselected page, applying the another reference voltage to the first ground selection line to turn on the first channels of the unselected page a plurality of ground selection switches, applying the shutdown voltage to the second ground selection line to turn off the plurality of ground selection switches on the second channels of the unselected page, such that the first bit lines of the unselected page The first voltage across the plurality of memory cells is higher than the second voltage of the plurality of memory cells on the second bit lines of the unselected page.

In order to better understand the above and other aspects of the present invention, the following specific embodiments, together with the drawings, are described in detail below:

100‧‧‧ memory device

BL1-BL4‧‧‧ bit line

SSL0-SSL3‧‧‧ string selection line

GSL‧‧‧ Grounding selection line

WL1-WLN‧‧‧ character line

CSL_odd‧‧‧Common source line

CSL_even‧‧‧couple common source line

110‧‧‧Substrate

120‧‧‧ dielectric layer

130‧‧‧Insulation

140‧‧‧ memory cell

I1-I2‧‧‧ current path

T01-TG1, T02-TG2, T03-TG3, T04-TG4‧‧‧O crystal

BL1’-BL4’‧‧‧ bit line

T01'-TG1', T02'-TG2', T03'-TG3', T04'-TG4'‧‧‧ transistor

400‧‧‧ memory device

GSL_odd‧‧‧odd ground selection line

GSL_even‧‧‧ even ground selection line

CSL‧‧‧Common source line

410‧‧‧Substrate

420‧‧‧ dielectric layer

430‧‧‧Insulation

440‧‧‧ memory cell

I3-I4‧‧‧ current path

Fig. 1 is a cross-sectional view showing a portion of a memory device according to a first embodiment of the present invention.

2A and 2B are diagrams showing a reading method (force-bias) according to the first embodiment of the present invention.

3A and 3B show a schematic diagram of another reading method (self-boosting) according to the first embodiment of the present invention.

Figure 4 is a cross-sectional view showing a portion of a memory device in accordance with a second embodiment of the present invention.

5A and 5B are views showing a reading method (forced bias) according to a second embodiment of the present invention.

6A and 6B are diagrams showing another reading method (self-boosting) according to the second embodiment of the present invention.

The technical terms of the present specification refer to the idioms in the technical field, and some of the terms are explained or defined in the specification, and the explanation of the terms is based on the description or definition of the specification. Various embodiments of the present disclosure each have one or more of the technical features. Those skilled in the art can selectively implement some or all of the technical features of any embodiment, or selectively combine some or all of the technical features of these embodiments, where possible.

Referring now to Figure 1, there is shown a cross-sectional view of a portion of a memory device 100 in accordance with a first embodiment of the present invention. As shown in FIG. 1, the memory device 100 according to the first embodiment of the present invention includes: a bit line BL1-BL3, a string select line (SSL) SSL0-SSL3, and a ground select line (GSL). , word line WL1-WLN (N is a positive integer), odd common source line CSL_odd, even common source line CSL_even, substrate 110, dielectric layer 120, A plurality of insulating layers 130 and a plurality of memory cells 140.

An insulating layer 130 is interposed between the string selection line SSL0 and the word line WL1; an insulating layer 130 is also interposed between the adjacent two word lines; and an insulating layer 130 is also interposed between the word line WLN and the ground selection line GSL. .

The insulating layer 130 includes, for example, an interlayer dielectric material such as silicon dioxide or other materials having a dielectric constant.

The above structure is formed on the dielectric layer 120, and the dielectric layer 120 is formed on the substrate 110.

In addition, the memory unit cell 140, which can be used to store data, includes, for example, a multilayer tunneling structure, a dielectric charge trapping layer, and a blocking layer.

In the memory device 100 of FIG. 1, the common source line CSL includes an odd common source line CSL_odd and an even common source line CSL_even, wherein the odd common source line CSL_odd is coupled to all odd bit lines (such as BL1). , BL3...); and the even common source line CSL_even is coupled to all even bit lines (eg BL2, ...).

In the memory device 100 of FIG. 1 , the string selection lines, the word lines and the ground selection lines are stacked in a plurality of conductive stack structures, wherein, for example, the string selection lines and the first characters of the word lines The line groups (eg, word lines WL1, WL2, . . . ) are stacked into a first conductive stack structure, and the ground selection line and the second word line group of the word lines (eg, word line WLN...) are stacked into a first Two conductive stack structures. The memory cells 140 of the memory device 100 are formed within the conductive stack structure. For example, the memory cells 140 are formed on the sidewalls of the conductive stacks. Above (sidewall). The bit lines are formed over the conductive stack structures.

The odd common source line CSL_odd is insulated from the even common source line CSL_even. The odd common source line CSL_odd and the even common source line CSL_even are formed on the conductive stack structures.

Regardless of which page is selected, the string current transmitted by the odd bit line flows through the channel (ie, through an associated conductive stack structure) and flows to the odd common source line CSL_odd, such as the current path. I1 is shown. Similarly, the string currents transmitted by the even bit lines flow through the channel (i.e., through an associated conductive stack structure) and flow to the even common source line CSL_even as shown by current path I2.

Referring now to Figures 2A and 2B, there is shown a schematic diagram of a reading method (force-bias) according to a first embodiment of the present invention. Fig. 2A is a view showing the operation of the forced page reading method according to the first embodiment of the present invention on the selection page. Fig. 2B is a view showing the operation of the forced bias reading method according to the first embodiment of the present invention on the unselected page.

In FIG. 2A, one page includes at least bit lines BL1-BL4, and each of the bit lines BL1-BL4 is coupled to a plurality of transistors T01-TG1, T02-TG2, T03-TG3, T04-TG4, respectively. Of course, the present case is not limited to the number of bit lines or transistors shown in the figures.

The gates of the transistors T01-T04 are all coupled to the string selection line SSL (so, the transistor T01-T04 can also be referred to as a string selection switch); the gates of the transistors T11-T14 are all coupled to the first word line WL1; the gates of the transistors T21-T24 are all coupled to the second word line WL2; the gates of the transistors T31-T34 are all coupled to the third word line WL3;...; the gates of the transistors TN1-TN4 are all coupled to the Nth word line WLN; the gates of the transistors TG1-TG4 are all coupled to the ground selection line GSL (so, the transistors TG1-TG4 can also be called Select the switch for grounding).

The coupling of Figure 2B is similar. The other page includes at least bit lines BL1'-BL4', and each of the bit lines BL1'-BL4' is coupled to a plurality of transistors T01'-TG1', T02'-TG2', T03'-TG3', T04'-TG4'. The gates of the transistor T01'-TG1' (serial selection switch) are all coupled to the string selection line SSL; the gates of the transistors T11'-T14' are all coupled to the first word line WL1; the transistor T21'- The gates of T24' are all coupled to the second word line WL2; the gates of the transistors T31'-T34' are all coupled to the third word line WL3; ...; the gates of the transistors TN1'-TN4' are The gate is coupled to the Nth word line WLN; the gates of the transistors TG1'-TG4' (ground selection switch) are all coupled to the ground selection line GSL.

In FIGS. 2A and 2B, each of the transistors T11-TN1, T12-TN2, T13-TN3, T14-TN4, T11'-TN1', T12'-TN2', T13'-TN3', T14'- TN4' constitutes a memory unit cell. The same applies to FIGS. 3A, 3B, 5A, 5B, 6A and 6B.

As shown in FIG. 2A, for the selected page, all of the bit lines BL1-BL4 are applied with a voltage VBL, which is a positive voltage greater than 0V, typically 0.6-1V. The string selection line SSL is applied with a voltage Vss1 such that the transistors T01-T04 are turned on. Here, the transistor on the read word line WL3 will be described as an example. The word line WL3 is applied with a read voltage Vread to turn on the transistors T31-T34 coupled to the word line WL3, and the remaining word lines are applied with a voltage Vpass to turn on the coupled transistors. The ground selection line GSL is then applied with a voltage Vgs1 to conduct the transistors TG1-TG4 coupled to the ground selection line GSL. That is to say, in this reading method, all the channels of the selected page are turned on, wherein the channel means that all the transistors coupled to the same bit line are composed.

In the first reading method (forced bias) of the first embodiment of the present case, if the odd bit line of the selected page is to be read, the odd common source line CSL_odd is applied with the ground potential (0V), and The even common source line CSL_even applies a voltage VBL. Similarly, if the even bit line of the selected page is to be read, the odd common source line CSL_odd is applied with the voltage VBL, and the even common source line CSL_even is applied with the ground potential (0V).

Through the voltage application method of the above formula, the gate-source voltage across the unread/unselected transistor can be alleviated to slow the reading interference error. For example, taking Figure 2A as an example, when reading the odd bit line of the selected page, the gate-source voltage across the transistor (such as T32) on the even bit line (such as BL2) is (Vpass). -VBL). In contrast, in the current practice, when reading the odd bit line of the selected page, the gate-source voltage of the transistor (such as T32) on the even bit line (such as BL2) is ( Vpass-0). Therefore, it can be seen from this that in the first embodiment of the present case, the gate-source voltage across the unread transistor on the selected page is relatively reduced, so that the read disturb error can be slowed down.

Similarly, for unselected pages, the string selection line SSL is applied with a voltage Vunssl such that the transistors T01'-T04' are turned off. As for the voltages applied to the bit lines BL1'-BL4', the word lines WL1-WLN, and the ground selection line GSL, the voltages are the same or similar to the bit lines BL1-BL4 and word lines applied to the selected page. The voltages of WL1-WLN and ground selection line GSL are not repeated here.

Similarly, for unselected pages, the gate-source voltage across the transistor on the even bit line (eg, transistor T32' on bit line BL2') is (Vpass-VBL) (if currently When reading the odd bit line of the selected page), it is relatively low, so the reading interference error can be effectively slowed down. As for the transistor on the odd bit line of the unselected page (for example, the transistor T31' on the bit line BL1'), the gate-source voltage is (Vpass-0V) (if currently selected in the read) The odd bit line of the page).

Referring now to FIGS. 3A and 3B, there is shown a schematic diagram of another reading method (self-boosting) according to the first embodiment of the present invention. Fig. 3A is a view showing the operation of the selection page by the self-boost reading method of the first embodiment of the present invention. Fig. 3B is a diagram showing the operation of the unselected page by the self-boosting reading method of the first embodiment of the present invention.

As shown in FIG. 3A, the odd bit line of the selected page is taken as an example for description. The odd bit lines BL1, BL3, ... all apply the bit line voltage VBL, and the even bit lines BL2, BL4, ... are applied. The reference voltage Vcc (which is higher than the voltage Vssl). The string selection line SSL is applied with a voltage Vcc such that the transistors T01-T04 are turned on. Here, the transistor on the word line WL3 is read as an example. The word line WL3 is applied with a read voltage Vread to turn on the transistors T31-T34 coupled to the word line WL3, and the remaining word lines are applied with a voltage Vpass to conduct the transistors coupled to other word lines. The ground select line GSL is then applied with a voltage Vcc (which is higher than the voltage Vgsl) to turn on the coupled transistor.

The second reading method (self boosting) in the first embodiment of the present case If the odd bit line of the selected page is to be read, the odd common source line CSL_odd is applied with the ground potential (0V), and the even common source line CSL_even is applied with the voltage Vcc, so as shown in FIG. 3A It is shown that the transistors TG1 and TG3 are turned on, and the transistors TG2 and TG4 are turned off. Similarly, if the even bit line of the selected page is to be read, the odd common source line CSL_odd is applied with the voltage Vcc, and the even common source line CSL_even is applied with the ground potential (0V).

During the reading process, in the selected page, on the unselected bit line (such as BL2), the ground selection switch (such as transistor TG2) at one end of the channel is turned off, and the string selection switch at the other end of the channel is closed. (such as transistor T02) is turned on.

Thereafter, the word lines WL1 - WLN are applied with a pass voltage Vpass (except that the word voltage WL3 to be read is applied with the read voltage Vread). Through the coupling effect, the source voltage of the transistor TN2 is pulled up to the potential Vch, wherein the value of the potential Vch is related to the pass voltage Vpass and the coupling coefficient C. For example, with a coupling coefficient C of 0.8 and a pass voltage Vpass of 8V, the potential Vch=Vpass*C=6.4V. Therefore, for the transistor TN2 on the unread bit line of the selected page, the gate-source voltage across the gate is Vpass-Vch. Compared with the prior art, the gate-source voltage of the transistor on the unread bit line of the selected page is Vpass-0V, and the second reading mode of the first embodiment of the present invention can effectively slow down the reading. Take the interference error.

That is to say, in this reading method, in the selected page, the transistors on the unrecorded bit line are floating (except for the transistors (such as T02 and TG2) at both ends of the channel), such as a transistor. T12-TN2, T14-TN4, etc., these floating transistors will be affected by voltage coupling, causing their gate-source voltage to be reduced to Vpass-Vch.

Similarly, for the unselected page, as in Fig. 3B, the string selection line SSL is applied with the voltage Vunssl, so that the transistors T01'-T04' are turned off. The voltages applied to the bit lines BL1'-BL4' and the word lines WL1-WLN are the same or similar to the voltages applied to the bit lines BL1-BL4 and the word lines WL1-WLN of the selected page, the details of which are This is not repeated. The ground selection line GSL of the unselected page is also applied with a voltage Vcc.

Similarly, when the odd bit line of the selected page is read, the transistors (e.g., T12'-TN2') on the even bit line of the unselected page are also floated, so a self boosting operation is also applied. For example, the gate-source voltage across the transistor (e.g., T32') on the even bit line BL2' is (Vpass-Vch), which is relatively low, so that the read disturb error can be effectively alleviated.

Referring now to Figure 4, there is shown a cross-sectional view of a portion of a memory device in accordance with a second embodiment of the present invention. As shown in FIG. 4, the memory device 400 includes: a bit line (BL1-BL2), a string selection line (SSL0), an odd ground selection line GSL_odd, an even ground selection line GSL_even, a word line WL1-WLN, and a common source. The epipolar line CSL, the substrate 410, the dielectric layer 420, the plurality of insulating layers 430, and the plurality of memory cells 440.

Basically, the substrate 410, the dielectric layer 420, and the plurality of insulating layers 430 are the same as or similar to the substrate 110 of FIG. 1, the dielectric layer 120, the plurality of insulating layers 130, and the plurality of memories. The unit cell 140 is omitted here.

Unlike the memory device 100 of FIG. 1, in the memory device 400 of FIG. 4, the common source line CSL is coupled to the complex bit line. The odd ground select line GSL_odd is coupled to all odd bit lines (eg, BL1, . . . ), and the even ground select line GSL_even is coupled to all even bit lines (eg, BL2, . . . ). Regardless of which page is selected, the string current transmitted by the odd bit line flows through the channel and flows to the common source line CSL as shown by current path I3. Similarly, the string current from the even bit line flows through the channel and flows to the common source line CSL as shown by current path I4.

Referring now to FIGS. 5A and 5B, there is shown a schematic diagram of a reading method (forced bias) according to a second embodiment of the present invention. Fig. 5A is a view showing the operation of the forced page reading method according to the second embodiment of the present invention on the selection page. Fig. 5B is a view showing the operation of the forced bias reading method for the unselected page according to the second embodiment of the present invention.

In FIGS. 5A and 5B, the ground selection line is divided into an odd ground selection line GSL_odd and an even ground selection line GSL_even. The odd ground select line GSL_odd is coupled to all odd bit lines, and the even ground select line GSL_even is coupled to all even bit lines. In addition, the common source line CSL is coupled to all bit lines.

As shown in FIG. 5A, for the selected page, all of the bit lines BL1-BL4 are applied with a voltage VBL. The string selection line SSL is applied with a voltage Vpass or Vcc such that the transistors T01-T04 are turned on. Here, the transistor on the word line WL3 is read as an example. The word line WL3 is applied with a read voltage Vread to turn on the transistors T31-T34 coupled to the word line WL3, and the remaining word lines are applied with a voltage Vpass to conduct the transistors coupled to other word lines. The odd ground connection line GSL_odd coupled to the odd bit line to be read is applied with a voltage Vpass or Vcc to conduct a pass coupling The transistors TG1, TG3, . . . connected to the odd ground selection line GSL_odd. The even ground selection line GSL_even coupled to the unread even bit line is applied with a voltage VGSL to turn off the transistors TG2, TG4, . . . coupled to the even ground selection line GSL_even. The common source line CSL is applied with a ground potential (0V).

In the first reading method (forced bias) of the second embodiment of the present invention, the gate-source voltage across the unread/unselected transistor can be alleviated by the voltage application method of the above formula to slow the reading. Take the interference error. For example, taking Figure 5A as an example, when reading the odd bit line of the selected page, the gate-source voltage across the transistor (such as T32) on the even bit line (such as BL2) is (Vpass). -VBL) (because of the self-boosting relationship). The reason is that, in the transistor on the even bit line, except for the transistors TG2, TG4, the transistors T12-TN2, T14-TN4 are floating, so the source of the floating transistors T12-TN2, T14-TN4 The voltage is self boosted to VBL.

In contrast, in the current practice, when reading the odd bit line of the selected page, the gate-source voltage of the transistor (such as T32) on the even bit line (such as BL2) is ( Vpass-0). Therefore, it can be seen that in the second embodiment of the present invention, the gate-source voltage across the transistor on the unread bit line on the selected page is reduced, so that the read interference can be slowed down. error.

Further, in the first reading method of the second embodiment, since all of the bit lines are applied with the same voltage, the coupling capacitance value between the bit lines is greatly reduced, so that the precharge can be effectively improved.

Similarly, for the unselected page, as shown in Fig. 5B, the string selection line SSL is applied with the voltage Vunss1 so that the transistors T01'-T04' are turned off. As for the voltages applied to the bit lines BL1'-BL4', the word lines WL1-WLN are the same or similar to the voltages applied to the bit lines BL1-BL4 and the word lines WL1-WLN of the selected page, the details of which are This is not repeated. The odd ground selection line GSL_odd coupled to the read odd bit line is applied with a voltage Vpass or Vcc to turn on the transistors TG1, TG3, ... coupled to the odd ground select line GSL_odd. The even ground selection line GSL_even coupled to the unread even bit line is applied with a voltage VGSL to turn off the transistors TG2, TG4, . . . coupled to the even ground selection line GSL_even. The common source line CSL is applied with a ground potential (0V).

Similarly, in Fig. 5B, the conducting current crystals (e.g., transistors T02'-TN2') on the unselected bit lines are self-boosted for the reasons described above. That is to say, the gate-source voltage of the conducting current crystal on the even bit line of the unselected page is reduced to (Vpass-Vch), so that the reading interference error can be effectively alleviated. As for the transistor of the unselected page, the gate-source voltage of the transistor is Vpass-0V.

That is, in Fig. 6A, although it is a forced bias reading method, the transistors that are not read on the bit line are still self-boosting.

Referring now to FIGS. 6A and 6B, there is shown a schematic diagram of another reading method (self-boosting) according to the second embodiment of the present invention. Fig. 6A is a view showing the operation of the self-boosting reading method on the selection page according to the second embodiment of the present invention. Fig. 6B is a view showing the operation of the self-boosting reading method according to the second embodiment of the present invention on the unselected page.

Here, an example of reading a strange bit line of a selected page will be described. As shown in FIG. 6A, the voltages VBL are applied to the odd bit lines BL1, BL3, ... of all selected pages. The voltages Vcc are applied to all of the selected bit lines BL2, BL4, .... The string selection line SSL is applied with a voltage Vpass or Vcc such that the transistors T01-T04 are turned on. Here, the transistor on the word line WL3 is read as an example. The word line WL3 is applied with a read voltage Vread to turn on the transistors T31-T34 coupled to the word line WL3, and the remaining word lines are applied with a voltage Vpass to conduct the transistors coupled to other word lines. The odd ground selection line GSL_odd coupled to the odd bit line to be read is applied with a voltage Vpass or Vcc to turn on the transistors TG1, TG3, ... coupled to the odd ground selection line GSL_odd. The even ground selection line GSL_even coupled to the unread even bit line is applied with a voltage VGSL to turn off the transistors TG2, TG4, . . . coupled to the even ground selection line GSL_even. The common source line CSL is applied with a ground potential (0V).

In the second reading method (self-boosting) of the second embodiment of the present invention, the gate-source voltage across the unread/unselected transistor can be alleviated by the voltage application method of the above formula to slow the reading. Take the interference error. For example, taking Figure 6A as an example, when reading the odd bit line of the selected page, the gate-source voltage across the transistor (such as T32) on the even bit line (such as BL2) is (Vpass). -VBL) (due to the self-boosting relationship), in which the transistors on the even bit line, the transistors T12-TN2, T14-TN4 are floating, so, floating transistors T12-TN2, T14-TN4... The source voltage is self boosted to VBL.

In contrast, in the current practice, when reading the odd bit line of the selected page, the gate-source voltage of the transistor (such as T32) on the even bit line (such as BL2) is ( Vpass-0). Therefore, it can be seen from this that in the second embodiment of the present case, In the case of a transistor on an unread bit line on the page, the gate-source voltage across the gate is reduced, so the read disturb error can be slowed down.

As for the gate-source voltage of the transistor on the odd bit line of the selected page, it is still Vpass-0V or Vread-0V.

Similarly, for the unselected page, as shown in Fig. 6B, the string selection line SSL is applied with the voltage Vunss1 so that the transistors T01'-T04' are turned off. As for the voltages applied to the bit lines BL1'-BL4', the word lines WL1-WLN are the same or similar to the voltages applied to the bit lines BL1-BL4 and the word lines WL1-WLN of the selected page, the details of which are This is not repeated. The odd ground selection line GSL_odd coupled to the odd bit line is applied with a voltage Vpass or Vcc to turn on the transistors TG1, TG3, ... coupled to the odd ground select line GSL_odd. The even ground selection line GSL_even coupled to the unread even bit line is applied with a voltage VGSL to turn off the transistors TG2, TG4, . . . coupled to the even ground selection line GSL_even. The common source line CSL is applied with a ground potential (0V).

Similarly, for the unselected pages, in Figure 6B, the conductive crystals on the even bit lines (such as transistors T02'-TN2') are self-boosted, for the reasons described above. Repeat again. That is to say, the gate-source voltage of the conducting current crystal on the even bit line of the unselected page is reduced to (Vpass-Vch), so that the reading interference error can be effectively alleviated. As for the transistor of the unselected page, the gate-source voltage of the transistor is Vpass-0V.

In the second embodiment of the present case, Table 1 below shows how to apply a voltage to the odd ground selection when the string selection line SSL and the bit line are selected during the read operation. Select the line GSL_odd and the even ground selection line GSL_even.

In the above Table 1, when the page related to SSL0 is selected to be read, (1) when the odd bit line is read, the voltage applied to the odd common source line GSL_odd is Vcc, and is applied to the even common source. The voltage of the line GSL_even is VGSL; (2) when the even bit line is read, the voltage applied to the odd common source line GSL_odd is VGSL, and the voltage applied to the even common source line GSL_even is Vcc.

Similarly, when selecting to read the page related to SSL1, (1) when reading the odd bit line, the voltage applied to the odd common source line GSL_odd is VGSL, and is applied to the even common source line GSL_even The voltage is Vcc; (2) When the even bit line is read, the voltage applied to the odd common source line GSL_odd is Vcc, and the voltage applied to the even common source line GSL_even is VGSL.

Select the voltage to read the pages of SSL2, SSL4, SSL6... The application is the same as the voltage application of SSL0. When you select a page to read SSL3, SSL5, SSL7..., the voltage application is the same as the voltage application of SSL1.

In summary, in the above two embodiments of the present invention, whether it is forced bias or self-boosting, the gate-source voltage across the unselected/unread transistor can be It is effectively reduced, so the occurrence of read disturb errors can be effectively reduced.

In addition, for the pre-charging, in the above embodiment of the present invention, if both the odd bit line and the even bit line are applied with the same voltage, the coupling capacitance value can be effectively reduced, so that the pre-charging can be effectively improved. Inductive noise and current consumption.

In summary, although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present case. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

100‧‧‧ memory device

BL1-BL3‧‧‧ bit line

SSL0-SSL1‧‧‧ string selection line

GSL‧‧‧ Grounding selection line

WL1, WLN‧‧‧ character line

CSL_odd‧‧‧Common source line

CSL_even‧‧‧couple common source line

110‧‧‧Substrate

120‧‧‧ dielectric layer

130‧‧‧Insulation

140‧‧‧ memory cell

I1-I2‧‧‧ current path

Claims (11)

A memory device includes: a plurality of conductive stack structures, each of the conductive stack structures including at least one string of select lines, complex digital lines, and at least one ground select line; and a plurality of memory cells formed within the conductive stack a plurality of bit lines formed on the conductive stack structures; and at least one odd common source line, and at least one even source line formed on the conductive stack structures; wherein the odd common source The pole line is coupled to the plurality of odd bit lines of the bit lines, and the even common source lines are coupled to the complex even bit lines of the bit lines. The memory device of claim 1, wherein a string of currents transmitted by any one of the odd bit lines flows through an associated conductive stack structure of the conductive stack structures. And flowing to the odd common source line; another series of currents transmitted by any of the even bit lines of the even bit lines flow through another associated conductive stack structure of the conductive stacked structures, and then flow to the a common source line; the string selection line and one of the first word line groups of the word lines are stacked into a first conductive stack structure of the conductive stack structures; the ground selection line and the word lines One of the second word line groups is stacked into one of the conductive stack structures; the memory cells form a plurality of sidewalls of the conductive stack; The odd common source line is insulated from the even common source line. A memory device includes: a plurality of conductive stack structures including at least one string of select lines, complex digital element lines, at least one odd ground select line, and at least one even ground select line, each of the conductive stack structures including the string selection line and the And a word line including one of the odd ground selection line and the even ground selection line; a plurality of memory cells formed within the conductive stack structure; and a plurality of bit lines formed on the conductive stack Above the structure; and at least one common source line formed on the conductive stack structures; wherein the odd ground select lines are coupled to the plurality of odd bit lines of the bit lines, the even ground select lines A plurality of even bit lines coupled to the bit lines. The memory device of claim 3, wherein a string of currents transmitted from any of the odd bit lines of the odd bit lines flows through an associated conductive stack structure of the conductive stack structures. And flowing to the common source line; another series of currents transmitted by any of the even bit lines of the even bit lines flow through another associated conductive stack structure of the conductive stack structures, and then flow to the common a source line; the string selection line and one of the first word line groups of the word lines are stacked into a first conductive stack structure of the conductive stack structures; the ground selection line and one of the word lines Stacking a second word line group into a second conductive stack structure of the conductive stack structures; the memory cells forming a plurality of sidewalls of the conductive stacks; The odd ground selection line is insulated from the even ground selection line. A method for reading a memory device, the memory device comprising a plurality of first bit lines, a plurality of second bit lines, coupled to at least one first common source line of the first bit lines, and a coupling Connecting to the at least one second common source line of the second bit lines, the reading method includes: applying a reference voltage to the selected one when reading the first bit lines of a selected page a first common source line of the page; applying a bit line voltage to the first bit lines of the selected page; and applying either the bit line voltage and a further reference voltage to The second bit line of the selected page and the second common source line, the bit line voltage is higher than the reference voltage, and the other reference voltage is higher than the reference voltage, so that the selected page is The first span voltage of one of the plurality of memory cells on the first bit line is higher than the second span voltage of one of the plurality of memory cells on the second bit lines of the selected page; for an unselected page Applying the reference voltage to the first common source line of the unselected page; applying the bit line voltage to the first of the unselected pages And applying the bit line voltage and the other reference voltage to the second bit line of the unselected page and the second common source line, such that the unselected page The first voltage across the plurality of memory cells on the first bit line is higher than the second voltage across the plurality of memory cells on the second bit lines of the unselected page. The reading method of claim 5, wherein when reading the first bit lines of the selected page, If the bit line voltage is applied to the second bit lines of the selected page and the second common source line: applying a series of selected turn-on voltages to the first and second bits of the selected page a plurality of string selection switches on the line to turn on the string selection switches of the selected page; and applying a ground selection turn-on voltage to the plurality of ground selection switches on the first and second bit lines of the selected page To turn on the ground selection switches of the selected page; and for the unselected page: if the bit line voltage is applied to the second bit lines of the selected page and the second common source line: Applying a series of select string turn-off voltages to the plurality of string select switches of the first and second bit lines of the unselected page to turn off the string select switches of the unselected page; and applying the ground select turn-on voltage And a plurality of grounding switches on the first and the second bit lines of the unselected page to turn on the grounding switches of the unselected pages. The reading method of claim 5, wherein, when reading the first bit lines of the selected page, if the another reference voltage is applied to the second of the selected pages a bit line and the second common source line: applying the another reference voltage to the first and second portions of the selected page a plurality of string selection switches on the bit line to turn on the string selection switches of the selected page; applying the other reference voltage to the plurality of ground selection switches on the first bit lines of the selected page to turn on the Selecting the grounding switches on the first bit lines of the selected page; applying the other reference voltage to the plurality of grounding switches on the second bit lines of the selected page to close the selected page The grounding switches on the second bit lines; and after turning off the grounding switches on the second bit lines of the selected page, applying a pass voltage or a read voltage to the complex digital element a line such that the memory cells of the second bit lines of the selected page are floating to form the floating memory cells on the second bit lines of the selected page One of the terminal voltages is self-boosted to a voltage by voltage coupling, the voltage being related to the other reference voltage and a coupling coefficient; and for the unselected page: if the other reference voltage is applied to the unselected page a second bit line and the second common source line: applying one Selecting a turn-off voltage to the plurality of string selection switches on the first and second bit lines of the unselected page to turn off the string selection switches on the first and second bit lines of the unselected page Applying the other reference voltage to the plurality of grounding switches on the first bit lines of the unselected page to turn on the first bit lines of the unselected page Grounding a switch; applying the other reference voltage to the plurality of grounding switches on the second bit lines of the unselected page to turn off the grounding switches on the second bit lines of the unselected page; And after the grounding switches on the second bit lines of the unselected page are turned off, applying the pass voltage or the read voltage to the word lines to make the second of the unselected pages The memory cells on the bit line are floating to self-boost the voltage of one of the floating memory cells on the second bit lines of the selected page through voltage coupling to the voltage . A method for reading a memory device, the memory device comprising a plurality of first bit lines, a plurality of second bit lines, coupled to the first bit lines and at least one of the second bit lines a source line, controlling one of the first ground selection lines of the plurality of first channels, and controlling one of the second ground selection lines of the plurality of second channels, the reading method comprising: reading the first bits of a selected page a line, applying a reference voltage to the common source line of the selected page; applying a bit line voltage to the first bit lines of the selected page; and applying the bit line voltage to the other Any one of the reference voltages to the second bit lines of the selected page, the bit line voltage is higher than the reference voltage, the other reference voltage is higher than the reference voltage, and the another reference voltage is applied Up to the first ground selection line to turn on the plurality of ground selection switches on the first bit lines, applying a shutdown voltage to the second ground selection line to turn off the plurality of ground selection switches on the second bit lines, such that The plurality of memory on the first bit line of the selected page a first voltage across one of the unit cells is higher than a second voltage across the plurality of memory cells on the second bit lines of the selected page; for an unselected page: applying the reference voltage to the unselected page a common source line; applying the bit line voltage to the first bit lines of the unselected page; and applying the bit line voltage to the other reference voltage to the unselected page The second bit lines, applying the other reference voltage to the first ground selection line to turn on the plurality of ground selection switches on the first channels of the unselected page, applying the shutdown voltage to the second ground Selecting a line to turn off the plurality of ground selection switches on the second channels of the unselected page such that the first voltage across the plurality of memory cells on the first bit lines of the unselected page is higher than the The second cross-over of the plurality of memory cells on the second bit lines of the page. The reading method of claim 8, wherein when the first bit lines of the selected page are read, if the bit line voltage is applied to the second of the selected pages Bit line: a plurality of string selection switches that turn on the first and second bit lines of the selected page; and for the unselected page: if the bit line voltage is applied to the selected page a second bit line: applying a string of selection off voltages to the plurality of string selection switches on the first and second bit lines of the unselected page to close the first and the other of the unselected pages The string selection switches on the second bit line. The reading method of claim 8, wherein, when reading the first bit lines of the selected page, if the another reference voltage is applied to the second of the selected pages Bit line: applying the other reference voltage to the plurality of string selection switches on the first and second bit lines of the selected page to turn on the first and second parts of the selected page The string selection switches on the bit line; and after turning off the string selection switches on the second bit lines of the selected page, applying a pass voltage or a read voltage to the complex digital line to make The memory cells of the second bit lines of the selected page are floating to transmit a voltage of one of the floating memory cells on the second bit lines of the selected page Voltage-coupling self-boosting to a voltage related to the other reference voltage and a coupling coefficient; and for the unselected page: if the other reference voltage is applied to the second bit of the unselected page Line: applying a series of selected off voltages to the first and second bits of the unselected page a plurality of string selection switches on the line to turn off the string selection switches on the first and second bit lines of the unselected page; and the second bit lines on the unselected pages After the grounding switch is selected, the pass voltage or the read voltage is applied to the word lines such that the memory cells on the second bit lines of the unselected page are floating to One of the floating-cell memory cell voltages on the second bit lines of the page selects self-boost to the voltage through voltage coupling. A memory device includes: a plurality of conductive stack structures, each of the conductive stack structures comprising a plurality of conductive layers and a plurality of insulating layers, wherein the conductive layers and the insulating layers are alternately stacked in the conductive stack, each of the conductive layers The conductive layers in the stack include at least one string of selection lines, complex digital element lines, and at least one ground selection line; a plurality of memory cells are formed within the conductive stack structures; and a plurality of bit lines are formed in the plurality of lines Above the conductive stack structure; and at least one odd common source line, and at least one even source line formed on the conductive stack structure; wherein the odd common source line is coupled to the bit lines The plurality of odd bit lines are coupled to the complex even bit lines of the bit lines.