TW201324530A - Semiconductor memory device - Google Patents

Abstract

A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing the chip area, comprises the memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a select signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the select signal, and a pump circuit raising the voltage level of the select signal. The word line decoder 120 has lines WR(i) to transmit the select signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a method of driving a word line of a NAND type flash memory.

As a storage device, flash memory can be widely used in electronic devices such as digital cameras and smart phones. In the market, more and more attention is paid to the miniaturization, large capacity, high-speed access, and low power consumption of flash memory.

The NAND type flash memory comprises a memory array including a plurality of NAND gate strings arranged in a row and column direction, and the NAND gate string comprises a series of complex memory cells and a selection transistor coupled to both ends thereof.

Conventionally, when writing data to a memory, a voltage of 0 V is applied to the P well, the drain, and the source of the memory cell substrate, and a high potential write voltage Vpgm (for example, 20 V) is applied to the control gate. When the deletion operation is performed, a voltage of 0 V is applied to the control gate, and a high voltage (for example, 20 V) is applied to the P well to delete the data on the memory block. On the other hand, when the read operation is performed, a voltage of 0 V is applied to the control gate for selecting the memory cell, and a voltage Vread higher than the power supply voltage Vcc is applied to the control gate of the other memory cell. Therefore, the flash memory needs to generate different voltages higher than the power supply voltage Vcc during operation, and apply these voltages to the memory cells through the word lines.

One way to boost the voltage is to use a charging pump. When the word line decoder has a charging pump, the volume of the word line decoder is greatly increased due to the capacitance. In order to solve this problem, Patent Document 1 discloses a word line decoder that does not use a charging pump to reduce the layout area. The word line decoder can self-boost to enable the word line enable signal of the word line to suppress the voltage drop of the word line enable signal.

When the charge pump is used to boost the write voltage Vprm or Vread, the threshold voltage of the NMOS transistor is increased by the bulk effect, and it is difficult to sufficiently boost the voltage. In order to deal with such a problem, the word line decoder of Patent Document 2 applies a voltage to a gate and a drain of a pass-transistor connected to a word line at different time points by transmitting a transistor. Self-boosting prevents the operating voltage from dropping, which in turn reduces the circuit area.

[Patent Document 1] JP-A-2002-197882

[Patent Document 2] JP-A-2006-107701

However, the word line decoder of the conventional flash memory still has the following problems. Figure 1A illustrates the layout of a conventional word line decoder for flash memory. One end of the memory array 10 in the column direction is provided with a word line decoder and a level shifter (hereinafter collectively referred to as a word line decoder 20) and a word line drive circuit 22, and a page buffer is arranged at one end in the row direction. 30. In this example, the memory array 10 is divided into two memory arrays. The word line decoder 20 supplies the required operating voltages for the selected word line and the non-selected word line in response to the address signal. The operating voltage is a write voltage Vpgm supplied to the selected word line at the time of data writing, and a non-selected word line transmission voltage, and a ground voltage supplied to the selected word line when the read operation is performed, and the supply voltage is not supplied. The read voltage Vread of the selected word line.

The word line drive circuit 22 includes a transfer transistor for transmitting the operating voltage from the word line decoder 20 to the gate of the memory cell, and supplies the operating voltage to the corresponding memory cell by turning on the transfer transistor. The word line drive circuit 22 suppresses the decrease in the operating voltage by applying a high voltage to the gate of the transfer transistor.

In the layout shown in FIG. 1A, the word line WL connecting the word line drive circuit 22 must be wired across the column direction of the memory array 10. The word line WL needs to apply a high write voltage Vpgm (for example, 20V) when performing a write operation, and when the load capacity (RC) of the word line WL increases, it takes more time for the voltage to reach the end of the word line. . In addition, in order to transfer the write voltage Vpgm to the memory cell at the end, a high write voltage Vpgm must be applied to the word line write, which greatly increases power consumption. Further, in order to ensure a constant wiring width in order to lower the wiring impedance of the word line WL, it is difficult to reduce the memory array.

On the other hand, the transmission transistor of the word line driving circuit 22 is constituted by an N-channel MOS transistor, and in order to suppress the threshold voltage drop of the writing voltage Vpgm, it is necessary to apply a voltage greater than the writing voltage Vpgm to the gate, so in order to raise the gate The withstand voltage of the pole oxide layer must increase the thickness of the gate oxide film (for example, 400) As a result, the transistor is enlarged, and the circuit area of the word line driving circuit 22 is also increased. In addition, if the word line drive circuit 22 is arranged with a narrow gap, a latch-up phenomenon is likely to occur between adjacent transfer transistors, so that there must be an appropriate interval between the transfer transistors, but at the same time, the wafers are also The area is increased.

Figure 1B shows another conventional flash memory layout. In this example, word line decoders 20A and 20B and word line drive circuits 22A and 22B are disposed on the left and right sides of the memory array. The word line decoder 20A and the word line drive circuit 22A operate for the memory array 10A, and the word line decoder 20B and the word line drive circuit 22B operate for the memory array 10B. The lower page buffer 30A reads or writes data of odd bit lines, and the upper page buffer 30B reads or writes data of even bit lines.

In the layout shown in FIG. 1B, although the wiring length in the direction of the character line WL column can be shortened to half of that in the first AA picture, relatively, the word line decoder and the word line decoder must be respectively disposed on both sides of the memory array. The word line driver circuit also causes an increase in the area of the chip.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art and to provide a semiconductor memory device capable of reducing an electric field applied to a word line on a memory array and reducing a wafer area including a memory array and peripheral circuits.

The semiconductor memory device of the present invention comprises: a memory array, which is configured by a plurality of cell groups, wherein the cell groups are electrically rewritable memory cells connected in series; a word line decoder selects a memory array according to the address signals. a specific memory block, outputting a selection signal to the selected memory block; and a word line driving circuit including switching a switching circuit for supplying an operating voltage to the memory cell according to the selection signal, and boosting the boosting of the selection signal Circuit. The switching circuit includes a transistor that self-boosts the selection signal in response to an operating voltage.

In a preferred embodiment, the switching circuit includes a plurality of transmission transistors for transmitting the operating voltage to a gate of the memory cell, and the gate of the complex transmission transistor is supplied with the selection signal, and the plurality of transmission transistors are The selection signal should be self-boosted by the supply of voltage. In a preferred embodiment, the word line driving circuit is disposed between the first and second memory arrays extending in the column direction, and the word line driving circuit is shared by the first and second memory arrays. .

In a preferred embodiment, the boosting circuit includes a node pre-charged above a power supply voltage, and a boosting transistor connected to the node, the boosting transistor boosting the selection signal by supplying a signal to the drain The potential of the node. In a preferred embodiment, the word line decoder includes a boost circuit that supplies a select signal boosted to a higher voltage than the supply voltage to the word line drive circuit. In a preferred embodiment, the word line decoder includes a driver circuit for driving the bit line selection transistor and the source selection transistor of the cell group.

In a preferred embodiment, the memory array is divided into two in the column direction, and the word line driving circuit is disposed between the divided memory arrays, and the word line decoder is disposed in one of the memory arrays. An end portion, the word line decoder includes a wiring layer that transmits the selection signal, the wiring layer being extended by the word line decoder to the word line driving circuit, spanning one of the memory arrays in a column direction . A preferred embodiment is that word lines are extended by the word line drive circuit to respective memory arrays.

According to the present invention, the selection signal of the word line driver circuit is boosted by self-boosting of the transistor, and the voltage applied to the transistor can be lowered and the transistor can be reduced as compared with the prior art. Furthermore, compared with the prior art, self-boosting can be used to reduce the boost circuit such as the charge pump, and the layout area of the word line driver circuit or the layout area of the word line decoder can be reduced. Furthermore, it is not necessary to consider the bulk effect of charge boosting to boost the selection signal by more than necessary. In addition, by arranging the word line driving circuits between the memory arrays in the column direction, the wiring length from the word line driving circuit can be shortened to reduce the load, and on the other hand, the electric field of the selection signal can be reduced to the memory array. influences.

Next, an embodiment of the present invention will be described with reference to the drawings. The preferred embodiment of the present invention is exemplified by a NAND type flash memory. In the drawings, the parts of the memory are emphasized for ease of understanding, so the ratio of the schema to the actual device is not the same.

Fig. 2 is a schematic layout of a flash memory of an embodiment of the present invention. As shown in FIG. 2, the flash memory 100 includes a memory array 110 divided into at least two memory arrays 110A and 110B, and a word line decoder and level disposed at the end of the column direction of the memory array 110. a shifter (hereinafter collectively referred to as a word line decoder 120); a word line driving circuit 130 disposed between the memory arrays 110A and 110B; disposed in a row direction of the memory array 110, sensing bit line readout The data or the data that remains written has a page buffer 140 of the sense amplifier. However, although not shown here, the flash memory 100 further includes an input/output buffer for externally transmitting information, a controller for controlling each unit based on an external command, and the like.

The memory arrays 110A and 110B are divided into a plurality of memory blocks BLK(0), BLK(1), ..., BLK(m) in the row direction, and the configuration of each memory block includes a plurality of pages. Figure 4 is a circuit diagram showing the architecture of a NAND gate string formed within a memory block. In one page, a plurality of NAND gate trains (hereinafter referred to as unit groups NU) in which a plurality of memory cells are connected in series are formed in the row direction. In the example shown in Fig. 4, one cell group NU includes 32 memory cells MCi (i = 0, 1, ..., 31) connected in series, and bit line selection transistor BST and source selection power connected to both ends. Crystal SST. The drain of the bit line selection transistor BST is connected to the corresponding one bit line GBL, and the source selection transistor SST is connected to the common source line SL. The control gate of the memory cell MCi corresponds to the word line WLi. The gate of the bit line selection transistor BST and the source selection transistor SST corresponds to the selection gate lines SGD, SGS extending parallel to the word line WLi.

The memory cell typically has a MOS structure, including a source/drain of the N-type diffusion region, a tunneling oxide layer formed on the channel between the source/drain, and a floating gate formed on the tunneling oxide layer. a dielectric layer on the floating gate and a gate formed on the dielectric layer. Generally, when there is no charge accumulation in the floating gate, the data is "1", the threshold voltage is negative, and the memory cell is normally open. When the floating gate has charge accumulation, the data is "0", the threshold voltage shift is positive, and the memory cell is normally closed.

3 is a block diagram showing the construction of the word line decoder 120 and the word line driver circuit 130. However, for convenience of explanation, it is assumed that one memory block is composed of one page (2 pages) on the left and right sides of the memory arrays 110A and 110B, and the adjacent two memory blocks BLK(0), BLK are shown in FIG. (1).

The word line decoder 120 includes a block selection circuit 122 that selects a memory block according to the address signal Ax, a level shifter 124 that generates a required operating voltage according to a control signal C of a controller (not shown), and is connected to The bit line selects the gate of the transistor BST and the source select transistor SST and supplies the SGS/SGD drive circuit 126 of the gate select signal SGS/SGD.

The word line decoder 120 generates an operation voltage GWL (0: 31) supplied to the corresponding word line WL (0: 31) by the level shifter 124 based on the address signal Ax and the control signal C. That is to say, when the data is written, the input word line write voltage Vpgm (for example, 20 V) is supplied, and the non-selected word line transfer voltage (for example, 10 V) is supplied, and when the read operation is performed, the supply of the selected word line is grounded. The potential is supplied to the non-selected word line read voltage Vread (for example, 4.5V).

The block selection circuit 122-0 transmits the selection signal PASSV(0) to the switching circuit 132-0 of the word line driving circuit 130 when, for example, the memory block BLK(0) is selected. The selection signal PASSV(0) has a voltage (e.g., 10V) boosted by the level shifter 124 to a power supply voltage Vcc or higher. The SGS/SGD driving circuit 126-0 supplies the gate selection transistor SST and the source selection transistor SST of the block BLK(0) to the gate selection signal SGS/SGD boosted to about 5 to 6V. Similarly, when the block BLK(1) is selected, the block selection circuit 122-1 supplies the selection signal PASSV(1) to the switching circuit 132-1 of the word line driving circuit 130. The SGS/SGD drive circuit 126-1 supplies the gate line selection transistor BST and the source selection transistor SST of the block BLK(1) with a gate selection signal SGS/SGD boosted to about 5 to 6V. Wherein, as shown, the gate selection signals SGD_01 transmitted by the SGS/SGD driver circuits 126-0 and 126-1 to the bit line selection transistor BST are common.

Here, referring to Fig. 2, the wiring layout of the word line decoder 120 and the word line drive circuit 130(i) of the i-th memory block is taken as an example. The i-th block selection circuit 120-i of the word line decoder 120 is connected to the switch circuit 132-i of the word line drive circuit 130 through the metal wiring WR(i) extending over the memory array 110B. This metal wiring WR(i) transmits a selection signal PASSV(i). . The metal wiring WD/WS extending in the column direction of the memory arrays 110A, 110B transmits the gate selection signal SGD/SGS from the SGS/SGD driving circuit 126-i. Among them, the metal wiring WD/WS does not contact the word line driving circuit 130, and straddles the entire memory array in the column direction.

Fig. 5 is a structural diagram of a switching circuit of a word line driving circuit. As shown in FIG. 5, the left side of the word line driving circuit 130-0 forms a switching circuit 132A-0 connected to the memory cell of the memory array 110A, and the right side forms a switching circuit 132B connected to the memory cell of the memory array 110B. 0. Similarly, the left side of the word line drive circuit 130-1 forms the switch circuit 132A-1, and the right side forms the switch circuit 132B-1. Each of the switch circuits 132A-0, 132B-0, 132A-1, and 132B-1 has the same configuration, and therefore only the switch circuit 132A-0 will be described.

The switching circuit 132A-0 includes a plurality of N-channel transmission transistors connected to the word lines WL(0) to WL(31) of the cell group NU. The respective gates of these transfer transistors are commonly supplied with a selection signal PASSV_INT from the word line drive circuit 130-0. The selection signal PASSV_INT is a signal generated in response to the selection signal PASSV of the word line decoder 120, and therefore, when the memory block is selected, the selection signal PASSV_INT has a voltage capable of sufficiently turning on the transmission transistor so that the word line decoder is derived. The operating voltage GWL (0:31) of 120 can be transferred to the corresponding word line WL (0:31). On the other hand, when the memory block is not selected, the selection signal PASSV is a non-operation level (L level), so the selection signal PASSV_INT is also a non-operation level, and the transmission transistor is not turned on.

Fig. 6 is an architectural circuit diagram of the word line drive circuit 130. The word line drive circuit 130 has a switch circuit 132 that is switched by the selection signal PASSV_INT, and a boost circuit 134 that boosts the node in response to the selection signal PASSV. The boosting circuit 134 includes a high-voltage N-channel first transistor TR1 and a high-voltage N-channel second transistor TR2 whose gate is connected to the transistor TR1. In operation, the gate of the first transistor TR1 receives the signal VXD boosted to a potential Vp higher than the power supply voltage Vcc (for example, 3 V), and is connected to the source when the drain is applied with the signal LPVBST having the equivalent potential Vp. The node LPVBST_1 generates a potential of Vp-Vt (Vt is the threshold voltage of the transistor TR1).

The gate of the second transistor TR2 is connected to the node LPVBST_1, the drain is supplied with the selection signal PASSV from the word line decoder 120, and the source is connected to the gate of each transistor PTR of the switch circuit 132. The node LPVBST_1 generates a voltage of Vp-Vt. When the drain of the second transistor is applied with a selection signal PASSV greater than the voltage of Vp-Vt, the node LPVBST_1 is combined by the gate/drain capacitance of the transistor TR2. Self-boosting. Since the second transistor TR2 is turned on by the self-boosting gate voltage, the selection signal PASSV_INT can be generated without lowering the voltage of the selection signal PASSV.

In the switch circuit 132, the gate of each transfer transistor PTR is applied with the selection signal PASSV_INT, and when the drain is applied with the operating voltage GWL (for example, the write voltage Vpgm), the selection signal PASSV_INT connected to the gate of the transmission transistor PTR is self-literated. Pressure. Therefore, the voltage drop due to the transfer transistor PTR does not occur, and the operating voltage can be communicated to the corresponding word line.

Fig. 7 is a timing chart for explaining the operation at the time of writing of the word line drive circuit of the present embodiment. First, at time t1, the gate of the first transistor TR1 is applied with a signal VXD boosted to, for example, 6V, and then at time t2, the drain of the first transistor TR1 is applied to a signal LPVBST which is boosted, for example, to 6V. . Thereby, the node LPVBS_1 is precharged to 6V-Vt. Next, at time t3, when the drain of the second transistor TR2 is applied with the write voltage Vpgm (for example, 16 V) as the selection signal PASSV, the node LPVBS_1 self-boosts (6V-Vt+Boost). Thereby, the boosting circuit 134 can supply the selection signal PASSV_INT of the voltage equal to the write voltage Vpgm to the switch circuit 132 without lowering the write voltage Vpgm.

Next, at time t4, by lowering the signal LPVBST to Vcc, the node LPVBST_1 is discharged through the first transistor TR1 to the voltage Vcc. Next, at time point t5, the operating voltage GWL is applied to the drain of the transmission transistor PTR. That is, the selected word line WL_SEL is successively applied with the transfer voltage Vpass and the write voltage Vpgm, and the non-selected word line WL_USEL is applied with the transfer voltage Vpass. The voltage Vpass is transmitted (for example, 10V). The selection signal PASSV_INT self-boosts to Vpgm+Boost in response to the operating voltage GWL applied to the transfer transistor PTR. Thereby, the transmission transistor PTR is strongly turned on, and the operating voltage GWL is transmitted to the corresponding word line. After that, the next operation is performed in the same way. In the read operation, although the non-selected word line is supplied with a read voltage (for example, 4.5 V) larger than the power supply voltage Vcc, the operation is performed in the same manner.

According to the present embodiment, the selection signal PASSV_INT from the boosting circuit 134 is applied to the gate of the transmission transistor PTR, and the operating voltage GWL is applied to the drain, thereby utilizing the capacity combination between the gate/drain and the source. The selection signal PASSV_INT is self-boosted, so that the voltage applied to the transmission transistor PTR can be lowered to be lower than the large voltage applied directly between the gate/source of the selection transistor without using self-boosting. The transmission transistor PTR is shrunk to reduce the circuit area of the switching circuit 132. In addition, the boost voltage applied to the word line can be reduced more than conventionally.

In the above embodiment, although one word line decoder 120 is allocated to all of the memory blocks BLK(0)...BLK(m) of the memory array 110, a plurality of word line decoders may be arranged for each. Memory block. In this case, a particular word line decoder can be selected from a plurality of word line decoders based on the address signal.

Further, in the above embodiment, the word line drive circuit 130 is disposed between the two memory arrays 110A and 110B in the column direction. However, the present invention is not limited thereto, and the word line may be driven as shown in FIG. 8A. The circuit 130 is disposed on one side of the memory array 110. Alternatively, as shown in FIG. 8B, the memory arrays 110A, 110B, 110C, and 110D may be divided, and the plurality of word line drive circuits 130A and 130B may be disposed between the memory arrays divided in the column direction.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

100. . . Flash memory

10, 10A, 10B, 110, 110A, 110B, 110C, 110D. . . Memory array

120, 20, 20A, 20B. . . Character line decoder

122-0, 122-1. . . Block selection circuit

124. . . Level shifter

126-0, 126-1. . . SGS/SGD drive circuit

130, 130A, 130B, 22, 22A, 22B. . . Word line driver circuit

132, 132-0, 132-1, 132A, 132A-0, 132A-1, 132B, 132B-0, 132B-1. . . Switch circuit

134. . . Boost circuit

140, 30, 30A, 30B,. . . Page buffer

Ax. . . Address signal

BST. . . Bit line selection transistor

BLK(0), BLK(1)...BLK(m). . . Memory block

C. . . control signal

GBL0, GBL1...GBLn-1, GBLn. . . Bit line

GWL. . . Operating voltage

LPVBST. . . signal

LPVBST_1. . . node

MC0, MC1...MC31. . . Memory cell

NU. . . Unit group

PASSV, PASSV (0), PASSV (1) PASSV_INT. . . Selection signal

PTR. . . Transmission transistor

SGD, SGD_01, SGS(0), SGS(1). . . Gate selection signal

SL. . . Common source line

SST. . . Source selective transistor

TR1. . . First transistor

TR2. . . Second transistor

Vcc. . . voltage

Vpass. . . Transmission voltage

Vpgm. . . Write voltage

VXD. . . 1st transistor gate signal

WD, WR(i), WS. . . Metal wiring

WL0, WL1...WLn. . . Word line

WL_SEL. . . Select word line

WL_USEL. . . Non-selected word line

Figures 1A and 1B illustrate the layout of conventional flash memory.

Figure 2 is a diagram showing the layout of the flash memory of the present invention.

Figure 3 is a block diagram showing the construction of a word line decoder and a word line driver circuit.

Figure 4 is a circuit diagram showing the NAND gate train architecture.

Fig. 5 is a structural diagram of a word line driving circuit of an embodiment of the present invention.

Fig. 6 is a configuration diagram of a booster circuit of a word line drive circuit of an embodiment of the present invention.

Fig. 7 is a timing chart for explaining the operation of the word line driving in the embodiment of the present invention.

8A and 8B are other layout views of the word line drive circuit of the present invention.

100. . . Flash memory

110, 110A, 110B. . . Memory array

120. . . Character line decoder

130. . . Word line driver circuit

140. . . Page buffer

BLK(0), BLK(1)...BLK(m). . . Memory block

WD, WR(i), WS. . . Metal wiring

WL0, WL1...WLn. . . Word line

Claims (8)

A semiconductor memory device comprising: a memory array configured by a plurality of cell groups, wherein the cell groups are electrically rewritable memory cells connected in series; and a word line decoder for selecting a specific one in the memory array according to the address signal a memory block, outputting a selection signal to the selected memory block; and a word line driving circuit, comprising: switching a switching circuit for supplying an operating voltage to the memory cell according to the selection signal, and a boosting circuit for boosting the selection signal; Wherein the switching circuit includes a transistor that self-boosts the selection signal in response to an operating voltage. The semiconductor memory device of claim 1, wherein the switching circuit comprises a plurality of transmission transistors for transmitting the operating voltage to a gate of the memory cell, the gate of the complex transmission transistor being supplied with the selection The signal, the plurality of transmission transistors self-boost the selection signal due to the supply of the operating voltage. The semiconductor memory device according to claim 1 or 2, wherein the word line driving circuit is disposed between the first and second memory arrays extending in the column direction, and the word line is driven The circuit is shared by the first and second memory arrays. The semiconductor memory device according to any one of claims 1 to 3, wherein the boosting circuit comprises a node precharged to a power supply voltage or higher, and a boosting transistor to which the gate is connected to the node, the liter The piezoelectric crystal raises the potential of the node in response to the selection signal supplied to the drain. The semiconductor memory device according to any one of claims 1 to 4, wherein the word line decoder comprises a boosting circuit, and a selection signal boosted to be higher than a power supply voltage is supplied to the word line driving circuit. The semiconductor memory device according to any one of claims 1 to 5, wherein the word line decoder comprises a driving circuit for driving a bit line selection transistor and a source selection transistor of the cell group. The semiconductor memory device according to any one of claims 1 to 6, wherein the memory array is divided into two in a column direction, and the word line driving circuit is disposed between the divided memory arrays, the word A line decoder is disposed at an end of one of the memory arrays, the word line decoder including a wiring layer transmitting the selection signal, the wiring layer being extended by the word line decoder to the word line driving circuit Across the memory array in the column direction. The semiconductor memory device of claim 7, wherein the word lines are extended by the word line driver circuit to respective memory arrays.