TWI570389B - Amplitude calibration circuit and signal calibration circuit using the same - Google Patents

Description

Amplitude correction circuit and signal correction circuit thereof

The present invention relates to a circuit for correcting an alternating current signal output by a sensing device.

Orthogonal signals are widely used in many places for sensing or signal processing, including, for example, Global Positioning System (GPS), crossover technology, phase sensing, ultrasonic, Doppler measurement, and Positioning sensing and other applications. The sensing device to which the orthogonal signal is applied includes, for example, a magnetic ruler, an optical scale, a laser interferometer, a rotary encoder, etc., which can perform distance sensing using orthogonal signals, for example, generating orthogonal signals by grating interference. Or use optical wavelength interference to generate orthogonal signals, which can be converted into length measurements by phase calculation, accumulation or analysis of orthogonal signals. Correction of the AC signal output by the sensing device is an important issue in the art.

The present invention is a signal correction circuit related to an amplitude correction circuit and its application.

According to an embodiment of the present invention, an amplitude correction circuit is provided. The amplitude correction circuit includes a phase shift circuit, an averaging circuit, and an amplifying circuit. The phase shift circuit generates a plurality of phase shift output signals according to the plurality of input signals, the phase shift output signals including M first phase shift signals and M second phase shift signals, and the phase difference between the M first phase shift signals Δφ, the M second phase shift signals have a phase difference Δφ, and the M first phase shift signals are opposite in polarity to the M second phase shift signals, wherein M is a positive integer. The averaging circuit is operative to generate an amplitude gain based on the weighted sum of the input signals and the phase shifted output signals, the averaging circuit being powered by a unipolar power supply. The amplifying circuit adjusts the amplitudes of the input signals according to the amplitude gain to generate a plurality of corrected signals.

In accordance with another embodiment of the present invention, a signal correction circuit is provided that includes a bias correction circuit and an amplitude correction circuit. The bias correction circuit includes a bias correction phase shift circuit, a bias correction averaging circuit, and a subtraction circuit. The bias correction phase shift circuit generates a plurality of bias correction phase shift output signals according to the plurality of sense input signals, the bias correction phase shift output signals comprising N first bias correction phase shift signals, N first offsets The pressure correction phase shift signal has a bias correction phase difference Δφ1 between them, where N is a positive integer. A bias correction averaging circuit is operative to generate an average DC bias based on the sensed input signals and the weighted sum of the bias corrected phase shifted output signals. A subtraction circuit is used to subtract the average DC bias from the sensed input signals to produce a plurality of input signals. The amplitude correction circuit includes a phase shift circuit, an averaging circuit, and an amplifying circuit. A phase shifting circuit generates a plurality of phase shifted output signals based on the input signals, the phase shifted output signals including M first phase shifted signals and M first The two phase shift signals have a phase difference Δφ between the M first phase shift signals, and have a phase difference Δφ between the M second phase shift signals, M first phase shift signals and M second phase shift signals The opposite polarity, where M is a positive integer. The averaging circuit is operative to generate an amplitude gain based on the weighted sum of the input signals and the phase shifted output signals, the averaging circuit being powered by a unipolar power supply. The amplifying circuit adjusts the amplitudes of the input signals according to the amplitude gain to generate a plurality of corrected signals.

In order to better understand the above and other aspects of the present invention, various embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

1‧‧‧Signal Correction Circuit

2‧‧‧ bias correction circuit

21‧‧‧ bias correction phase shift circuit

22‧‧‧ bias correction averaging circuit

23‧‧‧Subtraction circuit

3‧‧‧Amplitude correction circuit

31‧‧‧ Phase shift circuit

32, 32a, 32b, 32c‧‧‧ averaging circuit

33‧‧‧Amplification circuit

A‧‧‧first input signal

A’‧‧‧ third input signal

B‧‧‧second input signal

B’‧‧‧ fourth input signal

f ₁ ~f _N ‧‧‧First bias correction phase shift signal

f _{1_1} ~f _{1_M ‧‧‧First} phase shift signal

f _{2_1} ~f _{2_M ‧‧‧Second} phase shift signal

Ps‧‧‧ phase shift output signal

Ps1‧‧‧bias corrected phase shift output signal

OP_22, OP_23, OP_32, OP_33, OP_321, OP_324‧‧‧Operational Amplifier

Rf_22, Rf_32‧‧‧ feedback resistor

V _dc ‧‧‧ average DC bias

V _gain ‧‧‧amplitude gain

V _ref1 , V _ref2 , V _ref3 ‧‧‧reference voltage

x‧‧‧Sensing input signal

y‧‧‧Input signal

Z‧‧‧corrected signal

R ₁ ~ R ₄ , R _c1 ~ R _c20 , R _c1 '~ R _c20 ', R _s1 ~ R _s20 , R _s1 '~R _s20 '‧‧‧ resistance

Ri, R _v1 ~ R _v11 ‧‧‧ input resistance

R _{1_1} ~R _{1_M ‧‧‧First} input resistance

R _{2_1} ~R _{2_M ‧‧‧second} input resistance

T1‧‧‧O crystal

V _c1 ~V _c19 , V _c1 '~V _c19 ', V _s1 ~V _s19 , V _s1 '~V _s19 '‧‧‧ phase shift signal

1 is a block diagram of a signal correction circuit in accordance with an embodiment of the present invention.

2 is a block diagram of a bias correction circuit in accordance with an embodiment of the present invention.

3 is a block diagram of an amplitude correction circuit in accordance with an embodiment of the present invention.

4A to 4D are diagrams showing a plurality of example resistor chain structures.

FIG. 5 is a circuit diagram of a bias correction averaging circuit in accordance with an embodiment of the present invention.

FIG. 6 is a circuit diagram of a subtraction circuit in accordance with an embodiment of the present invention.

Figure 7 is a diagram showing the execution effect of an exemplary averaging circuit powered by a unipolar power supply.

8A to 8C are circuit diagrams showing an averaging circuit in accordance with various embodiments of the present invention.

9A and 9B are schematic diagrams showing an example average circuit output result corresponding to four resistor chains and eight resistor chains.

FIG. 10 is a circuit diagram of an amplifying circuit in accordance with an embodiment of the present invention.

11 is a block diagram of a signal correction circuit in accordance with an embodiment of the present invention.

12A to 12G are diagrams showing signal waveforms of signal correction circuits at respective nodes in accordance with an embodiment of the present invention.

During the sensing process, the sensing device may cause an error variation of the quadrature signal due to the non-ideality of the environment or device. For example, due to uncontrollable factors such as glass surface flatness, assembly error, environmental pollution, etc., the DC offset (Offset) and amplitude (Amplitude) error of the quadrature signal may be changed. These changes may cause machine tool control. The displacement calculation error of the device does not provide accurate positioning. In order to make the orthogonal signal output by the sensing device (for example, the optical scale) conform to the accuracy range required by the machine tool controller, the present disclosure proposes a signal correction circuit for correcting the bias voltage and amplitude of the signal.

1 is a block diagram of a signal correction circuit in accordance with an embodiment of the present invention. The signal correction circuit 1 includes a bias correction circuit 2 and an amplitude correction circuit 3. The plurality of sensing input signals x are derived, for example, from a sensing device. After the plurality of sensing input signals x pass through the bias correction circuit 2, the DC bias voltage can be eliminated to generate a plurality of input signals y, and the average of the plurality of input signals y. The DC bias value is, for example, 0V. Next, the amplitude correction circuit 3 corrects the amplitudes of the plurality of input signals y to generate a plurality of corrected signals z, and the amplitudes of the plurality of corrected signals z can be maintained at a fixed value, for example.

2 is a block diagram of a bias correction circuit in accordance with an embodiment of the present invention. The bias correction circuit 2 includes a bias correction phase shift circuit 21, a bias correction averaging circuit 22, and a subtraction circuit 23. The bias correction phase shift circuit 21 generates a plurality of bias correction phase shift output signals ps1 based on the plurality of sense input signals x, and the bias correction phase shift output signal ps1 includes N first bias correction phase shift signals f ₁ ~ f _N , N first bias correction phase shift signals f ₁ ~ f _N have a bias correction phase difference Δφ1, where N is a positive integer. The average bias correction circuit 22 a weighted sum of the phase shifted output signal ps1 is generated in accordance with the average DC bias voltage V _dc sensing a plurality of input signals x and a plurality of bias correction, the correction of the averaging circuit 22 to bias bipolar supply. The subtraction circuit 23 subtracts the average DC bias voltage V _dc input signals from a plurality of sensing to produce a plurality of input signals x y. Of which 45° (N+1)×(△φ1) 135°, in one embodiment, (N+1)×(Δφ1)=90°.

3 is a block diagram of an amplitude correction circuit in accordance with an embodiment of the present invention. The amplitude correction circuit 3 includes a phase shift circuit 31, an averaging circuit 32, and an amplification circuit 33. The phase shift circuit 31 generates a plurality of phase shift output signals ps according to the plurality of input signals y, and the phase shift output signals ps include M first phase shift signals f _{1_1} ~ f _{1_M} and M second phase shift signals f _{2_1} ~ f _{2_M} , M first phase shift signals f _{1_1} ~ f _{1_M} have a phase difference Δφ, and M second phase shift signals f _{2_1} ~ f _{2_M} have a phase difference Δφ, M first phase shift signals f _{1_1} ~f _{1_M is opposite in polarity} to the M second phase shift signals f _{2_1} ~f _{2_M} , where M is a positive integer. The averaging circuit 32 generates a plurality of amplitude gain V _gain according to a plurality of input signals and a weighted sum of y phase shifted output signal ps, the averaging circuit 32 is unipolar power supply. The amplifying circuit 33 adjusts the amplitudes of the plurality of input signals y according to the amplitude gain V _gain to generate a plurality of corrected signals z. Of which 45° (M+1)×(△φ) 135°, in one embodiment, (M+1) × (Δφ) = 90°.

The present invention does not limit the signal received by the signal correction circuit 1, and may be, for example, two orthogonal signals or four orthogonal signals output by the sensing device. For convenience of description, the following embodiments illustrate four orthogonal signals, which are a first input signal A, a second input signal B, a third input signal A', and a fourth embodiment. Four input signals B', and use different lowercase letters to represent the four orthogonal signal components of the different signals. For example, the sensing input signal x includes a first input signal Ax, a second input signal Bx, a third input signal Ax', and a fourth input signal Bx', and the first to fourth input signals sequentially have one Signal phase difference α, of which 45° α 135°, (N+1)×(Δφ1)=α, (M+1)×(Δφ)=α. The following embodiment illustrates that the signal phase difference α is 90° as an example, but this is merely illustrative, and the present invention is not limited to the signal phase difference being equal to 90°. When α = 90°, the input signal is represented by a sine wave, and the first to fourth input signals can be expressed as: Ax = V _{dc 1} + V _{ac 1} sin θ, Bx = V _{dc 2} + V _{ac 2} sin( θ+90°), Ax '= V _{dc 3} + V _{ac 3} sin(θ+180°), Bx '= V _{dc 4} + V _{ac 4} sin(θ+270°). V _dc1 ~V _dc4 are the DC bias voltages of the first to fourth input signals, respectively, and V _ac1 ~V _ac4 are the amplitudes of the first to fourth input signals respectively. Under ideal conditions, the DC bias voltages are all the same V _dc1 = V _dc2 =V _dc3 =V _dc4 and the amplitude is the same V _ac1 =V _ac2 =V _ac3 =V _ac4 . Taking an instrument used in the industry as an example, the DC bias voltage may be V _dc1 = V _dc2 = V _dc3 = V _dc4 = 2.5V, and the alternating current component (sin θ) of the first input signal Ax is communicated with the third input signal Ax'. The composition (sin(θ+180°)=-sin θ) has opposite polarities, and the alternating component of the second input signal Bx (sin(θ+90°)=cos θ) and the alternating component of the fourth input signal Bx' (sin( θ+270°)=-cos θ) The opposite polarity. In actual situations, the DC bias voltages of the first to fourth input signals may be different and the amplitudes may be different, so the signal correction circuit 1 of the present disclosure may be used for the first to fourth input signals Ax, Bx, Ax', Bx' is corrected, and the bias correction circuit 2 and the amplitude correction circuit 3 will be described in detail below.

In practical applications, some power tool controllers detect the orthogonal signals output by the sensing device immediately after supplying power to the sensing device to determine whether the sensing device is working normally. If the orthogonal signal exceeds the acceptable range of the machine tool controller, it is determined that the sensing device may cause a risk to the machine tool control system, and immediately enters an abnormal trip state to maintain the safety of the machine tool.

In this case, the quadrature signal correction circuit cannot perform the bias and amplitude correction of the input signal by accumulating the input signal information of several cycles, and must receive the first to fourth input signals Ax, Bx, Ax', At Bx', the bias and amplitude information of the input signal is immediately obtained as a basis for correction.

However, the first to fourth input signals Ax, Bx, Ax', Bx' voltage signals include three influence factors: phase (θ), DC bias voltage (V _dc ), and AC amplitude (V _ac ), in the sensing device. After a short period of time after power transmission (assuming θ does not change), the voltage signals from the first to fourth input signals Ax, Bx, Ax', Bx' cannot estimate the correct DC bias and amplitude information, and the input signal is biased. Pressure and amplitude correction to obtain a more correct phase (θ). However, if the effect of phase (θ) can be removed, the correct DC bias and amplitude information can be obtained from a single Ax, Bx, Ax', Bx' voltage signal.

Taking the first input signal Ax and the second input signal Bx as an example, since there is a fixed phase (for example, 90°) between Ax and Bx, if a series of voltages between the Ax and Bx phases can be generated according to the phase shift method Signal, and the series of voltage The DC bias and amplitude are related to the Ax and Bx voltage signals, which can remove the influence of phase (θ), obtain correct DC bias and amplitude information, and perform bias and amplitude correction on the input signal.

The bias correction phase shift circuit 21 can be implemented in various ways. One embodiment uses a resistor chain, that is, a plurality of resistors connected in series, and the junction of the resistors can output a bias correction phase shift output signal ps1. 4A to 4D are diagrams showing a plurality of example resistor chain structures. In these resistor chain examples, the signals at both ends of the resistor chain have a phase difference of 90°, and each resistor chain has 10 series resistors for output. The nine phase-shifted signals, that is, the phase difference of the signals across the resistance chain are divided into 10 equal parts, and each of the phase-shifted signals output has a phase difference = 90°/10 = 9°. Of course, the number of resistors used in the resistor chain is not limited thereto. For example, six resistors may be used, so that each phase shift signal has a phase difference=90°/6=15°, which can be determined according to the actual operating environment and design requirements. The number of resistors.

Taking the example of FIG. 4A as an example, the left end of the resistance chain Chain1 is coupled to the first input signal Ax, and the right end is coupled to the second input signal Bx. In order to simplify the following calculations, in the case of no loss of generality, in this case, It is assumed that the amplitudes of the first input signal Ax and the second input signal Bx are both equal to 1, and the DC bias voltage is 0V, that is, Ax=sin θ, Bx=cos θ. The resistor chain Chain1 includes ten resistors R _s1 ~ R _s10 and outputs nine phase shift signals V _s1 ~ V _s9 . According to the resistance partial pressure theorem, the voltage V _sk of the kth phase shift signal can be calculated as Where R _s = R _{s 1} + R _{s 2} +...+ R _{s 10} , R _s,k = R _{s 1} + R _{s 2} +...+ R _sk , k =1~9. Then, the formula can be calculated by a trigonometric function, and the corresponding phase difference Δφ×k is substituted to calculate the value of A _sk . Further _, the value of R _s,k can be obtained.

Table 1 below lists the proportional relationship of the respective resistors R _sk when Δφ = 9°, and the respective resistance values can be adjusted according to the proportional relationship.

Another example of the resistor chain Chain5 in FIG. 4A is that the left end is coupled to the second input signal Bx=cos θ, and the right end is coupled to the third input signal Ax′=−sin θ, and the calculation manner is similar to the above-mentioned resistance chain Chain1, and the resistance is similar. Chain Chain 5 includes ten resistors R _c1 ~ R _c10 and outputs nine phase shift signals V _c1 ~ V _c9 . According to the resistance partial pressure theorem, the voltage V _ck of the kth phase shift signal can be calculated as Where R _c = R _{c 1} + R _{c 2} +...+ R _{c 10} , R _c,k = R _{c 1} + R _{c 2} +...+ R _ck , k =1~9. Then, the formula can be calculated by a trigonometric function and substituted into the corresponding phase difference Δφ×k to calculate the value of A _ck . Further _, the value of R _c,k can be obtained.

The resistor chain Chain2 of FIG. 4B is coupled to the third input signal Ax' at the left end, and coupled to the fourth input signal Bx' at the right end, and the fourth input signal Bx' is coupled to the left end of the resistor chain Chain6, and the first input signal is coupled to the right end of the resistor chain Chain6. Ax. That is to say, in an ideal situation, the phase shift signal outputted by the resistor chain Chain1 and the phase shift signal output by the resistor chain Chain2 should be of the same value and opposite in polarity, and the phase shift signal outputted by the resistor chain Chain5 and the phase shift signal output by the resistor chain Chain6 are also It should be the same value and the opposite polarity. However, due to the influence of the sensing device and the real uncontrollable factors of the measured environment, the four signals output by the sensing device are not ideal. Therefore, the phase shift signals output by the resistance chain Chain1 and the resistance chain Chain2 are approximately opposite in polarity. However, the values are not exactly the same. Similarly, the phase shift signals output by the resistor chain Chain5 and the resistor chain Chain6 are similar to the opposite polarity, and the values are not completely the same.

In an embodiment, the bias correction phase shift circuit 21 can use four resistor chains of the resistor chains Chain1, Chain2, Chain5, and Chain6 as shown in FIGS. 4A and 4B, and thus the bias correction phase shift circuit 21 A total of 9 × 4 = 36 bias correction phase shift output signals ps1 can be generated, plus the original first to fourth input signals Ax, Bx, Ax', Bx', and the bias correction averaging circuit 22 can calculate these 40 The average of the signals is used to determine the average DC bias of the sine waves corresponding to the first to fourth input signals Ax, Bx, Ax', Bx'. It is worth noting that the amplitudes A _{sk of the} respective phase shift signals V _sk according to the equation (2) are not the same, so the average value of the 40 signals calculated here is actually the weighted sum of 40 signals. That is, the amplitude A _{sk of} each phase shift signal V _sk needs to be first adjusted by an appropriate weight coefficient, and then the weighted sum is calculated.

A circuit implementation that calculates the weighted sum can be seen in Figure 5. A circuit diagram of a bias correction averaging circuit in accordance with an embodiment of the present invention is shown. The bias correction averaging circuit 22 can calculate the weighted sum of 40 signals, and for simplicity of illustration and convenience of explanation, the example bias correction averaging circuit 22 shown in FIG. 5 is for the phase shift of the resistance chain Chain1 output. The signal and the first input signal Ax and the second input signal Bx across the resistance chain Chain1 calculate a weighted sum of the 11 signals.

The bias correction averaging circuit 22 includes an operational amplifier OP_22, a feedback resistor Rf_22, and input resistors R _v1 to R _v11 . The non-inverting input of the operational amplifier OP_22 is coupled to the ground potential GND, and the operational amplifier OP_22 is powered by a bipolar power supply, that is, the positive supply of the operational amplifier OP_22 is connected to +V _DD and the negative supply is connected to -V _DD . The feedback resistor Rf_22 is coupled between the output terminal of the operational amplifier OP_22 and the inverting input terminal. The input resistor R _v1 ~ R _{v11 is} coupled to the inverting input terminal of the operational amplifier OP_22, wherein the input resistor R _{v1 is} coupled to the first input signal Ax, the input resistor R _{v11 is} coupled to the second input signal Bx, and the input resistor R _v2 ~ R _v10 The nine phase shift signals V _s1 ~V _s9 output by the resistor chain Chain1 are coupled. As described above, the amplitudes A _{sk of the} respective phase shift signals V _sk are not the same, and therefore the proportional relationship of the resistance values of the input resistors R _v2 to R _v10 can be adjusted in accordance with the proportional relationship of the amplitudes A _sk . The input voltage received by the bias correction averaging circuit 22 is sequentially expressed as V ₁ ~V ₁₁ (V ₁ =Ax, V ₂ =V _s1 , V ₃ =V _s2 ,..., V ₁₀ =V _s9 , V ₁₁ = Bx), the average DC bias voltage V _dc generated by the bias correction averaging circuit 22 can be expressed as Table 2 below shows the proportional relationship between the input resistance R _vk and the feedback resistor Rf_22 when Δφ = 9°.

FIG. 5 is only an example of a bias correction averaging circuit 22. Of course, the present invention is not limited thereto, and the actual number of resistors and the ratio of resistance values may correspond to the bias correction phase shift circuit 21 of the previous stage. The resistor chain to be used is adjusted correspondingly, and the bias correction averaging circuit 22 may not use an operational amplifier, and may be a circuit capable of performing a calculation of a weighted sum. For example, it may be implemented by an adder of a digital circuit and an arithmetic logic circuit. In addition, in the foregoing embodiment, the bias correction averaging circuit 22 is powered by a bipolar power supply. In the circuit implementation, the bias correction averaging circuit 22 can also be powered by a unipolar power supply, for example, phase shift can be corrected for bias voltage. The output signal ps1 applies an additional DC bias such that the voltage amplitude range of the bias corrected phase shifted output signal ps1 falls entirely within the voltage range of the unipolar power supply.

In the above embodiment, the bias correction phase shift circuit 21 includes a plurality of resistor chains. In another embodiment, the bias correction phase shift circuit 21 may not include any resistance chain, that is, the bias correction phase shift circuit 21 may directly output the sensing input signal x, and then the bias correction averaging circuit 22 The weighted sum of the first to fourth input signals Ax, Bx, Ax', Bx' is calculated, and the average DC bias voltage V _dc can also be obtained in this circuit implementation.

The bias correction averaging circuit 22 calculates the average DC bias voltage V _dc , and then subtracts the average DC bias voltage V _{dc from the} sensed input signal x through the subtraction circuit 23 to obtain the input signal y, and the input signal y is eliminated. The signal of the bias error. FIG. 6 is a circuit diagram of a subtraction circuit in accordance with an embodiment of the present invention. To simplify the illustration, the subtraction circuit 23 in Fig. 6 only shows a subtraction operation for one of the input signal components, and the circuit can be modified, for example, by copying the same circuit to perform a subtraction operation on the four input signals. The subtraction circuit 23 includes an operational amplifier OP_23 and resistors R ₁ to R ₄ . The operational amplifier OP_23 can be powered by a bipolar power supply. The voltage signals received by the subtraction circuit 23 are V ₁₁ and V ₁₂ , respectively, and the output signal V _Out can be expressed as By setting the appropriate resistors R ₁ to R ₄ , V _{11 is} coupled to the average DC bias voltage V _dc , and V _{12 is} coupled to the first input signal Ax to obtain an output signal V _Out =Ax-V _dc . In another embodiment, the subtraction circuit 23 can sense the four components Ax, Bx, Ax', Bx' of the input signal x. The average DC bias voltage V _{dc is} subtracted to obtain the input signal y. The subtraction circuit 23 can also be implemented in other combinations by other analog circuit elements, or can also be implemented by an adder or a subtractor of the digital circuit.

After being processed by the bias correction circuit 2, the input signal y has eliminated the DC bias, and then the amplitude correction circuit 3 corrects the amplitude of the input signal y. In accordance with the above embodiment, the input signal y includes: a first input signal Ay, a second input signal By, a third input signal Ay', and a fourth input signal By', and these input signals Ay, By, Ay', By' The DC bias has been eliminated. The constituent elements and operation modes of the amplitude correction circuit 3 will be described below.

The amplitude correction circuit 3 includes a phase shift circuit 31, an averaging circuit 32, and an amplification circuit 33. The phase correction circuit 21 among the bias correction phase shift circuit 21 and the amplitude correction circuit 3 in the bias correction circuit 2 can use the same or similar circuit structure, and the operation principle of the two is similar, and the phase shift circuit 31 can also use the resistance chain. To generate a plurality of phase shifted output signals ps.

For the averaging circuit 32 in the amplitude correction circuit 3, the purpose is to calculate the instantaneous average amplitude of a plurality of signals to correct the signal. If the bias correction averaging circuit 22 is used as in the bias correction circuit 2, Since the first to fourth input signals Ay, By, Ay', and By' have eliminated the DC bias, the calculated average value is 0V. Thus, in one embodiment, the averaging circuit 32 is powered by a unipolar power supply to calculate an average value for the positive voltage portion of the signal to obtain an average amplitude.

Figure 7 is a diagram showing the execution effect of an exemplary averaging circuit powered by a unipolar power supply. The waveform on the upper left of Figure 7 shows a sine wave signal Y ₁ (t), and the upper right Y ₁ '(t) waveform shows the effect of the sine wave signal Y ₁ (t) on the averaging circuit powered by a unipolar power supply. Since the averaging circuit 32 in this embodiment employs an inverse amplifying circuit, the upper right waveform (output signal Y ₁ '(t)) will be opposite in polarity to the upper left waveform (input signal Y ₁ (t)). The averaging circuit 32 ignores the portion of the upper right waveform waveform in which the sine wave signal Y ₁ '(t) voltage is less than 0, and calculates the average value of the sine wave signal Y ₁ '(t) at the positive voltage portion. However, in this way, it can be found that half of the information of the original sine wave signal Y ₁ (t) disappears, so the calculated average value may not be accurate enough.

The waveform diagram at the bottom left of Figure 7 shows two sine wave signals Y ₁ (t) and Y ₂ (t), where Y ₂ (t) is opposite in polarity to Y ₁ (t), that is, when Y ₁ (t) is less than 0V When Y ₂ (t) is greater than 0V. The waveform diagram at the bottom right of Fig. 7 shows the effect of the averaging circuit powered by the unipolar power supply on the two sine wave signals Y ₁ (t) and Y ₂ (t), since the averaging circuit 32 in this embodiment uses the inverse To the amplifier circuit, the lower right waveform (output signals Y ₁ '(t) and Y ₂ '(t)) will be opposite in polarity to the lower left waveform (input signals Y ₁ (t) and Y ₂ (t)). In the lower right waveform diagram, since Y ₁ '(t) is less than 0V, information related to the sine wave signal Y ₁ '(t) can be obtained from another sine wave signal Y ₂ '(t), The information of the sine wave signal Y ₁ (t) is preserved at all times, and the average value thus calculated can be more accurate.

Based on the above, in an embodiment, the averaging circuit 32 is powered by a unipolar power supply, and the phase shift output signal ps output by the phase shift circuit 31 may include M first phase shift signals f _{1_1} ~f _{1_M} and M The two phase shift signals f _{2_1} ~f _{2_M} , and the M first phase shift signals f _{1_1} ~f _{1_M are opposite in polarity} to the M second phase shift signals f _{2_1} ~f _{2_M} , so that the amplitude calculated by the averaging circuit 32 can be made The gain V _gain is more accurate. The number of M can be determined according to design requirements. The following description uses M=9 as an example.

When M=9, the implementation of the phase shift circuit 31 can refer to the resistance chains Chain1~Chain8 and related descriptions shown in FIG. 4A to FIG. 4D. For example, the phase shift circuit 31 may include the resistance chain Chain1 of FIG. 4A and the resistance chain Chain2 of FIG. 4B. The resistor chain Chain1 includes 10 resistors connected in series, the left end is coupled to the first input signal Ay, and the right end is coupled to the second input signal By. The resistor chain Chain2 includes 10 resistors connected in series, the left end is coupled to the third input signal Ay', and the right end is coupled to the fourth input signal By'. Since the first input signal Ay is opposite in polarity to the third input signal Ay', the second input signal By is opposite in polarity to the fourth input signal By', so the nine first phase shift signals f _{1_1} ~ f _{1_9} output by the resistance chain _Chain1 The nine second phase shift signals f _{2_1} ~f _{2_9} outputted by the resistor chain Chain2 are opposite in polarity. Regarding the phase shift signal having the phase difference Δφ=9° (90°/10) generated by the resistance chain, the correlation calculation will not be repeated here.

The phase shift circuit 31 can have various embodiments as long as it can output a phase shift signal including opposite polarities. In addition to the foregoing embodiments using the resistor chains Chain1 and Chain2, in another embodiment, the phase shift circuit 31 may also be a resistor chain Chain5 including FIG. 4A and a resistor chain Chain6 of FIG. 4B. The second input signal By and the third input signal Ay' are coupled, and the two ends of the resistor chain Chain6 are respectively coupled to the fourth input signal By' and the first input signal Ay, so the phase shift signal and the resistor chain output by the resistor chain Chain5 The phase shift signal output from Chain6 is reversed in polarity. In still another embodiment, the phase shift circuit 31 can further include four resistance chains, Chain1, Chain2, Chain5, and Chain6, to facilitate obtaining a more accurate average amplitude value.

In an embodiment, the phase shift circuit 31 may further include the resistor chain Chain3 shown in FIG. 4C. For example, the phase shift circuit 31 includes the resistor chains Chain1, Chain2, and Chain3. In the foregoing resistance chains Chain1, Chain2, Chain5, and Chain6, a phase shift signal having a phase difference Δφ=9° is generated. However, in order to further increase the accuracy of the amplitude gain V _gain obtained by the averaging circuit 32, The third phase shift signal f _{3_1} ~f _{3_9} having another phase difference Δφ' is generated using the resistance chain Chain3, and Δφ' is not equal to Δφ. In this embodiment, the phase shift output signal ps includes first phase shift signals f _{1_1} ~f _{1_9} , second phase shift signals f _{2_1} ~f _{2_9 ,} and third phase shift signals f _{3_1} ~f _{3_9} . For example, △φ'=9.5°, so that in addition to the phase shift signal of the original phase difference Δφ=9°, the phase shift signal of another phase difference Δφ′=9.5° can be known, and the sine wave is obtained. The signal value of the signal at more different phases, which is equivalent to increasing the resolution of the sampling of the sinusoidal signal, makes the result calculated by the averaging circuit 32 more accurate.

The signal received at both ends of the resistor chain Chain3 is the same as that of the resistor chain Chain1, that is, the first input signal Ay and the second input signal By are coupled respectively. However, since the resistor chain Chain3 and the resistor chain Chain1 have different resistance values, the resistor chain can be made. resistive chain third phase-shifted signal generated Chain3 _{f 3_1} ~ f 3_9 having other phase difference △ φ '. For the calculation of the phase difference and the resistance value, reference can be made to equations (1) and (2). Table 3 below lists the proportional relationship of the resistors R _sk ' when Δφ' = 9.5°, which can be based on this proportional relationship. Adjust the resistance values. The resistance values in Table 3 are different from the resistance values in Table 1.

Table 3

As described above, the resistor chain Chain3 corresponds to the resistor chain Chain1, where "correspondence" refers to receiving the same input and generating phase shift signals having different phase differences with different resistance values. Similarly, the resistor chain Chain7 of FIG. 4C may correspond to the resistor chain Chain5, and the resistor chain Chain4 of FIG. 4D may correspond to the resistor chain Chain2 and the resistor chain Chain8 may correspond to the resistor chain Chain6. In an embodiment, the phase shift circuit 31 may include a resistor chain Chain1, Chain2, Chain3, and Chain4, which can generate phase shift signals having opposite polarity characteristics and phase shift signals having different phase differences. In another embodiment, the phase shift circuit 31 can include all eight resistor chains Chain1~Chain8 illustrated in FIGS. 4A-4D.

The bias correction circuit 2 and the amplitude correction circuit 3 are inspected and compared, wherein the bias correction phase shift circuit 21 operates similarly to the phase shift circuit 31, whereas in the amplitude correction circuit 3, the average value of the positive voltage portion is obtained, and the phase shift is performed. Circuit 31 can generate phase shifted signals of opposite polarity, and in one embodiment, phase shifting circuit 31 can employ more resistor chains to produce phase shifted signals having different phase differences, enabling more accurate calculations.

In an embodiment, the bias correction phase shift circuit 21 and the phase shift circuit 31 can be independent, that is, there is no relationship between the resistor chains used by the two. For example, the bias correction phase shift output signal ps1 output by the bias correction phase shift circuit 21 may include N first bias correction phase shift signals, and the N first bias correction phase shift signals have a bias between The phase difference Δφ1 is corrected, and (N+1) × (Δφ1) = 90°. The phase shift output signal ps outputted by the phase shift circuit 31 may include M first phase shift signals and M second phase shift signals, and the N value and the M value may be respectively determined, and the bias correction phase shift circuit 21 and the phase shift The number of resistor chains used in the circuit 31 and the resistance values used in the resistor chain can also be determined individually.

In an embodiment, the bias correction phase shift circuit 21 may be associated with a phase shift circuit 31, for example, the bias correction phase shift circuit 21 includes P bias correction resistor chains, and the phase shift circuit 31 includes 2P amplitude correction resistor chains. , P is a positive integer. For example, when P=4, the bias correction phase shift circuit 21 may include four resistance chains Chain1, Chain2, Chain5, and Chain6 as shown in FIGS. 4A-4D. The phase shift circuit 31 may include eight resistor chains Chain1 to Chain8 as shown in FIGS. 4A to 4D, that is, four resistor chains of the phase shift circuit 31 have four resistor chains (Chain1, Chain2, Chain5, Chain6) and the bias correction phase shift circuit 21 can use the same resistance chain resistance value, and another four resistor chains (Chain3, Chain4, Chain7, Chain8) and the resistor used in the bias correction phase shift circuit 21 Chains can have different resistance values.

The bias correction averaging circuit 22 is similar to the averaging circuit 32, however, the bias correction averaging circuit 22 is powered by a bipolar power supply to obtain an average DC bias value. The averaging circuit 32 is powered by a unipolar power supply to obtain an average amplitude value of the positive voltage portion to produce an amplitude gain _Vgain . Assuming that M = 9, on average, the number of phase shift output signals ps is increased by 10 each time a phase shift circuit 31 is added. When the phase shift circuit 31 uses four resistor chains, the averaging circuit 32 calculates the weighted sum of the 40 phase shift output signals ps. Similarly, when the phase shift circuit 31 uses eight resistor chains, the averaging circuit 32 calculates 80. The weighted sum of the phase shifted output signals ps.

8A to 8C are circuit diagrams showing an averaging circuit in accordance with various embodiments of the present invention. As shown in FIG. 8A, the averaging circuit 32a includes an operational amplifier OP_32, a feedback resistor Rf_32, M first input resistors R _{1_1} ~ R _{1_M,} and M second input resistors R _{2_1} ~ R _{2_M} . The non-inverting input of the operational amplifier OP_32 is coupled to the ground potential GND, and the operational amplifier OP_32 is powered by a unipolar power supply, that is, the positive supply of the operational amplifier OP_32 is connected to +V _DD and the negative supply is connected to the ground potential GND. The feedback resistor Rf_32 is coupled between the output terminal of the operational amplifier OP_32 and the inverting input terminal. One end of the M first input resistors R _{1_1} ~ R _{1_M} is coupled to the inverting input terminal of the operational amplifier OP_32, and the other end is coupled to the M first phase shift signals f _{1_1} ~ f _{1_M} , _respectively , and the resistances of the M first input resistors The value is determined by the phase difference Δφ. One end of the M second input resistors R _{2_1} ~ R _{2_M} is coupled to the inverting input terminal of the operational amplifier OP_32, and the other end is coupled to the M second phase shift signals f _{2_1} ~ f _{2_M} , and the resistances of the M second input resistors The value is determined by the phase difference Δφ. The averaging circuit 32 can also include other input resistors coupled to the first through fourth input signals Ay, By, Ay', By', respectively. The calculation formula of the averaging circuit 32 and the resistance value can be referred to the equation (7) and the second table, except that when the result calculated by the equation (7) is negative, since the averaging circuit 32 is powered by the unipolar power supply Therefore, the actual output of the op amp OP_32 will be 0V.

FIG. 8B is a circuit diagram of an averaging circuit 32b according to an embodiment of the present invention. The non-inverting input terminal of the operational amplifier OP_32 can be coupled to the reference voltage V _ref1 via a resistor, and can be used for an operational amplifier that cannot operate near 0V. The averaging circuit 32b shown in Fig. 8B. In the embodiment illustrated in FIG. 8A and FIG. 8B, the averaging circuit 32 is an inverse amplifying circuit using an operational amplifier, but the present invention is not limited thereto, and the averaging circuit may also adopt a non-inverting amplifying circuit of the operational amplifier. achieve.

The averaging circuit 32 corresponds to the design of the phase shift circuit 31. In the above example, the averaging circuit 32 uses two sets of input resistors, corresponding to the case where the phase shift circuit 31 uses two resistor chains. When the phase shift circuit 31 uses eight resistor chains, the averaging circuit 32 uses a total of eight sets of M input resistors, and the resistance values of each group of input resistors are generated according to the corresponding resistor chains in the phase shift circuit 31. Determined by the phase difference. For an averaging circuit using a plurality of sets of input resistors, in addition to the averaging circuits as shown in FIGS. 8A and 8B, another usable implementation can be referred to FIG. 8C, which is illustrated in FIG. 8C. According to a circuit diagram of the averaging circuit 32c according to an embodiment of the present invention, the averaging circuit 32c in this embodiment may be composed of a plurality of operational amplifiers.

9A and 9B are schematic diagrams showing an example average circuit output result corresponding to four resistor chains and eight resistor chains. As described above, in one embodiment, the phase shift circuit 31 can include four resistor chains, Chain1, Chain2, Chain5, and Chain6, (without another phase difference Δφ' information). In another embodiment, the phase shift circuit 31 includes eight resistor chains Chain1~Chain8. Figure 9A shows the result of the output of the corresponding averaging circuit 32 using the phase shift circuit 31 of the four resistor chains Chain1, Chain2, Chain5, and Chain6, and Figure 9B shows the phase shift circuit using the eight resistor chains Chain1~Chain8. 31, the result of the corresponding average circuit 32 output. It can be seen that since 8 resistor chains have a higher phase resolution, a smoother and continuous amplitude gain V _gain can be obtained in FIG. 9B compared to FIG. 9A, and a more accurate amplitude correction effect can be achieved. .

After the averaging circuit 32 obtains the amplitude gain V _gain , the amplifying circuit 33 adjusts the amplitude of the input signal y according to the amplitude gain V _gain to generate the corrected signal z, for example, the first to fourth input signals Ay, By among the input signals y. , Ay', By', respectively, or multiplied by the amplitude gain V _gain to obtain the respective components Az, Bz, Az', Bz' of the corrected signal z, the corrected signal z generated by the amplitude correcting circuit 3, The amplitudes of the respective components Az, Bz, Az', and Bz' remain the same.

The amplifying circuit 33 may include an output stage amplifying unit (for example, an operational amplifier) and a transistor. The output stage amplifying unit has an ability to adjust the signal amplitude. The control end of the transistor may be coupled to the amplitude gain V _gain for adjusting the output stage amplifying unit. Amplitude magnification. FIG. 10 is a circuit diagram of an amplifying circuit in accordance with an embodiment of the present invention. The amplifying circuit 33 includes an output stage operational amplifier OP_33, a transistor T1, and an input resistor Ri. The non-inverting input of the output stage operational amplifier OP_33 is coupled to the reference voltage signal V _ref3 . The transistor T1 is, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or a Junction Field-Effect Transistor (JFET), and a control terminal of the transistor T1 ( For example, the gate of the transistor is coupled to the amplitude gain V _gain , and when the transistor T1 is operated in the Ohmic Region, the transistor T1 can be used as a variable resistor controlled by the amplitude gain V _gain . The input resistor Ri is coupled between one of the first to fourth input signals Ay, By, Ay', By' and the inverting input of the output stage operational amplifier OP_33. When the on-resistance of the transistor T1 is represented by R _fet , the amplification factor of the amplifier circuit 33 is R _fet /Ri. The amplitude gain V _{gain is} related to the on-resistance R _fet , and is related to the type of the transistor T1 and the channel component. The amplifying circuit 33 in FIG. 10 only shows amplification of one of the input signal components, and the circuit can be modified, for example, by copying the same circuit for the first to fourth input signals Ay, By, Ay', By' The amplified circuit is performed to adjust the amplitudes of the first to fourth input signals Ay, By, Ay', By'. The signal is coupled to a reference voltage V _ref3 OP_33 output stage of the operational amplifier non-inverting input, it is possible to adjust the DC level of the corrected signal z.

11 is a block diagram of a signal correction circuit in accordance with an embodiment of the present invention. The respective constituent blocks of the bias correction circuit 2 and the amplitude correction circuit 3 have been described in detail as before, and the following signal waveforms are used to explain the operation results of the respective constituent blocks. 12A to 12G are diagrams showing signal waveforms of signal correction circuits at respective nodes in accordance with an embodiment of the present invention.

Figure 12 is a waveform of the sensing input signal x, including the first to fourth input signals Ax, Bx, Ax', Bx', it can be seen that the DC average voltage of the sensing input signal x is not equal to 0V, and each input signal The amplitudes of Ax, Bx, Ax', and Bx' are also different. A plurality of bias correction phase shift output signals ps1 (e.g., 40) are generated by bias correction phase shift circuit 21 (e.g., four resistor chains), and the waveform is seen in Fig. 12B. The average bias correction circuit 22 calculates a plurality of corrected phase shift biasing signal ps1 output weighted sum to obtain the average DC bias voltage V _dc, the first waveform can be seen in FIG. 12C. The subtraction circuit 23 subtracts the average DC bias voltage V _dc from the first to fourth input signals Ax, Bx, Ax', Bx' to obtain an input signal y, and the waveform can be seen in Fig. 12D. It can be seen that the input signal y generated via the bias correction circuit 2 has eliminated the DC bias error, and the input signal y includes the first to fourth input signals Ay, By, Ay', By', each of the input signals Ay, By The dc averages of Ay' and By' are all 0V, but the amplitude of each input signal Ay, By, Ay', By' still changes with time.

Next, the input signal y is corrected by the amplitude correcting circuit 3, and the input signal y is passed through a phase shift circuit 31 (for example, eight resistor chains) to generate a plurality of phase shift output signals ps (for example, 80), and the waveform is seen in Fig. 12E. The averaging circuit 32 calculates the weighted sum of the plurality of phase-shifted output signals ps to obtain an amplitude gain _Vgain which is visible in the 12th FF, corresponding to the average amplitude at each time point. The amplifying circuit 33 obtains the corrected signal z by dividing the first to fourth input signals Ay, By, Ay', and By' by the amplitude gain _Vgain , and the waveform is shown in Fig. 12G. By setting the reference voltage signal V _{ref3 in} FIG. 10 , the DC level of the corrected signal z can be set to 2.5 V, and the corrected signal z generated via the signal correction circuit 1 can be seen, not only the DC average value is 2.5. V, and the amplitude is also fixed, the corrected signal z can meet the needs of the industry's actual application of 2.5V ± 0.5V. In this way, the sensing input signal x outputted by the sensing device can be corrected to the corrected signal z, and the biasing error and the amplitude error can be effectively eliminated, so that the sensing device can be connected to the machine tool controller for use.

In the embodiments shown in FIGS. 5, 6, 8A to 8C, and 10, the inverse amplifier circuit of the operational amplifier is taken as an illustrative embodiment, but the present invention is not limited thereto. When implementing these circuits, a non-inverting amplifying circuit of an operational amplifier can also be used. For example, in the bias correction averaging circuit 22 in FIG. 5, the input resistors R _v1 to R _v11 may be coupled to the non-inverting input terminal of the operational amplifier OP_22, and the calculation result of the equation (7) has no negative sign. The rest of the circuit diagram configuration can be changed in a similar manner as in FIG. 6, FIG. 8A to FIG. 8C, and FIG. 10, and details are not described herein again. In the implementation of the circuit, an inverse amplification circuit or a non-inverting amplification circuit is used, which can be determined by visualizing the subsequent circuit and components (such as the type and characteristics of the FET).

The respective circuit blocks described in the above embodiments include, for example, a bias correction phase shift circuit 21, a bias correction averaging circuit 22, a subtraction circuit 23, a phase shift circuit 31, an averaging circuit 32, and an amplifying circuit 33, except that analog circuits can be used. In addition, it can also be realized by an analog to digital converter (ADC) with a digital circuit. For example, in the foregoing embodiment, the phase shift circuit 31 is implemented by a resistor chain, and according to the equations (1)-(4), the voltage output by the phase shift circuit 31 is a plurality of linear combinations of input voltages, and thus The equations (1)-(4) are implemented by the basic components of the multiplier, the adder, the lookup table, and the like of the digital circuit.

According to the amplitude correction circuit proposed by the present disclosure, since the phase shift circuit generates a phase shift signal having an opposite polarity and the averaging circuit is powered by the unipolar power source, the use of a full-wave rectifier (Rectifier) can be avoided to achieve full-wave rectification. Can effectively save circuit area. The bias correction circuit of the present disclosure and The amplitude correction circuit mainly corrects these errors by generating multiple sets of signals by phase shift and operations of multiple sets of signals, and does not require full cycle sampling to calculate, and the correction can be calculated very quickly. Signal correction can be performed for the power-on instant, the stop state, the motion in one cycle, and the fast motion.

In addition, since the phase shift circuit can use the resistor chain to generate a phase-shifted output signal, in such an analog circuit implementation, a plurality of phase-shifted signals can be quickly generated at the instant of receiving the signal, and the average amplitude value is immediately obtained. Compared with digital circuit implementations (for example, with an ADC with a microprocessor or a digital signal processor), it can have a shorter delay time and achieve a higher bandwidth, especially when the sensing device has a high bandwidth requirement. A wider application space.

The signal correction circuit disclosed in the present invention can effectively reduce the bias and amplitude errors of the optical scale or encoder sine wave analog signal, and replace the digital operator with a simple analog circuit to perform the mathematical operations required for signal processing, and the future read head In the integrated circuitization phase, electronic design automation (EDA) tools and intellectual property (IP) costs can be saved.

In the above, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

3‧‧‧Amplitude correction circuit

31‧‧‧ Phase shift circuit

32‧‧‧Average circuit

33‧‧‧Amplification circuit

f _{1_1} ~f _{1_M ‧‧‧First} phase shift signal

f _{2_1} ~f _{2_M ‧‧‧Second} phase shift signal

Ps‧‧‧ phase shift output signal

V _gain ‧‧‧amplitude gain

y‧‧‧Input signal

Z‧‧‧corrected signal

Claims (21)

An amplitude correction circuit includes: a phase shift circuit for generating a plurality of phase shift output signals according to a plurality of input signals, the phase shift output signals comprising M first phase shift signals and M second phase shift signals, the M a phase difference Δφ between the first phase shift signals, the M phase shift signals having the phase difference Δφ, the M first phase shift signals and the M second phase shift signal polarities Rather, where M is a positive integer; an averaging circuit for generating an amplitude gain based on the weighted sum of the input signals and the phase shifted output signals, the averaging circuit being powered by a unipolar power supply; and an amplifying circuit, The amplitude gain adjusts the amplitudes of the input signals to produce a plurality of corrected signals. The amplitude correction circuit of claim 1, wherein the input signals comprise a first input signal, a second input signal, a third input signal, and a fourth input signal, the first to the first The four input signals sequentially have a signal phase difference α, where (M+1) × (Δφ) = α, 45° α 135°. The amplitude correction circuit of claim 2, wherein the phase shift circuit comprises: a first resistance chain comprising (M+1) first resistors connected in series, the two ends of the first resistor chain are respectively coupled Connecting the first input signal and the second input signal, the (M+1) The first resistors are respectively connected to the M first phase shift signals; and a second resistor chain includes (M+1) second resistors connected in series, and the two ends of the second resistor chain are respectively coupled to the The third input signal and the fourth input signal, the connection of the (M+1) second resistors respectively output the M second phase shift signals. The amplitude correction circuit of claim 3, wherein the averaging circuit comprises: an operational amplifier having an input end and an output terminal, the operational amplifier being powered by the unipolar power supply, the output end of the operational amplifier Outputting the weighted sum; M first input resistors, one end of the M first input resistors being coupled to the input end of the operational amplifier, and the other ends of the M first input resistors respectively coupled to the M first phases Shifting signals, the resistance values of the M first input resistors are determined according to the phase difference Δφ; and M second input resistors, one end of the M second input resistors being coupled to the input end of the operational amplifier, The other ends of the M second input resistors are respectively coupled to the M second phase shift signals, and the resistance values of the M second input resistors are determined according to the phase difference Δφ. The amplitude correction circuit of claim 3, wherein the phase shift output signals further comprise M third phase shift signals, the phase shift circuit further comprising: a third resistor chain, including (M+1) a third resistor connected in series, the two ends of the third resistor chain are respectively coupled to the first input signal and the second input signal, and the connection of the (M+1) third resistors respectively outputs the M third Phase shift signal, the M number There is another phase difference Δφ' between the three-phase shift signals, where Δφ' is not equal to Δφ. The amplitude correction circuit of claim 5, wherein the phase shift output signals further comprise M fourth phase shift signals, the phase shift circuit further comprising: a fourth resistor chain, including (M+1) a fourth resistor connected in series, the two ends of the fourth resistor chain are respectively coupled to the third input signal and the fourth input signal, and the connection of the (M+1) fourth resistors respectively outputs the M fourth The phase shift signal has the other phase difference Δφ' between the M fourth phase shift signals. The amplitude correction circuit of claim 6, wherein the phase shift output signals further comprise M fifth phase shift signals and M sixth phase shift signals, the phase shift circuit further comprising: a fifth resistor The chain includes (M+1) fifth resistors connected in series, and the two ends of the fifth resistor chain are respectively coupled to the second input signal and the third input signal, and the (M+1) fifth resistors are connected And outputting the M fifth phase shift signals respectively, wherein the M fifth phase shift signals have the phase difference Δφ; and a sixth resistor chain including (M+1) sixth resistors connected in series, The two ends of the sixth resistance chain are respectively coupled to the fourth input signal and the first input signal, and the connection of the (M+1) sixth resistors respectively outputs the M sixth phase shift signals, the M first The phase difference Δφ is present between the five phase shift signals. The amplitude correction circuit of claim 7, wherein the phases are The shift output signal further includes M seventh phase shift signals and M eighth phase shift signals, and the phase shift circuit further includes: a seventh resistor chain including (M+1) seventh resistors connected in series, the seventh The two ends of the resistance chain are respectively coupled to the second input signal and the third input signal, and the connection of the (M+1) seventh resistors respectively outputs the M seventh phase shift signals, the M seventh phases The shifting signal has the other phase difference Δφ′; and an eighth resistor chain comprising (M+1) eighth resistors connected in series, and the two ends of the eighth resistor chain are respectively coupled to the fourth input signal And the first input signal, where the (M+1) eighth resistors respectively output the M eighth phase shift signals, and the M eighth phase shift signals have the other phase difference Δφ' . The amplitude correction circuit of claim 1, wherein the amplifying circuit comprises: an output stage amplifying unit having an ability to adjust signal amplitude; a transistor having a control end coupled to the amplitude gain, It is used to adjust the amplitude magnification of the output stage amplification unit. A signal correction circuit includes: a bias correction circuit comprising: a bias correction phase shift circuit for generating a plurality of bias correction phase shift output signals based on the plurality of sense input signals, the bias correction phase shift outputs The signal includes N first bias correction phase shift signals between the N first bias correction phase shift signals Having a bias correction phase difference Δφ1, where N is a positive integer; a bias correction averaging circuit for generating an average DC offset based on the weighted sum of the sense input signals and the bias corrected phase shift output signals And a subtraction circuit for subtracting the average DC bias from the sensed input signals to generate a plurality of input signals; and an amplitude correction circuit comprising: a phase shift circuit, according to the input signals, Generating a plurality of phase shift output signals, the phase shift output signals comprising M first phase shift signals and M second phase shift signals, wherein the M first phase shift signals have a phase difference Δφ between the M Between the second phase shift signals having the phase difference Δφ, the M first phase shift signals are opposite in polarity to the M second phase shift signals, wherein M is a positive integer; an averaging circuit is used according to the The input signal and the weighted sum of the phase shifted output signals produce an amplitude gain, the averaging circuit is powered by a unipolar power supply; and an amplifying circuit that adjusts the amplitudes of the input signals according to the amplitude gain to generate a plurality of After a positive signal. The signal correction circuit of claim 10, wherein the input signals comprise a first input signal, a second input signal, a third input signal, and a fourth input signal, the first to the first The four input signals sequentially have a signal phase difference α, where (M+1) × (Δφ) = α, 45° α 135°. The signal correction circuit of claim 11, wherein the phase shift circuit comprises: a first resistance chain comprising (M+1) first resistors connected in series, the two ends of the first resistor chain are respectively coupled Connecting the first input signal and the second input signal, the connection of the (M+1) first resistors respectively output the M first phase shift signals; and a second resistance chain, including (M+1) a second resistor connected in series, the two ends of the second resistor chain are respectively coupled to the third input signal and the fourth input signal, and the connection of the (M+1) second resistors respectively outputs the M second Phase shift signal. The signal correction circuit of claim 12, wherein the averaging circuit comprises: an operational amplifier having an input and an output, the operational amplifier being powered by the unipolar power supply, the output of the operational amplifier Outputting the weighted sum; M first input resistors, one end of the M first input resistors being coupled to the input end of the operational amplifier, and the other ends of the M first input resistors respectively coupled to the M first phases Shifting signals, the resistance values of the M first input resistors are determined according to the phase difference Δφ; and M second input resistors, one end of the M second input resistors being coupled to the input end of the operational amplifier, The other ends of the M second input resistors are respectively coupled to the M second phase shift signals, and the resistance values of the M second input resistors are determined according to the phase difference Δφ. The signal correction circuit of claim 12, wherein the phase shift output signals further comprise M third phase shift signals, the phase shift circuit further comprising: a third resistor chain, including (M+1) a third resistor connected in series, the two ends of the third resistor chain are respectively coupled to the first input signal and the second input signal, and the connection of the (M+1) third resistors respectively outputs the M third The phase shift signal has another phase difference Δφ' between the M third phase shift signals, wherein Δφ' is not equal to Δφ. The signal correction circuit of claim 14, wherein the phase shift output signals further comprise M fourth phase shift signals, the phase shift circuit further comprising: a fourth resistor chain, including (M+1) a fourth resistor connected in series, the two ends of the fourth resistor chain are respectively coupled to the third input signal and the fourth input signal, and the connection of the (M+1) fourth resistors respectively outputs the M fourth The phase shift signal has the other phase difference Δφ' between the M fourth phase shift signals. The signal correction circuit of claim 15, wherein the phase shift output signals further comprise M fifth phase shift signals and M sixth phase shift signals, the phase shift circuit further comprising: a fifth resistor The chain includes (M+1) fifth resistors connected in series, and the two ends of the fifth resistor chain are respectively coupled to the second input signal and the third input signal, and the (M+1) fifth resistors are connected And outputting the M fifth phase shift signals respectively, wherein the M fifth phase shift signals have the phase difference Δφ between; a sixth resistor chain includes (M+1) sixth resistors connected in series, and the two ends of the sixth resistor chain are respectively coupled to the fourth input signal and the first input signal, and the (M+1)th The M sixth phase shift signals are respectively outputted at the junction of the six resistors, and the phase difference Δφ is between the M fifth phase shift signals. The signal correction circuit of claim 16, wherein the phase shift output signals further comprise M seventh phase shift signals and M eighth phase shift signals, the phase shift circuit further comprising: a seventh resistor The chain includes (M+1) seventh resistors connected in series, and the two ends of the seventh resistor chain are respectively coupled to the second input signal and the third input signal, and the (M+1) seventh resistors are connected And outputting the M seventh phase shift signals respectively, the M seventh phase shift signals having the another phase difference Δφ′; and an eighth resistor chain including (M+1) series connected eighth a resistor, the two ends of the eighth resistor chain are respectively coupled to the fourth input signal and the first input signal, and the connection of the (M+1) eighth resistors respectively outputs the M eighth phase shift signals, where The other phase difference Δφ' is between the M eighth phase shift signals. The signal correction circuit of claim 10, wherein the amplifying circuit comprises: an output stage amplifying unit having an ability to adjust signal amplitude; a transistor having a control end coupled to the amplitude gain, It is used to adjust the amplitude magnification of the output stage amplification unit. The signal correction circuit of claim 10, wherein the bias correction phase shift circuit of the bias correction circuit comprises P bias correction resistor chains, the phase shift circuit of the amplitude correction circuit comprising 2P amplitudes Correct the resistance chain, P is a positive integer. The signal correction circuit of claim 19, wherein the resistance values of the first to the Pth amplitude correction resistor chains are the same as the resistance values of the P bias correction resistor chains, and the P+1th ~ The 2P amplitude correction resistor chains are different from the resistance values of the P bias correction resistor chains. The signal correction circuit of claim 10, wherein the bias correction averaging circuit is powered by a bipolar power source.