TWI569572B - Power limiting amplifier - Google Patents
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- TWI569572B TWI569572B TW104124207A TW104124207A TWI569572B TW I569572 B TWI569572 B TW I569572B TW 104124207 A TW104124207 A TW 104124207A TW 104124207 A TW104124207 A TW 104124207A TW I569572 B TWI569572 B TW I569572B
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Description
本發明係關於一種功率限制放大器。 The present invention is directed to a power limiting amplifier.
音頻放大器是一種用來放大音頻信號之功率放大器。傳統音頻放大器可分類為A類、B類、AB類和D類放大器,其中D類放大器由於具有高效率及低功耗的優點,近年來已成為音頻功率放大器的主流。圖1顯示一習知之D類放大器之方塊圖。如圖1所示,該D類放大器100包含兩輸入電容C1和C2、一增益放大級12、一脈寬調變器13、兩回授網路14和15以及兩功率級16和18。 An audio amplifier is a power amplifier used to amplify an audio signal. Traditional audio amplifiers can be classified into Class A, Class B, Class AB, and Class D amplifiers. Class D amplifiers have become the mainstream of audio power amplifiers in recent years due to their high efficiency and low power consumption. Figure 1 shows a block diagram of a conventional Class D amplifier. As shown in FIG. 1, the class D amplifier 100 includes two input capacitors C1 and C2, a gain amplifier stage 12, a pulse width modulator 13, two feedback networks 14 and 15, and two power stages 16 and 18.
參照圖1,該輸入電容C1和C2用以濾除一音頻輸入信號的直流偏壓,以產生信號AI1和信號AI2。該增益放大級12藉由電阻R1至R4的比例來放大信號AI1和信號AI2的電壓差值,以產生信號AG1和信號AG2。該脈寬調變器13在接收類比型式的信號AG1和信號AG2後,輸出兩脈寬調變訊號PWMP和PWMN至功率級16和18。該脈寬調變器13通常包含一積分器(未繪出)以積分類比信號AG1和信號AG2的電壓差值。該等脈寬調變訊號PWMP和PWMN也會藉由回授網路14 和15產生回授信號給該脈寬調變器13。該等功率級16和18用以推動一負載電路19,例如一耳機或是喇叭等音頻輸出裝置。 Referring to Figure 1, the input capacitors C1 and C2 are used to filter out the DC bias of an audio input signal to produce signal AI1 and signal AI2. The gain amplification stage 12 amplifies the voltage difference between the signal AI1 and the signal AI2 by the ratio of the resistors R1 to R4 to generate the signal AG1 and the signal AG2. The pulse width modulator 13 outputs two pulse width modulation signals PWMP and PWMN to the power stages 16 and 18 after receiving the analog type signals AG1 and AG2. The pulse width modulator 13 typically includes an integrator (not shown) to integrate the voltage difference between the analog signal AG1 and the signal AG2. The pulse width modulation signals PWMP and PWMN are also fed back to the network 14 And 15 generates a feedback signal to the pulse width modulator 13. The power stages 16 and 18 are used to drive a load circuit 19, such as an audio output device such as a headset or speaker.
在應用上,當音頻輸入信號的振幅過大時,該D類放大器100可能需要一電路以限制輸出功率在一特定範圍內,藉以避免對負載電路19造成損害。 In application, when the amplitude of the audio input signal is too large, the class D amplifier 100 may require a circuit to limit the output power to a particular range to avoid damage to the load circuit 19.
本發明係提供一種功率限制放大器,包含一運算放大器、一第一降增益單元、一比較單元、一充電泵單元、一低通濾波器單元、一第一電阻以及一第二電阻。該運算放大器包含一第一輸入端、一第二輸入端和一第一輸出端。該第二電阻耦接於該運算放大器的該第一輸入端和該運算放大器的該第一輸出端之間。該第一降增益單元耦接於該第一電阻和該運算放大器的該第一輸入端之間。該比較單元用以比較產生於該運算放大器的至少一輸出信號和至少一預設電壓值,藉以產生至少一比較結果。該充電泵單元用以接收該至少一比較結果,藉以產生至少一控制信號。該低通濾波器單元耦接於該充電泵單元,其用以濾除該至少一控制信號的高頻成分。該第一降增益單元根據該至少一控制信號以改變其阻值。 The invention provides a power limiting amplifier comprising an operational amplifier, a first gain reduction unit, a comparison unit, a charge pump unit, a low pass filter unit, a first resistor and a second resistor. The operational amplifier includes a first input, a second input, and a first output. The second resistor is coupled between the first input of the operational amplifier and the first output of the operational amplifier. The first gain reduction unit is coupled between the first resistor and the first input of the operational amplifier. The comparing unit is configured to compare the at least one output signal generated by the operational amplifier with the at least one preset voltage value to generate at least one comparison result. The charge pump unit is configured to receive the at least one comparison result to generate at least one control signal. The low pass filter unit is coupled to the charge pump unit for filtering high frequency components of the at least one control signal. The first down-gain unit changes its resistance according to the at least one control signal.
100‧‧‧D類放大器 100‧‧‧D class amplifier
12‧‧‧增益放大級 12‧‧‧ Gain amplification stage
13‧‧‧脈寬調變器 13‧‧‧ Pulse Width Modulator
14,15‧‧‧回授網路 14,15‧‧‧Return to the network
16,18‧‧‧功率級 16,18‧‧‧Power level
19‧‧‧負載電路 19‧‧‧Load circuit
20,30,40,50‧‧‧功率限制放大器 20, 30, 40, 50‧‧‧ power limiting amplifier
22‧‧‧降增益單元 22‧‧‧Down Gain Unit
24,24’‧‧‧運算放大器 24,24’‧‧‧Operational Amplifier
26,26’,26”‧‧‧偵測單元 26,26’,26”‧‧‧Detection unit
262,264,265‧‧‧電壓比較器 262,264,265‧‧‧Voltage comparator
266‧‧‧多工器 266‧‧‧Multiplexer
42‧‧‧降增益單元 42‧‧‧Down Gain Unit
62,64‧‧‧充電泵 62,64‧‧‧Charging pump
66,68‧‧‧低通濾波器 66,68‧‧‧low pass filter
C1,C2‧‧‧輸入電容 C1, C2‧‧‧ input capacitor
I1~I4‧‧‧電流源 I1~I4‧‧‧current source
M1~M7‧‧‧電晶體 M1~M7‧‧‧O crystal
R1~R4‧‧‧電阻 R1~R4‧‧‧ resistor
RB‧‧‧電阻 RB‧‧‧resistance
SW1,SW2‧‧‧開關 SW1, SW2‧‧‧ switch
VB‧‧‧偏壓源 VB‧‧‧ bias source
圖1顯示一習知之D類放大器之方塊圖。 Figure 1 shows a block diagram of a conventional Class D amplifier.
圖2顯示結合本發明一實施例之一功率限制放大器的方塊示意圖。 2 is a block diagram showing a power limiting amplifier in accordance with an embodiment of the present invention.
圖3顯示結合本發明另一實施例之一功率限制放大器的方塊示意圖。 3 is a block diagram showing a power limiting amplifier in accordance with another embodiment of the present invention.
圖4顯示結合本發明又一實施例之一功率限制放大器的方塊示意圖。 4 is a block diagram showing a power limiting amplifier in accordance with still another embodiment of the present invention.
圖5顯示結合本發明再一實施例之一功率限制放大器的方塊示意圖。 Figure 5 shows a block diagram of a power limiting amplifier in accordance with yet another embodiment of the present invention.
圖6顯示結合本發明一實施例之該偵測單元的方塊示意圖。 FIG. 6 is a block diagram showing the detecting unit in combination with an embodiment of the present invention.
圖2顯示結合本發明一實施例之一功率限制放大器20的方塊示意圖。參照圖2,該功率限制放大器20包含一偏壓電壓源VB、一降增益單元22、一運算放大器24、一偵測單元26、一輸入電容C1以及複數個電阻R1和RB。該運算放大器24具有一正輸入端,一負輸入端和一輸出端。該降增益單元22耦接於該電阻R1和該運算放大器24的該負輸入端之間。該電阻RB耦接於該運算放大器24的該正輸入端和該輸出端之間。 2 shows a block diagram of a power limiting amplifier 20 in accordance with one embodiment of the present invention. Referring to FIG. 2, the power limiting amplifier 20 includes a bias voltage source VB, a falling gain unit 22, an operational amplifier 24, a detecting unit 26, an input capacitor C1, and a plurality of resistors R1 and RB. The operational amplifier 24 has a positive input, a negative input and an output. The gain reduction unit 22 is coupled between the resistor R1 and the negative input terminal of the operational amplifier 24. The resistor RB is coupled between the positive input terminal of the operational amplifier 24 and the output terminal.
參照圖2,該偵測單元26係由兩電壓比較器262和264所組成。該電壓比較器262用以比較產生於該運算放大器24的該輸出端的一輸出信號VO和一預設電壓值REFH,藉 以產生一控制信號CP1。該電壓比較器264用以比較該輸出信號VO和一預設電壓值REFL,藉以產生一控制信號CP2。該等信號CP1和CP2用以改變該降增益單元22的阻值。在本實施例中,該降增益單元22由兩電晶體M1和M2所組成。該電晶體M1耦接於該電阻R1,而該電晶體M2耦接於該電晶體M1和該運算放大器24的該正輸入端之間。 Referring to FIG. 2, the detecting unit 26 is composed of two voltage comparators 262 and 264. The voltage comparator 262 is configured to compare an output signal VO and a preset voltage value REFH generated at the output end of the operational amplifier 24, To generate a control signal CP1. The voltage comparator 264 is configured to compare the output signal VO with a predetermined voltage value REFL to generate a control signal CP2. The signals CP1 and CP2 are used to change the resistance of the gain reduction unit 22. In the present embodiment, the gain reduction unit 22 is composed of two transistors M1 and M2. The transistor M1 is coupled to the resistor R1, and the transistor M2 is coupled between the transistor M1 and the positive input terminal of the operational amplifier 24.
在運作上,一類比信號VIN由該功率限制放大器20的一輸入端進入後,經由該輸入電容C1以濾除類比輸入信號的直流偏壓。接著,根據電阻RA和電阻RB的阻值比例,信號A1會被放大(RB/RA)倍數以產生該輸出信號VO。在本實施例中,電阻RA的阻值由電阻R1的阻值和該降增益單元22的等效阻值所加總而成,而該降增益單元22的等效阻值由兩電晶體M1和M2的導通阻值所決定。 In operation, an analog signal VIN is input from an input of the power limiting amplifier 20, via which the DC bias of the analog input signal is filtered out. Then, according to the resistance ratio of the resistor RA and the resistor RB, the signal A1 is amplified (RB/RA) multiple to generate the output signal VO. In this embodiment, the resistance of the resistor RA is formed by summing the resistance of the resistor R1 and the equivalent resistance of the gain unit 22, and the equivalent resistance of the gain unit 22 is determined by the two transistors M1. And the conduction resistance of M2 is determined.
當該輸出信號VO的電壓值落於該預設電壓值REFH和該預設電壓值REFL之間時,表示該類比信號VIN的電壓振幅為負載可接受範圍,因此該電壓比較器262會產生位於邏輯1位準的該控制信號CP1,而該電壓比較器264會產生位於邏輯1位準的該控制信號CP2,藉以完全導通該等電晶體M1和M2。此時,電阻RA的阻值實質上等於電阻R1的阻值。 When the voltage value of the output signal VO falls between the preset voltage value REFH and the preset voltage value REFL, it indicates that the voltage amplitude of the analog signal VIN is a load acceptable range, so the voltage comparator 262 is generated. The control signal CP1 is logic 1 level, and the voltage comparator 264 generates the control signal CP2 at the logic 1 level, thereby fully turning on the transistors M1 and M2. At this time, the resistance of the resistor RA is substantially equal to the resistance of the resistor R1.
當該輸出信號VO的電壓值大於該預設電壓值REFH時,表示該類比信號VIN的電壓振幅超過負載可接受範圍。此時,該電壓比較器262會產生低於邏輯1位準的該控制 信號CP1,藉以部分導通該電晶體M1。因此,該電阻RA的阻值會由電阻R1的阻值和該電晶體M1的等效阻值所加總。由於該電阻RA的阻值提升,該信號A1的放大倍數會下降,藉以限制該輸出信號VO的電壓不大於該預設電壓值REFH。 When the voltage value of the output signal VO is greater than the preset voltage value REFH, it indicates that the voltage amplitude of the analog signal VIN exceeds the load acceptable range. At this time, the voltage comparator 262 generates the control below the logic 1 level. The signal CP1 is used to partially turn on the transistor M1. Therefore, the resistance of the resistor RA is summed by the resistance of the resistor R1 and the equivalent resistance of the transistor M1. As the resistance of the resistor RA increases, the amplification factor of the signal A1 decreases, thereby limiting the voltage of the output signal VO to be no greater than the preset voltage value REFH.
類似地,當該輸出信號VO的電壓值小於該預設電壓值REFL時,表示該類比信號VIN的電壓振幅超過負載可接受範圍。此時,該電壓比較器264會產生低於邏輯1位準的該控制信號CP2,藉以部分導通該電晶體M2。因此,該電阻RA的阻值會由電阻R1的阻值和該電晶體M2的等效阻值所加總。由於該電阻RA的阻值提升,該信號A1的放大倍數會下降,藉以限制該輸出信號VO的電壓不低於該預設電壓值REFL。 Similarly, when the voltage value of the output signal VO is less than the preset voltage value REFL, it indicates that the voltage amplitude of the analog signal VIN exceeds the load acceptable range. At this time, the voltage comparator 264 generates the control signal CP2 lower than the logic 1 level, thereby partially turning on the transistor M2. Therefore, the resistance of the resistor RA is summed by the resistance of the resistor R1 and the equivalent resistance of the transistor M2. As the resistance of the resistor RA increases, the amplification factor of the signal A1 decreases, thereby limiting the voltage of the output signal VO not lower than the preset voltage value REFL.
圖3顯示結合本發明另一實施例之一功率限制放大器30的方塊示意圖,其中圖3中類似圖2之元件以類似的參考數字顯示。參照圖3,該降增益單元22’由一電晶體M3所組成。該電晶體M3耦接於該電阻R1和該運算放大器24的該負輸入端之間。 3 is a block diagram showing a power limiting amplifier 30 in accordance with another embodiment of the present invention, wherein elements in FIG. 3 similar to FIG. 2 are shown with like reference numerals. Referring to Figure 3, the gain reduction unit 22' is comprised of a transistor M3. The transistor M3 is coupled between the resistor R1 and the negative input terminal of the operational amplifier 24.
該偵測單元26係由複數個電壓比較器262、264和265以及一多工器266所組成。在運作上,當該輸出信號VO的電壓值落於該預設電壓值REFH和該預設電壓值REFL之間時,表示該類比信號VIN的電壓振幅為負載可接受範圍,因此該電壓比較器262會產生位於邏輯1位準的該控制信號 CP1,而該電壓比較器264會產生位於邏輯1位準的該控制信號CP2。在該輸入信號VIN的電壓值大於一電壓值VCM時,該多工器266選擇輸出該控制信號CP1。在該輸入信號VIN的電壓值小於該電壓值VCM時,該多工器266選擇輸出該控制信號CP2。該電壓值VCM為該輸入信號VIN電壓振幅的中心值。由於在該輸出信號VO的電壓值落於該預設電壓值REFH和該預設電壓值REFL之間時,該等控制信號CP1和CP2都是邏輯1位準,因此該等電晶體M1和M2完全導通。在此狀況下該輸出信號VO會是信號A1的(RB/RC)倍數。 The detecting unit 26 is composed of a plurality of voltage comparators 262, 264 and 265 and a multiplexer 266. In operation, when the voltage value of the output signal VO falls between the preset voltage value REFH and the preset voltage value REFL, it indicates that the voltage amplitude of the analog signal VIN is an acceptable range of the load, and thus the voltage comparator 262 will generate the control signal at the logic 1 level CP1, and the voltage comparator 264 generates the control signal CP2 at the logic 1 level. When the voltage value of the input signal VIN is greater than a voltage value VCM, the multiplexer 266 selectively outputs the control signal CP1. When the voltage value of the input signal VIN is less than the voltage value VCM, the multiplexer 266 selectively outputs the control signal CP2. The voltage value VCM is the center value of the voltage amplitude of the input signal VIN. Since the control signals CP1 and CP2 are both logic 1 when the voltage value of the output signal VO falls between the preset voltage value REFH and the preset voltage value REFL, the transistors M1 and M2 Fully conductive. In this case the output signal VO will be a multiple of (RB/RC) of the signal A1.
當該輸出信號VO的電壓值大於該預設電壓值REFH時,表示該類比信號VIN的電壓振幅超過負載可接受範圍。藉由該等電壓比較器262、264和265以及該多工器266的運作,該偵測單元26’會輸出低於邏輯1位準的該控制信號CT,藉以部分導通該電晶體M3。因此,該電阻RA的阻值會由電阻R1的阻值和該電晶體M3的等效阻值所加總。由於該電阻RA的阻值提升,該信號A1的放大倍數會下降,藉以限制該輸出信號VO的電壓不大於該預設電壓值REFH。 When the voltage value of the output signal VO is greater than the preset voltage value REFH, it indicates that the voltage amplitude of the analog signal VIN exceeds the load acceptable range. With the operation of the voltage comparators 262, 264, and 265 and the multiplexer 266, the detecting unit 26' outputs the control signal CT lower than the logic 1 level, thereby partially turning on the transistor M3. Therefore, the resistance of the resistor RA is summed by the resistance of the resistor R1 and the equivalent resistance of the transistor M3. As the resistance of the resistor RA increases, the amplification factor of the signal A1 decreases, thereby limiting the voltage of the output signal VO to be no greater than the preset voltage value REFH.
當該輸出信號VO的電壓值小於該預設電壓值REFL時,表示該類比信號VIN的電壓振幅超過負載可接受範圍。藉由該等電壓比較器262、264和265以及該多工器266的運作,該偵測單元26’會輸出低於邏輯1位準的該控制信號CT,藉以部分導通該電晶體M3,藉以限制該輸出信號VO的 電壓不低於該預設電壓值REFL。 When the voltage value of the output signal VO is less than the preset voltage value REFL, it indicates that the voltage amplitude of the analog signal VIN exceeds the load acceptable range. With the operation of the voltage comparators 262, 264, and 265 and the multiplexer 266, the detecting unit 26' outputs the control signal CT lower than the logic 1 level, thereby partially turning on the transistor M3. Limiting the output signal VO The voltage is not lower than the preset voltage value REFL.
圖2和圖3所例示的運算放大器24為雙端差動輸入,單端輸出的放大器型態。然而,本發明所揭示之輸入功率限制方法亦可使用於雙端差動輸入,雙端差動輸出的放大器型態,如圖4所示,其中圖4中類似圖2之元件以類似的參考數字顯示。 The operational amplifier 24 illustrated in Figures 2 and 3 is a double-ended differential input, single-ended output amplifier type. However, the input power limiting method disclosed in the present invention can also be applied to a double-ended differential input, an amplifier type of a double-ended differential output, as shown in FIG. 4, wherein the components in FIG. 4 are similar to those in FIG. Digital Display.
參照圖4,該運算放大器24’具有一正輸入端,一負輸入端、一正輸出端和一負輸出端。互為反相的類比輸入信號VIP和VIN由該功率限制放大器40的一對差動輸入端進入後,經由輸入電容C1和C2以濾除類比輸入信號的直流偏壓。接著,根據電阻RD和電阻RB的阻值比例,信號A1會被放大(RB/RD)倍數以產生該輸出信號VO。在本實施例中,電阻R1的阻值與電阻R2的阻值相同,電阻R3的阻值與電阻RB的阻值相同。 Referring to Figure 4, the operational amplifier 24' has a positive input, a negative input, a positive output, and a negative output. The inverting analog input signals VIP and VIN are entered by a pair of differential inputs of the power limiting amplifier 40, and the DC bias of the analog input signal is filtered out via input capacitors C1 and C2. Then, according to the resistance ratio of the resistor RD and the resistor RB, the signal A1 is amplified (RB/RD) multiples to generate the output signal VO. In this embodiment, the resistance of the resistor R1 is the same as the resistance of the resistor R2, and the resistance of the resistor R3 is the same as the resistance of the resistor RB.
參照圖4,該功率限制放大器40另包含一降增益單元42。該降增益單元42由兩電晶體M5和M6所組成。該電晶體M5耦接於該電阻R2,而該電晶體M6耦接於該電晶體M5和該運算放大器24的該負輸入端之間。在本實施例中,該等電晶體M5和M6的寬長比等於該等電晶體M1和M2的寬長比,因此該等電晶體M5和M6的導通阻值會等於該等電晶體M1和M2的導通阻值。在運作上,該降增益單元42會根據該等控制信號CP1和CP2以改變其阻值。該降增益單元42的工作 原理相同於該降增益單元22的工作原理,於茲不贅述。 Referring to FIG. 4, the power limiting amplifier 40 further includes a down-gain unit 42. The gain reduction unit 42 is composed of two transistors M5 and M6. The transistor M5 is coupled to the resistor R2, and the transistor M6 is coupled between the transistor M5 and the negative input terminal of the operational amplifier 24. In this embodiment, the width-to-length ratio of the transistors M5 and M6 is equal to the aspect ratio of the transistors M1 and M2, so that the on-resistances of the transistors M5 and M6 are equal to the transistors M1 and The conduction resistance of M2. In operation, the gain reduction unit 42 changes its resistance according to the control signals CP1 and CP2. The operation of the down-gain unit 42 The principle is the same as that of the gain reduction unit 22, and will not be described again.
圖5顯示結合本發明又一實施例之一功率限制放大器50的方塊示意圖,其中圖5中類似圖3之元件以類似的參考數字顯示。參照圖5,該功率限制放大器50另包含一降增益單元52。該降增益單元52由一電晶體M7所組成。該電晶體M7耦接於該電阻R2和該運算放大器24’的該負輸入端之間。在本實施例中,該電晶體M7的寬長比等於圖3中的該電晶體M3的寬長比。在運作上,該降增益單元42會根據該控制信號CT以改變其阻值。該降增益單元42的工作原理相同於圖3中的該降增益單元22的工作原理,於茲不贅述。 Figure 5 shows a block diagram of a power limiting amplifier 50 in accordance with yet another embodiment of the present invention, wherein elements in Figure 5 similar to Figure 3 are shown with like reference numerals. Referring to FIG. 5, the power limiting amplifier 50 further includes a down-gain unit 52. The down-gain unit 52 is composed of a transistor M7. The transistor M7 is coupled between the resistor R2 and the negative input terminal of the operational amplifier 24'. In the present embodiment, the width to length ratio of the transistor M7 is equal to the width to length ratio of the transistor M3 in FIG. In operation, the gain reduction unit 42 changes its resistance according to the control signal CT. The operation principle of the down-gain unit 42 is the same as that of the down-gain unit 22 in FIG. 3, and will not be described again.
參照圖4,該等控制信號CP1和CP2的產生除了藉由該等比較器262和264外,亦可藉由其他方式,例如一充電泵(charge pump)而產生。圖6顯示結合本發明一實施例之一偵測單元26”的方塊示意圖。參照圖6,該偵測單元26”包含一比較器262、一比較器264、一充電泵62、一充電泵64、一低通濾波器66以及一低通濾波器68。 Referring to Figure 4, the generation of the control signals CP1 and CP2 may be generated by other means, such as a charge pump, in addition to the comparators 262 and 264. 6 is a block diagram showing a detecting unit 26" according to an embodiment of the present invention. Referring to FIG. 6, the detecting unit 26" includes a comparator 262, a comparator 264, a charging pump 62, and a charging pump 64. A low pass filter 66 and a low pass filter 68.
該充電泵62包含一上拉電流源I1、一開關SW1和一下拉電流源I2。該充電泵64包含一上拉電流源I3、一開關SW2和一下拉電流源I4。該充電泵62用以轉換該比較器262的比較結果,藉以產生該控制信號CP1。該低通濾波器66用以濾除該控制信號CP1的高頻成分。該充電泵64用以轉換該比較器264的比較結果,藉以產生該控制信號CP2。該低通濾波 器68用以濾除該控制信號CP2的高頻成分。 The charge pump 62 includes a pull-up current source I1, a switch SW1, and a pull-down current source I2. The charge pump 64 includes a pull-up current source I3, a switch SW2, and a pull-down current source I4. The charge pump 62 is configured to convert the comparison result of the comparator 262 to generate the control signal CP1. The low pass filter 66 is configured to filter out high frequency components of the control signal CP1. The charge pump 64 is configured to convert the comparison result of the comparator 264 to generate the control signal CP2. Low pass filtering The device 68 is configured to filter out high frequency components of the control signal CP2.
在運作上,當圖4中的該輸出信號VOP的電壓值大於該預設電壓值REFH時,或者小於該預設電壓值REFL時,該等充電泵62和64以及該等低通濾波器66和68會一同運作以產生低於邏輯1位準的該控制信號CP1,或是低於邏輯1位準的該控制信號CP2,藉以控制圖4中的該等降增益單元22和42的阻值。依此方式,該輸出信號VO的電壓可限制於該預設電壓值REFH和該預設電壓值REFL之間。 In operation, when the voltage value of the output signal VOP in FIG. 4 is greater than the preset voltage value REFH, or less than the preset voltage value REFL, the charge pumps 62 and 64 and the low pass filters 66 And 68 will operate together to generate the control signal CP1 below the logic 1 level, or the control signal CP2 below the logic 1 level, thereby controlling the resistance values of the falling gain units 22 and 42 in FIG. . In this way, the voltage of the output signal VO can be limited between the preset voltage value REFH and the preset voltage value REFL.
本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為隨後之申請專利範圍所涵蓋。 The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be
20‧‧‧功率限制放大器 20‧‧‧Power Limiting Amplifier
22‧‧‧降增益單元 22‧‧‧Down Gain Unit
24‧‧‧運算放大器 24‧‧‧Operational Amplifier
26‧‧‧偵測單元 26‧‧‧Detection unit
262,264‧‧‧電壓比較器 262,264‧‧‧Voltage comparator
C1‧‧‧輸入電容 C1‧‧‧ input capacitor
M1,M2‧‧‧電晶體 M1, M2‧‧‧ transistor
R1,RB‧‧‧電阻 R1, RB‧‧‧ resistance
VB‧‧‧偏壓源 VB‧‧‧ bias source
Claims (8)
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TW104124207A TWI569572B (en) | 2015-07-23 | 2015-07-23 | Power limiting amplifier |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5245229A (en) * | 1992-02-28 | 1993-09-14 | Media Vision | Digitally controlled integrated circuit anti-clipping mixer |
US20030179039A1 (en) * | 2002-03-22 | 2003-09-25 | Te-Yu Liang | Amplifying circuit capable of limiting amplitude of output signal supplied to a speaker |
US20110133837A1 (en) * | 2009-12-08 | 2011-06-09 | Hiroshi Komori | Variable gain amplifier |
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- 2015-07-23 TW TW104124207A patent/TWI569572B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5245229A (en) * | 1992-02-28 | 1993-09-14 | Media Vision | Digitally controlled integrated circuit anti-clipping mixer |
US20030179039A1 (en) * | 2002-03-22 | 2003-09-25 | Te-Yu Liang | Amplifying circuit capable of limiting amplitude of output signal supplied to a speaker |
US20110133837A1 (en) * | 2009-12-08 | 2011-06-09 | Hiroshi Komori | Variable gain amplifier |
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