TWI568255B - Serial peripheral interface device and method of transmitting signal - Google Patents
Serial peripheral interface device and method of transmitting signal Download PDFInfo
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- TWI568255B TWI568255B TW104127104A TW104127104A TWI568255B TW I568255 B TWI568255 B TW I568255B TW 104127104 A TW104127104 A TW 104127104A TW 104127104 A TW104127104 A TW 104127104A TW I568255 B TWI568255 B TW I568255B
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Description
本發明涉及一種串列周邊介面裝置。The present invention relates to a tandem peripheral interface device.
串列周邊介面（Serial Peripheral Interface，SPI）裝置包括主裝置(Master)與從裝置(Slave)，該主裝置與從裝置之間的資料傳輸主要採用串列周邊介面（Serial Peripheral Interface，SPI）傳輸資料，串列周邊介面允許主裝置與從裝置之間進行串列資料交換。然主裝置與從裝置各自獨立的時鐘訊號，主裝置與從裝置的時鐘訊號可能不同步而導致從裝置在解碼訊號時產生錯誤。The Serial Peripheral Interface (SPI) device includes a master device and a slave device. The data transmission between the master device and the slave device is mainly transmitted by using a Serial Peripheral Interface (SPI). Data, serializing the peripheral interface allows serial data exchange between the master device and the slave device. However, the clock signals independently of the master device and the slave device may be out of synchronization with the clock signals of the master device and the slave device, causing the slave device to generate an error when decoding the signal.
有鑑於此，有必要提供一種可減少解碼錯誤的串列周邊介面裝置及訊號傳輸方法。In view of the above, it is necessary to provide a serial peripheral interface device and a signal transmission method that can reduce decoding errors.
一種串列周邊介面裝置，包括：水平同步訊號引腳，用於在主裝置與從裝置之間傳輸水平同步訊號；串列訊號引腳，用於在該主裝置與從裝置之間傳輸串列訊號，且該從裝置在解碼該串列訊號時使用該水平同步訊號作為時鐘訊號。A serial peripheral interface device comprising: a horizontal synchronization signal pin for transmitting a horizontal synchronization signal between a master device and a slave device; and a serial signal pin for transmitting a serial port between the master device and the slave device a signal, and the slave device uses the horizontal sync signal as a clock signal when decoding the serial signal.
一種訊號傳輸方法，包括：A signal transmission method includes:
主裝置將資料訊號轉換為串列訊號；The main device converts the data signal into a serial signal;
主裝置輸出水平同步記號與串列訊號至從裝置；及The main device outputs a horizontal sync mark and a serial signal to the slave device;
該從裝置使用該水平同步訊號作為時鐘訊號解碼該串列訊號。The slave device decodes the serial signal using the horizontal sync signal as a clock signal.
相較於先前技術，本發明的串列周邊介面裝置及訊號傳輸方法中從裝置使用主裝置的水平同步訊號作為時鐘訊號解碼串列訊號，因此可避免先前技術中主裝置與從裝置而導致的串列訊號解碼錯誤。Compared with the prior art, in the serial peripheral interface device and the signal transmission method of the present invention, the slave device uses the horizontal sync signal of the master device as the clock signal to decode the serial signal, thereby avoiding the master device and the slave device in the prior art. Serial signal decoding error.
圖1是本發明串列周邊介面裝置示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a tandem peripheral interface device of the present invention.
圖2是圖1所示串列周邊介面裝置的主裝置資料傳輸時序控制圖。2 is a timing diagram of data transmission timing of a master device of the serial peripheral interface device shown in FIG. 1.
圖3是圖1所示串列周邊介面裝置的從裝置資料傳輸時序控制圖。3 is a timing chart of slave device data transmission timing control of the serial peripheral interface device shown in FIG. 1.
下面結合附圖具體說明本發明串列周邊介面裝置。The serial peripheral interface device of the present invention will be specifically described below with reference to the accompanying drawings.
請參閱圖1，圖1是本發明串列周邊介面裝置10之示意圖。該串列周邊介面裝置10包括主裝置(Master)110與從裝置(Slave)120。該主裝置110傳輸串列訊號至該從裝置120。該主裝置100包括水平同步訊號輸出引腳111與串列訊號輸出引腳113。該從裝置120包括水平同步訊號輸入引腳121與串列訊號輸入引腳123。該水平同步訊號輸出引腳111輸出水平同步訊號(Hsync)至該水平同步訊號輸入引腳121，該串列訊號輸出引腳113輸出串列訊號至該串列訊號輸入引腳123。在本實施方式中，該串列周邊介面裝置10可以是，但不限於液晶面板的資料驅動器，該資料驅動器用於為液晶面板提供畫面資料，該資料驅動器包括主裝置110與該從裝置120，該主裝置110與該從裝置120分別為液晶面板的一個區域提供畫面資料。Please refer to FIG. 1. FIG. 1 is a schematic diagram of a tandem peripheral interface device 10 of the present invention. The serial peripheral interface device 10 includes a master 110 and a slave 120. The master device 110 transmits a serial signal to the slave device 120. The main device 100 includes a horizontal sync signal output pin 111 and a serial signal output pin 113. The slave device 120 includes a horizontal sync signal input pin 121 and a serial signal input pin 123. The horizontal sync signal output pin 111 outputs a horizontal sync signal (Hsync) to the horizontal sync signal input pin 121, and the serial signal output pin 113 outputs a serial signal to the serial signal input pin 123. In this embodiment, the serial peripheral interface device 10 may be, but not limited to, a data driver of a liquid crystal panel, and the data driver is configured to provide screen data for the liquid crystal panel, and the data driver includes the main device 110 and the slave device 120. The master device 110 and the slave device 120 respectively provide screen data for an area of the liquid crystal panel.
該主裝置110生成欲傳輸至該從裝置12的資料訊號，然後該主裝置10將該資料訊號與垂直同步訊號(Vsync)編碼為串列訊號Dsync。該主裝置110經該水平同步訊號輸出引腳111輸出水平同步訊號Hsync，經該串列訊號輸出引腳113輸出串列訊號Dsync。該從裝置120經該水平同步訊號輸入引腳121接收該水平同步訊號Hsync，同時該從裝置120經該串列訊號輸入引腳123接收該串列訊號Dsync。該從裝置120將該水平同步訊號Hsync作為時鐘訊號解碼該串列訊號獲取資料訊號與垂直同步訊號Vsync。在本實施方式中，該水平同步訊號(Hsync)決定畫出一條橫越液晶面板的橫線所需的時間，垂直同步訊號(Vsync)則是決定從液晶面板頂部畫到底部，再返回原始位置所需的時間。在本實施方式中，該主裝置110將該資料訊號與該垂直同步訊號Vsync轉換成諸如低壓差分訊號(LVDS)和躍變最小化差分訊號(TMDS)的串列訊號。The master device 110 generates a data signal to be transmitted to the slave device 12, and then the master device 10 encodes the data signal and the vertical sync signal (Vsync) into the serial signal Dsync. The main device 110 outputs a horizontal synchronizing signal Hsync via the horizontal synchronizing signal output pin 111, and outputs a serial signal Dsync via the serial signal output pin 113. The slave device 120 receives the horizontal synchronization signal Hsync via the horizontal synchronization signal input pin 121, and the slave device 120 receives the serial signal Dsync via the serial signal input pin 123. The slave device 120 decodes the serial signal acquiring data signal and the vertical synchronization signal Vsync by using the horizontal synchronization signal Hsync as a clock signal. In this embodiment, the horizontal sync signal (Hsync) determines the time required to draw a horizontal line across the liquid crystal panel, and the vertical sync signal (Vsync) is determined from the top of the liquid crystal panel to the bottom, and then returns to the original position. The time required. In this embodiment, the main device 110 converts the data signal and the vertical synchronization signal Vsync into a serial signal such as a low voltage differential signal (LVDS) and a transition minimized differential signal (TMDS).
請一併參閱圖2，圖2是圖1所示串列周邊介面裝置10的主裝置110之訊號時序圖。如下以該主裝置110輸出黑畫面與紅畫面為例進行說明。Please refer to FIG. 2 together. FIG. 2 is a signal timing diagram of the main device 110 of the serial peripheral interface device 10 shown in FIG. The main device 110 outputs a black screen and a red screen as an example for description.
在T1時間段，該主裝置110輸出黑畫面訊號(000)，且在T1時間段內，該資料訊號Data由0變為2促使在下一次顯示畫面期間顯示紅畫面。During the T1 period, the master device 110 outputs a black screen signal (000), and during the time period T1, the data signal Data changes from 0 to 2 to cause the red screen to be displayed during the next display of the screen.
T2時間段為顯示黑畫面與紅畫面之間的間隙時間，在T2時間段開始時，該垂直同步訊號Vsnyc由高電位”1”躍變為低電位”0”，同時該主裝置110輸出串列訊號Dsync。本發明中該主裝置110在顯示黑畫面與畫面的間隙之間傳輸串列訊號Dsync，因此不會干擾到畫面訊號。The T2 time period is a gap time between the black picture and the red picture. When the T2 time period starts, the vertical synchronization signal Vsnyc transitions from a high potential "1" to a low potential "0", and the main device 110 outputs a string. Column signal Dsync. In the present invention, the main device 110 transmits the serial signal Dsync between the display of the black screen and the gap of the picture, so that the picture signal is not disturbed.
T3時間段，該垂直同步訊號Vsync由低電位”0”躍變為高電位”1”,同時該主裝置110輸出紅畫面訊號(010)。During the T3 period, the vertical sync signal Vsync transitions from a low potential "0" to a high potential "1", and the master device 110 outputs a red picture signal (010).
請一併參閱圖3，圖3是圖1所示的串列周邊介面裝置10的從裝置120之訊號時序圖。如下以該從裝置120接收黑畫面與紅畫面為例進行說明。Please refer to FIG. 3 together. FIG. 3 is a timing diagram of the slave device 120 of the serial peripheral interface device 10 shown in FIG. The black screen and the red screen are received by the slave device 120 as an example.
在T1時間段，該從裝置120接收黑畫面訊號(000)。During the T1 time period, the slave device 120 receives the black picture signal (000).
T2時間段為顯示黑畫面與紅畫面之間的間隙時間，在T2時間段開始時，該垂直同步訊號Vsnyc由高電位”1”躍變為低電位”0”，同時該從裝置120接收串列訊號Dsync。本發明中該從裝置120在顯示黑畫面與畫面的間隙之間傳輸串列訊號Dsync，因此不會干擾到畫面訊號。The T2 time period is a gap time between the black picture and the red picture. When the T2 time period starts, the vertical synchronization signal Vsnyc transitions from a high potential "1" to a low potential "0", and the slave device 120 receives the string. Column signal Dsync. In the present invention, the slave device 120 transmits the serial signal Dsync between the display of the black screen and the gap of the picture, so that the picture signal is not disturbed.
在T3時間段，該垂直同步訊號Vsync由低電位”0”躍變為高電位”1”,同時該從裝置120接收紅畫面訊號(010)。During the T3 period, the vertical sync signal Vsync transitions from a low potential of "0" to a high potential "1" while the slave device 120 receives a red picture signal (010).
本發明的串列周邊介面裝置及訊號傳輸方法中從裝置使用主裝置的水平同步訊號作為時鐘訊號解碼串列訊號，而不是主裝置與從裝置分別產生時鐘訊號用於編解碼，因此可避免主裝置之時鐘訊號與從裝置之時鐘訊號不同步而導致的串列訊號解碼錯誤。In the serial peripheral device device and the signal transmission method of the present invention, the slave device uses the horizontal sync signal of the master device as the clock signal to decode the serial signal, instead of the master device and the slave device respectively generating clock signals for encoding and decoding, thereby avoiding the main The serial signal decoding error caused by the clock signal of the device and the clock signal of the slave device are not synchronized.
如上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。As described above, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.
10‧‧‧串列周邊介面裝置10‧‧‧Sequence peripheral interface device
110‧‧‧主裝置110‧‧‧Main device
120‧‧‧從裝置120‧‧‧ slave device
111‧‧‧水平同步訊號輸出引腳111‧‧‧ horizontal sync signal output pin
113‧‧‧串列訊號輸出引腳113‧‧‧Serial signal output pin
121‧‧‧水平同步訊號輸入引腳121‧‧‧Horizontal sync signal input pin
123‧‧‧串列訊號輸入引腳123‧‧‧Serial signal input pin
Hsync‧‧‧水平同步訊號Hsync‧‧‧ horizontal sync signal
Vsync‧‧‧垂直同步訊號Vsync‧‧‧ vertical sync signal
Dsync‧‧‧串列訊號Dsync‧‧‧ serial signal
無no
10‧‧‧串列周邊介面裝置 10‧‧‧Sequence peripheral interface device
110‧‧‧主裝置 110‧‧‧Main device
120‧‧‧從裝置 120‧‧‧ slave device
111‧‧‧水平同步訊號輸出引腳 111‧‧‧ horizontal sync signal output pin
113‧‧‧串列訊號輸出引腳 113‧‧‧Serial signal output pin
121‧‧‧水平同步訊號輸入引腳 121‧‧‧Horizontal sync signal input pin
123‧‧‧串列訊號輸入引腳 123‧‧‧Serial signal input pin
Hsync‧‧‧水平同步訊號 Hsync‧‧‧ horizontal sync signal
Dsync‧‧‧串列訊號 Dsync‧‧‧ serial signal
Claims (10)
主裝置將資料訊號轉換為串列訊號；
主裝置輸出水平同步記號與串列訊號至從裝置；及
該從裝置使用該水平同步訊號作為時鐘訊號解碼該串列訊號。 A signal transmission method includes:
The main device converts the data signal into a serial signal;
The master device outputs a horizontal sync mark and a serial signal to the slave device; and the slave device decodes the serial signal using the horizontal sync signal as a clock signal.
The signal transmission method of claim 8, wherein the slave device decodes the serial signal as a clock signal to obtain a data signal and a vertical synchronization signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201130288A (en) * | 2009-06-29 | 2011-09-01 | Sony Corp | Image data transmitting apparatus, control method, and program |
| TW201346874A (en) * | 2012-05-14 | 2013-11-16 | Lg Display Co Ltd | Display device |
| TW201413679A (en) * | 2012-09-24 | 2014-04-01 | Samsung Electronics Co Ltd | Display driver integrated circuit, a display system having the same, and a display data processing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201130288A (en) * | 2009-06-29 | 2011-09-01 | Sony Corp | Image data transmitting apparatus, control method, and program |
| TW201346874A (en) * | 2012-05-14 | 2013-11-16 | Lg Display Co Ltd | Display device |
| TW201413679A (en) * | 2012-09-24 | 2014-04-01 | Samsung Electronics Co Ltd | Display driver integrated circuit, a display system having the same, and a display data processing method thereof |
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| TW201709715A (en) | 2017-03-01 |
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