TWI568197B - Encoding and decoding techniques using low-density parity check codes - Google Patents

Description

Encoding and decoding techniques using low-density parity check codes

Many electrical devices and systems exchange information with each other via transmission media such as metal conductors, fiber optic cables, and air. A poor or defective transmission medium can cause errors in this information. Exceeding the transmission capacity of the media (eg, transmission rate) can also cause errors. In some cases, the error can be corrected. Many conventional techniques use codes to verify their validity after receiving information. Some codes can also assist in correcting these errors. For example, a low density parity check (LDPC) code can be used for error correction. However, in some conventional techniques, the use of an LDPC code may involve complex write operations or may require the operation of a large number of circuit components. Therefore, an LDPC code may not be suitable for some devices or systems.

The embodiment according to FIG. 1 shows one embodiment of the present invention is configured by comprising a relative LDPC code encoding information message to form one code word u V _m one encoder 101, one block apparatus 100 of FIG. The device 100 can include an information source 110 for providing message information u and a memory region 120 for receiving the code word V _m from the encoder 101. Information source 110 can be provided by a device such as a memory controller or a processor. Memory area 120 may comprise a memory array for storing one code word V _m. Encoder 101 and memory region 120 may be included in the same device, such as a memory device or a memory controller. Device 100 can include a memory module, a system or device capable of transmitting or receiving information wirelessly, and/or other communication systems and devices having the ability to provide error correction in the transmission of information. FIG. 1 omits additional details of device 100 to focus on the embodiments set forth herein.

Encoder 101 relative to a self H- matrix 130 generates message information u in the form of one LDPC encoder implemented codeword V _m. The H-matrix 130 can be stored internally in the device 100 or external to the device 100. The H-matrix 130 may comprise an parity check matrix H of an LDPC code. As understood by those skilled in the art, an H-matrix (such as H-matrix 130) for transmitting one of the information codes can be constructed using various codes (such as a progressive edge-grown LDPC code construction, a Lied Solomon) (Reed Solomon) LDPC code construction, LDPC code construction based on Euclidian geometry, LDPC code construction based on Vandermonde matrix and cyclically arranged blocks, and various other LDPC constructs (eg, construction) . An H-matrix (such as H-matrix 130) can be generated by a computer.

1 shows a codeword V _m =[ pu ] of a systematic codeword for indicating that the codeword V _m can be combined with one of the parity information p and the message information u . The message information u can contain several information bits. The parity information p can contain several co-located bits. The codeword V _m =[ pu ] may be defined by the H-matrix 130, wherein the message bit of the message information u may correspond to a part of the row of the H-matrix 130 and the parity bit of the parity information p may correspond to the H- Another part of the trip to matrix 130. FIG 1 shows one example of a codeword V _m = [pu], where p parity information based positioned in a first position code word, followed by system information message u. The order can be reversed. Message-based information u may be positioned in the first code word position, followed by the Department of parity information p, so that the code word V _m = [up].

In the device 100, since the message information u is conventional, for a given H-matrix of one code (such as the H-matrix 130), the encoding operation performed by the encoder 101 involves based on the received message information u. And the established H-matrix generates the parity information p . Then, the encoder 101 can combine the received message information u with the generated parity information p to form a codeword V _m = [ pu ]. V _m decoded codeword to retrieve the original message information u can be based in a reverse order. For example, the codeword V _m may be a reverse order to be executed during the program to generate an encoded with information bits of p (e.g., step) to produce the decoded information. The same H-matrix used for encoding can then be used during decoding to generate the original message information u based on the decoded information. The description herein focuses on encoded to generate a codeword V _m = [pu] Based on the received information message u and one LDPC code is a matrix H- established, as described with reference to FIG. 2 to FIG. 7 in detail.

Figure 2 shows an example of an parity check matrix H of one of the LDPC codes. The matrix H is configured as columns and rows and has a size (n-k+m) x (n) corresponding to (n-k+m) columns and n rows. The parameter m corresponds to the number of related columns of the matrix H. The rank of a matrix is the number of associated columns of the array. Therefore, if the matrix H is a full rank matrix, the parameter m=0. If the matrix H is a matrix with insufficient rank (eg, non-full rank), the parameter m>0. The parameter n is the number of code bits in a codeword. The parameter k is the number of information bits in a codeword. Thus, in each column (each codeword) of matrix H, there are n total code bits formed by combining k information bits with one of n-k parity bits.

As shown in Figure 2, matrix H is an example of one binary matrix with only zero ("0") and 壹 ("1") elements. The LDPC code uses a parity check matrix H containing most zeros and a finite number of 壹. For the sake of simplicity, Figure 1 shows only some of the elements of the matrix H. Based on a parity check matrix H (such as matrix H in FIG. 1), one of the encoders (e.g., encoder 101 in FIG. 1) described herein can generate a parity associated with the message information. Information to generate a codeword that contains a combination of co-located information and message information.

3 is a flow diagram of one method 300 of encoding information based on one parity check matrix H of an LDPC code, in accordance with an embodiment of the present invention. The parity check matrix H used in method 300 may comprise a matrix H of one of the LDPC codes described above with reference to Figures 1 and 2.

In Figure 3, the method 300 may include check bits for matrix H from the same (e.g., FIG. 1, and the matrix H in FIG. 2) generates a first matrix (e.g., H _m) one of the activities 310. The first matrix can be generated such that it has a triangular submatrix on one of the upper left corners of the first matrix. Activity 310 may also include calculating a rank for generating a parity check matrix H of the first matrix.

If the total number of columns of the upper triangular submatrix is equal to the rank of the parity check matrix H, the method 300 can include an activity 320 to generate parity information for encoding the message information based at least in part on the first matrix. Method 320 can be stopped after activity 320 is performed.

If the total number of columns of the first upper triangular submatrix is less than the rank of the parity check matrix H, the method 300 may continue to perform an up-triangulation operation on the second sub-matrix of the first matrix by means of the activity 330 (eg, , forming a second matrix (eg, H _{m 2} ). Activity 340 of method 300 can generate co-located information for encoding message information based at least in part on the second matrix.

Some or all of the activities 310, 320, 330, and 340 of method 300 may be performed by a processor of an electronic unit, such as a computer. For example, activities 310, 320, and 330 can be performed by a computer. Some or all of the activities 310, 320, 330, and 340 of method 300 may also be performed by an encoder, such as encoder 101 of FIG. This encoder can be included in one A device (such as a processor, a memory controller, or a memory device). Method 300 can include one or more of the activities set forth below with reference to Figures 4-7.

4 shows a block structure of a matrix H _m generated from a parity check matrix H of an LDPC code in accordance with an embodiment of the present invention. The matrix H _m may be generated from a parity check matrix H of one of the LDPC codes (such as the matrix H in FIG. 1 or FIG. 2). One encoder set forth herein (e.g., the encoder 101 of FIG. 1) may receive the message and use the information to generate a matrix H _m information and parity of the received codeword of the message information.

Conventionally, a generator matrix G _m encoded message information. For example, a matrix H=[I _nk |P] can be generated from a matrix H, where I _nk is a recognition sub-matrix, and P is a sub-matrix of matrix G. Then, a matrix G from the matrix G _m can be produced, so that ^{_{G m = [P T | I}} k], where P ^T represents the transpose of sub-matrix P. A codeword = u * G _m can be generated, and the symbol "*" in this equation represents multiplication. Thus, in a conventional encoding, the generator matrix G _m used to encode the message information. However, conventional approaches can be complex and unsuitable for certain systems or devices. For example, a large number of circuit components may be required (e.g., "exclusive or" (XOR) gate) and to process and store information or both the generator matrix G _{m m} matrix H and the generator matrix G of the associated.

Set forth herein may be from the encoder matrix H _m direct codeword, without generating a matrix (such as a conventional generator matrix G _m). As set forth herein, is generated based on the matrix H _m of codeword based encoder may be less complex and may have a reduced number of components (e.g., "exclusive or" gate).

As shown in Figure 4 comprises a matrix H _m H _m located at respective portions of the sub-matrix of matrix T, A, B, E, C and D. For example, the sub-matrix T is located in the upper left corner portion of one of the matrices H _m . The sub-matrix B is located in the upper right corner portion of one of the matrices H _m . The sub-matrix A is positioned in an intermediate portion of the matrix H _m between the sub-matrix T and the sub-matrix B. The sub-matrix E is located in a lower left corner portion of the matrix H _m below the sub-matrix T. The sub-matrix D is positioned in a lower right corner portion of the matrix H _m . The sub-matrix C is located in an intermediate portion of the matrix H _m between the sub-matrix E and the sub-matrix D and below the sub-matrix A. The size of these sub-matrices is as follows.

T: (n-k-g) × (n-k-g).

A: (n-k-g) × g.

B: (n-k-g) × k.

C: g × g.

D: g × k.

E: g × (n-k-g).

The matrix H _m can be generated by performing a program called a greedy up-triangulation operation. This operation produces an upper triangular matrix (which is a sub-matrix T) in the upper left corner of the matrix H _m . This operation involves exchanging only the columns of the parity check matrix H, exchanging only its rows, or exchanging only its columns and rows. In this operation, arithmetic operations are not performed on the columns of the parity check matrix H (for example, no Gaussian erase operation).

The submatrix T has a triangular matrix of (nkg) columns and (nkg) rows of right angles. The submatrix T causes all 壹 in its diagonal elements and all zeros are below its diagonal elements. If the number of columns of sub-matrices T is equal to the rank R of the parity check matrix H, then the parameter g=0 in the matrix H _m such that (nk-g)=R, where g=0. Furthermore, if g=0, the sub-matrix A is eliminated and becomes part of the sub-matrix B, and the sub-matrices E, C, and D are eliminated and become part of the sub-matrix T and the sub-matrix B. In this case (nk=R), the matrix H _m =[T|B], where the sub-matrix T has a size (nk=R)×(nk=R) and the sub-matrix B has a size (nk=R) ×k.

When an encoder (such as in the FIG. 1 encoder 101) using the matrix H _m to produce a codeword V _m = [pu] (wherein u represents message information), the same bit of information (p) may be generated as follows (for g = 0). For the matrix H _m , one of the valid codewords V _m is one of the magnitudes nk of all zero vectors such that the equation H _m * V _m ^T =0 is satisfied. Since H _m = [T|B] and V _m = [ pu ], by replacing V _m ^T = [ pu ] ^T with the equation H _m * V _m ^{T =} 0, the following equation can be obtained.

Solving the above equation yields the following equation (1): T p =B u , so p =T ^-1 B u . (Equation 1)

An encoder (such as the 101 encoded FIG. 1) may be configured to generate a code word V _m of parity information p. Therefore, a parity check matrix H is established for one of the LDPC codes, and the matrix H _m shown in FIG. 4 can be generated. If the total number of columns of the sub-matrix T of the matrix H _m is equal to the rank R of the parity check matrix H, the encoder can be configured to generate the parity information p based on equation (1). Parity information with the message information can be combined to produce a received codeword u V _m = [pu]. Since set forth herein, one encoder may be equal to Equation (1) produce a codeword V _m with the condition rank R of bit check matrix H of based on the total number of series of H _m of the matrix sub-matrix T's, so that the encoder The matrix H _m (not the parity check matrix H) and T ^-1 may be stored (eg, stored in a memory) for encoding, since other values (eg, B and u ) may be from the matrix H. _m and obtained from the message information u . During the encoding, the encoder may access a memory to capture matrix T ^-1 H _m and the elements are stored based on Equation (1) to generate parity information and generating a codeword p V _m = [pu].

If the total number of columns of the sub-matrix T of the matrix H _m is less than the rank R of the parity check matrix H, additional operations may be performed on the matrix H _m of FIG. 4 to generate co-located information, as explained below with reference to FIGS. 5 and 6 .

As set forth above with reference to FIG. 4, may be exchanged only by the parity check matrix H of columns or rows or both generate a matrix H _m. Used to generate a matrix of H _m may also include generating a program (e.g., form) a recording track (e.g., a map). This trace traceable (e.g., maps) the position number of the column of parity check matrix H is generated during the matrix H _m or a line of the exchange has. Since the sub-matrix T of the matrix H _m is generated by exchanging the rows of the parity check matrix H, the trace record also contains one of the at least one row position number of the sub-matrix T and one of the at least one row of the parity check matrix H. A link between the numbers.

Tracking can be used to obtain the original message record information u during the decoding of codewords of V _m. For example, during decoding, an operation such as a de-interlacing operation can be performed. Such calculation may be based on a recording track (but in a reverse order) exchange line V _m of codeword to produce a codeword V (which is not based in a systematic form). A decoder can be used to decode the codeword V using the parity check matrix H to produce the original message information u .

During the triangulation operation over the sub-matrix T used to generate the matrix H _m , several rows of the parity check matrix H may be randomly selected to generate rows of the sub-matrices T. This random selection may increase the probability that the sub-matrix T has a size R x R (where the R is the rank of the parity check matrix H). When the sub-matrix T has a size R x R, the total number of columns of the sub-matrix T is equal to R. If the size of the sub-matrix T is R x R, the matrix H _m may have a full triangular structure, for example, H _m = [T|B], wherein the parameter in FIG. 4 is equal to zero (for example, nk=R). As explained above with reference to Figure 4, Equation 1 can be used in an encoder where the sub-matrix T has a size R x R.

In some cases, depending on the value of the elements of the parity check matrix H, the up-triangulation operation may fail to produce a sub-matrix T having a size R x R (eg, the total number of columns of sub-matrices T is less than R). In this case, the matrix H _m but not having full triangular structure having a substantially triangular configuration (shown in FIG. 4), wherein the system parameter g is not zero. In this case, equation (1) is not suitable for generating co-located information. However, the matrix H _m to perform additional operation to generate a matrix H _{m. 1} (FIG. 5), and the matrix H _{m 2} (FIG. 6). The parity information can be generated based on the matrix H _{m 2} .

5 and 6 are graphs showing the matrix H _m arising from the embodiment of FIG. 4 of the matrix H _m H _{m 1} and ₂ of block structure in accordance with one embodiment of the present invention. H _m can be used FIG. 6 of the matrix ₂ generates codewords V _m, as set forth above in the matrix of FIG. 5 explained later of the ₁ H _m.

As shown in FIG. 5, the matrix H _{m 1} has the same block structure as the block structure of the matrix H _m of FIG. However, the values of the elements of the sub-matrices E, C _m1 and D _m1 of the matrix H _{m 1} of FIG. 5 are different from the values of the elements of the corresponding sub-matrices E, C and D of the matrix H _m of FIG. 4 . As shown in FIG. 5, all elements of the sub-matrix E are zero ("0"). Compared to the corresponding sub-matrices C and D of FIG. 4, the sub-matrices _Cm1 and _Dm1 may be less sparse (more dense) due to the operation performed on the sub-matrix E to make all its elements zero. Such operations may include arithmetic operations, such as Gaussian elimination operations. As part of the same column of the row sub-matrix H _m E, C, and D lines of the matrix, so the calculation performed by the column matrix H of _m sub-matrices E are also modified sub-matrix H of _m rows C and D of the matrix. Therefore, after all the elements of the sub-matrix E become zero, the sub-matrices C and D in FIG. 4 become the sub-matrices C _m1 and D _{m1 in} FIG.

6 shows a block structure of a matrix H _{m 2} generated from a matrix H _{m 1} in accordance with an embodiment of the present invention. From the matrix H _{m 2} , calculations can be performed to obtain equations for generating parity information for the codeword V _m . Illustrated in Figure 6, has the same matrix H _{m 2} of the matrix of the matrix of FIG. 5 H _m block structure of block structure. However, the matrix H _{m 2} may contain a number of columns r with all zero elements. The particular size of the matrix H _{m 1} and the particular number of rows and the sub-matrices of the matrix H _{m 1} shown in Figure 6 are for illustrative purposes only to help focus on the description herein.

As explained above with reference to Figure 4, an up-triangulation operation can be performed on the parity check matrix H to produce an upper triangular sub-matrix T (as shown in Figure 6). In FIG 5 and FIG 6, the sub-matrix C _{m 1} may perform an additional operation to make the upper triangular sub-matrix of C _m as many as possible with _a diagonal of one ( "1"). The extra up-triangulation operation may not cause all elements in the diagonal of the sub-matrix C _{m 1 to} have a value 壹. However, the additional up-triangulation operation may result in at least one of the diagonals of the sub-matrices C _{m 1} having a value 壹. For example, as shown in FIG. 6, an additional calculation based on triangulation can lead to the diagonal sub-matrix in C _{m 1} has a value of three fifths One element. The element x in the submatrix C _{m 1} can be either 壹 or zero. When no extra turns can be formed in the diagonal of the sub-matrix C _{m 1} , the additional up-triangulation operation can be stopped, such as in the case shown in FIG. Additional upper triangularization operation can cause one of Liezi matrix D _m in the bottom of _one or more has a value of zero. An additional up-triangulation operation produces a matrix H _{m 2} . As shown in FIG. 6, the matrix H _{m 2} having a plurality of columns in which all elements have a zero of r. Figure 6 shows r = 2 as an example. The value of r can vary.

The r columns (having elements with all zeros) correspond to the associated columns in the parity check matrix H. Therefore, the r columns can be removed from the matrix H _{m 2} . Therefore, after removing the r columns, the matrix H _{m 2} may have fewer columns (less r columns) than the matrix H _{m 1} .

Additional upper triangular matrix C _m of the sub-operation ₁ may comprise performing the exchange column, the exchange line and arithmetic operations (e.g., Gaussian elimination operation) of any combination thereof. As a comparison, the triangulation operation performed on the parity check matrix H to produce the triangular submatrix T (Fig. 4) may not include arithmetic operations (e.g., only swapping columns and rows).

The additional up-triangulation operations performed on the sub-matrix _Cm1 may also modify the columns and rows of the sub-matrices A, B, _Cm1, and _Dm1 . Therefore, after the additional up-triangulation operation, the sub-matrices A, B, C _m1 and D _{m1 of the} matrix H _{m 1} (Fig. 5) become the sub-matrices A _m2 , B _m2 , C _m2 and D _m2 of the matrix H _{m 2} of Fig. 6. .

When an encoder (such as encoder 101 in Fig. 1) uses matrix H _m2 to generate codeword V _m = [ pu ] (where u represents message information), the parity information p can be generated as follows.

As described above with reference to FIGS. 4, 5 and 6 set forth, H _m2 based matrix resulting from a matrix H _{m 1,} the matrix H _{m 1} and line generated from the matrix H _m (FIG. 4). Since the matrix H _m has an approximate triangular structure (where the parameter g is not zero), the parity information p of the systematic codeword of V _m =[ p _m u ] can be regarded as consisting of two parts: one (nkg) bit The homotopic portion p ₁ and the g-bit long isotopic portion p _{2 of the} meta-length. Therefore, p = [ p ₁ p ₂ ], so V _m = [ pu ] = [ p ₁ p ₂ u ].

For the matrix H _m2 , one of the valid codewords V _m is one of the magnitudes nk of all zero vectors such that the equation H _m2 * V _m ^{T =} 0 is satisfied.

Since V _m = [ p ₁ p ₂ u ], V _m ^T = [ p ₁ p ₂ u ] ^T . As shown in Figure 6, By replacing V _m ^T = [ p ₁ p ₂ u ] ^T with the equation H _m2 * V _m ^{T =} 0, the following equation can be obtained.

Solving the above equation yields equations (2) and (3) below.

C _{m 2} p ₂ = D _{m 2} u . Therefore, p ₂ =( C _{m 2} ^-1 D _{m 2} ) (Equation 2)

Tp ₁ = (A _{m 2} p ₂ + B _{m 2} u ). Therefore, p ₁ = T ^-1 (A _{m 2} p ₂ + B _{m 2} u ). Substituting p ₂ =( C _{m 2} ^-1 D _{m 2} ) from equation (2) into the equation p ₁ =T ^-1 (A _{m 2} p ₂ +B _{m 2} u ) yields equation (3).

p ₁ =T ^-1 (A( C _{m 2} ^-1 D _{m 2} )+B _{m 2} u ) (Equation 3)

Based on equations (2) and Equation (3), an encoder (such as the encoder of FIG. 1101) may be configured to generate a code word V _m of parity information p. Therefore, by setting the parity check matrix H for one of the LDPC codes, the matrix H _m2 shown in FIG. 6 can be generated. Then, based on the matrix H _m2 , equations (2) and (3) can be calculated to produce parity information p ₁ and p ₂ . The encoder can combine the parity information p ₁ and p ₂ with the received message information u to generate the codeword V _m =[ p ₁ p ₂ u ].

As set forth above, and for generating a matrix H _m1 H _m2 of the program may also include generating (e.g., form) a recording track (e.g., a map). This tracking record tracks the position number of the column or row that has been exchanged during the generation of the matrices H _m1 and H _m2 by the parity check matrix H. For example, the trace record can track the parity check matrix H that has been swapped during the operation to make all elements of the sub-matrix E zero and the triangulation performed on the sub-matrix matrix C _{m 1} Or the location number of the line. This tracking record may also link (eg, map) the position number of the column or row that has been exchanged during the generation of the matrices H _m1 and H _m2 by the parity check matrix H. Therefore, this tracking record also contains a link between the position number of the row of the matrix H _m2 and the position number of the row of the parity check matrix H.

The combination of the tracking record generated during the generation of the matrices H _m1 and H _m2 (Figs. 5 and 6) and the tracking record generated during the generation of the matrix H _m (Fig. 4) may be during the decoding of the codeword V _m Used with the parity check matrix H to obtain the original message information u . Matrix H _m, H _m1 and of generating H _m2 and associated activities (such as, trace Records generated equations 1, 2 and 3 of) can be tied by an electronic unit (such as a computer) execute. For example, the electronic unit can receive input information associated with the parity check matrix H. Then, based on the input information, the electronic unit may generate output information, such as a matrix H _m, H _m1 and H _m2, and an equation recording track 1, 2 and 3.

As set forth above, one encoder may be based on equations (2) and (3) V _m generated codeword set forth herein. The multiplication of the parameters in equations (2) and (3) can be obtained by an operation such as "mutual exclusion" or addition. Therefore, the encoder can store only the matrix H _m2 (instead of the parity check matrix H) and the product C _{m 2} ^-1 D _{m 2} , because other values (for example, A, B, and u ) can be derived from the matrix H _{m2 .} And obtained from the message information u . Further calculations can provide D _m =ET ^-1 B. Since the line D _m can be obtained from the matrix H _m1, D _{m 2} can be obtained a modified version of one of the lines and line D _{m 2} D _m, D _{m 2} and therefore need not be stored for an encoding operation. Therefore, another option is that the encoder can store (e.g., store in a memory) only the matrices H _m2 and C _{m 2} ^-1 and T ^-1 (without storing D _{m 2} ). During encoding, the encoder can access a memory to extract elements of the matrix H _m2 and C _{m 2} ^-1 and T ^-1 to generate co-located p ₁ and p ₂ based on equations (2) and (3) and generate code The word Vm = [ p ₁ p ₂ u ].

As a comparison, a conventional encoding store generator matrix G _m of the sub-matrix P. The sub-matrix P has a size k × (nk). In the encoding set forth herein, each of the sub-matrices C _{m 2} ^-1 and D _{m 2} and T ^-1 of the matrix H _m2 has a size smaller than one of the sizes of the sub-matrices P.

FIG. 7 shows a block diagram of a system 700 including an encoder 701 in accordance with an embodiment of the present invention. Encoder 701 may correspond to encoder 101 of FIG. For example, the encoder 701 relative to a self H- matrix 730 generates message information u in the form of one LDPC encoder implemented codeword V _m. The H-matrix 730 can be stored internally in system 700 or external to system 700.

System 700 can be a memory system having a memory device for storing information. For example, system 700 can include a device 710 that can include a memory controller for controlling transmission to and from one of device 720, and device 720 can include a memory device.

As shown in FIG. 7, the information transmitted to the device 720 may comprise a code corresponding to the above set forth with reference to FIG. 1 to 6 of the word of the code word V _m V _m. Device 720 can include a memory cell 721. Device 720 may be self-device during a write operation 710 received codeword and the codeword V _m V _m is stored in the memory cell 721. 720 may also include means for outputting codewords V _m to 710 means reads one operation. The memory cell 721 can comprise a volatile memory cell, a non-volatile memory cell, or both. Examples of volatile memory cells include random access memory (RAM) cells. Examples of non-volatile memory cells include flash memory cells, resistive random access memory (RRAM) cells, and phase change memory cells, as well as other types of non-volatile memory cells.

System 700 can store the parameters associated with the encoding operation in one or both of memory 725 of device 710 and memory cell 721 of device 720. These parameters may include tracking records, such as the tracking records set forth above with reference to Figures 4-6. One of decoder device 710 may use the stored parameters 702 and 730 H- decoded codeword matrices V _m (received from the device 720) to obtain the original information message u.

System 700 can also include a device 740, which can include a processor (such as a general purpose processor) or a special application integrated circuit (ASIC). In one of the operations of device 720 (e.g., a write operation), device 710 can receive message information u at its input coupled to interface 751. Device 710 may generate a codeword having a V _m of the message information and the code word u V _m provides to its output coupled to the interface 752. In another operation of the apparatus 720 (e.g., a read operation), the device 710 may receive via the interface device 752 from the output 720 of the code word V _m, V _m decoded code word to obtain the information message u, and then post the information u Transmitted to device 740 via interface 751. The interface 751 can include a wired interface or a wireless interface or a combination of the two. The interface 752 can include a wired interface or a wireless interface or a combination of the two. Each of the interfaces 751 and 752 can include a two-way interface. For example, interface 752 may comprise bidirectional conductors (e.g., a serial bus or a parallel bus) to transmit the same bi-directional V _m codewords on conductor 720 to the device from the device 720 and sends the codeword V _m.

System 700 can also include a storage device 760. A portion of the storage device 760 or the entire memory 725 can be external to the system 700. The storage device 760 can comprise any form of computer readable storage medium, including by one or more processors (eg, a computer or a wireless communication device) or by a device All or a portion of the instruction code executable operations that result with the herein described embodiments 710 or 740 V _m of the associated word in the sum. For example, storage device 760 can include instructions for generating matrices (such as matrices H _m , H _{m 1 ,} and H _{m 2} ), and calculating equations (such as equations (1), (2), and (3)). And generating the tracking records (eg, column and row exchanges) set forth above with reference to Figures 1 through 6. A processor executing instructions stored in storage device 760 can be included in a system external to system 700. For example, the processor can be part of a computer that is different from one of the systems 700.

Alternatively, or in addition to storage device 760, an electronic unit 770 can also operate to: generate matrices (such as matrices H _m , H _{m 1} and H _{m 2} ), calculate equations (such as equations (1), (2), and (3)) and generating the tracking records (e.g., column and row exchanges) set forth above with reference to Figures 1 through 6. For example, electronic unit 770 can receive input information associated with parity check matrix H. Then, based on the input information, the electronic unit 770 may generate output information, such as a matrix H _m, H _m1 and H _m2, and an equation recording track 1, 2 and 3. At least some of the information generated by the electronic unit 770 (eg, included in the matrices H _m , H _{m 1} and H _{m 2} , equations (1), (2), and (3) and information in the tracking record at least some of the information) used by the encoder 701 to generate a code word used in the 702 V _m and V _m codeword decoded by a decoder.

All of the portions of system 700 (e.g., devices 710 and 720) or system 700 can be included in the same semiconductor wafer, in the same integrated circuit package, or in the same circuit board.

The illustration of a device (e.g., device 100) and a system (e.g., system 700) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a device or system that may utilize the structures set forth herein. One of all the components and features is fully explained.

Any of the components set forth above with reference to Figures 1 through 7 can be implemented in a number of ways, including simulation via software. Accordingly, the devices (eg, device 100) and systems (eg, system 700) described above may be fully characterized herein as "several modules" (or "modules"). Depending on the architecture of the device (eg, device 100) and depending on the particular implementation of various embodiments, such modules may include hardware circuitry, single and/or multiprocessor circuitry, memory circuitry, software stylization Modules and objects and/or firmware and combinations thereof. For example, the modules can be included in a system operation analog package, such as a software electrical signal analog package, a power usage and distribution analog package, a capacitor inductance analog package, a power/heat dissipation analog package, and a The signal transmission receives a combination of analog packages and/or software and hardware for operating or simulating the operation of various possible embodiments.

Apparatus and systems of various embodiments may be included or included in high speed computers, communication and signal processing circuits, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message switchers, and multiple layers In the electronic circuit of the special application module of the multi-chip module. Such devices and systems may further be included as sub-components in various electronic systems such as televisions, cellular phones, personal computers (eg, laptops, desktops, handheld computers, tablets, etc.) ), workstations, radios, video players, audio players (eg, MP3 (Animation Experts Group, Audio Layer 3) players), vehicles, medical devices (eg, heart monitors, blood pressure monitors, etc.), video conversion And other devices.

The embodiments set forth above with reference to Figures 1 through 7 include apparatus and methods for encoding message information. The apparatus and method can include generating a first matrix having one of the upper triangular sub-matrices using a parity check matrix of one of the low density parity check (LDPC) codes. If the total number of columns of the upper triangular sub-matrix is equal to the rank of the parity check matrix, the parity information used to encode the information of the message may be generated based on the first matrix. If the total number of columns of the upper triangular submatrix is less than the rank of the parity check matrix, a triangulation operation may be performed in one of the second submatrix of the second portion of the first matrix to generate A second matrix. The parity information used to encode the information of the message may be generated based on the second matrix. The encodings described herein can combine co-located information and message information to form a codeword. The decoding of the code words can also be performed. For example, a program (eg, a step) performed during encoding to generate co-located information can be performed in reverse order to produce decoded information. The same H-matrix used for encoding can then be used to generate the original message during decoding. News. The invention sets forth additional embodiments incorporating additional equipment and methods.

The above description and the drawings are intended to illustrate the embodiments of the invention Other embodiments may incorporate structural, logical, electrical, program, and other changes. The examples represent only possible variations. Portions and features of certain embodiments may be included in or substituted for parts and features of other embodiments. Many other embodiments will be apparent to those skilled in the art upon reading and understanding.

0‧‧‧submatrix

100‧‧‧ Equipment

101‧‧‧Encoder

110‧‧‧Information source

120‧‧‧ memory area

130‧‧‧H-matrix

700‧‧‧ system

701‧‧‧Encoder

702‧‧‧Decoder

710‧‧‧ device

720‧‧‧ device

721‧‧‧ memory cells

725‧‧‧ memory

730‧‧‧H-matrix

740‧‧‧ device

751‧‧‧ interface

752‧‧‧ interface

760‧‧‧Storage device

770‧‧‧Electronic unit

A‧‧‧submatrix

A _m2 ‧‧‧submatrix

B‧‧‧Submatrix

B _m2 ‧‧‧submatrix

C‧‧‧Submatrix

C _m1 ‧‧‧submatrix

C _m2 ‧‧‧submatrix

D‧‧‧Submatrix

D _m1 ‧‧‧submatrix

D _m2 ‧‧‧submatrix

E‧‧‧submatrix

H‧‧‧ parity check matrix/matrix

H _m ‧‧‧ matrix

H _m1 ‧‧‧ matrix

H _m2 ‧‧‧ matrix

T‧‧‧Submatrix

u‧‧‧Original message information

V _m ‧‧‧ code words

1 shows a block diagram of an apparatus comprising one of an encoder configured to encode message information relative to an LDPC code to form a codeword, in accordance with an embodiment of the present invention.

2 shows an example of one of the parity check matrices H of one of the LDPC codes in accordance with an embodiment of the present invention.

3 is a flow chart of one of the methods for encoding information based on one parity check matrix H of an LDPC code according to an embodiment of the present invention.

4 shows a block structure of a matrix generated from one parity check matrix H of an LDPC code in accordance with an embodiment of the present invention.

5 and 6 show the block structure of a matrix generated from the matrix of FIG. 4 in accordance with an embodiment of the present invention.

7 shows a block diagram of a system including an encoder in accordance with an embodiment of the present invention.

700‧‧‧ system

701‧‧‧Encoder

702‧‧‧Decoder

710‧‧‧ device

720‧‧‧ device

721‧‧‧ memory cells

725‧‧‧ memory

730‧‧‧H-matrix

740‧‧‧ device

751‧‧‧ interface

752‧‧‧ interface

760‧‧‧Storage device

770‧‧‧Electronic unit

u‧‧‧Original message information

V _m ‧‧‧ code words

Claims (35)

An encoding method, comprising: receiving message information; generating a portion of the parity information based on one of the first equations calculated according to at least one of the first sub-matrices in one of the first portions of a matrix, the first sub-matrix comprising a value of one diagonal element of "1"; generating an additional portion of the parity information based on one of the second equations calculated from at least one of the triangular sub-matrices of the second portion of the matrix; and based at least in part on The portion of the parity information and the additional portion of the parity information generates codewords wherein the first equation comprises p ₂ =(C _m2 ^-1 D _m2 ) u , and the second equation comprises p ₁ =T ^-1 (A _M2 p ₂ +B _m2 u ), where p ₁ and p ₂ represent the portion of the isomorphic information and the additional portion, C _m2 represents the first sub-matrix, T represents the triangular sub-matrix, and A _m2 , B _m2 and D _m2 represents other sub-matrices of the matrix, the matrix has a block structure An encoding method, comprising: receiving message information; generating a portion of the parity information based on one of the first equations calculated according to at least one of the first sub-matrices in one of the first portions of a matrix, the first sub-matrix comprising a value of one diagonal element of "1"; generating an additional portion of the parity information based on a second equation calculated from at least one of the triangular sub-matrices in the second portion of the matrix; and Generating codewords based at least in part on the portion of the co-located information and the additional portion of the co-located information, wherein the codewords comprise the portion of the co-located information, the additional portion of the co-located information, and one of the message information . An encoding method, comprising: generating a first matrix from a parity check matrix of a low density parity check code, the first matrix having a triangular submatrix in a first portion of the first matrix; And the total number of columns of the triangular sub-matrices is equal to one of the ranks of the parity check matrix, and the parity information used to encode the information of the information is generated based at least in part on the first matrix; and if the first triangular sub-matrix is And the total number is less than the rank of the parity check matrix, and performing a triangulation operation on a second sub-matrix of the second portion of the first matrix to generate a second matrix, and based at least in part on the The second matrix generates co-located information for encoding the information of the message. The method of claim 3, wherein the co-located information generated based on the first matrix to encode the message information is based on a program p = T ^-1 (B u ), where p represents the co-located information, T ^{- 1} indicates that one of the triangular sub-matrices is inverted, B represents one of the third sub-matrices of the first matrix, and u represents message information. The method of claim 3, wherein the co-located information generated based on the second matrix to encode the message information is based on a program p ₂ =(C _m2 ^-1 D _m2 ) u , wherein p ₂ represents the co-located In one part of the information, C _m2 ^-1 indicates that one of the first sub-matrices in the second matrix is inverted, D _m2 represents one of the second sub-matrices in the second matrix, and u represents the message information. The method of claim 5, wherein the co-located information generated to encode the message information based at least in part on the second matrix is further based on a second equation p ₁ =T ^-1 (A _m2 p ₂ +B _m2 u ) Wherein p ₁ represents an additional portion of the parity information, T ^-1 represents one of the triangular sub-matrices, A _m2 represents a third sub-matrix in the second matrix, and B _m2 represents one of the second matrices The fourth submatrix. The method of claim 3, wherein generating the first matrix comprises randomly selecting a plurality of rows among the plurality of rows of the parity check matrix to generate the triangular submatrix. The method of claim 7, wherein performing the triangulation operation on the second sub-matrix comprises performing an arithmetic operation on at least one column of the second sub-matrix. The method of claim 7, further comprising: generating a record linking a location number of at least one of the at least one row of the triangular submatrix and a location number of at least one of the parity check matrix. The method of claim 3, wherein generating the first matrix comprises performing at least one of: exchanging only the column of the parity check matrix, exchanging only the row of the parity check matrix, and exchanging only the parity check matrix The list and the line. The method of claim 3, wherein generating the first matrix comprises performing an arithmetic operation on the columns of the parity check matrix. The method of claim 3, wherein the parity check matrix is a rank under-matrix. The method of claim 3, wherein the triangular submatrix is an upper triangular submatrix. An encoding method comprising: performing a first triangulation operation on a parity check matrix of a low density parity check code to generate a first matrix, the first matrix having a first portion of the first matrix a triangular submatrix having a total number of columns smaller than one of the ranks of the parity check matrix; performing a second triangulation operation on at least a portion of one of the second matrices in the second portion of the first matrix So that at least one column of the first matrix includes all zero elements; removing the at least one column of the first matrix containing all zero elements to generate a second matrix, wherein performing the first triangulation, performing the second Triangulating and removing at least one of the at least one column of the first matrix is performed by an electronic unit; and calculating at least one equation to generate at least a portion of the parity information based at least in part on the second matrix. The method of claim 14, wherein the first matrix comprises a block structure Sub-matrices T, A, B, C _m1 , D _m1 and 0, where T represents the triangular sub-matrix and C _m1 represents the sub-matrix in the second portion of the first matrix. The method of claim 15, wherein the second matrix is configured as a block structure , wherein the sub-matrices A _m2 , B _m2 , C _{m2 ,} and D _m2 are respectively sub-matrices A of the first matrix generated by the triangulation operation performed on the sub-matrix in the second portion of the first matrix, Modified versions of B, C _m1 and D _m1 . The method of claim 16, wherein the forming the at least one equation comprises: forming a first equation p ₂ = (C _m2 ^-1 D _m2 ) u , wherein p ₂ represents a portion of the parity information, and u represents the message information; And forming a second equation p ₁ =T ^-1 (A _m2 p ₂ +B _m2 u ), where p ₁ represents another part of the isomorphic information. The method of claim 14, wherein performing the first triangulation operation comprises randomly selecting a plurality of rows among the plurality of rows of the parity check matrix to form at least a portion of the rows of the triangular submatrix using the selected rows. The method of claim 18, wherein performing the second triangulation operation comprises performing an arithmetic operation on at least one column of the sub-matrix in the second portion of the first matrix. The method of claim 14, wherein the triangular submatrix is an upper triangular submatrix. The method of claim 20, wherein performing the second triangulation operation comprises performing an up-triangulation operation. The method of claim 14, further comprising: generating a record that links a location number of at least a portion of the first matrix, at least a portion of the second matrix, and the parity check At least part of the matrix. An encoding method includes: generating a matrix from a parity check matrix of a low density parity check code, the parity check matrix having a size (n-k+m)×n and a rank R, wherein the R system Less than (n-k+m), the matrix has a size R×n and has sub-matrices T and B configured as a block structure [TB] having a size R×(nR), wherein the sub-matrix T a triangular submatrix having a size R×R; and at least in part based on one of the triangular submatrices being inverted to form a program to generate co-located information, wherein generating a matrix and forming at least one of the equations is performed by an electron Unit execution. The method of claim 23, wherein the equation comprises p = T ^-1 (B u ), where u represents message information and p represents co-located information associated with the message information. The method of claim 23, wherein generating the matrix comprises randomly selecting a row among the plurality of rows of the parity check matrix, and exchanging one of the selected row positions and one of the plurality of rows of the plurality of rows to A row of the sub-matrix T is generated such that the sub-matrix T contains the selected row. The method of claim 23, further comprising: generating a record that tracks a location number of the selected row relative to a location number of one of the parity check matrices. An encoding device includes: an input for receiving message information; and a module for generating codewords having the message information and parity information, the module being configured to be based on a matrix One of the first equations calculated by at least one of the first sub-matrices in a first portion produces a portion of the isomorphic information, the first sub-matrix comprising a diagonal element having a value of "1", the mode The group is also configured to generate an additional portion of the parity information based on one of the second equations calculated from at least one of the triangular sub-matrices of the second portion of the matrix; and an output for providing the codewords Wherein the first equation comprises p ₂ =(C _m2 ^-1 D _m2 ) u , the second equation comprises p ₁ =T ^-1 (A _m2 p ₂ +B _m2 u ), wherein p ₁ and p ₂ represent the For the portions of the parity information, C _m2 represents the first sub-matrix in the first portion of a matrix, T ^-1 represents one of the triangular sub-matrices inverted, and A _m2 , B _m2 and D _m2 represent the other matrix Submatrix, the matrix has a block structure . An encoding device includes: an input for receiving message information; and a module for generating codewords having the message information and parity information, the module being configured to be based on a matrix One of the first equations calculated by at least one of the first sub-matrices in a first portion produces a portion of the isomorphic information, the first sub-matrix comprising a diagonal element having a value of "1", the mode The group is also configured to generate an additional portion of the parity information based on one of the second equations calculated from at least one of the triangular sub-matrices of the second portion of the matrix; and an output for providing the codewords And wherein the module is configured to store the inverted elements of the triangular sub-matrix and the inverted elements of the first sub-matrix in the first portion of a matrix. An encoding device includes: an input for receiving message information; and a module for generating codewords having the message information and parity information, the module being configured to be based on a matrix One of the first equations calculated by at least one of the first sub-matrices in a first portion produces a portion of the isomorphic information, the first sub-matrix comprising a diagonal element having a value of "1", the mode The group is also configured to generate an additional portion of the parity information based on one of the second equations calculated from at least one of the triangular sub-matrices of the second portion of the matrix; and an output for providing the codewords The module is configured to store elements of a parity check matrix of a low density parity check code, and wherein the matrix is generated from the parity check matrix. The device of claim 29, wherein the module is configured to store a record that links at least a portion of the row number of the matrix to at least a portion of the row number of the parity check matrix. An encoding device includes: an input for receiving message information; and a module for generating codewords having the message information and parity information, the module being configured to be based on a matrix One of the first equations calculated by at least one of the first sub-matrices in a first portion produces a portion of the isomorphic information, the first sub-matrix comprising a diagonal element having a value of "1", the mode The group is also configured to generate an additional portion of the parity information based on a second equation calculated from at least one of the triangular sub-matrices in the second portion of the matrix; and An output for providing the codewords, wherein the module includes a memory device having memory cells for storing the codewords. A computer readable storage medium comprising instructions for, when implemented by one or more processors, to generate a first matrix from a parity check matrix of a low density parity check code, the first matrix Having a triangular submatrix in a first portion of the first matrix; if the total number of columns of the triangular submatrix is equal to the rank of the parity check matrix, based at least in part on the first matrix generation Coordinate information encoding the message information; and if the total number of columns of the triangular submatrix is less than the rank of the parity check matrix, performing one of the second submatrix of the second portion of the first matrix Triangulation operations to generate a second matrix, and based on the second matrix, generate parity information for encoding the message information. The computer readable storage medium of claim 32, wherein the operation to generate the first matrix comprises randomly selecting a plurality of rows among the plurality of rows of the parity check matrix to generate the triangular submatrix. The computer readable storage medium of claim 32, wherein the operation of performing a triangulation operation on the second sub-matrix comprises performing an arithmetic operation on at least one of the at least one second portion of the first matrix. The computer readable storage medium of claim 34, wherein the operations further comprise: generating an operation of a record relative to the parity check A position number of at least one of the rows of the matrix tracks a position number of at least one of the rows of the triangular submatrix.