TWI566427B - Light-emitting device and manufacturing method thereof - Google Patents

Light-emitting device and manufacturing method thereof Download PDF

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TWI566427B
TWI566427B TW104142599A TW104142599A TWI566427B TW I566427 B TWI566427 B TW I566427B TW 104142599 A TW104142599 A TW 104142599A TW 104142599 A TW104142599 A TW 104142599A TW I566427 B TWI566427 B TW I566427B
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substrate
semiconductor stacked
semiconductor
stacked block
light
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TW104142599A
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TW201611323A (en
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黃建富
詹燿寧
徐子傑
陳怡名
邱新智
呂志強
許嘉良
張峻賢
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晶元光電股份有限公司
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發光元件及其製造方法Light-emitting element and method of manufacturing same

本發明係關於一種發光元件及其製造方法;特別是關於一種增加半導體疊層的利用之發光元件及其製造方法。 The present invention relates to a light-emitting element and a method of fabricating the same, and more particularly to a light-emitting element for increasing the utilization of a semiconductor laminate and a method of fabricating the same.

發光二極體(Light-Emitting Diode;LED)具有耗能低、操作壽命長、防震、體積小、反應速度快以及輸出的光波長穩定等特性,因此適用於各種照明用途。如圖1所示,目前發光二極體晶片之製作,係在一基板101上形成發光疊層(圖未示),再形成切割道103v,103h而分割出複數之發光二極體晶片102。然而目前複數之發光二極體晶片102之分割大多係以雷射光切割,而受限於雷射光光束之尺寸(beam size)以及切割時易形成副產物(byproduct)造成漏電情形,切割道103v,103h之寬度D在設計上均至少必須維持20μm以上。若可節省此切割道103v,103h之面積,大約可增加25%的發光疊層面積。 Light-Emitting Diode (LED) has characteristics such as low energy consumption, long operating life, shock resistance, small size, fast response speed, and stable wavelength of output light, so it is suitable for various lighting applications. As shown in FIG. 1, the current LED chip is formed by forming a light-emitting layer (not shown) on a substrate 101, and forming dicing streets 103v, 103h to divide a plurality of light-emitting diode chips 102. However, at present, the division of the plurality of LED chips 102 is mostly laser light cutting, and is limited by the beam size of the laser beam and the leakage of the byproduct during the cutting, the cutting channel 103v, The width D of 103h must be designed to maintain at least 20 μm or more. If the area of the dicing streets 103v, 103h can be saved, the area of the illuminating laminate can be increased by about 25%.

本發明係揭露一種發光元件之製造方法,包括:提供一第一基板及複數個半導體疊層塊於該第一基板上,各該複數個半導體疊層塊包括一第一電性半導體層、一發光層位於該第一電性半導體層之上、以及一第二電性半導體層位於該發光層之上,其中該第一基板上更包括一分隔道分隔兩相鄰之半導體疊層塊且該分隔道具有一寬度小於10μm;實行一第一分離步驟,包括:提供一第二基板,包括一第一電極;實行一第一接合步驟,包括對位接合該複數之半導體疊層塊中之一第一半導體疊層塊與該第二基板,以使該第一半導體疊層塊與該第一電極對位連接並形成電性連接;以及分離該第一半導體疊層塊與該第一基板,且該第一基板存留有該複數之半導體疊層塊中之一第二半導體疊層塊。 The present invention discloses a method for fabricating a light-emitting device, comprising: providing a first substrate and a plurality of semiconductor stacked blocks on the first substrate, each of the plurality of semiconductor stacked blocks including a first electrical semiconductor layer, The light emitting layer is disposed on the first electrical semiconductor layer, and a second electrical semiconductor layer is disposed on the light emitting layer, wherein the first substrate further includes a dividing channel separating the two adjacent semiconductor stacked blocks and the Separating the props having a width of less than 10 μm; performing a first separating step comprising: providing a second substrate comprising a first electrode; performing a first bonding step comprising aligning one of the plurality of semiconductor stacked blocks a semiconductor stacked block and the second substrate such that the first semiconductor stacked block is aligned and electrically connected to the first electrode; and the first semiconductor stacked block and the first substrate are separated, and The first substrate houses a second semiconductor stacked block of the plurality of semiconductor stacked blocks.

本發明係揭露一種發光元件之製造方法,包括:提供一第一基板及複數個半導體疊層塊於該第一基板上,各該複數個半導體疊層塊包括一第一電性半導體層、一發光層位於該第一電性半導體層之上、以及一第二電性半導體層位於該發光層之上,其中該第一基板上更包括一分隔道分隔兩相鄰之半導體疊層塊且該分隔道具有一寬度小於10μm;實行一第一分離步驟,包括:提供一第二基板;實行一第一接合步驟,包括接合該複數之半導體疊層塊中之一第一半導體疊層塊與該第二基板;以及分離該第一半導體疊層塊與該第一基板,且該第一基板存留有該複數之半導體疊層塊中之一第二半導體疊層塊;以及實施一第二接合步驟包括對位接合該第一半導體疊層塊與該第二半導體疊層塊。 The present invention discloses a method for fabricating a light-emitting device, comprising: providing a first substrate and a plurality of semiconductor stacked blocks on the first substrate, each of the plurality of semiconductor stacked blocks including a first electrical semiconductor layer, The light emitting layer is disposed on the first electrical semiconductor layer, and a second electrical semiconductor layer is disposed on the light emitting layer, wherein the first substrate further includes a dividing channel separating the two adjacent semiconductor stacked blocks and the Separating the props having a width of less than 10 μm; performing a first separating step comprising: providing a second substrate; performing a first bonding step comprising bonding one of the plurality of semiconductor stacked blocks to the first semiconductor stacked block and the first a second substrate; and separating the first semiconductor stacked block from the first substrate, and the first substrate retains a second semiconductor stacked block of the plurality of semiconductor stacked blocks; and performing a second bonding step comprises The first semiconductor stacked block and the second semiconductor stacked block are bonded in alignment.

101‧‧‧基板 101‧‧‧Substrate

102‧‧‧發光二極體晶片 102‧‧‧Light Emitter Wafer

103v,103h‧‧‧切割道 103v, 103h‧‧‧ cutting road

D‧‧‧切割道寬度 D‧‧‧ cutting path width

201‧‧‧第一基板 201‧‧‧First substrate

202‧‧‧半導體疊層 202‧‧‧Semiconductor laminate

202a‧‧‧第一電性半導體層 202a‧‧‧First electrical semiconductor layer

202b‧‧‧發光層 202b‧‧‧Lighting layer

202c‧‧‧第二電性半導體層 202c‧‧‧Second electrical semiconductor layer

211‧‧‧第一犧牲層 211‧‧‧First Sacrifice Layer

212‧‧‧分隔道 212‧‧‧ divider

221‧‧‧第二基板 221‧‧‧second substrate

231,232,233,234及235‧‧‧半導體疊層塊 231, 232, 233, 234 and 235‧‧ ‧ semiconductor laminated blocks

d‧‧‧分隔道之寬度 d‧‧‧The width of the divider

231e1‧‧‧第一電極 231e1‧‧‧first electrode

231e2‧‧‧第二電極 231e2‧‧‧second electrode

240‧‧‧介電層 240‧‧‧ dielectric layer

241‧‧‧雷射光 241‧‧‧Laser light

301‧‧‧第一基板 301‧‧‧First substrate

302‧‧‧半導體疊層 302‧‧‧Semiconductor laminate

331,333‧‧‧半導體疊層塊 331,333‧‧‧Semiconductor laminated block

331e1,333e1及335e1‧‧‧第一電極 331e1, 333e1 and 335e1‧‧‧ first electrode

331e2,333e2及335e2‧‧‧第二電極 331e2, 333e2 and 335e2‧‧‧ second electrode

340‧‧‧介電層 340‧‧‧ dielectric layer

361‧‧‧元件基板 361‧‧‧ element substrate

361TE1,361TE2‧‧‧穿孔電極 361TE1,361TE2‧‧‧perforated electrode

361E1,361E2‧‧‧圖形化之金屬層 361E1,361E2‧‧‧Graphical metal layer

361S1,361S2,361S3及361S4‧‧‧圖形化之金屬層 361S1, 361S2, 361S3 and 361S4‧‧‧ graphical metal layers

602‧‧‧半導體疊層 602‧‧‧Semiconductor laminate

602a‧‧‧第一電性半導體層 602a‧‧‧First electrical semiconductor layer

602b‧‧‧發光層 602b‧‧‧Lighting layer

602c‧‧‧第二電性半導體層 602c‧‧‧second electrical semiconductor layer

611‧‧‧第一犧牲層 611‧‧‧First Sacrifice Layer

621,621’‧‧‧第二基板 621,621'‧‧‧second substrate

621T1,621T1’‧‧‧第一穿孔 621T1, 621T1’‧‧‧ first perforation

621T2,621T2’‧‧‧第二穿孔 621T2, 621T2’‧‧‧ second perforation

622TE1,622TE1’‧‧‧第一穿孔電極 622TE1, 622TE1'‧‧‧ first perforated electrode

622TE2,622TE2’‧‧‧第二穿孔電極 622TE2, 622TE2'‧‧‧ second perforated electrode

631E1,631E1’‧‧‧第一導電連接線 631E1, 631E1'‧‧‧ first conductive cable

631E2,631E2’‧‧‧第二導電連接線 631E2, 631E2'‧‧‧Second conductive cable

632‧‧‧半導體疊層塊 632‧‧‧Semiconductor laminated block

640‧‧‧絕緣層 640‧‧‧Insulation

641,641’‧‧‧透明封裝材料 641,641'‧‧‧Transparent packaging materials

701‧‧‧第一基板 701‧‧‧First substrate

702‧‧‧半導體疊層 702‧‧‧Semiconductor laminate

702a‧‧‧第一電性半導體層 702a‧‧‧First electrical semiconductor layer

702b‧‧‧發光層 702b‧‧‧Lighting layer

702c‧‧‧第二電性半導體層 702c‧‧‧Second electrical semiconductor layer

711‧‧‧第一犧牲層 711‧‧‧First Sacrifice Layer

721‧‧‧第二基板 721‧‧‧second substrate

721T‧‧‧穿孔 721T‧‧‧Perforation

721TE‧‧‧第一穿孔電極 721TE‧‧‧first perforated electrode

722EE及722E‧‧‧電極 722EE and 722E‧‧‧ electrodes

731,732,733及734‧‧‧半導體疊層塊 731,732,733 and 734‧‧‧Semiconductor laminated blocks

791,792‧‧‧導電氧化層 791,792‧‧‧conductive oxide layer

793‧‧‧反射金屬層 793‧‧‧reflective metal layer

794‧‧‧歐姆接觸金屬層 794‧‧‧Ohm contact metal layer

795‧‧‧絕緣層 795‧‧‧Insulation

第1圖所示為傳統製作發光二極體晶片之基板。 Figure 1 shows a conventional substrate for a light-emitting diode wafer.

第2A至2E圖所示為本發明之發光元件之製造方法所使用之一分離方法之實施例。 2A to 2E are views showing an embodiment of a separation method used in the method of manufacturing a light-emitting element of the present invention.

第2F圖所示為本發明之發光元件之製造方法之第一實施例之中間步驟。 Fig. 2F is a view showing an intermediate step of the first embodiment of the method for producing a light-emitting element of the present invention.

第3A圖至3F圖所示為本發明之發光元件之製造方法之第一實施例(並聯情形)。 3A to 3F show a first embodiment (parallel case) of a method of manufacturing a light-emitting element of the present invention.

第4圖所示為本發明之發光元件之製造方法之第一實施例(並聯情形)。 Fig. 4 is a view showing a first embodiment (parallel case) of a method of manufacturing a light-emitting element of the present invention.

第5圖所示為本發明之發光元件之製造方法之第一實施例(串聯情形)。 Fig. 5 is a view showing a first embodiment (in the case of a series connection) of a method of manufacturing a light-emitting element of the present invention.

第6A至6B圖所示為本發明之發光元件之製造方法之第二實施例。 6A to 6B are views showing a second embodiment of the method of manufacturing a light-emitting element of the present invention.

第6C至6D圖所示為本發明之發光元件之製造方法之第三實施例。 Fig. 6C to Fig. 6D show a third embodiment of the method of manufacturing a light-emitting element of the present invention.

第7A至7G圖所示為本發明之發光元件之製造方法之第四實施例。 7A to 7G are diagrams showing a fourth embodiment of the method of manufacturing a light-emitting element of the present invention.

第7H至7K圖所示為本發明之發光元件之製造方法之第五實施例。 7H to 7K show a fifth embodiment of the method of manufacturing a light-emitting element of the present invention.

圖2A至2E顯示為本發明之發光元件之製造方法所使用之一分離方法之實施例。圖3至圖5顯示本發明之發光元件之製造方法之第一實施例,其中圖3A至3F、及圖4顯示複數之半導體疊層塊之並聯所形成之發光元件;而 圖5則顯示複數之半導體疊層塊之串聯所形成之發光元件。 2A to 2E show an embodiment of a separation method used in the method of manufacturing a light-emitting element of the present invention. 3 to 5 show a first embodiment of a method of fabricating a light-emitting device of the present invention, wherein FIGS. 3A to 3F and FIG. 4 show light-emitting elements formed by parallel connection of a plurality of semiconductor stacked blocks; Fig. 5 shows a light-emitting element formed by a series connection of a plurality of semiconductor stacked blocks.

在圖2A中,於第一基板201上形成一半導體疊層202,此半導體疊層202包括一第一電性半導體層202a;一發光層202b位於第一電性半導體層202a之上;以及一第二電性半導體層202c位於發光層202b之上。第一電性半導體層202a和第二電性半導體層202c電性相異,例如第一電性半導體層202a是n型半導體層,而第二電性半導體層202c是p型半導體層。第一電性半導體層202a、發光層202b、及第二電性半導體層202c為III-V族材料所形成,例如為磷化鋁鎵銦(AlGaInP)系列材料或氮化鋁鎵銦(AlGaInN)系列材料。在圖2B中,實施一圖形化步驟,形成寬度為d之分隔道212,而半導體疊層202被圖形化成複數之半導體疊層塊231,232,233,234及235。即兩相鄰之半導體疊層塊係被分隔道212隔開。而為了增加半導體疊層202的利用面積,分隔道之寬度d可以儘量縮小,例如小於20μm,更佳的是小於10μm,在一實施例中,分隔道之寬度d小於5μm。而上述之圖形化一般是指經覆蓋光阻並曝光顯影後加以蝕刻之製程。但圖形化之方法並不限於此,其他方法,例如以雷射直接切割半導體疊層202亦為一實施例。另外,上述複數之半導體疊層塊於圖形化後各具有一上視形狀,且此上視形狀可以包含菱行、正方形、長方形、三角形、或圓形。值得注意的是,上述半導體疊層202可能係在第一基板201上所成長,即第一基板201是半導體疊層之成長基板;但也可能半導體疊層202在另一成長基板形成後,經移轉技術而將半導體疊層移轉至此第一基板201上,於此情形時,半導體疊層202與第一基板201間可能更包括一黏結層(圖未示)。移轉技術為熟悉此技術領域之人士所習知,在此不予贅述。或者,在另一實施例中,半導體疊層202係在另一成長基板形成且被圖形化成上述複數之半導體疊層塊231,232,233,234及235之 後,才經移轉技術而將這些半導體疊層塊231,232,233,234及235移轉至此第一基板201上,形成圖2B之情形,同樣地,於此情形時,半導體疊層塊231,232,233,234及235與第一基板201間可能更包括一黏結層(圖未示)。接著,在欲移離之半導體疊層塊上形成一第一犧牲層211以利實行分離步驟,在本實施例中,欲移離之半導體疊層塊為半導體疊層塊232及234。此第一犧牲層211之形成可以是先在整個第一基板201上形成一整層第一犧牲層211之材料後,再以黃光及蝕刻製程選擇性地在欲移離之半導體疊層塊232及234上存留下此第一犧牲層211。值得注意的是,熟悉此技術領域之人士亦了解,在製程順序上,也可以是先在欲移離之半導體疊層塊232及234之位置上形成此第一犧牲層211後,才以另一黃光及蝕刻製程以完成前述之半導體疊層202之圖形化成複數之半導體疊層塊231,232,233,234及235之步驟。第一犧牲層211之材料可以是導電材料或非導電材料,導電材料例如是金屬氧化物、金屬、或合金,其中金屬氧化物可以例如是氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋅(ZnO);金屬可以例如是鋁、金、鉑、鋅、銀、鎳、鍺、銦、錫、鈦、鉛、銅、鈀;而合金可以例如是上述金屬之合金;非導電材料例如是高分子材料、氧化物、或氮化物(SiNx),其中高分子材料可以例如是BCB、Epoxy等高分子材料;氧化物可以例如是氧化矽(SiO2)及氧化鋁(Al2O3);氮化物可以例如是氮化矽(SiNx)。上述第一犧牲層211之材料的選擇可由熟悉此技術領域之人士視後續製程及產品需要導電與否及需要透光與否而選擇採用。在圖2C中,實行分離步驟,包括:提供一第二基板221,並將第二基板221與第一犧牲層211接合;第二基板221可以是透明基板或不透明基板,透明基板例如是玻璃,藍寶石(Al2O3),CVD鑽石;不透明基板例如是矽(Si)基板、氮化鋁(AlN)、陶瓷基板。 上述第二基板221之材料的選擇可由熟悉此技術領域之人士視後續製程及產品需要透光與否及需要導電與否而選擇採用。之後,如圖2D所示,將欲移離之半導體疊層塊232及234與第一基板201分離。在實施上述步驟時,可在欲移離之半導體疊層塊232及234與第一基板201之界面施以一雷射光241照射,以使半導體疊層塊232及234與第一基板201較易分離。又如前所述,半導體疊層202亦可能係在另一成長基板形成後,再經移轉技術而移轉至第一第一基板201上,於此情形時,亦可在半導體疊層202移轉至第一基板201時,選擇性地在欲移離之半導體疊層塊232及234之位置上,先形成與第一基板201間之一犧牲層(圖未示),此犧牲層可選擇本身材料較脆弱或與第一基板201之接合力較弱之材料,如此可在欲移離之半導體疊層塊232及234與第一基板201分離時,使欲移離之半導體疊層塊232及234與第一第一基板201較易分離。 In FIG. 2A, a semiconductor stack 202 is formed on the first substrate 201. The semiconductor stack 202 includes a first electrical semiconductor layer 202a; a light emitting layer 202b is disposed over the first electrical semiconductor layer 202a; The second electrical semiconductor layer 202c is located above the light emitting layer 202b. The first electrical semiconductor layer 202a and the second electrical semiconductor layer 202c are electrically different, for example, the first electrical semiconductor layer 202a is an n-type semiconductor layer, and the second electrical semiconductor layer 202c is a p-type semiconductor layer. The first electrical semiconductor layer 202a, the light emitting layer 202b, and the second electrical semiconductor layer 202c are formed of a III-V material, such as an aluminum gallium indium phosphide (AlGaInP) series material or aluminum gallium indium nitride (AlGaInN). Series of materials. In FIG. 2B, a patterning step is performed to form a trench 212 of width d, and the semiconductor stack 202 is patterned into a plurality of semiconductor stacked blocks 231, 232, 233, 234 and 235. That is, two adjacent semiconductor stacked blocks are separated by a divider 212. In order to increase the area of use of the semiconductor stack 202, the width d of the spacers may be minimized, for example, less than 20 μm, more preferably less than 10 μm. In one embodiment, the width d of the spacers is less than 5 μm. The above-mentioned patterning generally refers to a process of etching after covering the photoresist and exposing it to development. However, the method of patterning is not limited thereto, and other methods, such as direct cutting of the semiconductor stack 202 by laser, are also an embodiment. In addition, the plurality of semiconductor stacked blocks each have a top view shape after being patterned, and the top view shape may include a diamond line, a square, a rectangle, a triangle, or a circle. It should be noted that the semiconductor stack 202 may be grown on the first substrate 201, that is, the first substrate 201 is a growth substrate of the semiconductor laminate; however, it is also possible that the semiconductor laminate 202 is formed after another growth substrate is formed. The semiconductor stack is transferred to the first substrate 201 by the transfer technique. In this case, the semiconductor layer 202 and the first substrate 201 may further include a bonding layer (not shown). The transfer technique is known to those skilled in the art and will not be described here. Alternatively, in another embodiment, the semiconductor stack 202 is formed by another growth substrate and patterned into the plurality of semiconductor stacked blocks 231, 232, 233, 234 and 235, and then transferred to the semiconductor stacked blocks 231, 232, 233, 234 by a transfer technique. 235 is transferred to the first substrate 201 to form the case of FIG. 2B. Similarly, in this case, the semiconductor stacked blocks 231, 232, 233, 234 and 235 and the first substrate 201 may further include a bonding layer (not shown). Next, a first sacrificial layer 211 is formed on the semiconductor stacked block to be removed to facilitate the separation step. In the present embodiment, the semiconductor stacked blocks to be removed are the semiconductor stacked blocks 232 and 234. The first sacrificial layer 211 may be formed by forming a whole layer of the first sacrificial layer 211 on the entire first substrate 201, and then selectively removing the semiconductor stacked block in the yellow light and etching process. The first sacrificial layer 211 is left on 232 and 234. It should be noted that those skilled in the art also understand that in the process sequence, the first sacrificial layer 211 may be formed at the position of the semiconductor stacked blocks 232 and 234 to be removed. A yellow light and etching process is performed to complete the steps of patterning the plurality of semiconductor stacked blocks 231, 232, 233, 234 and 235 of the semiconductor stack 202 described above. The material of the first sacrificial layer 211 may be a conductive material or a non-conductive material, such as a metal oxide, a metal, or an alloy, wherein the metal oxide may be, for example, indium tin oxide (ITO), indium oxide (InO), oxidation. Tin (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc oxide (ZnO); metals such as aluminum, gold, platinum, zinc, silver, nickel, antimony, indium, tin, titanium, lead And copper, palladium; and the alloy may be, for example, an alloy of the above metals; the non-conductive material is, for example, a polymer material, an oxide, or a nitride (SiNx), wherein the polymer material may be, for example, a polymer material such as BCB or Epoxy; The material may be, for example, cerium oxide (SiO 2 ) and aluminum oxide (Al 2 O 3 ); the nitride may be, for example, tantalum nitride (SiNx). The selection of the material of the first sacrificial layer 211 can be selected by those skilled in the art depending on whether the subsequent process and the product need to be electrically conductive or not. In FIG. 2C, the separating step is performed, including: providing a second substrate 221 and bonding the second substrate 221 to the first sacrificial layer 211; the second substrate 221 may be a transparent substrate or an opaque substrate, and the transparent substrate is, for example, glass. Sapphire (Al 2 O 3 ), CVD diamond; the opaque substrate is, for example, a bismuth (Si) substrate, an aluminum nitride (AlN), or a ceramic substrate. The selection of the material of the second substrate 221 can be selected by those skilled in the art depending on whether the subsequent process and the product need to be transparent or not. Thereafter, as shown in FIG. 2D, the semiconductor stacked blocks 232 and 234 to be removed are separated from the first substrate 201. When the above steps are performed, a laser beam 241 is applied to the interface between the semiconductor stacked blocks 232 and 234 to be removed and the first substrate 201 to make the semiconductor stacked blocks 232 and 234 and the first substrate 201 easier. Separation. As also mentioned above, the semiconductor stack 202 may also be transferred to the first first substrate 201 after the formation of another growth substrate, and then transferred to the first first substrate 201. In this case, the semiconductor laminate 202 may also be used. When transferring to the first substrate 201, a sacrificial layer (not shown) is formed between the first substrate 201 and the semiconductor substrate 232 and 234. The sacrificial layer may be formed. The material which is weak in material or weak in bonding force with the first substrate 201 is selected, so that the semiconductor stacked blocks to be removed can be removed when the semiconductor stacked blocks 232 and 234 to be removed are separated from the first substrate 201. 232 and 234 are easier to separate from the first first substrate 201.

圖2E則顯示實行分離步驟後,半導體疊層塊232及234與第一基板201分離之情形,而第一基板201則保留有半導體疊層塊231,233及235。值得注意的是,第二基板221及其上之半導體疊層塊232及234,或第一基板201及其上之半導體疊層塊231,233及235,兩者均可以在下述之本發明之發光元件之製造方法之實施例中被使用。 2E shows the case where the semiconductor stacked blocks 232 and 234 are separated from the first substrate 201 after the separation step is performed, and the first substrate 201 retains the semiconductor stacked blocks 231, 233 and 235. It should be noted that the second substrate 221 and the semiconductor stacked blocks 232 and 234 thereon, or the first substrate 201 and the semiconductor stacked blocks 231, 233 and 235 thereon, both of which may be in the light-emitting element of the present invention described below It is used in the embodiment of the manufacturing method.

參考圖2F,接續上述圖2A至2E所顯示之分離方法,以第一基板201及其上之半導體疊層塊231,233及235為例示說明本發明之發光元件之製造方法之第一實施例,其形成方法更包含:在半導體疊層塊231及233上分別形成一個第一電極231e1對應地電性連接半導體疊層塊231及233之第一電性半導體層202a,且在半導體疊層塊231及233上分別形成一個第二電極231e2對應地電性連接半導體疊層塊231及233之第二電性半導體層202c。其中製程方法可以是 先對半導體疊層塊231及233等施以一蝕刻製程以曝露部份各半導體疊層塊至其第一電性半導體層202a。其後於第一基板201上形成介電層240,再以圖形化定義出第一電極231e1及第二電極231e2之位置於介電層240中,最後再形成上述複數之第一電極231e1及複數之第二電極231e2,其形成方法例如以金屬蒸鍍或電鍍填入金屬材料於介電層240中第一電極231e1及第二電極231e2之位置後再以化學研磨(CMP)除去鍍於介電層240上多餘之金屬材料。 Referring to FIG. 2F, following the separation method shown in FIGS. 2A to 2E, the first substrate 201 and the semiconductor stacked blocks 231, 233 and 235 thereon are used as an example to illustrate the first embodiment of the method for manufacturing the light-emitting device of the present invention. The forming method further includes: forming a first electrode 231e1 on the semiconductor stacked blocks 231 and 233, respectively correspondingly electrically connecting the first electrical semiconductor layer 202a of the semiconductor stacked blocks 231 and 233, and in the semiconductor stacked block 231 and A second electrode 231e2 is formed on the 233 to electrically connect the second electrical semiconductor layer 202c of the semiconductor stacked blocks 231 and 233, respectively. The process method can be First, an etching process is applied to the semiconductor stacked blocks 231 and 233 and the like to expose a portion of each of the semiconductor stacked blocks to the first electrically conductive semiconductor layer 202a. Thereafter, a dielectric layer 240 is formed on the first substrate 201, and the positions of the first electrode 231e1 and the second electrode 231e2 are defined in the dielectric layer 240, and finally the plurality of first electrodes 231e1 and the plurality are formed. The second electrode 231e2 is formed by, for example, metal deposition or electroplating to fill the position of the first electrode 231e1 and the second electrode 231e2 in the dielectric layer 240, and then remove the plating by dielectric polishing (CMP). Excess metal material on layer 240.

圖3A至3C之元件在結構及材料等等均與圖2F所示相同或相似,故相同或相似元件代碼僅將第一碼由”2”改為”3”。圖3A中顯示提供第一基板301上具有一半導體疊層302,而在圖3B中,半導體疊層302經上述分離方法,存留有半導體疊層塊331,333及335等半導體疊層塊於第一基板301上,同樣須注意的是,為說明方便,以下僅以半導體疊層塊331及333為主進行說明。圖3C則示意了如同上述圖2F之結果,包括形成介電層340及複數之第一電極331e1及複數之第二電極331e2。 3A to 3C are identical or similar in structure and material, etc., as shown in Fig. 2F, so the same or similar component code only changes the first code from "2" to "3". 3A shows that a semiconductor substrate 302 is provided on the first substrate 301, and in FIG. 3B, the semiconductor laminate 302 has a semiconductor stacked block such as semiconductor stacked blocks 331, 333 and 335 by the above separation method. On the other substrate 301, it should be noted that, for convenience of explanation, only the semiconductor stacked blocks 331 and 333 will be mainly described below. FIG. 3C illustrates the result of forming the dielectric layer 340 and the plurality of first electrodes 331e1 and the plurality of second electrodes 331e2 as shown in FIG. 2F.

圖3D至3F則顯示本實施例在元件基板之製造方法,此元件基板用以與上述圖3C之第一基板301對接以形成本實施例最終結果之發光元件。在圖3D中顯示提供元件基板361,接著在圖3E中元件基板361形成兩穿孔電極361TE1及361TE2,每一穿孔電極係由一穿孔及填充於其內之導電物質所構成,此兩穿孔電極361TE1及361TE2用以提供本發明所揭示之發光元件輸入外接電源。在圖3F中顯示在元件基板361上,形成圖形化之金屬層361E1及361E2分別與兩穿孔電極361TE1及361TE2電性連接,以達成本實施例中複數之半導體疊層塊之並聯。在另一實施例中,圖形化之金屬層361E1及361E2與兩穿孔電極361TE1及361TE2係同一導電物質構成,即形成圖形化之金屬層361E1及361E2 之導電物質於形成時亦同時填入兩穿孔電極361TE1及361TE2之穿孔中。 3D to 3F show a method of manufacturing the element substrate of the present embodiment, which is used to interface with the first substrate 301 of Fig. 3C to form a light-emitting element of the final result of the embodiment. The element substrate 361 is shown in FIG. 3D, and then the element substrate 361 is formed with two perforated electrodes 361TE1 and 361TE2 in FIG. 3E. Each of the perforated electrodes is formed by a perforation and a conductive material filled therein. The two perforated electrodes 361TE1 And 361TE2 is used to provide an external power supply for the input of the light-emitting element disclosed in the present invention. In FIG. 3F, the patterned metal layers 361E1 and 361E2 are electrically connected to the two via electrodes 361TE1 and 361TE2, respectively, to achieve parallel connection of the plurality of semiconductor stacked blocks in the embodiment. In another embodiment, the patterned metal layers 361E1 and 361E2 are formed of the same conductive material as the two via electrodes 361TE1 and 361TE2, that is, the patterned metal layers 361E1 and 361E2 are formed. The conductive material is also filled into the perforations of the two perforated electrodes 361TE1 and 361TE2 at the same time.

圖4顯示本實施例之複數之半導體疊層塊之並聯之發光元件之製造方法,其係接續圖3C及圖3F。圖中(a)所示為前述圖3C中之第一基板301,將其翻轉180度後其情形如圖中(b)所示;圖中(c)所示為前述圖3F中之元件基板361;將圖中(b)之第一基板301與圖中(c)之元件基板361對位接合,形成本實施例最終結果之發光元件,如圖中(d)所示。圖(d)上方為其部份放大顯示。如放大部份所示,上述之對位接合係使圖形化之金屬層361E1與半導體疊層塊331及333之第一電極331e1接合,且圖形化之金屬層361E2與半導體疊層塊331及333之第二電極331e2接合,故半導體疊層塊331及半導體疊層塊333等複數之半導體疊層塊形成並聯連接。 Fig. 4 is a view showing a method of manufacturing a light-emitting element in parallel with a plurality of semiconductor stacked blocks of the present embodiment, which is continued from Fig. 3C and Fig. 3F. Figure (a) shows the first substrate 301 in Figure 3C, which is turned over 180 degrees, as shown in Figure (b); Figure (c) shows the element substrate in Figure 3F. 361; the first substrate 301 of the figure (b) is aligned with the element substrate 361 of the figure (c) to form a light-emitting element of the final result of the present embodiment, as shown in (d) of the drawing. Figure (d) above is a partial enlarged display. As shown in the enlarged portion, the above-described alignment bonding causes the patterned metal layer 361E1 to be bonded to the first electrodes 331e1 of the semiconductor stacked blocks 331 and 333, and the patterned metal layer 361E2 and the semiconductor stacked blocks 331 and 333. Since the second electrodes 331e2 are joined, a plurality of semiconductor stacked blocks such as the semiconductor stacked block 331 and the semiconductor stacked block 333 are connected in parallel.

圖5顯示本實施例之複數之半導體疊層塊之串聯之發光元件之製造方法,同樣地,以圖3C及圖3F為基礎,圖中(a)所示為前述圖3C中之第一基板301,將其翻轉180度後其情形如圖中(b)所示;圖中(c)所示係為元件基板361,其上具有圖形化之金屬層361S1,361S2,361S3及361S4;兩穿孔電極361TE1及361TE2則設置於元件基板361中,且分別位於圖中圖形化之金屬層361S1及361S2下方,用以提供本發明所揭示之發光元件輸入外接電源。最後,如圖中(d)所示,將圖中(b)之第一基板301與圖中(c)之元件基板361對位接合,形成本實施例之發光元件。圖中(d)下方為其部份放大顯示,如放大部份所示,上述之對位接合係使圖形化之金屬層361S1,361S2,361S3及361S4與半導體疊層塊331及333等複數之半導體疊層塊之第一電極331e1及第二電極331e2接合,故半導體疊層塊331及半導體疊層塊333等複數之半導體疊層塊形成串聯連接。 5 is a view showing a method of manufacturing a series of light-emitting elements of a plurality of semiconductor stacked blocks of the present embodiment, and similarly, based on FIG. 3C and FIG. 3F, (a) is a first substrate of the foregoing FIG. 3C. 301, after flipping it 180 degrees, the situation is as shown in (b) of the figure; (c) is a component substrate 361 having patterned metal layers 361S1, 361S2, 361S3 and 361S4; The electrodes 361TE1 and 361TE2 are disposed in the element substrate 361 and are respectively located under the patterned metal layers 361S1 and 361S2 in the figure to provide an external power source for inputting the light-emitting element disclosed in the present invention. Finally, as shown in (d) of the drawing, the first substrate 301 of the drawing (b) is aligned with the element substrate 361 of the drawing (c) to form the light-emitting element of the present embodiment. The part below (d) is enlarged for partial display. As shown in the enlarged part, the above-mentioned alignment bonding makes the patterned metal layers 361S1, 361S2, 361S3 and 361S4 and the semiconductor stacked blocks 331 and 333 and the like. Since the first electrode 331e1 and the second electrode 331e2 of the semiconductor stacked block are joined, a plurality of semiconductor stacked blocks such as the semiconductor stacked block 331 and the semiconductor stacked block 333 are connected in series.

上述第一實施例之說明雖以圖2F為基礎,以圖2E中之第一基板 201及其上之半導體疊層塊231及233為例示,但如同在圖2E中所提及,第二基板221及其上之半導體疊層塊232及234亦可為本發明之發光元件之製造方法之實施例所使用,故熟悉此技術領域之人士亦可基於上述之說明,以第二基板221及其上之半導體疊層塊232及234為基礎,而實施與上述第一實施例相同或類似之發光元件之製造,其情形不再贅述。 The description of the first embodiment above is based on FIG. 2F, and the first substrate in FIG. 2E is used. 201 and the semiconductor stacked blocks 231 and 233 thereon are exemplified, but as mentioned in FIG. 2E, the second substrate 221 and the semiconductor stacked blocks 232 and 234 thereon may also be the manufacture of the light-emitting element of the present invention. The embodiments of the method are used, and those skilled in the art can also implement the same as the first embodiment described above based on the second substrate 221 and the semiconductor stacked blocks 232 and 234 thereon based on the above description. The manufacture of similar light-emitting elements will not be repeated.

圖6A至圖6D顯示本發明之發光元件之製造方法之第二及第三實施例,其中圖6A及6B之第二實施例顯示當圖2E中之第二基板221為本實施例之發光元件之元件基板時之製造方法;而圖6C及圖6D之第三實施例則顯示使用其他基板為發光元件之元件基板時之製造方法。 6A to 6D show second and third embodiments of the method of fabricating the light-emitting device of the present invention, wherein the second embodiment of FIGS. 6A and 6B shows the second substrate 221 of FIG. 2E as the light-emitting element of the present embodiment. The manufacturing method of the element substrate; and the third embodiment of FIGS. 6C and 6D shows a manufacturing method when another substrate is used as the element substrate of the light-emitting element.

圖6A係以圖2E第二基板221及其上之半導體疊層塊232為例示,須注意的是,圖6A中與圖2E相同之元件僅將第一碼由”2”改為”6”,其元件在結構及材料等等均與圖2E所示相同或相似。但與圖2E不同的是,本實施例揭示之第二基板621上更包括一第一穿孔電極622TE1及第二穿孔電極622TE2,其中第一穿孔電極622TE1係由第二基板621所具有之一第一穿孔621T1及填充於其內之一第一導電物質構成,而第二穿孔電極622TE2係由第二基板621所具有之一第二穿孔621T2及填充於其內之一第二導電物質構成。在一實施例中,第一導電物質與第二導電物質為相同材料。接著,進行一對位接合製程,以接合圖6A之半導體疊層塊632與第二基板621,使半導體疊層塊632位於第二基板621之第一穿孔電極622TE1及第二穿孔電極622TE2間。之後,對半導體疊層塊632施以一蝕刻製程以曝露部份半導體疊層塊632至其第二電性半導體層602c。接著,如圖6B中所示,形成一絕緣層640於半導體疊層塊632之側壁,用以提供後續形成之第一導電連接線631E1與半導體疊層塊632間之電性絕緣。 之後,形成一第一導電連接線631E1及一第二導電連接線631E2,其中第一導電連接線631E1電性連接半導體疊層塊632中之第一電性半導體層602a及第一穿孔電極622TE1,第二導電連接線631E2電性連接半導體疊層塊632中之第二電性半導體層602c及第二穿孔電極622TE2。最後,形成一透明封裝材料641於第二基板621上並覆蓋半導體疊層塊632、第一導電連接線631E1、及第二導電連接線631E2。如此完成本發明第二實施例之發光元件,其中第一穿孔電極622TE1及第二穿孔電極622TE2用以提供本發明所揭示之發光元件輸入外接電源。 6A is taken as an example of the second substrate 221 of FIG. 2E and the semiconductor stacked block 232 thereon. It should be noted that the same components in FIG. 6A as in FIG. 2E only change the first code from "2" to "6". The components are identical or similar in structure, material, and the like to that shown in FIG. 2E. The second substrate 621 of the present embodiment further includes a first through electrode 622TE1 and a second through electrode 622TE2, wherein the first through electrode 622TE1 is formed by the second substrate 621. A through hole 621T1 and a first conductive material filled therein are formed, and the second through electrode 622TE2 is composed of a second through hole 621T2 of the second substrate 621 and a second conductive material filled therein. In an embodiment, the first conductive material and the second conductive material are the same material. Next, a one-bit bonding process is performed to bond the semiconductor stacked block 632 and the second substrate 621 of FIG. 6A such that the semiconductor stacked block 632 is located between the first via electrode 622TE1 and the second via electrode 622TE2 of the second substrate 621. Thereafter, the semiconductor stacked block 632 is subjected to an etching process to expose a portion of the semiconductor stacked block 632 to its second electrically conductive semiconductor layer 602c. Next, as shown in FIG. 6B, an insulating layer 640 is formed on the sidewall of the semiconductor stacked block 632 to provide electrical isolation between the subsequently formed first conductive connecting line 631E1 and the semiconductor stacked block 632. Then, a first conductive connection line 631E1 and a second conductive connection line 631E2 are formed, wherein the first conductive connection line 631E1 is electrically connected to the first electrical semiconductor layer 602a and the first perforated electrode 622TE1 of the semiconductor stacked block 632, The second conductive connection line 631E2 is electrically connected to the second electrical semiconductor layer 602c and the second via electrode 622TE2 of the semiconductor stacked block 632. Finally, a transparent encapsulating material 641 is formed on the second substrate 621 and covers the semiconductor stacked block 632, the first conductive connecting line 631E1, and the second conductive connecting line 631E2. Thus, the light-emitting element of the second embodiment of the present invention is completed, wherein the first perforated electrode 622TE1 and the second perforated electrode 622TE2 are used to provide an external power source for inputting the light-emitting element disclosed in the present invention.

而圖6C及圖6D例示使用其他基板為發光元件之元件基板時之製造方法。圖6C中係以第二基板221及其上之半導體疊層塊232及半導體疊層塊234為例示。本實施例雖例示同時利用複數之半導體疊層塊,例如半導體疊層塊232及半導體疊層塊234形成複數之發光元件之實施方法,故圖示中皆繪示了兩半導體疊層塊232及234,但實施時亦可以只針對單一半導體疊層塊232(或半導體疊層塊234)實施。第二基板221上接合有經前述分離步驟後分離自第一基板201之半導體疊層塊232(及/或半導體疊層塊234)。由於本實施例例示使用其他基板為發光元件之元件基板時之製造方法,故第二基板221在作用上是一暫時基板,而實施方法則包括提供一元件基板621’,此元件基板621’包括一第一穿孔電極622TE1’及第二穿孔電極622TE2’(須注意的是,本實施例亦例示同時利用複數之半導體疊層塊,例如半導體疊層塊232及半導體疊層塊234形成複數之發光元件之實施方法,故圖示中繪示了兩組第一穿孔電極622TE1’及第二穿孔電極622TE2’,係分別對應以供半導體疊層塊232及半導體疊層塊234之使用),其中第一穿孔電極622TE1’係由元件基板621’所具有之一第一穿孔621T1’及填充於其內之一第一導電物質構成,而第二穿孔電極622TE2’係由元件基板621’ 所具有之一第二穿孔621T2’及填充於其內之一第二導電物質構成。在一實施例中,第一導電物質與第二導電物質為相同材料。接著,實施一對位接合,接合半導體疊層塊232(及/或半導體疊層塊234)與元件基板621’,使半導體疊層塊232(及/或半導體疊層塊234)位於元件基板621’之第一穿孔電極622TE1’及第二穿孔電極622TE2’間。之後,分離半導體疊層塊232(及/或半導體疊層塊234)於第二基板221:同樣地,在實施此步驟時,亦可在半導體疊層塊232(及/或半導體疊層塊234)與第一犧牲層211之界面施以一雷射光照射(圖未示),以輔助半導體疊層塊232(及/或半導體疊層塊234)與第一犧牲層211之分離。 6C and 6D illustrate a manufacturing method in which another substrate is used as an element substrate of a light-emitting element. In FIG. 6C, the second substrate 221 and the semiconductor stacked block 232 and the semiconductor stacked block 234 thereon are exemplified. In this embodiment, although a plurality of semiconductor stacked blocks, for example, a semiconductor stacked block 232 and a semiconductor stacked block 234, are used to form a plurality of light-emitting elements, the two semiconductor stacked blocks 232 are illustrated. 234, however, may be implemented only for a single semiconductor stacked block 232 (or semiconductor stacked block 234). A semiconductor stacked block 232 (and/or a semiconductor stacked block 234) separated from the first substrate 201 by the separation step is bonded to the second substrate 221. Since the present embodiment exemplifies a manufacturing method in which another substrate is an element substrate of a light-emitting element, the second substrate 221 is functionally a temporary substrate, and the implementation method includes providing an element substrate 621 ′, the element substrate 621 ′ A first via electrode 622TE1' and a second via electrode 622TE2' (note that this embodiment also exemplifies the simultaneous use of a plurality of semiconductor stacked blocks, such as the semiconductor stacked block 232 and the semiconductor stacked block 234 to form a plurality of light. The method for implementing the components, so that two sets of first perforated electrodes 622TE1' and second perforated electrodes 622TE2' are respectively shown for the use of the semiconductor stacked block 232 and the semiconductor stacked block 234, wherein A perforated electrode 622TE1' is composed of one of the first through holes 621T1' of the element substrate 621' and a first conductive material filled therein, and the second perforated electrode 622TE2' is composed of the element substrate 621' It has one of the second through holes 621T2' and a second conductive material filled therein. In an embodiment, the first conductive material and the second conductive material are the same material. Next, a pair of bit bonding is performed to bond the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) and the element substrate 621' such that the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) is positioned on the element substrate 621. Between the first perforated electrode 622TE1' and the second perforated electrode 622TE2'. Thereafter, the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) is separated from the second substrate 221: similarly, in performing this step, the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) may also be used. A laser light irradiation (not shown) is applied to the interface of the first sacrificial layer 211 to assist in the separation of the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) from the first sacrificial layer 211.

接著,如圖6D中所示,對半導體疊層塊232(及/或半導體疊層塊234)施以一蝕刻製程以曝露部份半導體疊層塊232(及/或半導體疊層塊234)至其第一電性半導體層202a。然後,形成一絕緣層640於半導體疊層塊232(及/或半導體疊層塊234)之側壁,用以提供後續形成之第二導電連接線631E2’與半導體疊層塊232(及/或半導體疊層塊234)間之電性絕緣;之後,形成一第一導電連接線631E1’及一第二導電連接線631E2’,其中第一導電連接線631E1’電性連接半導體疊層塊232(及/或半導體疊層塊234)中之第一電性半導體層202a及第一穿孔電極622TE1’,第二導電連接線631E2’電性連接半導體疊層塊232(及/或半導體疊層塊234)中之第二電性半導體層202c及第二穿孔電極622TE2’。最後,形成一透明封裝材料641’於元件基板621’上並覆蓋半導體疊層塊232(及/或半導體疊層塊234)、第一導電連接線631E1’、及第二導電連接線631E2’。如此完成本發明第三實施例之發光元件,其中第一穿孔電極622TE1’及第二穿孔電極622TE2’用以提供本發明所揭示之發光元件輸入外接電源。在實施方法係同時針對半導體疊層塊232及半導體疊層塊234實施之情形下,則包括進一步如圖 中所示延著LL’線切割,得到複數之發光元件。 Next, as shown in FIG. 6D, an etch process is applied to the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) to expose a portion of the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) to Its first electrical semiconductor layer 202a. Then, an insulating layer 640 is formed on sidewalls of the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) to provide a subsequently formed second conductive connecting line 631E2' and a semiconductor stacked block 232 (and/or semiconductor) Electrically insulating between the stacked blocks 234); a first conductive connecting line 631E1' and a second conductive connecting line 631E2' are formed, wherein the first conductive connecting line 631E1' is electrically connected to the semiconductor stacked block 232 (and Or the first electrical semiconductor layer 202a and the first via electrode 622TE1' in the semiconductor stacked block 234), and the second conductive connection line 631E2' is electrically connected to the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) The second electrical semiconductor layer 202c and the second via electrode 622TE2'. Finally, a transparent encapsulating material 641' is formed on the element substrate 621' and covers the semiconductor stacked block 232 (and/or the semiconductor stacked block 234), the first conductive connecting line 631E1', and the second conductive connecting line 631E2'. Thus, the light-emitting element of the third embodiment of the present invention is completed, wherein the first via electrode 622TE1' and the second via electrode 622TE2' are used to provide an external power supply for the light-emitting element of the present invention. In the case where the implementation method is implemented for both the semiconductor stacked block 232 and the semiconductor stacked block 234, it includes further figures. The LL' line is cut as shown in the figure to obtain a plurality of light-emitting elements.

上述第二及第三實施例之說明雖以圖2E中之第二基板221及其上之半導體疊層塊232及/或半導體疊層塊234為例示,而如同在圖2E中所提及,第一基板201及其上之半導體疊層塊231及233亦可為本發明之發光元件之製造方法之實施例所使用,故熟悉此技術領域之人士亦可基於上述之說明,以第一基板201及其上之半導體疊層塊231及233為基礎,而實施與上述第一實施例相同或類似之發光元件之製造,其情形不再贅述。 The description of the second and third embodiments described above is exemplified by the second substrate 221 of FIG. 2E and the semiconductor stacked block 232 and/or the semiconductor stacked block 234 thereon, as mentioned in FIG. 2E. The first substrate 201 and the semiconductor stacked blocks 231 and 233 thereon may also be used as an embodiment of the method for fabricating the light-emitting device of the present invention, and those skilled in the art may also use the first substrate based on the above description. The manufacture of the light-emitting elements of the same or similar to the above-described first embodiment is based on the semiconductor stack blocks 231 and 233 on the basis of 201, and the description thereof will not be repeated.

圖7A至圖7G顯示本發明之發光元件之製造方法之第四實施例。接續利用上述圖2A至2E所顯示之分離方法,本第四實施例係以圖2E中之第二基板221及其上之半導體疊層塊232(及/或半導體疊層塊234)及第一基板201及其上之半導體疊層塊231(及/或半導體疊層塊233)為例示。 7A to 7G show a fourth embodiment of the method of manufacturing the light-emitting element of the present invention. Following the separation method shown in FIGS. 2A to 2E described above, the fourth embodiment is the second substrate 221 of FIG. 2E and the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) thereon and the first The substrate 201 and the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) thereon are exemplified.

須說明的是,圖7A中與圖2E相同之元件僅將第一碼由”2”改為”7”,其元件在結構及材料等等均與圖2E所示相同或相似。圖7A中之第二基板721更包括一第一穿孔電極721TE,其中第一穿孔電極721TE係由第二基板721所具有之一第一穿孔721T及填充於其內之一第一導電物質構成。此外,接合第二基板721與第一犧牲層711時是一對位接合製程,以使半導體疊層塊732(及/或半導體疊層塊734)與第一穿孔電極721TE對位連接且形成電性連接。故如圖7A中所示,第二基板721上接合有經分離步驟後分離自第一基板701之半導體疊層塊732(及/或半導體疊層塊734);第一基板701上經分離步驟後保留有半導體疊層塊731(及/或半導體疊層塊733);接著,實施一第二接合步驟以對位接合半導體疊層塊732(及/或半導體疊層塊734)於半導體疊層塊731(及/或半導體疊層塊733)之上,其情形如圖7B中所示。須注意的是,本實施例亦例示同時 形成複數之發光元件之實施方法,故圖示中繪示了兩組半導體疊層塊之接合,即半導體疊層塊732與半導體疊層塊731接合為一組,半導體疊層塊734與半導體疊層塊733為另一組;但實施時可以只針對上述組合中之任一單一組,或同時針對兩組實施(其後須施以切割以形成複數之發光元件,不再贅述說明)。 It should be noted that the same components in FIG. 7A as those in FIG. 2E only change the first code from "2" to "7", and the components in the structure, materials, and the like are the same as or similar to those shown in FIG. 2E. The second substrate 721 in FIG. 7A further includes a first via electrode 721TE, wherein the first via electrode 721TE is composed of a first via 721T of the second substrate 721 and a first conductive material filled therein. In addition, the bonding of the second substrate 721 and the first sacrificial layer 711 is a pair bonding process to connect the semiconductor stacked block 732 (and/or the semiconductor stacked block 734) to the first via electrode 721TE and form an electrical connection. Sexual connection. Therefore, as shown in FIG. 7A, the second substrate 721 is bonded with the semiconductor stacked block 732 (and/or the semiconductor stacked block 734) separated from the first substrate 701 after the separation step; the first substrate 701 is subjected to a separation step. Thereafter, a semiconductor stacked block 731 (and/or a semiconductor stacked block 733) is retained; then, a second bonding step is performed to bond the semiconductor stacked block 732 (and/or the semiconductor stacked block 734) to the semiconductor stacked Above block 731 (and/or semiconductor stack block 733), the situation is as shown in Figure 7B. It should be noted that this embodiment also exemplifies simultaneous A method of forming a plurality of light-emitting elements is illustrated, so that the bonding of two sets of semiconductor stacked blocks is illustrated, that is, the semiconductor stacked block 732 and the semiconductor stacked block 731 are bonded into a group, and the semiconductor stacked block 734 and the semiconductor stacked The slabs 733 are another group; however, they may be implemented only for any one of the above combinations, or for both groups at the same time (hereinafter, a dicing is required to form a plurality of illuminating elements, and the description will not be repeated).

接著,分離半導體疊層塊731(及/或半導體疊層塊733)與第一基板701,其情形如圖7C所示,圖7D則顯示圖7C轉置180度之情形。須說明的是,為說明方便,圖7D中僅繪示圖7C中一組半導體疊層塊接合之情形。另外,如圖7E中所示,在實施上述第二接合步驟之前,亦可以選擇性地分別形成一導電氧化層791於半導體疊層塊731(及/或半導體疊層塊733)與導電氧化層792於半導體疊層塊732(及/或半導體疊層塊734)上。導電氧化層791或導電氧化層792可提供與半導體疊層塊之歐姆接觸及/或作為接合層,導電氧化層可以例如是氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋅(ZnO)。在本實施例中,導電氧化層791及導電氧化層792均提供接合層之功能,而導電氧化層791尚提供與半導體疊層塊731(及/或半導體疊層塊733)之歐姆接觸。此外,亦可選擇地形成一金屬層於半導體疊層塊731(及/或半導體疊層塊733)與半導體疊層塊732(及/或半導體疊層塊734)中至少之一上,此金屬層可提供與半導體疊層塊之歐姆接觸及/或提供反射之功能。如圖7E中所示,在本實施例中,在形成上述導電氧化層792於半導體疊層塊732(及/或半導體疊層塊734)前,先形成歐姆接觸金屬層794及反射金屬層793於半導體疊層塊732(及/或半導體疊層塊734)上,歐姆接觸金屬層794提供與半導體疊層塊732(及/或半導體疊層塊734)之歐姆接觸,例如為鍺化金(GeAu),而反射金屬層793提供反射鏡之功能,例如為銀(Ag)。此外,歐姆接觸金屬層794及反射金屬層793可以是金屬或合金,金屬可 以例如是鋁、金、鍺、鉑、鋅、銀、鎳、鍺、銦、錫、鈦、鉛、銅、鈀;而合金可以例如是上述金屬之合金。而藉由上述導電氧化層791及導電氧化層792將半導體疊層塊731(及/或半導體疊層塊733)與半導體疊層塊732(及/或半導體疊層塊734)接合,且將第一基板701分離後,其轉置180度之情形如圖7F所示,同樣地,為說明方便,圖7F中僅繪示圖7E中一組半導體疊層塊接合之情形。 Next, the semiconductor stacked block 731 (and/or the semiconductor stacked block 733) is separated from the first substrate 701, as shown in FIG. 7C, and FIG. 7D shows the case where the transfer of FIG. 7C is 180 degrees. It should be noted that, for convenience of description, only a case where a group of semiconductor stacked blocks in FIG. 7C is bonded is illustrated in FIG. 7D. In addition, as shown in FIG. 7E, before performing the second bonding step, a conductive oxide layer 791 may be selectively formed on the semiconductor stacked block 731 (and/or the semiconductor stacked block 733) and the conductive oxide layer. 792 is on semiconductor stack 732 (and/or semiconductor stack 734). The conductive oxide layer 791 or the conductive oxide layer 792 may provide ohmic contact with the semiconductor stacked block and/or as a bonding layer, and the conductive oxide layer may be, for example, indium oxide (InO), tin oxide (SnO), or cadmium tin oxide (CTO). , antimony tin oxide (ATO), zinc oxide (ZnO). In the present embodiment, the conductive oxide layer 791 and the conductive oxide layer 792 both provide the function of the bonding layer, and the conductive oxide layer 791 provides ohmic contact with the semiconductor stacked block 731 (and/or the semiconductor stacked block 733). In addition, a metal layer may be selectively formed on at least one of the semiconductor stacked block 731 (and/or the semiconductor stacked block 733) and the semiconductor stacked block 732 (and/or the semiconductor stacked block 734). The layers can provide ohmic contact with the semiconductor stacked blocks and/or provide reflection. As shown in FIG. 7E, in the present embodiment, an ohmic contact metal layer 794 and a reflective metal layer 793 are formed before the conductive oxide layer 792 is formed on the semiconductor stacked block 732 (and/or the semiconductor stacked block 734). On semiconductor stack block 732 (and/or semiconductor stack block 734), ohmic contact metal layer 794 provides ohmic contact with semiconductor stack block 732 (and/or semiconductor stack block 734), such as gold telluride ( GeAu), while the reflective metal layer 793 provides the function of a mirror, such as silver (Ag). In addition, the ohmic contact metal layer 794 and the reflective metal layer 793 may be metal or alloy, and the metal may be For example, aluminum, gold, ruthenium, platinum, zinc, silver, nickel, ruthenium, indium, tin, titanium, lead, copper, palladium; and the alloy may be, for example, an alloy of the above metals. The semiconductor stacked block 731 (and/or the semiconductor stacked block 733) is bonded to the semiconductor stacked block 732 (and/or the semiconductor stacked block 734) by the conductive oxide layer 791 and the conductive oxide layer 792, and the first After the substrate 701 is separated, it is rotated by 180 degrees as shown in FIG. 7F. Similarly, for convenience of explanation, only a case where a group of semiconductor stacked blocks in FIG. 7E is bonded is illustrated in FIG. 7F.

接著,本實施例接續圖7F進行說明(應注意的是,在其他實施例中,也可以接續圖7D而進行以下製程),如圖7G中所示,在半導體疊層塊731及半導體疊層塊732側壁形成一絕緣層795。然後,形成一電極722EE及722E於第二基板721上且電性連接半導體疊層塊731之第一電性半導體層702a。上述絕緣層795提供電極722EE及722E與半導體疊層塊731及半導體疊層塊732間之電性絕緣。如此,完成本發明第四實施例之發光元件,此發光元件由於包含半導體疊層塊731及半導體疊層塊732,為一雙接合面之發光元件,並且電極722EE及722E及第一穿孔電極721TE用以提供本發明所揭示之發光元件輸入外接電源。 Next, the present embodiment will be described with reference to FIG. 7F (it should be noted that, in other embodiments, the following process may be performed in conjunction with FIG. 7D), as shown in FIG. 7G, in the semiconductor stacked block 731 and the semiconductor stacked layer. The sidewall of block 732 defines an insulating layer 795. Then, an electrode 722EE and 722E are formed on the second substrate 721 and electrically connected to the first electrical semiconductor layer 702a of the semiconductor stacked block 731. The insulating layer 795 provides electrical insulation between the electrodes 722EE and 722E and the semiconductor stacked block 731 and the semiconductor stacked block 732. Thus, the light-emitting element of the fourth embodiment of the present invention is completed. The light-emitting element includes a semiconductor stacked block 731 and a semiconductor stacked block 732, and is a light-emitting element of a double joint surface, and the electrodes 722EE and 722E and the first perforated electrode 721TE. It is used to provide an external power supply for the light-emitting element disclosed in the present invention.

圖7H至圖7K例示本發明之發光元件之製造方法之第五實施例,此第五實施例係上述第四實施例之變化形。在本實施例中,接續利用上述圖2A至2E所顯示之分離方法,先實施一第二接合步驟,即先以圖2E中之第二基板221上之半導體疊層塊232(及/或半導體疊層塊234)與第一基板201上之半導體疊層塊231(及/或半導體疊層塊233)進行對位接合,其情形如圖7H中所示。接著,如圖7I所示,使半導體疊層塊232(及/或半導體疊層塊234)與第二基板221分離。之後可接合一元件基板於半導體疊層塊232(及/或半導體疊層塊234),以作為發光元件之元件基板。在另一實施例中,亦可以是移除第一基板201以使半導體疊 層塊231(及/或半導體疊層塊233)與第一基板201分離,並將元件基板接合於接合半導體疊層塊231(及/或半導體疊層塊233)。之後,如上所述,於圖7J中,提供一第二基板721以作為發光元件之元件基板,此第二基板721包括一第一穿孔電極721TE,其中第一穿孔電極721TE係由第二基板721所具有之一第一穿孔721T及填充於其內之一第一導電物質構成。接著,實施一第三接合步驟,以對位接合半導體疊層塊232(及/或半導體疊層塊234)於此第二基板721,如圖7J所示使半導體疊層塊232(及/或半導體疊層塊234)與第二基板721之第一穿孔電極721TE對位連接且形成電性連接。最後,使半導體疊層塊231(及/或半導體疊層塊233)與第一基板201分離,並如圖7G中所說明地形成絕緣層795及電極722EE及722E,得到如圖7K之發光元件。須注意的是,於圖7H中進行第二接合步驟之對位接合前,即半導體疊層塊232(及/或半導體疊層塊234)與半導體疊層塊231(及/或半導體疊層塊233)進行對位接合前,如同圖7E中之說明,同樣可以選擇性地分別形成一導電氧化層於半導體疊層塊231(及/或半導體疊層塊233)與半導體疊層塊232(及/或半導體疊層塊234)上;且亦可選擇地形成一金屬層於半導體疊層塊231(及/或半導體疊層塊233)與半導體疊層塊232(及/或半導體疊層塊234)中至少之一上,其詳細已如上說明,不再贅述。另外,如同在圖7I中所提及,在另一實施例,所實施的亦可以是使半導體疊層塊231(及/或半導體疊層塊233)與第一基板201分離,被移除的是第一基板201,而後續在圖7J中實施之第三接合步驟則為對位接合半導體疊層塊231(及/或半導體疊層塊233)於第二基板721,並接著使半導體疊層塊232(及/或半導體疊層塊234)與第二基板221分離。 7H to 7K illustrate a fifth embodiment of the method of manufacturing the light-emitting element of the present invention, which is a variation of the above-described fourth embodiment. In the present embodiment, a second bonding step is first performed by using the separation method shown in FIGS. 2A to 2E, that is, the semiconductor stacked block 232 (and/or semiconductor) on the second substrate 221 in FIG. 2E. The laminated block 234) is in alignment with the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) on the first substrate 201, as shown in Fig. 7H. Next, as shown in FIG. 7I, the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) is separated from the second substrate 221. Thereafter, an element substrate may be bonded to the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) to serve as an element substrate of the light emitting element. In another embodiment, the first substrate 201 may be removed to make the semiconductor stack The layer block 231 (and/or the semiconductor stacked block 233) is separated from the first substrate 201, and the element substrate is bonded to the bonded semiconductor stacked block 231 (and/or the semiconductor stacked block 233). Then, as shown in FIG. 7J, a second substrate 721 is provided as an element substrate of the light-emitting element, and the second substrate 721 includes a first through-hole electrode 721TE, wherein the first through-hole electrode 721TE is composed of the second substrate 721. It has one of the first through holes 721T and one of the first conductive materials filled therein. Next, a third bonding step is performed to bond the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) to the second substrate 721, and the semiconductor stacked block 232 is formed as shown in FIG. 7J (and/or The semiconductor stacked block 234) is aligned and electrically connected to the first via electrode 721TE of the second substrate 721. Finally, the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) is separated from the first substrate 201, and the insulating layer 795 and the electrodes 722EE and 722E are formed as illustrated in FIG. 7G, resulting in a light-emitting element as shown in FIG. 7K. . It should be noted that before the alignment bonding of the second bonding step in FIG. 7H, that is, the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) and the semiconductor stacked block 231 (and/or the semiconductor stacked block) 233) Before performing the para-bonding, as described in FIG. 7E, a conductive oxide layer may be selectively formed on the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) and the semiconductor stacked block 232 (and And/or a semiconductor stacked block 234); and optionally a metal layer is formed on the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) and the semiconductor stacked block 232 (and/or the semiconductor stacked block 234) In at least one of them, the details have been explained above, and will not be described again. In addition, as mentioned in FIG. 7I, in another embodiment, the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) may be separated from the first substrate 201 and removed. Is the first substrate 201, and the third bonding step, which is subsequently performed in FIG. 7J, is to bond the semiconductor stacked block 231 (and/or the semiconductor stacked block 233) to the second substrate 721, and then to laminate the semiconductor. Block 232 (and/or semiconductor stack 234) is separated from second substrate 221.

於上述各不同實施例中,具有相同功用之元件於各實施例雖具有不同之圖示標號,其具有之物理、化學、或電學等特性,除非於各別實施例有 特別限定,應認為具有相同或類似相關特性,而勿須於各實施例一一贅述。 In the various embodiments described above, elements having the same function have different reference numerals in the embodiments, and have physical, chemical, or electrical characteristics, unless otherwise disclosed in the respective embodiments. In particular, it should be considered that they have the same or similar related characteristics, and need not be described in detail in the embodiments.

上述實施例僅為例示性說明本發明之原理及其功效,而非用於限制本發明。任何本發明所屬技術領域中具有通常知識者均可在不違背本發明之技術原理及精神的情況下,對上述實施例進行修改及變化。因此本發明之權利保護範圍如後述之申請專利範圍所列。 The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is as set forth in the appended claims.

201‧‧‧第一基板 201‧‧‧First substrate

202‧‧‧半導體疊層 202‧‧‧Semiconductor laminate

202a‧‧‧第一電性半導體層 202a‧‧‧First electrical semiconductor layer

202b‧‧‧發光層 202b‧‧‧Lighting layer

202c‧‧‧第二電性半導體層 202c‧‧‧Second electrical semiconductor layer

211‧‧‧第一犧牲層 211‧‧‧First Sacrifice Layer

221‧‧‧第二基板 221‧‧‧second substrate

231,232,233,234及235‧‧‧半導體疊層塊 231, 232, 233, 234 and 235‧‧ ‧ semiconductor laminated blocks

Claims (10)

一種發光元件之製造方法,包括: 提供一第一基板及複數個半導體疊層塊於該第一基板上,各該複數個半導體疊層塊包括一第一電性半導體層、一發光層位於該第一電性半導體層之上、以及一第二電性半導體層位於該發光層之上,其中該第一基板上更包括一分隔道分隔兩相鄰之半導體疊層塊且該分隔道具有一寬度小於10μm; 實行一第一分離步驟,包括: 提供一第二基板,包括一第一電極; 實行一第一接合步驟,包括對位接合該複數之半導體疊層塊中之一第一半導體疊層塊與該第二基板,以使該第一半導體疊層塊與該第一電極對位連接並形成電性連接;以及 分離該第一半導體疊層塊與該第一基板,且該第一基板存留有該複數之半導體疊層塊中之一第二半導體疊層塊。A method for manufacturing a light-emitting device, comprising: providing a first substrate and a plurality of semiconductor stacked blocks on the first substrate, each of the plurality of semiconductor stacked blocks including a first electrical semiconductor layer, and a light-emitting layer disposed thereon The first electrically conductive semiconductor layer and the second electrically conductive semiconductor layer are disposed on the luminescent layer, wherein the first substrate further comprises a dividing channel separating two adjacent semiconductor stacked blocks and the separating prop has a width A first separating step is performed, comprising: providing a second substrate including a first electrode; performing a first bonding step including aligning bonding one of the plurality of semiconductor stacked blocks to the first semiconductor stacked Blocking the second semiconductor substrate such that the first semiconductor stacked block is aligned with the first electrode and electrically connected; and separating the first semiconductor stacked block from the first substrate, and the first substrate A second semiconductor stacked block of the plurality of semiconductor stacked blocks remains. 如申請專利範圍第1項所述之發光元件之製造方法,更包括: 實施一第二接合步驟包括對位接合該第一半導體疊層塊於該第二半導體疊層塊之上;以及 分離該第二半導體疊層塊與該第一基板。The method of manufacturing a light-emitting device according to claim 1, further comprising: performing a second bonding step of aligning the first semiconductor stacked block on the second semiconductor stacked block; and separating the a second semiconductor stacked block and the first substrate. 如申請專利範圍第2項所述之發光元件之製造方法,更包括形成一第二電極於該第二基板上且電性連接該第二半導體疊層塊。The method for manufacturing a light-emitting device according to claim 2, further comprising forming a second electrode on the second substrate and electrically connecting the second semiconductor stacked block. 一種發光元件之製造方法,包括: 提供一第一基板及複數個半導體疊層塊於該第一基板上,各該複數個半導體疊層塊包括一第一電性半導體層、一發光層位於該第一電性半導體層之上、以及一第二電性半導體層位於該發光層之上,其中該第一基板上更包括一分隔道分隔兩相鄰之半導體疊層塊且該分隔道具有一寬度小於10μm; 實行一第一分離步驟,包括: 提供一第二基板; 實行一第一接合步驟,包括接合該複數之半導體疊層塊中之一第一半導體疊層塊與該第二基板;以及 分離該第一半導體疊層塊與該第一基板,且該第一基板存留有該複數之半導體疊層塊中之一第二半導體疊層塊;以及 實施一第二接合步驟包括對位接合該第一半導體疊層塊與該第二半導體疊層塊。A method for manufacturing a light-emitting device, comprising: providing a first substrate and a plurality of semiconductor stacked blocks on the first substrate, each of the plurality of semiconductor stacked blocks including a first electrical semiconductor layer, and a light-emitting layer disposed thereon The first electrically conductive semiconductor layer and the second electrically conductive semiconductor layer are disposed on the luminescent layer, wherein the first substrate further comprises a dividing channel separating two adjacent semiconductor stacked blocks and the separating prop has a width a first separating step, comprising: providing a second substrate; performing a first bonding step comprising bonding one of the plurality of semiconductor stacked blocks and the second substrate; Separating the first semiconductor stacked block from the first substrate, and the first substrate retains one of the plurality of semiconductor stacked blocks; and performing a second bonding step including aligning the a first semiconductor stacked block and the second semiconductor stacked block. 如申請專利範圍第4項所述之發光元件之製造方法,更包含於該第二接合步驟後,分離該第一半導體疊層塊與該第二基板。The method of manufacturing a light-emitting device according to claim 4, further comprising, after the second bonding step, separating the first semiconductor stacked block and the second substrate. 如申請專利範圍第5項所述之發光元件之製造方法,更包括: 提供一第三基板,其中該第三基板更包括一第一電極; 實施一第三接合步驟包括對位接合該第一半導體疊層塊於該第三基板,使該第一半導體疊層塊與該第一電極對位連接且形成電性連接;以及 分離該第二半導體疊層塊與該第一基板。The method of manufacturing the illuminating device of claim 5, further comprising: providing a third substrate, wherein the third substrate further comprises a first electrode; performing a third bonding step comprising aligning the first The semiconductor stacked block is on the third substrate, the first semiconductor stacked block is aligned with the first electrode and electrically connected; and the second semiconductor stacked block is separated from the first substrate. 如申請專利範圍第6項所述之發光元件之製造方法,更包括形成一第二電極於該第三基板上且電性連接該第二半導體疊層塊。The method for manufacturing a light-emitting device according to claim 6, further comprising forming a second electrode on the third substrate and electrically connecting the second semiconductor stacked block. 如申請專利範圍第4項所述之發光元件之製造方法,更包括於該第二接合步驟後,分離該第二半導體疊層塊與該第一基板。The method of manufacturing a light-emitting device according to claim 4, further comprising, after the second bonding step, separating the second semiconductor stacked block from the first substrate. 如申請專利範圍第8項所述之發光元件之製造方法,更包括: 提供一第三基板,其中該第三基板更包括一第一電極; 實施一第三接合步驟包括對位接合該第二半導體疊層塊於該第三基板使該第二半導體疊層塊與該第一電極對位連接且形成電性連接;以及 分離該第一半導體疊層塊與該第二基板。The method of manufacturing the illuminating device of claim 8, further comprising: providing a third substrate, wherein the third substrate further comprises a first electrode; performing a third bonding step comprising aligning the second The semiconductor stacked block is connected to the first electrode and electrically connected to the first semiconductor stacked block on the third substrate; and the first semiconductor stacked block and the second substrate are separated. 如申請專利範圍第9項所述之發光元件之製造方法,更包括形成一第二電極於該第三基板上且電性連接該第一半導體疊層塊。The method of manufacturing a light-emitting device according to claim 9, further comprising forming a second electrode on the third substrate and electrically connecting the first semiconductor stacked block.
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