TWI559724B - Initial synchronization method and apparatus assisted by inherent diversity over time-varying frequency-selective fading channels - Google Patents

Description

Method and apparatus for initial synchronization using essentially diversity in a time varying and frequency selective decay channel environment

The present invention relates to a method and apparatus for initial synchronization, and more particularly to an initial synchronization method and apparatus for estimating timing error and frequency drift.

Timing recovery and carrier frequency offset (CFO) compensation are considered important steps in any wireless communication application. Among various wireless communication technologies, a Pseudo-Noise (PN) sequence is usually used as a training preamble for time synchronization. Although the PN sequence can achieve high correlation by using the advantages of PN matched filtering (MF), the PN sequence can support high-resolution time synchronization, but they are easily damaged by carrier frequency drift. The main reason is that the correlation between the received signal and the local PN sequence is unpredictable during the correlation period of the PN matched filter. The phase change of the period is destroyed, and there is also a non-negligible carrier frequency drift.

In wireless communication, the carrier frequency drifts The occurrence is mainly due to the mismatch of the local oscillator at the receiving end. At the same time, the relative movement between the transmitting end and the receiving end also causes a Doppler spread, which is inevitably surrounded by the surroundings. Caused by reflected waves. Even in high-speed mobile environments, carrier frequency drift is still more dramatic than the effect of the Doppler frequency domain on the receiver.

a special synchronous burst called double tweezer The dual-chirp signal has been discussed in the Geostationary Earth Orbit (GEO) Mobile Radio (GMR) mobile-satellite communication, and its characteristics are already in many papers. Studied. Many studies have used the 啁啾 signal as a training sequence for the estimation of timing synchronization and carrier frequency drift in a wireless Orthogonal Frequency Division Multiplexing (OFDM) communication system. Zadoff-Chu (ZC) is also a chirp-like sequence that has been adopted in the Third-Generation Partnership Project (3GPP) Long-Term Evo-lution (LTE). Used for random access preamble sequences, primary synchronization sequences for cell search, and reference sequences for channel estimation. The study of synchronization mechanisms generally estimates time error and carrier frequency drift through autocorrelation and cross-correlation assessment. However, accurate analysis based on statistical derivation has been ignored, especially in multipath decay channels.

It is an object of the present invention to provide a method and apparatus for initial synchronization using essentially diversity in a time varying and frequency selective decay channel environment, and to achieve more accurate timing error and frequency drift estimation based on a 耙-type architecture.

In view of this, the present invention provides an initial synchronization device for receiving a received signal, and the received signal includes a training sequence. The initial synchronization device includes an oversampling unit, a receive buffer, a channel estimation unit, D matched filter operation units, a time maximum ratio synthesis unit, and a time decision unit. The oversampling unit samples the received signal to obtain N oversampled signals. The receiving buffer is coupled to the oversampling unit and has N storage units for storing the 0th to the N -1th oversampling signals. The channel estimation unit is coupled to the receive buffer, and performs a channel estimation on the oversampled signal according to the local training sequence to obtain D channel weight coefficients. The local training sequence includes D discrete training signals, denoted as s [0], s [1], ..., s [ D -1].

Each matched filter operation unit has D inputs, and the Jth input of each matched filter operation unit receives the oversampled signals in the M _T × J receive buffers. Wherein, the m 'th matched filter operation unit of the K input terminal of the super-sampling signal and the discrete training signal s [MOD (K - m' )] conjugate for matched filtering operation to obtain the K-th matching operation result, The m'th matched filter operation unit synthesizes all the matching operation results into the m'th filter signal, where MOD( x ) represents the remainder after x is divided by D. Time of maximum ratio synthesizing unit is coupled to matched filtering operation of the D channel estimation means and said means for conjugate I-th second filtered signal and the I channel performs a weighting coefficient operation addition, to obtain the I-th Time weights add results. The time maximum ratio synthesis unit synthesizes all time weight addition results into a time synthesis signal.

Each preset time, the receiving buffer is used to replace the Mth storage unit with the data of the M -1 storage unit, and update the first storage unit, and generate a new time synthesis every preset time. The signal, wherein the Qth preset time, produces the Qth time synthesis signal. The time decision unit is coupled to the time maximum ratio synthesizing unit for collecting R time synthesis signals, performing a maximum estimation on the R time synthesis signals, finding a maximum time synthesis signal, and extracting a maximum time synthesis signal corresponding to the time. The time index is used as a timing error estimate. Wherein, the above D , N , and M _T are all a positive integer, and N M _T × D , J , K , m′ , and I are integers between 0 and D −1 , and the above M is a positive integer, and 2 M N , the above R is a positive integer, and the above Q is a real number.

The initial synchronization device according to the preferred embodiment of the present invention further includes a frequency maximum ratio synthesis unit, an array temporary storage circuit, a Fourier transform unit, and a frequency decision unit. The frequency maximum ratio synthesis unit is coupled to the D matched filter operation units and the channel estimation unit, and is configured to perform an addition of each matching operation result of the Pth matched filter operation unit and a conjugate of the corresponding channel weight coefficient. Operation. The U -matching operation result of the P- th matched filter operation unit is subjected to an addition operation with the conjugate of the U- th channel weight coefficient to obtain a U- th frequency weight addition result. Frequency maximum ratio synthesizing unit all the frequency weight addition result synthesized as a frequency synthesizer vector, the frequency synthesizer vector contains D frequency synthesized signal, wherein the first V th frequency synthesized signal lines for the first V th frequency all matched filtering operation corresponding to the unit The sum of the weighted bonus results.

Each preset time, the receiving buffer is used to replace the Mth storage unit with the data of the M -1 storage unit, and update the first storage unit, and the maximum frequency synthesis unit of the frequency is used for each preset time. A new frequency synthesis vector is produced. Wherein, the Qth preset time, the frequency maximum ratio synthesis unit outputs the Qth frequency synthesis vector. The array temporary storage circuit is coupled to the frequency maximum ratio synthesis unit for storing R frequency synthesis vectors. The Fourier transform unit is coupled to the array temporary storage circuit, and according to the timing error estimation value, a specific frequency synthesis vector is taken out from the array temporary storage circuit, and Fourier transform is performed to obtain a plurality of frequency domain conversion signals. The frequency decision unit is coupled to the Fourier transform unit, receives the plurality of frequency domain converted signals, performs a maximum estimation on the plurality of frequency domain converted signals, finds a maximum frequency domain converted signal, and extracts a maximum frequency domain converted signal. The corresponding frequency index is used as a frequency drift estimation value. Wherein, the above P , U , and V are integers between 0 and D -1.

The present invention further provides an initial synchronization method comprising the steps of: receiving a received signal, wherein the received signal includes a training sequence; sampling the received signal to obtain N oversampled signals; providing a receive buffer, the receive buffer having N stores a unit for storing the 0th to the N -1th oversampling signals; performing a channel estimation on the oversampled signals according to a local training sequence to obtain D channel weight coefficients, wherein the local training sequence includes D Discrete training signal, expressed as s [0], s [1],..., s [ D -1]; D correlation operations are performed to obtain D filtered signals, and in each correlation operation, the first M is received. _T × J oversampling a signal reception buffer to the reception buffer D for D super-sampled signal a correlation calculation, where, J = 0,1,2, ..., D -1, wherein each of a plurality of correlation operation includes matched filtering operation and a synthesizing operation, wherein the first m 'K th matched filtering operation based on a m _T × K oversampled discrete training signal and a signal correlation computation s [ MOD (K - m ')] conjugate for matched filtering operation, To give K-th matching operation results, wherein all of the matching operation result of the m 'th combination calculation based on the m' th of the synthesized correlation processing for the first m 'of filtering signals, wherein, the MOD (x) denotes dividing x by the remainder after D; for a time to maximum ratio synthesis calculation, the I-th filter signal and the second I channel weighting factor an addition operation to obtain the I-th temporal weighting addition result, all the time weight adduct The result is synthesized into a time synthesis signal; at each preset time, the Mth storage unit of the receiving buffer is replaced with the data of the Mth -1 storage unit, and the first storage unit is updated, and each preset time is Generating a new time synthesis signal, wherein the Qth preset time, the Qth time synthesis signal is generated; the R time synthesis signals are collected; and the time decision operation is performed, and the R time synthesis signals are subjected to a maximum value Estimate, find a maximum time synthesis signal, and take the time index corresponding to the maximum time synthesis signal as a timing error estimate. Where D , N , and M _T are all a positive integer, and N M _T × D , J , K , m′ , and I are integers between 0 and D -1, M is a positive integer, and 2 M N , R is a positive integer, and Q is a real number.

The spirit of the invention lies in the use of decision guidance (decision-directed) mechanism, based on the 耙-type architecture, collects the information energy (including: timing and frequency drift information) propagating in the multiple paths to achieve the gain of the inherent frequency diversity. The timing and frequency synchronization system can work in a mobile communication environment, multipath interference, and low signal to noise ratio environment.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

110, 410‧‧‧Oversampling unit

120, 420‧‧‧ Receive buffer

130, 430‧‧‧ channel estimation unit

140-1~140- D ‧‧‧ D matching filter arithmetic unit

150‧‧‧ time maximum ratio synthesis unit

160‧‧‧Time Estimation Unit

440-1~440- D ‧‧‧Upper matched filter arithmetic unit

445-1~445- D ‧‧‧Bottom matched filter arithmetic unit

450‧‧‧Upper time maximum ratio synthesis unit

455‧‧‧time maximum ratio synthesis unit

460‧‧‧Upper time decision making unit

465‧‧‧time decision making unit

470‧‧‧ time average circuit

1010‧‧‧Upper frequency maximum ratio synthesis unit

1020‧‧‧Bottom frequency maximum ratio synthesis unit

1030‧‧‧Upper Array Temporary Circuit

1035‧‧‧Lower array temporary storage circuit

1040‧‧‧Upper Fourier Transform Unit

1045‧‧‧Next Fourier transform unit

1050‧‧‧Upstream frequency decision unit

1055‧‧‧Under frequency decision making unit

1060‧‧‧frequency average circuit

S1301~1311‧‧‧ steps of the initial synchronization method of the embodiment of the present invention

S1401~1406‧‧‧ steps of the initial synchronization method of the embodiment of the present invention

1 and 2 are block diagrams showing an initial synchronization device according to an embodiment of the present invention.

Figure 3 is a schematic diagram showing the shape of a double 啁啾 bundle wave.

4 to 9 are system block diagrams showing a timing error estimation portion in an initial synchronization device according to an embodiment of the present invention.

10, 11 and 12 are block diagrams showing the system of frequency drift estimation in the initial synchronization device according to an embodiment of the present invention.

FIG. 13 is a flow chart showing an initial synchronization method according to an embodiment of the present invention.

FIG. 14 is a flow chart showing an initial synchronization method according to an embodiment of the present invention.

In the digital communication system, the training terminal is equipped with a training preamble, and the receiving end uses the received training preamble and the good autocorrelation of the training preamble to perform timing error and frequency. Estimation of drift. In the embodiment of the present invention, based on statistical derivation, an environment suitable for time-varying and frequency-selective decay channel is designed, and an initial synchronization device is performed for estimating the timing error. The initial synchronization device of the embodiment of the present invention is shown in FIGS. 1 and 2. 1 and 2 are block diagrams showing an initial synchronization device according to an embodiment of the present invention.

Referring to FIG. 1 and FIG. 2, the initial synchronization device includes an oversampling unit 110, a receiving buffer 120, a channel estimating unit 130, D matching filtering arithmetic units 140-1~140- D , and a time maximum ratio synthesizing unit 150. And a time estimating unit 160. The oversampling unit 110 samples a received signal r ( t + T ) to obtain N oversampled signals r _os [ n ]. The receiving buffer 120 is coupled to the oversampling unit 110 and has N storage units for storing the 0th to the N -1th oversampling signals. The channel estimation unit 130 is coupled to the receive buffer 120 for performing a channel estimation on the oversampled signal according to the local training sequence s [ n ] to obtain D channel weight coefficients, which are represented in the figure as .

The D matched filter operation units 140-1~140- D are all coupled to the receive buffer 120. Each matched filter operation unit has D inputs, and the Jth input of each matched filter operation unit receives the M _T × J received buffer oversampling signals. In this embodiment, the local training sequence includes D discrete training signals, denoted as s [0], s [1], ..., s [ D -1]. Wherein the first m 'K-th input terminal of the super-sampling signal and the discrete training signal s matching filter calculation unit [MOD (K - m') ] matched filtering operation to obtain the K-th matching operation result, wherein the first The m' matching filter operation units synthesize all the matching operation results into the m'th filter signal y _{m '} , where MOD( x ) represents the remainder after x is divided by D.

Referring to FIG. 2 , the time maximum ratio synthesis unit 150 is coupled to the D matched filter operation units 140-1 ～ 140- D and the channel estimation unit 130 described above. Time to maximum ratio combining unit and the I-th second filtered signal I channel weighting factor an addition operation to obtain the I-th time weight addition result. The time maximum ratio synthesizing unit 150 synthesizes all the time weight addition results into a time synthesizing signal y .

In this embodiment, at each preset time, the receiving buffer 120 is configured to replace the Mth storage unit with the data of the M -1 storage unit, and update the first storage unit, and each preset time is produced. A new time synthesis signal y is generated, wherein the Qth preset time, the Qth time synthesis signal is generated. The time estimating unit 160 is coupled to the time maximum ratio synthesizing unit 150 for collecting R time synthesizing signals, performing a maximum estimation on the R time synthesizing signals, finding a maximum time synthesizing signal, and extracting the maximum time synthesizing signal. The time index corresponding to the signal as a timing error estimate .

Wherein, the variables D , N , and M _T are all a positive integer, and N M _T × D , J , K , m′ , and I are integers between 0 and D -1, M is a positive integer, and 2 M N , R is a positive integer, and Q is a real number.

Hereinafter, in order to facilitate the description of the present embodiment, the training preamble signal is, for example, a dual-chirp burst. Here, the fundamental frequency equivalent signal mathematical expression of the double 啁啾 burst can be expressed as follows:

Where μ is a parameter used to determine the sweeping bandwidth. In the above mathematical formula, the double-cluster burst contains up-chirp bursts ( t ) and down-chirp bursts ( t ), its mathematical expression is expressed as

In the above formula, Π( t ) is a unit rectangular pulse, and the mathematical expression can be expressed as

( t ) and ( t ) the instantaneous phase and frequency are expressed as Where - T /2 < t < T /2. Ups and downs (T) is the instantaneous frequency - extending μT / 2 to μT / 2, in other words, the frequency signals from low frequency will rise over a given period. Down frequency The instantaneous frequency of ( t ) extends from μT /2 to - μT /2, in other words, the frequency of the signal drops from high frequency to low frequency for a given period of time. Therefore, during the period ( -T /2, T /2), the frequency range of the double-twisted burst is B = μT . Figure 3 is a schematic diagram showing the shape of a double 啁啾 bundle wave. In Fig. 3, the abscissa is time and the ordinate is frequency. Since the double 啁啾 bundle wave has good autocorrelation property, the transmitting end sends out the double 啁啾 burst, and the receiving end can calculate and estimate the time and frequency offset by matching the filter and the peak time obtained after the decision. Although the present embodiment is based on a double plexus, it is known to those skilled in the art that the present invention can also be applied to other types of training preamble signals such as PN sequences or chirp-like sequences. Training sequence.

For application in a causal system, the above signal s' ( t ) is shifted by T /2 in the time domain, denoted as s ( t ). s ( t )= s' ( t -( T /2)), expressed as where

In the embodiment of the present invention, based on statistical derivation, an environment suitable for time-varying and frequency-selective decay channel is designed, and an initial synchronization device is performed for estimating the timing error and the carrier frequency offset. 4 and 9 are system block diagrams showing a timing error estimation portion in an initial synchronization device according to an embodiment of the present invention.

Please refer to Figure 4 first, the high frequency receiving signal r' ( t + T ) is down-converted and input to an analog low-pass filter to obtain a received signal r ( t + T ). The bandwidth of the analog low-pass filter can be designed, for example, as B /2. The above received signal mathematical expression can be expressed as

Indicates the Tap-weighting coefficient of the mth complex channel, τ and ε represent the estimated timing error and CFO, For the initial phase error. T _s =1/ B , B is the transmitted preamble or the null-to-null bandwidth of the transmitted training signal s ( t ). Among them, in the above mathematical formula, , m =0,1,2,..., M -1, ω' ( t ) denotes additive white Gaussian noise AWGN, ω' ( t )= ( t )+ ( t ).

Then, after the received signal r ( t + T ) is sampled by an oversampling unit 410, an oversampling signal r _os [ n ] is obtained and stored in a receiving buffer 420. The sampling frequency in this embodiment is designed to be 1/ t _s , and its value is expressed as M _T / T _s , T _s =1/ B . In other words, for each symbol time T _s , the received signal is sampled M _T times. In this embodiment, the length N of the receive buffer is designed to be N. M _T D . Where M _T and D are positive integers and their values are hardware design values. The value of the above supersampled signal r _os [ n ] can be expressed as r _os [ n ]= r ( nt _s + T ).

The channel estimation unit 430 receives the above-mentioned oversampling signal r _os [ n ], and uses the oversampled signal r _os [ n ] to perform channel estimation, and takes out an oversampled signal r _os [ n ] at intervals M _T . Channel estimation. The above-mentioned extracted oversampling signals are denoted as r _os [ n ], r _os [ n + M _T ], ..., r _os [ n + ( D -1) M _T ], and the number of extracted oversampling signals is D. In other words, multiple oversampled signals are extracted at intervals of T _s . Next, the plurality of oversampled signals taken are respectively multiplied by the local training signal s [ n ], and then obtained by using a plurality of digital low-pass filters to obtain a plurality of channel weight coefficients, which are expressed as . In this embodiment, the local training signal is, for example, a digital signal transmitted by a double burst.

In the channel estimation unit of the embodiment of the present invention, the plurality of digital low-pass filters are implemented by a plurality of integrated-and-dump filters (I/D). However, those skilled in the art should know that a plurality of digital low-pass filters can also use a Finite Impulse Response (FIR) filter or an Infinite Impulse Response (FIR) filter, and the like. The present invention is implemented to implement the present invention. In addition, although the channel estimation unit 430 of the embodiment extracts multiple channel weight coefficients through multiple multipliers and multiple digital low-pass filters However, those skilled in the art should know that the channel estimation technique capable of extracting the channel weight coefficient can be applied to the present invention. Therefore, the channel estimation implementation method of the present embodiment cannot be used to limit the present invention.

Please refer to FIG. 5 again. The embodiment further includes D up-Branch (UB) matching filter operation units 440-1~440- D and D down-Branch (DB) matching filter operation units. 445-1~445- D are respectively coupled to the receiving buffer 420. 420 stored on each branch matched filtering operation units 440-1 ~ 440- D are each lower branch received matched filtering operation units 445-1 ~ 445- D buffer oversampled signal r _os [n], it The received signal is r _os [ n ], r _os [ n + M _T ],..., r _os [ n +( D -1) M _T ].

In order to illustrate aspects of the present embodiment, referred to as first m 'of the matched filter calculating means branched (m' th UB MF) 'means branched matched filtering operation (next m' th DB MF) as well as the m described. Please refer to FIG. 6, FIG. 6 illustrates a first m 'of the upper branch of the first matched filtering operation unit m' is a circuit block at a matched filtering operation support unit. The m'th upper matched filter operation unit ( m' th UB MF) has D inputs coupled to the receive buffer 420 for receiving the oversampled signals r _os [ n ], r _os [ n + M _T ] ,..., r _os [ n +( D -1) M _T ], wherein each of the extracted signals is multiplied by the D multipliers and multiplied by the conjugate of the corresponding upper training sequence to obtain D upper branches. The result of the matching operation is expressed as z _{m' ; u , 0} , z _{m' ; u , 1} ,..., z _{m' ; u, D -1} . All the results of the upper matching operation will be synthesized into the m'th upper branch filtering signal, denoted as y _{m' ; u} . The conjugate of the corresponding upper training sequence multiplied by the multiplier is expressed as , ,..., . In this embodiment, the local training sequence includes an upper training sequence and a lower training sequence, wherein the upper training sequence corresponds to the above-mentioned up-frequency bursting s _u ( t ), and the lower training sequence corresponds to the above-mentioned descending Frequency 啁啾s _d ( t ). Wherein, the subscript d is represented as down frequency 啁啾, and the subscript u is represented as up frequency 啁啾.

Of m 'of the matched filter calculating means branched (m' th DB MF) having a D input terminal coupled to the receiving buffer 420 for receiving the oversampled signal _{r os [n], r os} [n + M T] ,..., r _os [ n +( D -1) M _T ], wherein each of the extracted signals is multiplied by the D multipliers and multiplied by the conjugate of the corresponding lower training sequence to obtain D lower branches. The result of the matching operation is expressed as z _{m' ; d , 0} , z _{m' ; d , 1} , ..., z _{m' ; d , D -1} . All the results of the next branch matching operation will be synthesized into the m'th lower branch filtering signal, denoted as y _{m' ; d} . The conjugate of the corresponding lower training sequence multiplied by the above multiplier is expressed as , ,..., .

According to the operation of the matched filter operation unit, in the m'th upper matched filter operation unit ( m' th UB MF), the sequence of the oversampled signal is multiplied by the training sequence (up-frequency 啁啾 发s _u) Conjugation of ( t )). Lower branched matched filter calculating means (m 'th DB MF), the oversampled signal sequence is multiplied by sequences (down-chirped burst s _d (t)) of conjugate. In terms of continuous time, according to the above formula (1), the m'th upper branch matching filter operation unit ( m' th UB MF) and the m'th lower branch matching filter operation unit ( m' th DB MF) The impulse response can be expressed as: _{Wherein, h m '; u (t} ) of m' of the upper branch matched filter calculating means (m 'th UB MF) of the impulse _{response, h m'; d (t} ) for the first m 'of the lower supporting matched filtering operation means (m 'th DB MF) of the impulse response. In discrete time, the above impulse response can be expressed as follows:

In the above mathematical expression, | x | _D represents the remainder after x is divided by D. The first m 'of the upper branch matched filter calculating means (m' th UB MF) obtained of m 'of the branched filtered signal may be expressed as _{y m'; u [n]} = y m '; u ((n + 1/2) T _s ). Of m 'of the lower supporting matched filter calculating means (m' th DB MF) obtained of m 'of the lower supporting filtered signal is denoted as _{y m'; d [n]} = y m '; d ((n + 1 / 2) T _s ).

Please refer to FIG. 7 and FIG. 8 . FIG. 7 illustrates circuit blocks within the upper time maximum ratio combining unit 450, and FIG. 8 illustrates circuit blocks of the lower branch time maximum ratio combining unit 455 . It can be seen from the above operation that the D upper matched filter operation units obtain D upper filter signals y _{0; u} , y _{1; u} , ..., y _{D -1; u} . Next, the Up-Branch Maximal Ratio Combining (UB MRC) unit 450 receives D upper-branch filter signals y _{0; u} , y _{1; u} , . . . , y _{D -1; u} . In the upper time maximum ratio synthesizing unit, the upper branch signal y _{0; u} , y _{1; u} , ..., y _{D -1; u} are multiplied by the conjugate of the channel weight coefficient obtained by the channel estimating unit 430, respectively. , ,..., To get multiple products. Then, a plurality of products will be added as a superimposed time synthesis signal, denoted as y _u .

By the same token, D lower matching filter operation units will obtain D lower branch filter signals y _{0; d} , y _{1; d} ,..., y _{D -1; d} , input to the next time maximum ratio synthesis Unit 455. In the lower-branch maximum ratio synthesis unit, the lower-branch filter signal y _{0; d} , y _{1; d} , ..., y _{D -1; d is} multiplied by the conjugate of the channel weight coefficient obtained by the channel estimation unit 430, respectively. , ,..., To get multiple products. Then, multiple products will be added as a sub-time synthesis signal, denoted as y _d .

Next, please continue to refer to FIG. 9, the upper time synthesis signal y _u will be input to an upper time decision unit 460. The lower time synthesis signal y _d will be input to the next branch time decision unit 465. The above y _u and y _d are obtained by receiving the oversampled signal r _os [ n ], r _os [ n + M _T ], ..., r _os [ n + ( D -1) M _T ] from the receiving buffer 420. Obtained later. However, in this embodiment, the supersampling signal stored in the receive buffer 420 will be updated at each preset time, for example, the Mth storage unit in the receive buffer 420 is stored in the M -1th. The data of the unit is replaced. The last storage unit will store a newly received oversampled signal, and the oversampled signal stored in the first storage unit before the original update will be discarded.

Therefore, in the present embodiment, after the receive buffer 420 is updated at the next preset time, each of the upper branch matching filter operation units 440-1~440- D and each of the lower branch matching filter operation units 445-1~445- D The received signal is r _os [ n +1], r _os [ n +1+ M _T ],..., r _os [ n +1+( D -1) M _T ], and a new one is generated. The filter signal y _{0; u} , y _{1; u} ,..., y _{D -1; u} and the new lower filter signal y _{0; d} , y _{1; d} ,..., y _{D -1; d} . The upper branch time maximum ratio synthesizing unit 450 will generate a new up-time synthesis signal y _u , and the lower-branch time maximum ratio synthesizing unit 455 will generate a new lower-branch synthesis signal y _d .

By analogy, after a plurality of preset times, the upper branch time decision unit 460 will collect the upper time synthesis signal y _{u of} different time indexes, and the lower time decision unit 465 will also collect the lower time of the different time index. Synthetic signal y _d . The upper branch time decision unit 460 will find a maximum upper time synthesis signal in the plurality of upper time synthesis signals y _u , and take out the corresponding time index as an upper branch timing error estimation value, expressed as . Similarly, the branch decision unit 465 will identify the time a maximum signal in the branched synthesis time of the plurality of branch signal y _d in the synthesis time, and remove the corresponding time index, as the timing error estimate what branched, represents for . Finally, the time averaging circuit 470 will calculate the upper timing error estimate. Estimated value of the timing error with the lower branch Average value, and output the timing error estimated in this embodiment , the value is .

It can be seen from the operation of the timing error estimation that the embodiment of the present invention utilizes a plurality of time synthesis signals y _u and y _d to find the maximum value to determine the timing error. The above y _u and y _d are to find the correlation of training sequences for different times via a plurality of matched filters. In addition, in this embodiment, the channel weight coefficient on each path is also utilized, and the correlation calculated by each matched filter is subjected to maximum proportional synthesis before the maximum value is determined. In other words, the embodiment of the present invention uses diversity combining to achieve more accurate timing error estimation under the 耙-style architecture.

The initial synchronization device proposed by the embodiment of the present invention can also be used to estimate the carrier frequency drift CFO, and does not need to re-calculate the received signal. In the embodiment of the present invention, the intermediate product of the matched filtering operation may be obtained by using the above-mentioned upper matching filtering operation unit and the lower matching filtering operation unit to perform estimation of carrier frequency drift. Please refer back to FIG. 6, according to the first m 'matches a branching filter operation unit (m' operation th UB MF) is seen, a plurality of multipliers to obtain the matching operation result of the plurality of branched z _{m '; u, 0,} z _{m' ; u ,1} ,..., z _{m' ; u , D -1} . Also, according to the first m 'of the matched filter calculating means branched (m' operation th DB MF) is seen, a plurality of multipliers to obtain a plurality of lower supporting matching operation result _{z m '; d, 0,} z m'; _{d , 1} ,..., z _{m' ; d,D -1} .

10 and 11 are block diagrams showing the system of the frequency drift estimation portion in the initial synchronization device according to the embodiment of the present invention. Referring to FIG. 10, the upper frequency maximum ratio synthesizing unit 1010 has D input terminals for respectively receiving the upper matching operation results generated by the D upper matching filtering operation units 440-1~440- D . The upper branch matching operation result generated by each of the upper branch matching filter operation units 440-1~440- D may constitute a first vector. Taking the m'th upper matched filtering operation unit ( m' th UB MF) as an example, the first vector can be expressed as . D upper matching filter operation units 440-1~440- D will obtain D first vectors ,..., . In the upper branch frequency maximum ratio synthesizing unit 1010, D first vectors ,..., The conjugate of the channel weight coefficient obtained by the channel estimation unit 430 is respectively multiplied , ,..., To get multiple products. Then, multiple products will be added as an upper frequency domain synthesis vector, expressed as . The length of the vector is D , and the mathematical expression can be expressed as .

Referring to FIG. 11, the lower-frequency maximum ratio synthesizing unit 1020 has D input terminals for respectively receiving the lower-branch matching operation results generated by the D lower-branch matching filter arithmetic units 445-1~445- D . The result of the lower branch matching operation generated by each of the lower matched filtering operation units 445-1 to 445- D may constitute a second vector. In the first m 'of the matched filter calculating means branched (m' th DB MF) as an example, the second vector can be represented as . D lower matching filter operation units 445-1~445- D will get D second vectors ,..., . In the lower frequency maximum ratio synthesis unit 1020, D second vectors ,..., The conjugate of the channel weight coefficient obtained by the channel estimation unit 430 is respectively multiplied , ,..., To get multiple products. Then, multiple products will be added as the next frequency domain synthesis vector, expressed as . The length of the vector is D , and the mathematical expression can be expressed as .

Please continue to refer to Figure 12, the upper frequency domain synthesis sequence An upper array array temporary storage circuit 1030 will be placed. In order to facilitate the description of the embodiment of the present invention, in FIG. 12, the upper array array temporary storage circuit 1030 is shown in the form of a matrix, and the upper frequency domain synthesis unit 1010 outputs the upper frequency domain synthesis vector. For example, it is placed in the first row of the upper array temporary storage circuit 1030. Similarly, the lower frequency domain synthesis vector output by the lower frequency maximum ratio synthesis unit 1020 For example, it is placed in the first row of the lower array array temporary storage circuit 1035.

As in the above description of the estimation time error estimation section, in the present embodiment, the pre-sampling signal r _os [ n ] temporarily stored in the reception buffer 220 will be updated at each preset time, and therefore, each on the upper The branch matching filter operation units 440-1~440- D and each of the lower branch matching filter operation units 445-1~445- D will generate a new vector as well as . The upper branch frequency maximum ratio synthesizing unit 1010 and the lower branch frequency maximum ratio synthesizing unit 1020 will also calculate a new frequency synthesizing vector. versus .

Updated upper frequency synthesis vector It will continue to be placed in the second row in the upper array temporary storage circuit 1030. Here, the upper array temporary storage circuit 1030 is, for example, a shift register, and therefore, when the updated upper frequency synthesis vector After being stored in the upper array temporary storage circuit 1030, the data stored in the first row in the upper array temporary storage circuit 1030, that is, the upper frequency synthesis vector obtained from the previous preset time observation time , will be moved right to the second row in the upper array temporary storage circuit 1030. Similarly, the lower array temporary storage circuit 1035 is, for example, a shift register, when the updated lower frequency synthesis vector After being stored in the first row in the lower array temporary storage circuit 1035, the data originally stored in the first row in the lower array temporary storage circuit 1035, that is, the lower frequency obtained by the previous preset time observation time Composite vector , will be moved right to the second row in the lower array temporary storage circuit 1035. By analogy, each row in the upper array temporary storage circuit 1030 and the lower array temporary storage circuit 1035 will be sequentially stored in the upper frequency synthesis vector of different time indexes. Synthetic vector with lower frequency .

The upper Fourier transform unit 1040 estimates the timing error calculated according to the time averaging circuit 470. , taken out from the upper array temporary storage circuit 1030 Corresponding row vector, that is, take out The specific upper frequency synthesis vector corresponding to the time index of the representative . The upper branch Fourier transform unit 1040 synthesizes a specific upper frequency synthesis vector Fourier transform is performed to obtain a plurality of upper frequency domain conversion signals. Then, the upper branch frequency decision unit 1050 finds an upper frequency domain conversion signal having a maximum value in the plurality of upper frequency domain conversion signals, and extracts a frequency index corresponding to the upper frequency domain conversion signal having the maximum value as An upper frequency drift estimate, expressed as .

Similarly, the lower Fourier transform unit 1045 estimates the timing error based on the time averaging circuit 470. , taken out from the lower array temporary storage circuit 1035 Corresponding row vector, that is, take out The specific lower frequency synthesis vector corresponding to the time index represented . The lower branch Fourier transform unit 1045 synthesizes a specific lower frequency synthesis vector Fourier transform is performed to obtain a plurality of lower frequency domain conversion signals. Next, the lower frequency decision unit 1055 finds a lower frequency domain conversion signal having a maximum value in the plurality of lower frequency domain conversion signals, and extracts a frequency index corresponding to the lower frequency domain conversion signal having the maximum value as The estimated frequency drift of the branch is expressed as . Finally, the frequency average circuit 1060 calculates versus Average value to obtain an estimate of carrier frequency drift , the value is .

The above-described upper branch Fourier transform unit 1040 And the lower Fourier transform unit 1045, for example, using fast Fourier transform real Now. In this embodiment, a zero padding unit may be coupled between the upper branch array unit 1040 and the upper array array temporary storage circuit 1030, and the row vector extracted by the upper array array temporary storage circuit 1030 will be complemented. After the zero operation, the Fourier transform is performed. Similarly, in this embodiment, a zero padding unit may be coupled between the lower branch Fourier transform unit 1045 and the lower array array temporary storage circuit 1035, and the row vector for extracting the lower array array temporary storage circuit 1035 will be performed. After the zero-padding operation, the Fourier transform is performed. The above zero-padding operation can improve the frequency domain accuracy of the estimation, and the line vector obtained can be added to the power of 2, and then the fast Fourier transform is performed.

From the estimation operation of the above frequency drift, the frequency synthesis vector is known. versus It is equivalent to the product sequence obtained by multiplying the received signal by the corresponding training sequence, and the product sequence is equivalent to a convolution operation after performing Fourier transform, that is, performing a correlation operation or a matching filtering operation. The above frequency decision unit is equivalent to finding the maximum correlation value, that is, the frequency adjustment value required for frequency alignment.

In the upper and lower array temporary storage circuits 1030 and 1035, the timing error is taken out. The sum of the corresponding row vectors is the time composite signal y _u and y _d having the largest value. And the above timing error The corresponding row vector is equivalent to finding the vector with the smallest time error versus .

For double-twisted bursts, the transmitted up-converted and down-converted channels pass through the channel with only a small amount of movement in time. However, due to the inverse relationship between the up-conversion and the time error of the down-conversion, the center value obtained after averaging has no timing error. In this embodiment, the timing error estimates of the up-frequency and down-frequency 计算 calculated by using the upper branch and the lower branch are separately calculated. versus And then take the average to get a timing error center value Therefore, in the present embodiment, accurate frequency drift estimation is performed in the case of timing error alignment, that is, without timing error.

In the above embodiment, the upper and lower array temporary storage circuits 1030 and 1035 are, for example, a matrix arrangement type of registers. However, those of ordinary skill in the art should be aware that as long as it is a frequency synthesis vector capable of storing different time indices versus The memory can be applied to the present invention, and therefore, the present invention does not limit the aspect of the array temporary storage circuit.

According to the operation of the initial synchronization device described above, An embodiment of the present invention can generalize an initial synchronization method. FIG. 13 is a flow chart showing the steps of the initial synchronization method according to an embodiment of the present invention. Referring to FIG. 13, the initial synchronization method of this embodiment includes the following steps: Step S1301: Start the initial synchronization method of the embodiment of the present invention.

Step S1302: Receive a received signal, where the received signal includes a training sequence transmitted by the transmitting end. As in the operation of FIG. 4 above, the high frequency signal received by the receiving end is down-converted and filtered to obtain a received signal, which is expressed as r ( t + T ).

Step S1303: sampling the received signal to obtain N oversampled signals. As with the oversampling unit 410 in FIG. 4 above, after the received signal is sampled, an oversampled signal is obtained, denoted as r _os [ n ]. Among them, the sampling frequency is designed, for example, as M _T / T _s .

Step S1304: Providing a receive buffer, the receive buffer having N storage units for storing the 0th to the N -1th oversampled signals. Like the receive buffer 420 in FIG. 4 above, the oversampled signals r _os [ n ] are sequentially stored in the receive buffer 420.

Step S1305: Perform a channel estimation on the oversampled signal r _os [ n ] according to a local training sequence to obtain D channel weight coefficients. As with the operation of the channel estimation unit 430 in FIG. 4 above, a plurality of multipliers and a plurality of digital low-pass filters are used to extract a plurality of channel weight coefficients. . In addition, although the channel estimation unit 430 of the embodiment extracts multiple channel weight coefficients through multiple multipliers and multiple digital low-pass filters However, those skilled in the art should know that the channel estimation technique capable of extracting the channel weight coefficient can be applied to the present invention. Therefore, the channel estimation implementation method of the present embodiment cannot be used to limit the present invention.

Step S1306: D correlation operations are performed to obtain D filtered signals. Wherein, the m 'th correlation calculation example of FIG. 6 m above the' branch matched filter operation unit (m 'th UB MF) of the previous operation. As is apparent from the above-described fifth and sixth drawings, in the present embodiment, when calculating the correlation, a plurality of upper-branch matching filter arithmetic units and a plurality of lower-branch matching filter arithmetic units are used. However, those skilled in the art should be aware that the present invention can be selected by the designer according to the channel condition of the actual application, the aspect of the training sequence or the hardware complexity, etc., to select the upper matching filter operation unit or the lower branch. Match one of the filter operation units and select the number of matched filter operation units.

Step S1307: Perform a time maximum ratio synthesis operation. A time synthesis signal is generated via the time maximum ratio synthesis operation, and the time maximum ratio synthesis operation is, for example, the operation of the upper time maximum ratio synthesis unit 450 in the above-described FIG. As is apparent from the above descriptions of Figs. 7 and 8, the present embodiment employs the maximum ratio synthesis operation of the upper branch time and the maximum ratio synthesis operation of the lower branch time. However, those skilled in the art should be aware that the present invention can be selected by the designer according to the channel condition of the actual application, the aspect of the training sequence or the hardware complexity, etc., and the maximum ratio synthesis operation or the lower time is selected. One of the maximum proportional synthesis operations.

Step S1308: The receiving buffer is updated every preset time, and a new time synthesizing signal is generated every preset time. In this embodiment, the receive buffer is, for example, a shift register. When a new oversampled signal is input to the receive register, each data in the storage unit will move to the right, and the rightmost storage unit The signal inside will be discarded. Taking Figure 4 as an example, for the next preset time, the new oversampled signal is r _os [ n + N ], and the discarded oversampled signal is r _os [ n ]. After receiving the buffer update, the above steps S1305 to 1307 are repeated to generate a new time synthesis signal.

Step S1309: Collect R time synthesis signals.

Step S1310: Perform a time decision operation. As in the operation of FIG. 9 above, synthesizing signals at a plurality of times to find a maximum time synthesis signal, and taking out the time corresponding to the maximum time synthesis signal Quoted as a timing error estimate. In the above-mentioned ninth figure, the present embodiment uses the upper branch and the lower branch time decision unit, and uses the time averaging circuit 470 to take the average value as the timing error estimated value. However, those skilled in the art should be aware that the present invention can be selected by the designer according to the channel conditions of the actual application, the aspect of the training sequence, or the hardware complexity, etc., to select the time-of-flight decision-making unit or the time of the branch. One of the decision units.

Step S1311: Ending the initial synchronization method of the embodiment of the present invention.

In the present embodiment, the initial synchronization method only estimates the time error. In order to obtain more accurate synchronization information, another embodiment will be presented below to explain how frequency drift can be estimated by the present invention. FIG. 14 is a flow chart showing the steps of the initial synchronization method according to an embodiment of the present invention. Referring to FIG. 14, the initial synchronization method of this embodiment includes the following steps: Step S1400: Start the initial synchronization method of the embodiment of the present invention.

Step S1401: Perform a frequency maximum ratio synthesis operation. Step S1401 is operated as the upper frequency maximum ratio synthesizing unit 1010 in the above-described Fig. 10 to obtain an upper frequency synthesizing vector. As is apparent from the above-described 10th and 11th drawings, the present embodiment employs the upper branch frequency maximum ratio synthesizing unit 1010 and the lower branch frequency maximum ratio synthesizing unit 1020. However, those skilled in the art should know that the present invention can be selected by the designer according to the channel condition of the actual application, the aspect of the training sequence or the hardware complexity, etc., and the maximum ratio of the upper frequency is selected. One of the synthesis unit or the maximum ratio synthesis unit of the lower branch frequency.

Step S1402: The receiving buffer is updated every preset time, and a new frequency synthesis vector is generated every preset time. In this embodiment, the receive buffer is, for example, a shift register. When a new oversampled signal is input to the receive register, each data in the storage unit will move to the right, and the rightmost storage unit The signal inside will be discarded. Taking Figure 4 as an example, for the next preset time, the new oversampled signal is r _os [ n + N ], and the discarded oversampled signal is r _os [ n ]. After receiving the buffer update, the above step S1401 is repeated to generate a new frequency synthesis vector.

Step S1403: Collecting a plurality of frequency synthesis vectors, such as the above-mentioned upper array array temporary storage circuit 1030 and the lower branch array temporary storage circuit 1035, sequentially storing the upper frequency synthesis vectors generated at each preset time. Synthetic vector with lower frequency .

Step S1404: Extract a specific frequency synthesis vector from the plurality of frequency synthesis vectors according to the timing error estimation value, perform Fourier transform, and obtain a plurality of frequency domain conversion signals. Step S1404 is like the operation of the upper branch Fourier transform unit 1040, and after the specific frequency synthesis vector is taken out, a zero-padding operation can also be performed to improve the frequency domain accuracy.

Step S1405: Perform a frequency decision operation, perform a maximum value estimation on the plurality of frequency domain conversion signals, find a maximum frequency domain conversion signal, and take out a frequency index corresponding to the maximum frequency domain conversion signal as a frequency drift estimation. Measured value. Step S1405 is like the upper branch frequency decision unit 1050 in the above-described Fig. 12.

The operation of Fig. 12 in this embodiment can be divided into the operation of the upper branch and the operation of the lower branch. However, those skilled in the art should be aware that the present invention can be selected by the designer according to the channel condition of the actual application, the aspect of the training sequence, or the hardware complexity, etc., and only the upper array array temporary storage circuit 1030 is selected. The upper Fourier transform unit 1040 and the upper branch frequency decision unit 1050. In the embodiment of Fig. 12, both the upper branch frequency decision unit 1050 and the lower branch frequency decision unit 1055 generate frequency drift estimation values, respectively versus . In this embodiment, the frequency decision operation of the above step S1405 further includes estimating the frequency drift value. versus Take the average and use this average as the frequency drift estimate.

Step S1406: Ending the implementation of the present invention The initial synchronization method of the example.

In summary, the present invention has at least the following advantages:

1. From the operation of the timing error estimation described above, the embodiment of the present invention utilizes a plurality of time synthesis signals y _u and y _d to find a maximum value to determine a timing error. The above y _u and y _d are to find the correlation of training sequences for different times via a plurality of matched filters. In addition, in this embodiment, the channel weight coefficient on each path is also utilized, and the correlation calculated by each matched filter is subjected to maximum proportional synthesis, and then the maximum value is determined. In other words, the embodiment of the present invention facilitates more accurate timing error estimation by using diversity combining under the 耙-type architecture.

2. In the embodiment of the present invention, when estimating the frequency drift, a plurality of products in the matched filter operation unit are used, in other words, The intermediate products produced in the estimation of the timing error are utilized, thereby reducing the amount of calculation of the estimated frequency drift.

3. The embodiment of the present invention utilizes the timing error estimation value to find out the product of the product having the greatest time correlation in the case of timing alignment, and then performs the estimation of the frequency drift. In other words, the embodiment of the present invention performs accurate frequency drift estimation without timing error.

The specific embodiments of the present invention are intended to be illustrative only and not to limit the invention to the above embodiments, without departing from the spirit of the invention and the following claims. The scope of the invention and the various changes made are within the scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S1301~1311‧‧‧ steps of the initial synchronization method of the embodiment of the present invention

Claims (17)

An initial synchronization device is configured to receive a received signal, wherein the received signal includes a training sequence, the initial synchronization device includes: an oversampling unit that samples the received signal to obtain N oversampled signals; and a receive buffer coupled Connected to the oversampling unit, having N storage units for storing 0th to N -1th oversampling signals; a channel estimation unit coupled to the receiving buffer for performing according to a local training sequence The oversampling signal performs a channel estimation to obtain D channel weight coefficients, wherein the local training sequence includes D discrete training signals, denoted as s [0], s [1], ..., s [ D -1]; D means a matched filtering operation, each of the matched filter calculating means has a D input terminal, the J input of each of a matched filter operation unit receiving a first M _T × J oversampled receive buffer signal, wherein the first m 'K-th input terminal of the super-sampled signal matching filter operation unit with the discrete training signal s [MOD (K-m' )] conjugate for matched filtering operation to obtain the K-th matching operation result , where the m'th match The filtering operation unit synthesizes all the matching operation results into the m'th filtering signal, where MOD( x ) represents the remainder after x is divided by D ; a time maximum ratio combining unit is coupled to the D matching filtering operation units and said channel estimation unit, to the I-th filter conjugated signal of I channel and weighting coefficients are an addition operation to obtain the I-th temporal weighting addition result, wherein the maximum ratio synthesizing unit time All the time weight addition results are combined into a time synthesis signal, wherein the receiving buffer is used to replace the Mth storage unit with the data of the Mth -1 storage unit and update the first one for each preset time. a storage unit, and each time preset, a new time synthesis signal is generated, wherein the Qth preset time, the Qth time synthesis signal is generated; and the time decision unit is coupled to the time maximum ratio synthesis unit, corresponding to the collected R signal synthesis time, the synthesis time of R signal estimation performed a maximum, the maximum time to find a synthesis signal, and the maximum time taken resultant signal Between the index, as a timing error estimate; wherein, D, N, M _T are both a positive integer, and N M _T × D , J , K, m′, I are all integers between 0 and D -1, M is a positive integer, and 2 M N , R is a positive integer, and Q is a real number. The initial synchronization device according to claim 1, wherein the local training sequence includes an upper training sequence and a lower training sequence, and the D matching filtering operation units are D upper matching filtering operation units, The time maximum ratio synthesis unit is a maximum time ratio synthesis unit, and the time decision unit is a time division decision unit, wherein the lower training sequence includes D lower branch discrete training signals, expressed as s _d [0], s _d [1],..., s _d [ D -1], the initial synchronization device further comprises: D lower branch matching filtering operation units, each of the lower matching filtering operation units having D input terminals, each a lower supporting matched filtering operation means the J input terminal for receiving the first m _T × J oversampled received signal buffers, wherein the first m 'of the matched filtering operation support means of the K signal input terminal of an oversampling Performing a matching filtering operation with the conjugate of the lower discrete training signal s _d [MOD( K-m' )] to obtain a Kth lower branch matching operation result, wherein the m'th lower branch matching filtering operation unit will be all under Match matching Synthesized for the first m 'of the lower supporting filtered signal; branched at the time maximum ratio combining unit, coupled to the lower branch of the D matched filter calculating means, and the channel estimation unit to the I-th and the first lower branch filtered signal I channel weights conjugated weighting coefficients is a an addition operation to obtain the I-th lower supporting temporal weighting addition results, wherein the lower branch time maximum ratio combining unit all the lower branch time weight addition result of the synthesis is about support a time synthesis signal, wherein, at each preset time, the receiving buffer is used to replace the Mth storage unit with the data of the M -1 storage unit, and update the first storage unit, and each preset time, Generating a new time-synthesis signal, wherein the Qth preset time, the Q- th time-synthesis signal is generated; the next-time decision-making unit is coupled to the bottom-time maximum-scale synthesis unit to collect R synthesis of the branched time signal, the time above the lower supporting R a resultant signal for estimating a maximum, the maximum branched find a synthesis time signal, and remove the time corresponding to the maximum time the branched synthesis signal a time-averaged circuit, coupled to the upper-branch time decision unit and the lower-branch time decision unit, receiving the timing error estimate value and the lower-branch timing error estimate value, An averaging operation is performed to obtain an average timing error value as the timing error estimate. The initial synchronization device described in claim 1 further includes: a frequency maximum ratio synthesis unit coupled to the D matched filter operation units and the channel estimation unit for using the Pth matched filter operation unit Each of the matching operation results is subjected to an addition operation with the conjugate of the corresponding channel weight coefficient, wherein the U -matching operation result of the P- th matched filtering operation unit is added to the conjugate of the U- th channel weight coefficient Computing to obtain a U- th frequency weight addition result, wherein the frequency maximum-scale synthesis unit combines all the frequency weight addition results into a frequency synthesis vector, where the frequency synthesis vector includes D frequency synthesis signals, wherein the Vth based frequency synthesis signal as the sum of the addition results of the heavy V th frequency weights of all matched filtering operation corresponding to a cell, wherein each of the preset time, the reception buffer for the storage units to the M-th number of M -1 storage The data of the unit is replaced, and the first storage unit is updated, and the maximum frequency synthesis unit of the above frequency outputs a new frequency combination every preset time. a vector, wherein, the Qth preset time, the frequency maximum ratio synthesis unit outputs a Qth frequency synthesis vector; an array temporary storage circuit coupled to the frequency maximum ratio synthesis unit for storing R frequency synthesis vectors; a Fourier transform unit coupled to the array temporary storage circuit, according to the timing error estimation value, taking a specific frequency synthesis vector from the array temporary storage circuit, performing Fourier transform to obtain a plurality of frequency domain conversion signals; and a frequency decision unit And the Fourier transform unit is coupled to receive the plurality of frequency domain converted signals, perform a maximum estimation on the plurality of frequency domain converted signals, find a maximum frequency domain converted signal, and take out the maximum frequency domain converted signal. The corresponding frequency index is used as a frequency drift estimation value; wherein, P, U, and V are integers between 0 and D -1. The initial synchronization device according to claim 3, wherein the local training sequence includes an upper training sequence and a lower training sequence, and the D matching filtering operation units are D upper matching filtering operation units, The time maximum ratio synthesis unit is a maximum time ratio synthesis unit, and the time decision unit is a time division decision unit, wherein the lower training sequence includes D lower branch discrete training signals, expressed as s _d [0], s _d [1],..., s _d [ D -1], the initial synchronization device further comprises: D lower branch matching filtering operation units, each of the lower matching filtering operation units having D input terminals, each a lower supporting matched filtering operation means the J input terminal for receiving the first m _T × J oversampled received signal buffers, wherein the first m 'of the matched filtering operation support means of the K signal input terminal of an oversampling Performing a matching filtering operation with the conjugate of the lower discrete training signal s _d [MOD( K-m' )] to obtain a Kth lower branch matching operation result, wherein the m'th lower branch matching filtering operation unit will be all under Match matching Synthesized for the first m 'of the lower supporting filtered signal; branched at the time maximum ratio combining unit, coupled to the lower branch of the D matched filter calculating means, and the channel estimation unit to the I-th and the first lower branch filtered signal I channel weights conjugated weighting coefficients is a an addition operation to obtain the I-th lower supporting temporal weighting addition results, wherein the lower branch time maximum ratio combining unit all the lower branch time weight addition result of the synthesis is about support a time synthesis signal, wherein, at each preset time, the receiving buffer is used to replace the Mth storage unit with the data of the M -1 storage unit, and update the first storage unit, and each preset time, Generating a new time-synthesis signal, wherein the Qth preset time, the Q- th time-synthesis signal is generated; and the first-lower-time decision unit is coupled to the bottom-time maximum-scale synthesis unit for Collecting R time-synthesis time synthesis signals, performing a maximum estimation on the R lower-branch time synthesis signals, finding a maximum lower-branch time synthesis signal, and extracting the maximum lower-branch time synthesis signal corresponding to a time index, as a sub-timer error estimation value; a time averaging circuit coupled to the upper branch time decision unit and the lower branch time decision unit, receiving the timing error estimate value and the lower branch timing error estimate value, An averaging operation is performed to obtain an average timing error value as the timing error estimate. The initial synchronization device according to claim 4, wherein the frequency maximum ratio synthesis unit is a top frequency maximum ratio synthesis unit, and the array temporary storage circuit is an upper array array temporary storage circuit, and the Fourier conversion unit The upper branch Fourier transform unit, and the frequency decision unit is an upper branch frequency decision unit, wherein the initial synchronization device further comprises: a maximum frequency synthesis unit of the lower branch frequency, coupled to the D lower matched filter operation unit and The channel estimation unit is configured to perform an addition operation on each of the lower branch matching operation results of the Pth lower matching filter operation unit and the conjugate of the corresponding channel weight coefficient, wherein the Pth lower branch matching filter The U -lower branch matching operation result of the operation unit is subjected to an addition operation with the conjugate of the U- th channel weight coefficient to obtain a U- th lower frequency weight addition result, wherein the lower-frequency maximum-scale synthesis unit All frequencies lower branch weights weight addition result to synthesis at a frequency synthesizer branched vector, the vector comprising the frequency synthesizer branched at the D Frequency synthesis signal, wherein the first lower branch of V-based frequency synthesizer signal V th is the sum of the weights of all the frequencies branched branched matched filtering operation corresponding to the unit weight of the addition results, wherein each of the preset time, the reception buffer for The Mth storage unit is replaced with the data of the Mth -th storage unit, and the first storage unit is updated, and each of the lower-frequency synthesis units of the lower-end frequency generates a new lower-frequency frequency for each preset time. the resultant vector, wherein the first predetermined time Q, the lower frequency branch maximum ratio combining unit Q output of the frequency synthesizer vector branched; click branched array register circuit, coupled to the frequency of the maximum ratio synthesizing unit, configured to store the R a lower frequency synthesis vector; a lower branch Fourier transform unit coupled to the lower array array temporary storage circuit, and based on the timing error estimation value, extracting a specific lower branch frequency synthesis vector from the lower array array temporary storage circuit, and performing Fourier transform Obtaining a plurality of lower frequency domain conversion signals; and a lower frequency decision unit coupled to the lower Fourier transform unit to receive the plurality of lower frequency domain conversion signals Performing a maximum value estimation on the plurality of lower frequency domain conversion signals to find a maximum lower frequency domain conversion signal, and extracting a frequency index corresponding to the maximum lower frequency domain conversion signal, as a frequency estimation of the lower frequency And a frequency averaging circuit coupled to the upper branch frequency decision unit and the lower branch frequency decision unit, receiving the frequency drift estimation value and the lower branch frequency drift estimation value, performing an averaging operation to obtain an average frequency Drift estimate. The initial synchronization device of claim 5, wherein the training sequence in the received signal is a dual-chirp burst, and the double plexus is expressed in continuous time s ( t ), whose time range is (0, T ), and its mathematical expression is among them, Where Π( t ) is a unit rectangular pulse, expressed as The scope of the patent described in item initial synchronization apparatus 6, the first m 'of the matched filtering operation support means in a continuous-time impulse response is expressed as The first m 'of the lower supporting unit impulse response matched filtering operation represented in continuous time Wherein, the above impulse response is expressed as discrete time Where | x | _D represents the remainder after x is divided by D. The patent range initial synchronization apparatus according to the item 5, wherein the matching operation result based upper support matching operation result, the upper support matching operation result of the m 'of the upper branch matched filter calculating means generated is expressed as z _{m '; u, 0, z m} '; u, 1, ..., z m '; u, D -1, the first m' on the support on a matching operation result of matched filtering operation support unit composed of a first generated Vector, the first vector is represented as The frequency synthesis vector is an upper frequency domain synthesis vector, and the upper frequency domain synthesis vector is represented as , the value is ,among them, , ,..., These weight coefficients for the right channel, wherein the first m 'matching operation result of a lower branch of the lower supporting unit generates matched filtering operation expressed as _{z m'; d, 0,} z m '; d, 1, ..., z _{m '; d, D -1,} of m' matches the computation result branched at a branch matched filter calculating unit generates a second vector composed of the second vector is represented as , the lower frequency domain synthesis vector is expressed as , the value is . The initial synchronizing apparatus according to claim 1, wherein the matched filtering operation is a multiplication operation, and the addition operation is a multiplication operation. An initial synchronization method includes the steps of: receiving a received signal, wherein the received signal includes a training sequence; sampling the received signal to obtain N oversampled signals; providing a receive buffer having N storages a unit for storing the 0th to the N -1th oversampling signals; performing a channel estimation on the supersampled signal according to a local training sequence to obtain D channel weight coefficients, wherein the local training sequence includes D discrete training signals, denoted as s [0], s [1],..., s [ D -1]; perform D correlation operations to obtain D filtered signals, in each of these correlation operations receiving a first M _T × J oversampling signal reception buffer to the reception buffer is super-sampled signal D is D a correlation calculation, where, J = 0,1,2, ... K-th filter operation based on m _T × K super-sample signal, D -1, wherein each of the correlation calculation comprising a plurality of filtering operations and synthesis calculation, wherein the first m 'of the correlation computing the discrete training signal s [MOD (K-m ' )] conjugate for matched filtering operation, To give K-th matching operation results, wherein all of the matching operation result of the m 'th combination calculation based on the m' th of the synthesized correlation processing for the first m 'of filtering signals, wherein, the MOD (x) denotes dividing x by the remainder after D; performing a time to maximum ratio synthesis calculation, the conjugate I-th filter signal and the second I channel weighting coefficients are an addition operation to obtain the I-th temporal weighting addition result and the time The maximum proportional synthesis operation combines all the time weight addition results into a time synthesis signal; at each preset time, the Mth storage unit of the reception buffer is replaced with the data of the Mth -1 storage unit, and updated. a first storage unit, and each time preset, a new time synthesis signal is generated, wherein the Qth preset time, the Qth time synthesis signal is generated; the R time synthesis signals are collected; and the time decision operation is performed, the above R time for a maximum estimation resultant signal, the maximum time to find a synthesis signal, and remove the corresponding maximum time of the synthesis time index signal as a timing error estimate; wherein, D N, M _T are both a positive integer, and N M _T × D , J , K, m′, I are all integers between 0 and D -1, M is a positive integer, and 2 M N, R is a positive integer, and Q is a real number. The initial synchronization method as described in claim 10, wherein the local training sequence includes an upper training sequence and a lower training sequence, and the D correlation operations are D upper correlation operations, and the time is the largest The proportional synthesis operation system is a maximum time proportional synthesis operation, wherein the time decision operation system is a time-dependent decision operation, and the timing error estimation value is a time-series error estimation value, wherein the lower training sequence includes D lower branches The discrete training signal is expressed as s _d [0], s _d [1],..., s _d [ D -1], and the initial synchronization method further includes the following steps: performing D sub-correlation operations to obtain D filtering the signal branch, the branch in each of the correlation calculation, the reception of M _T × J oversampling a signal reception buffer to the reception buffer for the D super-sampled signal at the D a correlation operation, where J =0, 1, 2, ..., D -1, wherein each of the lower branch correlation operations includes a plurality of lower branch filtering operations and a lower branch combining operation, wherein The Kth lower branch filter operation system of m's lower branch correlation operation The M _T × K oversampling signals are matched with the conjugate of the lower discrete training signal s _d [MOD( K-m' )] to obtain a Kth lower branch matching operation result, wherein the m'th branched combination calculation based the first m 'branch next all lower branch matching operation result of the correlation operation of synthesis for the first m' of the lower supporting filtered signal; conduct some branching time maximum ratio synthesis calculation, the I-th lower branch filtered signal and the second I channel weighting coefficient conjugate of an addition operation to obtain the I-th lower supporting temporal weighting addition result, and the lower branch time maximum ratio synthesizing operation all lower branch time weight addition result synthesis of The time-synthesis signal is synthesized; at each preset time, the Mth storage unit of the receiving buffer is replaced with the data of the M -th storage unit, and the first storage unit is updated, and each preset time, Generating a new sub-time synthesis signal, wherein the Qth preset time, the Q- th sub-time synthesis signal is generated; the R sub-time synthesis signals are collected; and the sub-time decision operation is performed, and the R times are Time synthesis signal for one maximum Estimating, finding the maximum time synthesis signal, and taking out the time index corresponding to the maximum time synthesis signal of the lower branch as the estimated value of the timing error; and estimating the timing error of the upper branch and the lower branch The timing error estimate is averaged to obtain an average timing error value as the timing error estimate. For example, the initial synchronization method described in claim 10 further includes the following steps: performing a frequency maximum ratio synthesis operation, and conjugate the result of each of the P correlation operations with the corresponding channel weight coefficient. Performing an addition operation, wherein the U -matching result of the Pth correlation operation and the conjugate of the U- th channel weighting coefficient perform the addition operation to obtain a U- th frequency weight addition result, wherein In the frequency maximum ratio synthesis operation, all frequency weight addition results are combined into a frequency synthesis vector, the frequency synthesis vector includes D frequency synthesis signals, wherein the Vth frequency synthesis signal is for each of the correlation operations a sum of the corresponding Vth frequency weight addition results, and the Mth storage unit of the receiving buffer is replaced with the data of the Mth -th storage unit and the first storage unit is updated every preset time. And each predetermined time, a new frequency synthesis vector is generated, wherein, at the Qth preset time, the Qth frequency synthesis vector is generated; and R frequency synthesis vectors are collected; according to the timing The error estimation value is obtained by taking a specific frequency synthesis vector from the R frequency synthesis vectors, performing Fourier transform to obtain a plurality of frequency domain conversion signals, and performing a maximum estimation on the plurality of frequency domain conversion signals to find a The maximum frequency domain converts the signal, and takes out the frequency index corresponding to the maximum frequency domain conversion signal as a frequency drift estimation value; wherein, P, U, and V are integers between 0 and D -1. The initial synchronization method as described in claim 12, wherein the local training sequence includes an upper training sequence and a lower training sequence, and the D correlation operations are D upper correlation operations, and the time is the largest The proportional synthesis operation system is a maximum time proportional synthesis operation, wherein the time decision operation system is a time-dependent decision operation, and the timing error estimation value is a time-series error estimation value, wherein the lower training sequence includes D lower branches The discrete training signal is expressed as s _d [0], s _d [1],..., s _d [ D -1], and the initial synchronization method further includes the following steps: performing D sub-correlation operations to obtain D filtering the signal branch, the branch in each of the correlation calculation, the reception of M _T × J oversampling a signal reception buffer to the reception buffer for the D super-sampled signal at the D a correlation operation, where J =0, 1, 2, ..., D -1, wherein each of the lower branch correlation operations includes a plurality of lower branch matching filtering operations and a next branch combining operation, wherein of m 'of the branched correlation computing lower branch of the K-th matched filter The M _T × K super-sampling signals of the wave computing system are matched and filtered by the conjugate of the lower discrete training signal s _d [MOD( K-m' )], and the K- th lower matching operation result is obtained, where m 'branch combination calculation based next the first m' branch next all lower branch matching operation result of the correlation operation of synthesis for the first m 'of the lower supporting filtered signal; conduct some branching time maximum ratio synthesis calculation, the I-th lower branched filtered signal and the second I channel weighting coefficient conjugate of an addition operation to obtain the I-th lower supporting temporal weighting addition result, and the lower branch time maximum ratio synthesizing operation all lower branch time weight adduct The result is synthesized into a sub-time synthesis signal; at each preset time, the Mth storage unit of the receiving buffer is replaced with the data of the M -th storage unit, and the first storage unit is updated, and each pre- Set a time to generate a new sub-time synthesis signal, where the Qth preset time, the Q- th sub-time synthesis signal is generated; the R sub-time synthesis signals are collected; and the next-time decision operation is performed, synthesis of a lower supporting R signals into time a maximum estimate, find out the maximum time synthesis signal, and take out the time index corresponding to the maximum time synthesis signal of the lower branch, as the estimated value of the timing error; and estimate the timing error of the upper branch and The lower timing error estimate value is averaged to obtain an average timing error value as the timing error estimate. The initial synchronization method according to claim 13, wherein the frequency maximum ratio synthesis operation system is a maximum ratio synthesis operation of the upper branch frequency, and the frequency synthesis vector is an upper branch frequency synthesis vector, and the plurality of frequency domain conversions. The signal is a plurality of upper frequency domain conversion signals, and the frequency drift estimation value is an upper frequency drift estimation value, wherein the initial synchronization device further comprises: a maximum frequency synthesis operation of the lower frequency, the Pth Each of the lower branch matching operation results of the lower branch correlation operation performs an additive operation with the conjugate of the corresponding channel weight coefficient, wherein the Uth lower branch matching operation result of the Pth lower branch correlation operation and the Uth The conjugate of the channel weight coefficients is subjected to an addition operation to obtain the U- th lower frequency weight addition result, wherein in the maximum proportional synthesis operation of the lower frequency, all the lower frequency weights are added to the resultant synthesis is branched at a frequency synthesizer vector, the vector comprising the frequency synthesizer branched at a branching frequency synthesizer D signal, wherein the first lower branch of V-based frequency synthesizer signal to all lower branch The results of the total weight of the addition of V the right lower leg frequencies corresponding correlation computing, wherein each of the predetermined time, the M-th reception buffer storing means to the first memory cell M -1 th data of the replacement, and Updating the first storage unit, and each of the preset times, the maximum ratio synthesis operation of the lower frequency outputs a new lower frequency synthesis vector, wherein the Qth preset time produces the Qth lower frequency synthesis Vector; collect R lower frequency synthesis vectors; according to the timing error estimation value, take a specific lower frequency synthesis vector from R lower frequency synthesis vectors, perform Fourier transform, and obtain multiple lower frequency domain conversion signals And performing a maximum estimation on the plurality of lower frequency domain conversion signals to find a maximum lower frequency domain conversion signal, and extracting a frequency index corresponding to the maximum lower frequency domain conversion signal as a frequency shift of the lower branch frequency The estimated value; and the estimated value of the upper branch frequency drift and the estimated value of the drift frequency of the lower branch are averaged to obtain an average frequency drift estimation value. The initial synchronization method as described in claim 14, wherein the training sequence in the received signal is a dual-chirp burst, and the double burst is expressed in continuous time s ( t ), whose time range is (0, T ), and its mathematical expression is among them, Where Π( t ) is a unit rectangular pulse, expressed as The patentable scope of the initial synchronization method described in item 14, such as the application, wherein the matching operation result based upper support matching operation result, the first m 'branched correlation computing last generated on branched matching operation result is expressed as Z _{m' ; u, 0, z m '} ; u, 1, ..., z m'; the branched matching operation result _{u, D -1,} the first m 'branched previous correlation computing a first composition of the resulting vector, The first vector is represented as The frequency synthesis vector is an upper frequency domain synthesis vector, and the upper frequency domain synthesis vector is represented as , the value is ,among them, , ,..., These weight coefficients for the right channel, wherein the first m 'branched correlation computing the next lower branch generated matching operation result is expressed as _{z m'; d, 0,} z m '; d, 1, ..., z m _{'; d, D -1,} of m' matches the computation result branched branched next correlation computing a second composition of the resulting vector, the second vector is represented as , the lower frequency domain synthesis vector is expressed as , the value is . The initial synchronization method according to claim 10, wherein the matched filtering operation is a multiplication operation, and the addition operation is a multiplication operation.