TWI559529B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

A transistor is a solid-state semiconductor component that has the advantages of small size, high efficiency, long life, and high speed. In recent years, due to advances in technology, there have been high-voltage, high-power-resistant transistors, so transistors have always played an important role in high-power components.

A bipolar junction transistor (BJT) is a transistor in which two different doped regions are used to form two PN junctions. BJT is a component with three ends of the emitter (Emitter, E), base (Base, B) and collector (Cector). BJT can amplify signals and has good power control, high speed operation and durability. Therefore, BJT is widely used in circuits that need to control current, such as switching elements for controlling DC power load, analog signal amplifiers, and three-dimensional bipolar simulation. (3D bipolar simulation), NPN components, AC frequency response and other fields. BJT is also an important component of ultra-high-speed discrete logic circuits, and its applications include emitter-coupled logic. (Emitter Coupled Logic, ECL), power switching components, and microwave power amplifiers. Therefore, in the application of the amplifier, how to amplify the signal, reduce the noise, and at the same time maintain a high breakdown voltage is an extremely problem to be solved.

The present invention provides a semiconductor element and a method of fabricating the same, which can improve the common-emitter current gain of the semiconductor element and maintain a high breakdown voltage of the element.

The present invention provides a semiconductor device comprising: a substrate having a first conductivity type, a first well region having a first conductivity type, a separation region having a second conductivity type, a first doping region having a first conductivity type, having a second doped region of the second conductivity type, a third doped region having a second conductivity type, and at least one field plate. The separation zone is located in the substrate and the first well zone is located in the separation zone. The first doped region is located in the first well region and a first voltage is applied. The second doped region is located in the first well region on the first side of the first doped region and a second voltage is applied. The third doped region is located in the separation region on the second side of the first doped region, and a third voltage is applied. At least one field of the plate is located on the substrate between the first doped region and the second doped region, or on the substrate between the first doped region and the third doped region, or in the first doped region and the second On the substrate between the doped regions and between the first doped region and the third doped region.

In an embodiment of the invention, the separation zone comprises: a second well region having a second conductivity type and a buried layer. The second well zone is located around the first well zone. With the first The buried layer of the second conductivity type is located in the substrate below the first well region and the second well region, and the doping concentration of the buried layer is different from the doping concentration of the second well region.

In an embodiment of the invention, the separation zone comprises a deep well zone having a second conductivity type.

In an embodiment of the invention, when the first conductivity type is a P type, the second conductivity type is an N type, the third voltage is greater than the first voltage, and the first voltage is greater than the second voltage.

In an embodiment of the invention, when the first conductivity type is an N type, the second conductivity type is a P type, the second voltage is greater than the first voltage, and the first voltage is greater than the third voltage.

In an embodiment of the invention, the semiconductor component further includes at least one isolation structure located under at least one of the plates, and at least one of the plates covers at least one isolation structure.

In an embodiment of the invention, the at least one plate material comprises polysilicon, metal or a combination thereof.

The present invention provides a semiconductor device comprising: a substrate having a first conductivity type, a first well region having a first conductivity type, a separation region having a second conductivity type, a first doping region having a first conductivity type, having a lightly doped region of the second conductivity type, a second doped region having a second conductivity type, a third doped region having a second conductivity type, and at least one field plate. The first well zone and the separation zone are located in the substrate, wherein the first well zone is located in the separation zone. A first doped region having a first conductivity type is located in the first well region. The lightly doped region is located in the first well region. a second doped region, located first in the first doped region In the lightly doped area of the side. The third doped region is located in the separation region on the second side of the first doped region. At least one plate, on a substrate between the first doped region and the second doped region and in contact with the lightly doped region, or on a substrate between the first doped region and the third doped region, or The substrate between the first doped region and the third doped region and on the substrate between the first doped region and the second doped region are in contact with the lightly doped region.

In an embodiment of the invention, the separation zone comprises: a second well region having a second conductivity type and a buried layer having a second conductivity type. The second well zone is located around the first well zone. The buried layer is located in the substrate below the first well region and the second well region, and the doping concentration of the buried layer is different from the doping concentration of the second well region.

The present invention provides a method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type. A first well region having a first conductivity type is formed in the substrate. A separation zone having a second conductivity type is formed in the substrate, wherein the first well zone is located in the separation zone. A first doped region having a first conductivity type is formed in the first well region. A lightly doped region having a second conductivity type is formed in the first well region. Forming a second doped region having a second conductivity type in the lightly doped region of the first side of the first doped region. A third doped region having a second conductivity type is formed in the separation region on the second side of the first doping region. Forming at least one plate on the substrate between the first doped region and the second doped region and in contact with the lightly doped region, or on the substrate between the first doped region and the third doped region, or The substrate between the first doped region and the third doped region and on the substrate between the first doped region and the second doped region are in contact with the lightly doped region.

The invention provides a semiconductor component, which can be applied not only to a DC circuit component but also to an Electrostatic Discharge (ESD) protection element. On the piece.

The present invention provides a method of fabricating a semiconductor device that is compatible with existing standard processes without requiring an additional reticle to increase the breakdown voltage.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ Field Board

11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22‧‧‧ semiconductor components

30, 32‧‧‧ isolation structure

100‧‧‧Base

110‧‧‧First Well Area

120‧‧‧Separation zone

130‧‧‧Second well area

140‧‧‧buried layer

150‧‧‧Shenjing District

160‧‧‧Outdoor well area

210‧‧‧First doped area

220‧‧‧Second doped area

225‧‧‧lightly doped area

230‧‧‧ Third doped area

240‧‧‧fourth doping zone

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention.

4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

Fig. 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

Figure 6 is a cross-sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

Figure 7 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present invention.

Figure 8 is a cross-sectional view showing a semiconductor device in accordance with an eighth embodiment of the present invention.

Figure 9 is a cross-sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

Figure 10 is a cross-sectional view showing a semiconductor device according to a tenth embodiment of the present invention.

Figure 11 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.

Figure 12 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.

In the following embodiments, when the first conductivity type is a P type, the second conductivity type is an N type; when the first conductivity type is an N type, the second conductivity type is a P type. The dopant of the P type is, for example, boron or boron difluoride. The dopant of the N type is, for example, phosphorus or arsenic. In this embodiment, the first conductivity type may be a P type, and the second conductivity type may be an N type, but the invention is not limited thereto.

In the following examples, the singular forms "a" and "the" In more detail, the field plates, structures, and/or components described below also represent at least one field, structure, and/or component, but the invention is not limited thereto.

Hereinafter, the semiconductor element of the present invention will be described in more detail by taking a bipolar junction transistor (BJT) as an example, but it does not mean that the semiconductor element structure of the present invention is limited to a bipolar junction transistor.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 11 according to a first embodiment of the present invention includes a substrate 100 having a first conductivity type, a first well region 110 having a first conductivity type, and a separation region 120 having a second conductivity type, having a first a conductive first doping region 210, a lightly doped region 225 having a second conductivity type, a second doping region 220 having a second conductivity type, a third doping region 230 having a second conductivity type, and at least one field Board 10.

The material of the substrate 100 is, for example, a semiconductor material. The semiconductor material is, for example, a material selected from at least one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, or an insulating layer overlying layer (SOI) or Any physical structure suitable for use in the process of the present invention.

A first well region 110 having a first conductivity type is located in the substrate 100. The first well region 110 is, for example, a stack of a P-type well, a P+buried layer, a P-implant region, or a combination thereof. In one embodiment, the dopant of the first well region 110 is, for example, boron or boron difluoride, and the doping concentration of the first well region 110 is, for example, 8 x 10 ¹⁴ /cm ³ to 5 x ^{10 17} /cm ³ .

A partition 120 having a second conductivity type is located in the substrate 100, and the first well region 110 is located in the partition 120. More specifically, in an embodiment, the separation region 120 includes a second well region 130 having a second conductivity type and a buried layer 140 having a second conductivity type. The second well zone 130 is located around the first well zone 110. The buried layer 140 is located in the substrate 100 below the first well region 110 and the second well region 130. The doping concentration of the buried layer 140 may be greater than the doping concentration of the second well region 130. The buried layer 140 is, for example, an N-epi layer, a deep N-type well, or a multiple N+ buried layer stack. The second well region 130 can be a stack of N-type wells, N+ buried layers, N-implants, or a combination thereof. In one embodiment, the dopant of the buried layer 140 and the second well region 130 is, for example, phosphorus or arsenic, and the doping concentration of the buried layer 140 is, for example, 8× ^{10 14} /cm ³ to 8× ^{10 17} /cm ³ ; The doping concentration of the well region 130 is, for example, ⁸ x 10 ¹⁴ /cm ³ to 1 x 10 ¹⁷ /cm ³ .

The semiconductor component 11 of the present invention further includes a peripheral well region 160 having a first conductivity type. The peripheral well region 160 is around the separation zone 120. The doping concentration of the first well region 110 and the doping concentration of the peripheral well region 160 may be the same or different. In one embodiment, the dopants of the first well region 110 and the peripheral well region 160 are, for example, boron or boron difluoride, and the doping concentration of the first well region 110 and the peripheral well region 160 is, for example, 8× ^{10 14} /cm ^{3 .} To 5x10 ¹⁷ /cm ³ .

A first doped region 210 having a first conductivity type is located in the first well region 110. The first doping region 210 is, for example, a P-type heavily doped (P+) region, which can serve as a base. In one embodiment, the dopant of the first doping region 210 is, for example, boron or boron difluoride, and the doping concentration of the first doping region 210 is, for example, 8× ^{10 17} /cm ³ to 4× ^{10 20} /cm ³ .

A lightly doped region 225 having a second conductivity type is located in the first well region 110 on the first side of the first doped region 210. A second doped region 220 having a second conductivity type is located in the lightly doped region 225 of the first side of the first doped region 210. The lightly doped region 225 is, for example, an N-type lightly doped region; and the second doped region 220 is, for example, an N-type heavily doped (N+) region, which can serve as an emitter. In one embodiment, the dopant of the second doping region 220 is, for example, arsenic or phosphorus, and the doping concentration of the second doping region 220 is, for example, 8× ^{10 17} /cm ³ to 4× ^{10 20} /cm ³ . The doping concentration of the lightly doped region 225 is between the doping concentration of the above-described separation region 120 and the doping concentration of the second doping region 220. More specifically, the doping concentration of the lightly doped region 225 is 1/1000 to 1/100 of the doping concentration of the second doping region 220. In an embodiment, the doping concentration of the lightly doped region 225 is, for example, 8× ^{10 14} /cm ³ to 4× ^{10 18} /cm ³ ; and the doping concentration of the separation region 120 is, for example, 8× ^{10 14} /cm ³ to 8× ^{10 17} /cm ³ ; The doping concentration of the second doping region 220 is, for example, 8× ^{10 17} /cm ³ to 4× ^{10 20} /cm ³ .

A third doping region 230 having a second conductivity type is located in the separation region 120 of the second side of the first doping region 210. The doping concentration of the third doping region 230 may be the same as or different from the doping concentration of the second doping region 220. The third doping region 230 is, for example, an N-type heavily doped (N+) region, which can serve as a collector. In one embodiment, the dopant of the third doping region 230 is, for example, arsenic or phosphorus, and the doping concentration of the third doping region 230 is, for example, 8× ^{10 17} /cm ³ to 4× ^{10 20} /cm ³ .

The semiconductor device 11 of the present invention further includes a fourth doping region 240 having a first conductivity type. The fourth doped region 240 is located in the peripheral well region 160. The doping concentration of the fourth doping region 240 may be the same as or different from the doping concentration of the first doping region 210. The fourth doping region 240 is, for example, a P-type heavily doped (P+) region that can be electrically connected to the substrate 100. In one embodiment, the dopant of the fourth doping region 240 is, for example, boron or boron difluoride, and the doping concentration of the fourth doping region 240 is, for example, 8× ^{10 17} /cm ³ to 4× ^{10 20} /cm ³ .

The field plate 10 is located on the substrate 100 between the first doped region 210 and the second doped region 220 and is in contact with the lightly doped region 225. In more detail, the field plate 10 is located on the lightly doped region 225 and the first well region 110, and is in contact with the lightly doped region 225, which may partially cover the second doping region 220 or may not cover the second doping region. Area 220. The material of the field plate 10 includes polycrystalline germanium, metal, or a combination thereof.

Further, the semiconductor element 11 of the present invention is provided with an isolation structure 30 on the substrate 100 between the respective doped regions where the field plate 10 is not disposed. In more detail, the isolation structure 30 may be disposed on the first well region 110 and the second well region 130 between the first doping region 210 and the third doping region 230, and the third doping region 230 and the fourth region. On the second well region 130 between the doped regions 240, and on the peripheral well region 160 outside the fourth doped region 240. The material of the isolation structure 30 is, for example, ruthenium oxide, doped ruthenium oxide, tantalum nitride or a combination thereof.

The semiconductor element 11 of the present invention is symmetric with another semiconductor element and is disposed in a common emitter (second doped region 220) (as shown in FIG. 1), however, the semiconductor device of the present invention may also be combined with another semiconductor device. Asymmetric setting.

The semiconductor device 11 of the embodiment of the present invention can apply a first voltage V1 in the first doping region 210, a second voltage V2 in the second doping region 220, and a third voltage in the third doping region 230. V3. In one embodiment, the semiconductor device 11 is an NPN-type BJT device. When the applied third voltage V3 is greater than the first voltage V1 and the first voltage V1 is greater than the second voltage V2, the first doping region 210 and the second doping region The junction between the regions 220 is forward biased (eg, the emitter junction), and the junction between the second doped region 220 and the third doped region 230 is reverse biased (eg, the collector junction). The active region can obtain the maximum common emitter current gain (Beta), which makes the signal amplified. In another embodiment, the semiconductor device 11 is a PNP-type BJT device. When the applied second voltage V2 is greater than the first voltage V1 and the first voltage V1 is greater than the third voltage V3, the forward active region can obtain the maximum common emitter. The current gain causes the signal to be amplified.

The semiconductor device 11 of the embodiment of the present invention has a field plate 10 disposed on the substrate 100 between the doped regions to make the potential distribution of the semiconductor element 11 uniform, improving the first doping region 210 (eg, the base) and The breakdown voltage of the junction between the second doping regions 220 (e.g., the emitter), and thus the BJT device can be applied to high voltage semiconductor components and to DC circuit components of any voltage.

2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. Referring to FIG. 2, the semiconductor device 12 of the present embodiment is similar to the semiconductor device 11 of the first embodiment, except that the field plate 10 is located in the first doping region 210 and the third portion. On the substrate 100 between the doped regions 230. In more detail, the field plate 10 is located on the first well region 110 and the second well region 130. In addition, on the substrate 100 between the doped regions where the field plate 10 is not disposed, for example, on the substrate 100 between the first doping region 210 and the second doping region 220, the third doping region 230 and the fourth An isolation structure 30 is disposed on the substrate 100 between the doped regions 240 and on the substrate 100 outside the fourth doped region 240. The field plate 10 of the present embodiment can improve the breakdown voltage of the junction between the first doping region 210 (e.g., the base) and the third doping region 230 (e.g., the collector) to make the potential distribution uniform.

Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention. Referring to FIG. 3, the semiconductor device 13 of the present embodiment is similar to the semiconductor device 11 of the first embodiment, except that the field plate 10 of the semiconductor device 13 of the present embodiment is located not only in the first doping region 210 and the second. The lightly doped region 225 between the doped regions 220 is in contact with the first well region 110 and with the lightly doped region 225, while also being located between the first doped region 210 and the third doped region 230. Zone 110 and second well zone 130. The field plate 10 may partially cover the second doping region 220 or may not cover the second doping region 220. In addition, on the substrate 100 between the doped regions where the field plate 10 is not disposed, for example, on the second well region 130 between the third doping region 230 and the fourth doping region 240, and the fourth doping region An isolation structure 32 is disposed on the outer peripheral well region 160 outside the 240. The field plate 10 of the present embodiment can improve the breakdown voltage of the junction between the first doping region 210 (eg, the base) and the second doping region 220 (eg, the emitter) and the first doping region 210 (eg, the base) The breakdown voltage with the interface between the third doping region 230 (for example, the collector) makes the potential distribution uniform.

In the above semiconductor elements 11, 12, 13, the second doping region 220 (for example) The distance between the emitter and the third doped region 230 (eg, the collector) may be optimized to avoid lateral punch through. The field plate 10 can be used to separate the first doped region 210 (eg, the base) from the second doped region 220 (eg, the emitter), and the first doped region 210 (eg, the base) and the third doped region 230 ( For example, the collector) and uniform its potential distribution, therefore, the width of the base (first doped region 210) can be reduced to reduce the size of the entire component. Moreover, the size of the field plate 10 can also be precisely controlled by the process.

The semiconductor elements 11, 12, 13 are provided with a lightly doped region (eg, HNMLDD) 225 around the second doped region (eg, N+ emitter) 220, that is, the second doped region 220 is disposed in the lightly doped region 225. Since the doping concentration of the lightly doped region 225 is higher than the doping concentration of the first well region 110, the doping concentration of the region around the second doping region 220 can be increased by the arrangement of the lightly doped region 225, and the doping concentration is increased. Common emitter current gain of the BJT component. The common emitter current gain is an important parameter for defining the amplification capacity of the BJT component. When the signal is amplified, the BJT component applied to the amplifier can filter unnecessary noise.

Further, the above-described semiconductor elements 11, 13 are provided with the field plate 10 between the base (first doping region 210) and the emitter (second doping region 220), so that the potentials in the semiconductor elements 11, 13 can be evenly distributed. Further, the breakdown voltage of the junction region between the base and the emitter is raised. The above-mentioned semiconductor elements 12, 13 are provided with a field plate 10 between the base (first doped region 210) and the collector (third doped region 230), so that the potentials in the semiconductor elements 12, 13 can be evenly distributed, thereby enhancing The breakdown voltage of the junction of the doped region between the base and the collector. The distance between the collector and the emitter can be optimized to avoid lateral punch through. Therefore, the semiconductor component of the present invention can be applied to high voltage Semiconductor components, and not only for DC circuit components, but also for electrostatic discharge protection components.

4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. Figure 6 is a cross-sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

Referring to FIGS. 4 to 6, the semiconductor elements 14, 15, 16 of the fourth to sixth embodiments are similar to the semiconductor elements 11, 12, and 13 of the first to third embodiments, respectively, except that the fourth aspect of the present invention The semiconductor elements 14, 15, 16 of the sixth embodiment each include an isolation structure 32 disposed under the field plate 10 such that the field plate 10 covers a portion of the isolation structure 32. The isolation structure 32 includes a regional oxidation structure (LOCOS), a shallow trench isolation structure (STI), and a deep trench isolation structure (DTI).

Figure 7 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present invention. Figure 8 is a cross-sectional view showing a semiconductor device in accordance with an eighth embodiment of the present invention. Figure 9 is a cross-sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

Referring to FIGS. 7 to 9, the semiconductor elements 17, 18, 19 of the seventh to ninth embodiments are similar to the semiconductor elements 11, 12, 13 of the first to third embodiments, respectively, except that the separation region 120 is A deep well region 150 having a second conductivity type. The doping of the deep well region 150 is, for example, phosphorus or arsenic, and the doping concentration of the deep well region 150 is, for example, 5x10 ¹⁴ /cm ³ to 8x10 ¹⁷ /cm ³ . The deep well zone 150 can be applied to a triple well or multiple well process. The doping concentration of the deep well region 150 may be less than the doping concentration of the second well region 130 and the buried layer 140 to increase the breakdown voltage.

Figure 10 is a cross-sectional view showing a semiconductor device according to a tenth embodiment of the present invention. Figure 11 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment of the present invention. Figure 12 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.

Referring to FIGS. 10 to 12, the semiconductor elements 20, 21, and 22 of the tenth to twelfth embodiments are similar to the semiconductor elements 17, 18, 19 of the seventh to ninth embodiments, respectively, in that the present invention The semiconductor components 20, 21, 22 of the tenth to twelfth embodiments further include an isolation structure 32 under the field plate 10, and the field plate 10 covers a portion of the isolation structure 32.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to FIG. 1.

Referring to FIG. 1, a substrate 100 having a first conductivity type is provided. The material of the substrate 100 is, for example, a semiconductor material. The semiconductor material is, for example, a material selected from at least one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, or any physical structure suitable for use in the process of the present invention. .

A first well region 110 having a first conductivity type is formed in the substrate 100. The first well region 110 can be formed by forming an ion implantation mask on the substrate 100, implanting the dopant into the substrate 100 by ion implantation, and then forming it through a tempering process. In one embodiment, the dopant of the first well region 110 is, for example, boron or boron difluoride, and the doping amount of the first well region 110 is, for example, 8.00× ^{10 11} /cm ² to 8.00×10 ¹³ /cm ² .

A separation region 120 having a second conductivity type is formed in the substrate 100, wherein the first well region 110 is located in the separation region 120. More specifically, the method of forming the separation region 120 includes forming a second well region 130 having a second conductivity type around the first well region 110. A buried layer 140 having a second conductivity type is formed in the first well region 110, below the second well region 130, and in the substrate 100. The second well region 130 and the buried layer 140 may respectively form an ion implantation mask on the substrate 100, and the dopant is implanted into the substrate 100 by ion implantation, and then formed by a tempering process. The order in which the second well region 130 and the buried layer 140 are formed may be adjusted according to actual needs, and is not particularly limited. The doping concentration of the buried layer 140 may be different from the doping concentration of the second well region 130. In one embodiment, the dopant of the buried layer 140 and the second well region 130 is, for example, phosphorus or arsenic, and the doping amount of the buried layer 140 is, for example, 1.00× ^{10 12} /cm ² to 8.00× ^{10 14} /cm ² ; The doping amount of the second well region 130 is, for example, 1.00 x ^{10 12} /cm ² to 1.00 x ^{10 14} /cm ² .

In one embodiment, the semiconductor component of the present invention further includes a peripheral well region 160 having a first conductivity type. The peripheral well region 160 surrounds the perimeter of the separation zone 120. The peripheral well region 160 may first form an ion implantation mask on the substrate 100, and the dopant is implanted into the substrate 100 by ion implantation, and then formed by a tempering process. The dopant of the peripheral well region 160 is, for example, boron or boron difluoride, and the doping dose of the peripheral well region 160 is, for example, 1.00× ^{10 12} /cm ² to 5.00×10 ¹³ /cm ² , and the peripheral well region 160 and the first well region 110 can be formed at the same time.

A first doped region 210 having a first conductivity type is formed in the first well region 110. The first doping region 210 may be formed by implanting the dopant into the substrate 100 by ion implantation and then forming it through a tempering process. In one embodiment, the dopant of the first doping region 210 is, for example, boron or boron difluoride, and the doping amount of the first doping region 210 is, for example, ⁸ × ^{10 14} /cm ² to 8.00× ^{10 15} /cm ² .

A lightly doped region 225 is formed in the first well region 110 on the first side of the first doped region 210. The lightly doped region 225 can be formed by implanting the dopant into the substrate 100 by ion implantation and then forming it through a tempering process. The doping concentration of the lightly doped region 225 is between the doping concentration of the above-described separation region 120 and the doping concentration of the second doping region 220 described above. The doping amount of the lightly doped region 225 is, for example, 1.00×10 ¹³ /cm ² to 8.00× ^{10 14} /cm ² ; the doping amount of the separation region 120 is, for example, 1.00×10 ¹³ /cm ² to 1.10×10 ¹³ /cm ² ; The doping amount of the doping region 220 is, for example, 8.00× ^{10 14} /cm ² to 8.00× ^{10 15} /cm ² .

Forming a second doping region 220 having a second conductivity type in the lightly doped region 225, and forming a third doping region having a second conductivity type in the separation region 120 of the second side of the first doping region 210 230. The second doping region 220 and the third doping region 230 may be implanted into the substrate 100 by ion implantation, and then formed by a tempering process. In one embodiment, the dopant of the second doping region 220 and the third doping region 230 is, for example, arsenic or phosphorus, and the doping amount of the second doping region 220 is, for example, 8.00× ^{10 14} /cm ² to 8.00×10. ¹⁵ /cm ² .

In one embodiment, the method of fabricating a semiconductor device of the present invention further includes forming a fourth doped region 240 having a first conductivity type in the peripheral well region 160. The fourth doping region 240 can be formed by implanting the dopant into the substrate 100 by ion implantation and then forming it through a tempering process. In one embodiment, the dopant of the fourth doping region 240 is, for example, boron or boron difluoride, and the doping amount of the fourth doping region 240 is, for example, 8× ^{10 14} /cm ² to 8× ^{10 15} /cm ² . The fourth doping region 240 may be formed simultaneously with the first doping region 210.

Referring to FIG. 1 , on the substrate 100 between the first doping region 210 and the third doping region 230 , on the substrate 100 between the third doping region 230 and the fourth doping region 240 , and An isolation structure is formed on the substrate 100 outside the four doping regions 240, respectively. 30. The isolation structure 30 includes a regional oxidation structure, a shallow trench isolation structure, and a deep trench isolation structure. The field plate 10 is formed on the lightly doped region 225 between the first doped region 210 and the second doped region 220 and the first well region 110 to bring the field plate 10 into contact with the lightly doped region 225. The field plate 10 may partially cover the second doping region 220 or may not cover the second doping region 220.

The method of manufacturing the semiconductor elements 12, 13 of FIGS. 2 and 3 is similar to the method of fabricating the semiconductor device 11 of FIG. 1, with the difference that the positions of the field plate 10 and the isolation structure 30 are different.

The manufacturing methods of the semiconductor elements 14 to 16 of FIGS. 4 to 6 are similar to those of the semiconductor elements 11 to 13 of the above first to third embodiments, except that the isolation structure 32 is further formed under the field plate 10. The isolation structure 32 can be formed simultaneously with the isolation structure 30.

The manufacturing method of the semiconductor elements 17 to 19 of FIGS. 7 to 9 is similar to the manufacturing method of the semiconductor elements 11 to 13 of the above-described first to third embodiments, except that the separation region 120 is a deep well region having the second conductivity type. 150. The deep well region 150 can be formed by implanting the dopant into the substrate 100 by ion implantation and then forming it through a tempering process.

The manufacturing method of the semiconductor elements of the semiconductor elements 20 to 22 of FIGS. 10 to 12 is similar to the manufacturing method of the semiconductor elements 17 to 19 of FIGS. 7 to 9, except that the isolation structure 32 is further formed under the field plate 10. . The isolation structure 32 can be formed simultaneously with the isolation structure 30.

In summary, the present invention can be configured by configuring a second doped region (eg, an emitter) In the lightly doped region, the concentration of the second doped region (e.g., the emitter) is increased, thereby improving the common emitter current gain of the semiconductor device and maintaining a high breakdown voltage of the device. In addition, the present invention configures a field plate on the substrate between the doped regions to uniform the potential distribution within the semiconductor component and to increase the breakdown voltage of the junction.

In addition, the manufacturing method of the semiconductor device of the present invention can be compatible with existing standard processes, and can be applied to any process and any operating voltage without increasing the photomask and increasing the breakdown voltage of the semiconductor device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ Field Board

11‧‧‧Semiconductor components

30‧‧‧Isolation structure

100‧‧‧Base

110‧‧‧First Well Area

120‧‧‧Separation zone

130‧‧‧Second well area

140‧‧‧buried layer

160‧‧‧Outdoor well area

210‧‧‧First doped area

220‧‧‧Second doped area

225‧‧‧lightly doped area

230‧‧‧ Third doped area

240‧‧‧fourth doping zone

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

Claims (9)

A semiconductor device comprising: a substrate having a first conductivity type; a first well region having the first conductivity type, located in the substrate; and a separation region having a second conductivity type, located in the substrate Wherein the first well region is located in the separation region, the separation region includes: a second well region having the second conductivity type, located around the first well region; and a buried layer having the second conductivity type, Located in the first well region and the substrate below the second well region, the buried layer extends from below the upper well region to between the first well region and the substrate, and the buried layer and the first layer The well region is in direct contact; a first doped region having the first conductivity type is located in the first well region, and a first voltage is applied to the first doped region; and the second conductivity type is a lightly doped region, located in the first well region of a first side of the first doped region; a second doped region having the second conductivity type, located in the lightly doped region, and a second doping region applies a second voltage; a third doping region having the second conductivity type is located at the first a third voltage in the second side of the impurity region, and applying a third voltage to the third doped region; and at least one field plate between the first doped region and the second doped region and The substrate on which the lightly doped region contacts, or on the substrate between the first doped region and the third doped region, or between the first doped region and the second doped region And on the substrate in contact with the lightly doped region and the first doped region and the third doped region On the substrate. The semiconductor device of claim 1, wherein a doping concentration of the buried layer is different from a doping concentration of the second well region. The semiconductor device of claim 1, wherein when the first conductivity type is a P type and the second conductivity type is an N type, the third voltage is greater than the first voltage and the first voltage is greater than the The second voltage. The semiconductor device of claim 1, wherein when the first conductivity type is N-type and the second conductivity type is P-type, the second voltage is greater than the first voltage and the first voltage is greater than the The third voltage. The semiconductor device of claim 1, further comprising at least one isolation structure under the at least one field plate, and the at least one field plate covers a portion of the at least one isolation structure. The semiconductor component of claim 1, wherein the at least one plate material comprises polysilicon, metal or a combination thereof. A semiconductor device comprising: a substrate having a first conductivity type; a first well region having the first conductivity type, located in the substrate; and a separation region having a second conductivity type, located in the substrate Wherein the first well region is located in the separation region, the separation region includes: a second well region having the second conductivity type, located around the first well region; and a buried layer having the second conductivity type, Located in the first well region, below the second well region, and in the substrate, the buried layer extends from below the second well region to the first a well region and the substrate, and the buried layer is in direct contact with the first well region; a first doped region having the first conductivity type is located in the first well region; having the second a lightly doped region of the conductivity type, located in the first well region of a first side of the first doping region; a second doping region having the second conductivity type, located in the lightly doped region a third doped region having the second conductivity type, located in the spacer region on a second side of the first doped region; and at least one field plate located in the first doped region and the second doped region On the substrate between the doped regions and in contact with the lightly doped region, or on the substrate between the first doped region and the third doped region, or located in the first doped region and On the substrate between the third doped regions and on the substrate between the first doped region and the second doped region and in contact with the lightly doped region. The semiconductor device according to claim 7, wherein the doping concentration of the buried layer is different from the doping concentration of the second well region. A method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a first well region having the first conductivity type in the substrate; forming a second conductivity type in the substrate a separation zone, wherein the first well zone is located in the separation zone, the separation zone includes: a second well zone having the second conductivity type, located around the first well zone; and having the second conductivity type a buried layer located in the first well region, below the second well region, and in the substrate, the buried layer extending from below the second well region to the first a well region and the substrate, and the buried layer is in direct contact with the first well region; forming a first doped region having the first conductivity type in the first well region; Forming a lightly doped region having the second conductivity type in the first well region on a first side of the doped region; forming a second doped region having the second conductivity type in the lightly doped region Forming a third doped region having the second conductivity type in the spacer region on a second side of the first doped region; and forming at least one field plate in the first doped region and the second doped region On the substrate between the doped regions and in contact with the lightly doped region, or on the substrate between the first doped region and the third doped region, or in the first doped region and the first The substrate between the three doped regions and the substrate between the first doped region and the second doped region are in contact with the lightly doped region.