TW201344901A - Semiconductor structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a well having a first conductive type, a well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The wells having the firs and second conductive types are formed in the substrate, respectively. The body region is formed in the well having the second conductive type. The first and second doped regions are formed in the well having the first conductive type and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the well having the second conductive type and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure related to a Bipolar Junction Transistor (BJT) and a method of fabricating the same.

A bipolar transistor is one of the important semiconductor components in recent years. It is a three-terminal component consisting of two very tight pn junctions, called emitter, base, and collector (collector). ), where the base is extremely intermediate and indirect points in the three contacts of the bipolar transistor. Since the bi-carrier electro-crystal system uses both electron and hole carriers to conduct current, the bi-carrier element has the advantages of high speed and a large current in a small space, so A bipolar complementary crystal (BiCMOS) structure in which a carrier transistor and a complementary MOS transistor (CMOS) are combined has been proposed to increase the operating speed of the transistor.

However, when designing a bipolar junction transistor, increasing the impurity concentration of the emitter in order to increase the injection efficiency of the emitter tends to lower the breakdown voltage between the emitter and the base, and lower the bipolar transistor. performance.

The present invention relates to a semiconductor structure and a method of fabricating the same for improving the current gain of a common emitter circuit and increasing the breakdown voltage of the PN junction during reverse bias operation.

According to an aspect of the invention, a semiconductor structure includes a substrate, a first conductivity type well region, a second conductivity type well region, a body region, a first doping region, and a second doping. A zone, a third doped zone, and a plate. The first conductivity type well region and the second conductivity type well region are respectively formed in the substrate. The body region is formed in the well region of the second conductivity type. The first doped region and the second doped region are respectively formed in the well region of the first conductivity type and the body region. The polarity of the second doped region is the same as the polarity of the first doped region, and the impurity concentration of the second doped region is greater than the impurity concentration of the first doped region. The third doped region is formed in the well region of the second conductivity type and is located between the first doped region and the second doped region. The polarity of the third doped region is opposite to the polarity of the first doped region. The field plate is formed in a surface region between the second doped region and the third doped region.

According to another aspect of the present invention, a method of fabricating a semiconductor structure is provided, comprising the following steps. A substrate is provided. A well region of the first conductivity type and a well region of the second conductivity type are respectively formed in the substrate. A body region is formed in the well region of the second conductivity type. Forming a first doped region and a second doped region respectively in the well region and the body region of the first conductivity type. The polarity of the second doped region is the same as the polarity of the first doped region, and the impurity concentration of the second doped region is greater than the impurity concentration of the first doped region. Forming a third doped region in the well region of the second conductivity type and between the first doped region and the second doped region. The polarity of the third doped region is opposite to the polarity of the first doped region. Forming a surface region of the first field plate between the second doped region and the third doped region.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The semiconductor structure of the embodiment and the manufacturing method thereof, the surface region between the P-doped region and the N-type doped region is covered by the field plate (the first field plate and/or the second field plate), for example, the emitter is covered. a surface region between the doped region and the base doped region, a surface region between the base doped region and the collector doped region, or both, to improve the emitter and the base during reverse bias operation The junction breakdown voltage between the junction, the junction breakdown voltage between the base and the collector, or both. In addition, increasing the field plate not only improves the junction breakdown voltage, but also avoids the breakdown effect caused by the junction between the emitter doping region and the collector doping region. In addition, in order to improve the injection efficiency of the emitter, an emitter doping region of high impurity concentration is formed in the body region, for example, by ion implantation to reduce the resistivity of the emitter, so that the carrier is more likely to flow. Between the emitter and the base, the current of the extreme set is amplified, thereby increasing the current gain of the common-emitter amplifier circuit.

The following is a detailed description of various embodiments, which are intended to be illustrative only and not to limit the scope of the invention.

First embodiment

1 to 3 are schematic cross-sectional views showing three semiconductor structures in accordance with an embodiment of the present invention. Referring to FIG. 1 , the semiconductor structure 100 is, for example, a bi-electrode junction transistor of a common emitter, and includes a substrate 110 , a first conductivity type well region 121 , and a second conductivity type well region 122 . A body region 123, a first doping region 131, a second doping region 132, a third doping region 133, and a field plate 140. The substrate 110 is, for example, a P-type germanium substrate, and the first conductivity type well region 121 and the second conductivity type well region 122 are, for example, P-type well regions, which are respectively formed in the substrate 110. The first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type. However, the present invention is not limited thereto, and the first conductivity type may be an N type, and the second conductivity type may be a P type.

The body region 123 is, for example, a P-type doped region formed in the well region 122 of the second conductivity type. The body region 123 has a P-type impurity concentration, preferably greater than the impurity concentration of the well region 121 of the first conductivity type.

The first doping region 131 and the second doping region 132 are respectively formed in the first conductivity type well region 121 (for example, a P-type well region) and the body region 123 to do the collector doping region and the emitter doping. Area. The polarity of the second doping region 132 is the same as the polarity of the first doping region 131, for example, doping impurities of the same polarity (for example, P-type impurities). However, since the impurity concentration of the body region 123 is greater than the impurity concentration of the well region 121 of the first conductivity type, the impurity concentration of the second doping region 132 is also greater than the impurity concentration of the first doping region 131. The second doping region 132 is, for example, a P+ doping region, and can serve as a contact region of the emitter terminal E to reduce the resistivity of the second doping region 132.

In addition, the third doping region 133 is located between the first doping region 131 and the second doping region 132, and is located in a surface region of the second conductivity type well region 122 (eg, an N-type well region) as Base doped region. The polarity of the third doping region 133 is opposite to the polarity of the first doping region 131, for example, an N-type impurity and a P-type impurity are respectively doped, so that a PNP junction transistor can be formed, but the invention is not limited thereto. A transistor with an NPN junction can also be formed.

Taking a transistor with a PNP junction as an example, when a forward voltage is applied to the junction of the emitter terminal E and the base terminal B, and a reverse voltage is applied to the junction of the collector terminal C and the base terminal B, the micro-load flowing through the base terminal B The sub-current can amplify the current of the collector terminal E, so that the ratio of the current (Ic) of the collector terminal C to the current (Ib) of the base terminal B can be between 20 and 200, and the current gain effect is achieved. In this embodiment, increasing the impurity concentration in the emitter doping region reduces the resistance value of the emitter doping region and amplifies the current of the collector terminal C at a smaller base terminal B current (Ib) injection. (Ic), so the effect of current gain can be improved.

Next, referring to FIG. 1 , the field plate 140 is formed on a surface region between the second doping region 132 and the third doping region 133 and covers a partial surface region of the body region 123 . Field plate 140 may directly cover the surface area of the well region where field oxide 136 is not formed. In one embodiment, the material of the field oxide 136 is, for example, hafnium oxide for isolating the first doped region 131 (eg, the collector doped region) and the third doped region 133 (eg, the base doped region). . The material of the field plate 140 is, for example, polycrystalline germanium. Since the field plate 140 can change the electric field distribution between the second doping region 132 and the third doping region 133 and increase the range of the depletion region, the between the emitter extreme E and the base terminal B can be improved during the reverse bias operation. Junction breakdown voltage (BVebo). In addition, by increasing the field plate 140, it is further avoided that the emitter doping region is joined to the depletion region of the collector doping region to cause a breakdown effect.

Next, referring to the semiconductor structure 101 of FIG. 2, the field plate includes a first field plate 140 formed between the second doping region 132 and the third doping region 133 and formed in the first doping region 131 and the third A second field plate 141 between the doped regions 133. As described above, the first field plate 140 can increase the junction breakdown voltage (BVebo) between the emitter terminal E and the base terminal B. Similarly, the second field plate 141 can increase the junction breakdown voltage (BVcbo) between the collector terminal C and the base terminal B, and by adding the first field plate 140 and the second field plate 141, the first doping can also be avoided. A breakdown effect occurs between the region 131 and the second doping region 132.

Referring to the semiconductor structure 102 of FIG. 3, the field plate 141 is formed only between the first doping region 131 and the third doping region 133, and is originally formed in the second doping region 132 and the third doping region 133. The first field plate 140 is replaced by field oxide 136. With the field plate 141, it is also possible to increase the junction breakdown voltage (BVcbo) between the collector terminal C and the base terminal B and to avoid a breakdown effect between the first doping region 131 and the second doping region 132.

A method of fabricating the semiconductor structure 100 will be described below. Referring to FIG. 4A, a first conductivity type well region 121 and a second conductivity type well region 122 are respectively formed in the substrate 110, and a body region 123 is formed in the second conductivity type well region 122. The body region 123 has an impurity concentration of the first conductivity type, preferably greater than the impurity concentration of the well region 121 of the first conductivity type. Referring to FIG. 4B, a field oxide 136 is formed on a portion of the surface region for isolating the elements and defining the location and size of the first doped region 131. Next, a field plate 140 is formed on a portion of the surface region where the field oxide 136 is not formed to accurately define the position and size of the second doping region 132 and the third doping region 133. Referring to FIG. 4C, a doping process is performed to implant the first conductivity type impurity in the first doping region 131 and the second doping region 132, and implant the second conductivity type impurity in the third doping region. 133. The first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type, so that a PNP junction transistor can be formed. However, the invention is not limited thereto, and an NPN junction transistor can also be formed.

Since the second doping region 132 is buried in the P-type body region 123, the impurity concentration of the second doping region 132 is higher than the impurity concentration of the first doping region 131. In addition, the field plate 140 is located between the second doping region 132 and the third doping region 133 and covers a portion of the surface region of the body region 123. However, the field plate may also be formed between the first doping region 131 and the third doping region 133, such as the field plate 141 shown in FIGS. 2 and 3, and details are not described herein again.

Second embodiment

5 to 7 are schematic cross-sectional views showing three semiconductor structures in accordance with an embodiment of the present invention. Referring to FIG. 5, the semiconductor structure 200 is, for example, a bi-electrode junction transistor of a common emitter, and includes a substrate 210, a first conductivity type well region 221, and a second conductivity type well region 222. A body region 223, a first doped region 231, a second doped region 232, a third doped region 233, a field oxide 236, and a field plate 240. This embodiment differs from the first embodiment in that a field oxide 236 is formed first, and a field plate 240 covering the field oxide 236 is formed. Field oxide 236 is used to isolate the components and define the location and size of each doped region. Field oxide 236 is, for example, a local oxidation of silicon formed by thermal oxidation or a shallow trench spacer formed by etching. (shallow trench isolation, STI). With respect to the first embodiment, since the field plate 240 does not directly cover the surface area of the well region, the width dimension of the third doped region 233 (e.g., the base doped region) is susceptible to the size variation of the field oxide 236 (the beak area) ) and cannot be precisely controlled. However, in the first embodiment, when the field plate directly covers the surface area of the well region, the size of the doped region is not affected by the field oxide 136, so that the third doping region 133 (for example, the base) can be accurately controlled. The width dimension of the doped region) to improve reliability.

In FIG. 5, the field plate 240 is formed in a surface region between the second doping region 232 and the third doping region 233 to change the electric field distribution between the second doping region 232 and the third doping region 233. By increasing the range of the depletion zone, the junction breakdown voltage (BVebo) between the emitter extreme E and the base terminal B during the reverse bias operation can be improved. In addition, the configuration of the first field plate 240 and the second field plate 241 in FIG. 6 and the field plate 241 in FIG. 7 is similar to that of the first embodiment, and details are not described herein again.

Regarding the method of fabricating the semiconductor structure 200, the steps are substantially the same as those of the fourth to fourth embodiments. Referring to FIG. 8A, a first conductivity type well region 221 and a second conductivity type well region 222 are respectively formed in the substrate 210, and a body region 223 is formed in the second conductivity type well region 222. The body region 223 has a first conductivity type impurity concentration, preferably larger than the impurity concentration of the well region 221 of the first conductivity type. Referring to FIG. 8B, a field oxide 236 is formed on a portion of the surface region for isolating the elements and defining the position and size of the first doped region 231 and the third doped region 233. Next, a field plate 240 is formed on the field oxide 236 and a portion of the surface region of the body region 232 to define the location and size of the second doped region 232. Referring to FIG. 8C, a doping process is performed to implant the first conductivity type impurity in the first doping region 231 and the second doping region 232, and implant the second conductivity type impurity in the third doping region. 233. The first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type, so that a PNP junction transistor can be formed. However, the invention is not limited thereto, and an NPN junction transistor can also be formed.

Since the second doping region 232 is buried in the P-type body region 223, the impurity concentration of the second doping region 232 is higher than the impurity concentration of the first doping region 231. In addition, the field plate 240 is located between the second doping region 232 and the third doping region 233 and covers a portion of the surface region of the body region 223. However, the field plate 240 may also be formed between the first doping region 231 and the third doping region 233, such as the field plate 241 shown in FIGS. 6 and 7, which will not be described herein.

Please refer to FIG. 9 to FIG. 10, which respectively illustrate schematic diagrams of two protection circuits according to an embodiment of the invention. In Fig. 9, the emitter E and the collector C of the bipolar junction transistor 300 are connected to the high potential Vdd and the low potential Vss, respectively, and the emitter E is connected to the base B. As described above, the dual-carrier junction transistor 300 can increase the breakdown voltage by adding a field plate, and thus can be used as a clamp circuit for electrostatic discharge protection between power sources. In addition, in FIG. 10, the two-dial-electrode junction transistors 310, 320 are respectively connected in parallel with the N-type MOS transistor 302 and the P-type MOS transistor 304, and the bi-carrier junction transistor 310 The collector C and the emitter E of the other dual carrier junction transistor 320 are connected to an output/input pad 306. As described above, the two-dial-contact junction transistors 310, 320 can be used as an ESD protection circuit for the output/input pads 306 by increasing the breakdown voltage by the field plate.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100~102, 200~202. . . Semiconductor structure

110, 210. . . Base

121, 221. . . First conductivity type well area

122, 222. . . Second conductivity type well area

123, 223. . . Body area

131, 231. . . First doped region

132, 232. . . Second doped region

133, 233. . . Third doped region

136, 236. . . Field oxide

140, 240. . . Field board (first field board)

141, 241. . . Field plate (second field plate)

300, 310, 320. . . Double carrier junction transistor

302. . . N-type MOS transistor

304. . . P-type MOS transistor

306. . . Output/input pad

Vdd. . . High potential

Vss. . . Low potential

B. . . Base extreme

C. . . Extreme set

E. . . Shooting extreme

1 to 3 are schematic cross-sectional views showing three semiconductor structures in accordance with an embodiment of the present invention.

4A-4C are flow charts respectively showing a method of fabricating a semiconductor structure.

5 to 7 are schematic cross-sectional views showing three semiconductor structures in accordance with an embodiment of the present invention.

8A-8C are flow charts respectively illustrating a method of fabricating a semiconductor structure.

9 to 10 are schematic views respectively showing two protection circuits according to an embodiment of the present invention.

100. . . Semiconductor structure

110. . . Base

121. . . First conductivity type well area

122. . . Second conductivity type well area

123. . . Body area

131. . . First doped region

132. . . Second doped region

133. . . Third doped region

136. . . Field oxide

140. . . Field board

B. . . Base extreme

C. . . Extreme set

E. . . Shooting extreme

Claims (10)

A semiconductor structure comprising:
a substrate;
a first conductivity type well region and a second conductivity type well region are respectively formed in the substrate;
a body region formed in the well region of the second conductivity type;
a first doped region and a second doped region are respectively formed in the first conductivity type well region and the body region, and the second doped region has the same polarity as the first doped region And the impurity concentration of the second doping region is greater than the impurity concentration of the first doping region;
a third doped region is formed in the well region of the second conductivity type, and is located between the first doped region and the second doped region, and the polarity of the third doped region is different from the first doping region The regions are opposite in polarity; and a first field plate is formed in a surface region between the second doped region and the third doped region. The semiconductor structure of claim 1, further comprising a second field plate formed on a surface region between the first doped region and the third doped region, wherein the second field plate is made of a material Polycrystalline germanium. The semiconductor structure of claim 2, further comprising a field oxide formed on a surface region between the first doped region and the third doped region, and the second field plate covers the field oxide Things. The semiconductor structure of claim 1, further comprising a field oxide formed on a surface region between the second doped region and the third doped region, the first field plate covering the field oxide And covering a part of the surface area of the body region, the material of the first field plate is polysilicon. A semiconductor structure comprising:
a substrate;
a first conductivity type well region and a second conductivity type well region are respectively formed in the substrate;
a body region formed in the well region of the second conductivity type;
a first doped region and a second doped region are respectively formed in the first conductivity type well region and the body region, and the second doped region has the same polarity as the first doped region And the impurity concentration of the second doping region is greater than the impurity concentration of the first doping region;
a third doped region is formed in the well region of the second conductivity type, and is located between the first doped region and the second doped region, and the polarity of the third doped region is different from the first doping region The polarity of the region is reversed; and a field plate is formed in a surface region between the first doped region and the third doped region, and the field plate is made of polysilicon. A method of fabricating a semiconductor structure, the method comprising:
Providing a substrate;
Forming a first conductivity type well region and a second conductivity type well region in the substrate;
Forming a body region in the well region of the second conductivity type;
Forming a first doped region and a second doped region respectively in the well region of the first conductivity type and the body region, the polarity of the second doped region being the same as the polarity of the first doped region, and The impurity concentration of the second doping region is greater than the impurity concentration of the first doping region;
Forming a third doped region in the well region of the second conductivity type, and between the first doped region and the second doped region, the polarity of the third doped region and the first doping The polarity of the regions is reversed; and a surface region of the first field plate between the second doped region and the third doped region is formed. The method of claim 6, further comprising forming a surface region of the second field plate between the first doped region and the third doped region, wherein before forming the second field plate, The surface region including the formation of a field oxide between the first doped region and the third doped region, and after forming the second field plate, the second field plate covers the field oxide, and the second The material of the field plate is polycrystalline germanium. The method of claim 6, wherein before forming the first field plate, further comprising forming a surface region of a field oxide between the second doped region and the third doped region, and forming the After the first field plate, the first field plate covers the field oxide, and the first field plate covers a portion of the surface area of the body region, and the first field plate is made of polysilicon. A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a first conductivity type well region and a second conductivity type well region in the substrate;
Forming a body region in the well region of the second conductivity type;
Forming a first doped region and a second doped region respectively in the well region of the first conductivity type and the body region, the polarity of the second doped region being the same as the polarity of the first doped region, and The impurity concentration of the second doping region is greater than the impurity concentration of the first doping region;
Forming a third doped region in the well region of the second conductivity type, and between the first doped region and the second doped region, the polarity of the third doped region and the first doping The polarity of the regions is reversed; and a surface region is formed between the first doped region and the third doped region, and the field plate is made of polysilicon. The method of claim 9, wherein before forming the field plate, further comprising forming a surface region of a field oxide between the first doped region and the third doped region, and forming the field plate Thereafter, the field plate covers the field oxide.