TWI559312B - memory device and programming method thereof - Google Patents

Description

Memory device and its stylized method

The present invention relates to a device and method of operation thereof, and more particularly to a memory device and a method of stylizing the same.

Flash memory is typically a memory array using a NAND or NOR architecture, where NAND memory arrays are suitable for high-density data storage. In general, a NAND memory array includes a plurality of memory cell strings, and each memory cell string is electrically connected between the corresponding bit line and the common source line. In addition, the stylization method of the NAND memory array is mostly from the side of the NAND memory array close to the common source line, and the plurality of memory cells in the memory cell string are programmed one by one in the direction toward the bit line. In addition, when reading a stylized memory cell, the threshold voltage of the memory cell tends to shift in response to the back pattern effect. Therefore, the existing stylization method avoids the shift of the threshold voltage caused by the back model effect by changing the stylized order of the memory cells. However, as the stylized order of the memory cells changes, the channel voltage of the memory string that does not need to be programmed may be blocked by the memory cell with a high threshold voltage and cannot be normally raised, thereby causing program disturbance. ).

The invention provides a memory device and a stylized method thereof, which can avoid the influence of the back model effect, and can reduce the program disturbance by the advancement of the channel voltage of the memory cell.

The stylized method of the memory device of the present invention includes the following steps, wherein the memory array in the memory device includes first and second memory cell strings. During the first period, the first voltage from the common source line is transmitted to the first end of the first and second memory cell strings, and the second ends of the first and second memory cell strings are floated. Wherein, the common source line is on the first side of the memory array. And, during the second period, floating the first ends of the first and second memory strings, and transmitting the second and third voltages to the second ends of the first and second memory strings, respectively, and providing a program The voltage and the plurality of turn-on voltages are disabled to disable the stylization of the first memory cell string, and the plurality of memory cells in the second memory cell string are sequentially programmed from the second side of the memory array.

The memory device of the present invention includes a memory array and a memory controller. The memory array includes first and second memory cell strings. During the first period, the memory controller transmits a first voltage from the common source line to the first end of the first and second memory strings, and floats the second end of the first and second memory strings . Wherein, the common source line is on the first side of the memory array. During the second period, the memory controller floats the first ends of the first and second memory cell strings, and transmits the second and third voltages to the second ends of the first and second memory cell strings, respectively, and A stylized voltage and a plurality of turn-on voltages are provided to disable stylization of the first memory cell string, and sequentially program a plurality of memory cells in the second memory cell string from the second side of the memory array.

Based on the above, the present invention transmits the first voltage from the common source line to the first end of the memory cell string during the first period, and sequentially stylizes the memory from the second side of the memory array during the second period. Cell. Thereby, the influence of the back model effect can be avoided, and the program disturbance can be reduced by the advancement of the channel voltage of the memory cell.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. As shown in FIG. 1, the memory device 100 includes a memory array 110 and a memory controller 120. The memory array 110 can be, for example, a NAND memory array, and the memory array 110 includes a plurality of selection transistors 131 and 132, a plurality of ground transistors 141 and 142, and a plurality of memory cells 151~ 154 and 161~164. The selection transistors 131 and 132 are electrically connected to the string selection line SSL1, the grounding transistors 141 and 142 are electrically connected to the ground selection line GSL1, and the memory cells 151 to 154 and 161 to 164 are electrically connected to the word lines WL1 to WL4.

The memory cells 151 to 154 are connected in series to form a memory cell string 111. In addition, the first end of the memory cell string 111 is electrically connected to the common source line CSL1 through the grounding transistor 141, and the second end of the memory cell string 111 is electrically connected to the bit line BL1 through the selection transistor 131. By analogy, the first end of the memory cell string 112 formed by the memory cells 161-164 is electrically connected to the common source line CSL1 through the grounding transistor 142, and the second end of the memory cell string 112 is transmitted through the selection transistor 132. Electrically connected to the bit line BL2. The common source line CSL1 is located on the first side of the memory array 110, and the bit lines BL1 and BL2 are located on the second side of the memory array 110.

The memory controller 120 includes a first decoder 121 and a second decoder 122. The first decoder 121 and the second decoder 122 may select the memory cells in the memory array 110 according to the address of the address, so as to program, read, or erase the selected memory cells. Moreover, in an embodiment, the memory array 110 can be, for example, a 2D array structure, and the first decoder 121 and the second decoder 122 can be, for example, a row decoder and a row decoder. Column decoder. In another embodiment, the memory array 110 can be, for example, a 3D array structure, and the first decoder 121 includes a column decoder and a plane decoder, and the second decoder 122 can be, for example, Is the row decoder.

It is worth mentioning that the stylized program of the memory array 110 includes pre-charging operations and stylized operations. The memory string (eg, the memory cell string 112) to be programmed in the memory array 110 can be set as the selected memory cell string, and the remaining memory cell strings (eg, the memory cell string 111) can be set. For non-selected memory cell strings. During the stylization operation, the memory controller 120 can program the memory cells in the selected memory cell string one by one from the side of the memory array 110 near the bit line, along the direction toward the common source line CSL1. . In addition, the memory controller 120 can boost the channel voltage of each memory string through a precharge operation before the programmed memory string is programmed. Thereby, the pre-charging operation can pre-upgrade the channel voltage of the unselected memory cell string, thereby reducing the program disturb of the memory cell.

In order to make the invention more general in the art, FIG. 2 is a flow chart of a stylized method of a memory device in accordance with an embodiment of the present invention. As shown in step S210, during the first period, the memory controller 120 can transmit the first voltage from the common source line CSL1 to the first end of the memory cell string 111 (ie, the first memory cell string). The first voltage is transmitted to the first end of the memory string 112 (ie, the second memory string). In addition, the memory controller 120 can float the second ends of the memory strings 111 and 112. Thereby, the memory controller 120 will perform a precharge operation on the memory array 110 to boost the channel voltage of the memory strings 111 and 112 with the first voltage.

For example, FIG. 3 is a detailed flow chart for explaining the steps of FIG. 2, and FIG. 4 is a timing chart for explaining a stylized method of the memory device according to an embodiment of the present invention. Here, reference numerals VBL1, VBL2, VCSL1, VSSL1, and VGSL1 in FIG. 4 are used to indicate voltages supplied to the bit line BL1, the bit line BL2, the common source line CSL1, the string selection line SSL1, and the ground selection line GSL1, respectively.

As seen in the detailed steps of step S210, as shown in step S310, in the first period T41, the memory controller 120 can provide the first voltage V41 to the common source line CSL1. In addition, as shown in step S320, the memory controller 120 can provide the high voltage VH4 to the ground selection line GSL1 to turn on the ground transistors 141 and 142 with the high voltage VH4. Thereby, the first voltage V41 transmits the permeable grounded transistors 141 and 142 to the first ends of the memory strings 111 and 112. Furthermore, as shown in step S330, the memory controller 120 can provide the low voltage VL4 to the string selection line SSL1 to non-conduct the selection transistors 131 and 132 and cause the second ends of the memory strings 111 and 112 to remain floating. The state of the connection. In this way, in the first period T41, the memory controller 120 can advance the channel voltages of the memory cell strings 111 and 112 by using the first voltage V41.

Referring to FIG. 1 and FIG. 2, as shown in step S220, during the second period, the memory controller 120 can float the first ends of the memory strings 111 and 112, and separate the second voltage from the third voltage. It is transmitted to the second ends of the memory strings 111 and 112. Thereby, the memory cell string 111 will be regarded as a non-selected memory cell string, and the memory cell string 112 will be regarded as a selected memory cell string to be programmed. In addition, the memory controller 120 can provide a stylized voltage and a plurality of turn-on voltages to disable the stylization of the memory cell string 111, and sequentially program the memory in the memory cell string 112 from the second side of the memory array 110. Cell 161~164.

For example, referring to FIG. 1 , FIG. 3 and FIG. 4 simultaneously, in the second period T42, as shown in step S340, the memory controller 120 can transmit the second voltage V42 to the bit line BL1, and The third voltage V43 is transmitted to the bit line BL2. Wherein, the second voltage V42 may be, for example, a high voltage VH4 (eg, 3.3 volts), and the third voltage V43 may be, for example, a low voltage (eg, 0 volts). Further, the first voltage V41 may be, for example, 2 volts. That is, the first voltage V41 is smaller than the second voltage V42, and the first voltage V41 is greater than the third voltage V43. Furthermore, as shown in step S350, the memory controller 120 can turn off the ground transistors 141 and 142 by using the low voltage VL4 transmitted by the ground selection line GSL1, and can be turned on by using the high voltage VH4 transmitted by the string selection line SSL1. The transistors 131 and 132 are selected. Thereby, the first end of the memory cell string 111 will be floated, and the second end of the memory cell string 111 will receive the second voltage V42. Similarly, the first end of the memory cell string 112 will float and the second end of the memory cell string 112 will receive the third voltage V43.

As shown in step S360, the memory controller 120 may select each of the memory cells 112 one by one from the second side of the memory array 110 to set each of the memory cells 112 one by one. A selected memory cell. In addition, as shown in step S370, the memory array 110 can provide a stylized voltage V44 to the word line electrically connected to the selected memory cell, and provide the turn-on voltage V45 to the remaining word lines. For example, memory cell 164 will be selected as the selected memory cell. At this time, the memory controller 120 provides the stylized voltage V44 to the word line WL4 and provides the turn-on voltage V45 to the word lines WL1 WL WL3 to program the memory cell 164.

In other words, the memory controller 120 will provide the stylized voltage V44 to the word lines WL1 WL WL4 one by one from the second side of the memory array 110 to program the memory cells 161 164 164 one by one. That is, the memory controller 120 is a memory cell 161-164 in the memory cell string 112 that is programmed one by one from top to bottom. Therefore, although the stylized memory cell 161 has a high threshold voltage, the threshold voltage of the memory cell 161 can be prevented from being affected by the back model effect.

Moreover, when the memory cell string 112 (i.e., the selected memory cell string) is programmed, the channel voltage of the memory cell string 111 (i.e., the unselected memory cell string) is boosted in response to the turn-on voltage. It is worth mentioning that when the memory cell 154 in the memory cell string 111 adjacent to the second side of the memory array 110 has a high threshold voltage, the memory cell 154 will block the channel voltage increase of the memory cell string 111. In addition, when the channel voltage of the memory cell string 111 is too low, the threshold voltage of the memory cell in the memory cell string 111 will be affected by the stylization of the memory cell string 112, thereby causing program disturb. Therefore, in order to avoid the above-mentioned program disturb, the memory controller 120 may first boost the channel voltage of the memory cell string 111 by performing a precharge operation before performing the stylization of the memory cell string 112. In this way, during the programming of the memory cell string 112, the memory cell string 111 will have a sufficiently high channel voltage to avoid variations in the threshold voltage of the memory cells 151-154, thereby reducing program disturb.

For example, FIG. 5 is a schematic diagram for explaining a channel voltage of a memory cell string according to an embodiment of the invention. In the FIG. 5 embodiment, memory cell string 111 (i.e., unselected memory cell string) includes a plurality of memory cells coupled to word lines WL1 WL WL15. In addition, FIG. 5 illustrates the channel voltages of the selected transistor 131, the plurality of memory cells and the grounded transistor 141, and the corresponding string selection line SSL1, the word lines WL1 WL WL15 and the ground selection line GSL1 are along The horizontal axis is indicated.

As shown by curve 510, when the memory controller 120 does not pre-elevate the channel voltage of the memory cell string 111, and the memory cell 154 does not have a high threshold voltage, the channel voltage of the memory cell string 111 will rise to approximately in response to the turn-on voltage. 8.5 volts. Moreover, as shown by the curve 520, when the memory cell 154 has a high threshold voltage and the memory controller 120 does not pre-raise the channel voltage of the memory cell string 111, the channel voltage of the memory cell string 111 will rise in response to the turn-on voltage. To about 6.7 volts.

On the other hand, as shown by the curve 530, when the memory cell 154 has a high threshold voltage and the memory controller 120 first boosts the channel voltage of the memory cell string 111 through the precharge operation, the channel voltage of the memory cell string 111 will be responsive. Increased to approximately 8.5 volts at turn-on voltage. In other words, since the memory controller 120 can first increase the channel voltage of the memory cell string 111 through the precharge operation, during the programming of the memory cell string 112, the memory cell string 111 will have a sufficiently high channel voltage to avoid The threshold voltage of the memory cells 151 to 154 changes, so that the program disturbance can be reduced.

In summary, the present invention transmits the first voltage from the common source line to the first end of the memory cell string during the first period, thereby preliminarily increasing the channel voltage of the memory cell. Wherein, the common source line is on the first side of the memory array. In addition, the present invention sequentially programs the memory cells from the second side of the memory array during the second period. Thereby, the influence of the back model effect can be avoided, and the program disturbance can be reduced by the advancement of the channel voltage of the memory cell.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device
110‧‧‧Memory array
120‧‧‧ memory controller
111, 112‧‧‧ memory strings
131, 132‧‧‧Selecting a crystal
141, 142‧‧‧ Grounding crystal
151~154, 161~164‧‧‧ memory cells
SSL1‧‧‧ string selection line
GSL1‧‧‧ Grounding selection line
WL1~WL4‧‧‧ character line
BL1, BL2‧‧‧ bit line
CSL1‧‧‧Common source line
121‧‧‧First decoder
122‧‧‧Second decoder
S210, S220‧‧‧ steps in Figure 2
S310~S370‧‧‧Steps in Figure 3
VBL1, VBL2, VCSL1, VSSL1, VGSL1‧‧‧ voltage
First period of T41‧‧
Second period of T42‧‧
V41‧‧‧First voltage
V42‧‧‧second voltage
V43‧‧‧ third voltage
V44‧‧‧Standard voltage
V45‧‧‧ turn-on voltage
VH4‧‧‧ high voltage
VL4‧‧‧ low voltage
510~530‧‧‧ Curve

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. 2 is a flow chart of a stylized method of a memory device in accordance with an embodiment of the present invention. Figure 3 is a detailed flow chart for explaining the steps of Figure 2. 4 is a timing diagram for explaining a stylized method of a memory device in accordance with an embodiment of the present invention. FIG. 5 is a schematic diagram for explaining a channel voltage of a memory cell string according to an embodiment of the invention.

S210, S220‧‧‧ steps in Figure 2

Claims (10)

A staging method for a memory device, wherein a memory array in the memory device includes a first and a second memory cell string, and the stylized method of the memory device includes: during a first period, Transmitting a first voltage from a common source line to the first end of the first and second memory strings, and floating the second end of the first and second memory strings, and the common source a pole line is located on a first side of the memory array; and in a second period, floating the first end of the first and second memory cell strings, and respectively separating a second and a third voltage Transmitting to the second end of the first and second memory cell strings, and providing a stylized voltage and a plurality of turn-on voltages to disable stylization of the first memory cell string and from the memory array The two sides begin to programmatically program a plurality of memory cells in the second memory cell string. The method for staging a memory device according to claim 1, wherein the first end of the first and second memory strings are electrically connected to the common source through a first and a second grounding transistor. The first end and the second end of the second memory cell are electrically connected to a first and a second bit line through a first and a second selection transistor, and during the first period, Transmitting the first voltage from the common source line to the first end of the first and second memory cell strings, and floating the second end of the first and second memory cell strings comprises: providing The first voltage is applied to the common source line; the first and the second grounded transistors are turned on; and the first and second selected transistors are not turned on. The method for staging a memory device according to claim 2, wherein the first and the second memory cell are electrically connected to the plurality of word lines, and in the second period, floating the first And a first end of the second memory cell string, and transmitting the second and the third voltage to the second end of the first and second memory cell strings respectively, and providing the stylized voltage and the The step of turning on the voltage includes: transmitting the second and the third voltage to the first and second bit lines, respectively; turning on the first and second selection transistors, and not turning on the first and the first Two grounded transistors; each of the memory cells are selected one by one from the second side of the memory array to set each of the memory cells as a selected memory cell one by one; and the stylized voltage is supplied to the electrical The word line connecting the selected memory cells is connected and the turn-on voltages are supplied to the remaining word lines. The method for staging a memory device according to claim 3, wherein the first and the second selection transistors are electrically connected to a string of selection lines, and the first and the second ground transistors are electrically connected. a ground selection line, and the staging method of the memory device further includes: transmitting, during the first period, a high voltage and a low voltage to the ground selection line and the string selection line, respectively; and in the second During the period, the low voltage and the high voltage are respectively transmitted to the ground selection line and the string selection line. The method of staging a memory device according to claim 4, wherein the second voltage is equal to the high voltage, and the third voltage is equal to the low voltage. The method of staging a memory device according to claim 1, wherein the memory array is an inverted gate memory array. The method of staging a memory device according to claim 1, wherein the first voltage is less than the second voltage, and the first voltage is greater than the third voltage. A memory device includes: a memory array including a first and a second memory cell string; and a memory controller, wherein the memory controller will be from a common source line during a first period a first voltage is transmitted to the first end of the first and second memory cell strings, and floats to the second end of the first and second memory cell strings, the common source line is in the memory a first side of the array, and in a second period, the memory controller floats the first ends of the first and second memory strings, and transmits a second and a third voltage to And the second end of the first and the second memory cell string, and providing a stylized voltage and a plurality of turn-on voltages to disable stylization of the first memory cell string and from a second side of the memory array Begin to programmatically program a plurality of memory cells in the second memory cell string. The memory device of claim 8, wherein the first end of the first and second memory strings are electrically connected to the common source line through a first and a second grounding transistor, The first end and the second end of the second memory cell are electrically connected to a first and a second bit line through a first and a second selection transistor, and during the first period, the memory is controlled. The first voltage is supplied to the common source line, and the memory controller turns on the first and second grounding transistors, and does not turn on the first and second selection transistors. The memory device of claim 9, wherein the first and the second memory cell are electrically connected to the plurality of word lines, and during the second period, the memory controller provides the And the third voltage to the first and second bit lines, the memory controller turns on the first and second selection transistors, and does not turn on the first and second ground transistors, and The memory controller selects each of the memory cells one by one from the second side of the memory array to set each of the memory cells as a selected memory cell one by one, and the memory controller provides the program The voltage is electrically connected to the word line of the selected memory cell and the turn-on voltage is supplied to the remaining word lines.