KR20140016712A - Semiconductor memory device and operating method thereof - Google Patents

Semiconductor memory device and operating method thereof Download PDF

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Publication number
KR20140016712A
KR20140016712A KR1020120083835A KR20120083835A KR20140016712A KR 20140016712 A KR20140016712 A KR 20140016712A KR 1020120083835 A KR1020120083835 A KR 1020120083835A KR 20120083835 A KR20120083835 A KR 20120083835A KR 20140016712 A KR20140016712 A KR 20140016712A
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South Korea
Prior art keywords
memory cells
dummy
voltage
plurality
select
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KR1020120083835A
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Korean (ko)
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양해종
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에스케이하이닉스 주식회사
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Publication of KR20140016712A publication Critical patent/KR20140016712A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/344Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445Circuits or methods to verify correct erasure of nonvolatile memory cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • G11C11/5635Erasing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification

Abstract

The present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device according to the embodiment of the present invention includes: a selection transistor; a plurality of memory cells which are serially connected; and a plurality of dummy memory cells which are arranged between the selection transistor and the memory cells. In an erasing operation, a higher voltage is applied to each dummy memory cell accordingly as each dummy memory cell is closer to the selection transistor.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

The present invention relates to a semiconductor memory device and a method of operating the same.

Semiconductor memory is a memory device that is implemented using a semiconductor such as silicon (Si), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), or indium phosphide (InP). Semiconductor memory is divided into volatile memory and nonvolatile memory.

Volatile memory is a memory device that loses its stored data when its power supply is interrupted. Volatile memory includes static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory is a memory device that retains data that has been stored even when the power supply is turned off. Non-volatile memory includes Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash memory, Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. Flash memory is divided into NOR type and NOR type.

Dummy memory cells may be used in a memory cell array of a semiconductor memory device. In order to normally operate the memory cells disposed outside, dummy memory cells are provided, for example, to mitigate interference effects when various operations of the semiconductor memory device are performed.

An embodiment of the present invention is to provide a semiconductor memory device having improved reliability by reducing the degradation of the memory cell array.

In an embodiment, a semiconductor memory device may include a select transistor; A plurality of memory cells connected in series; And a plurality of dummy memory cells disposed between the selection transistor and the plurality of memory cells, wherein, in an erase operation, each of the plurality of dummy memory cells is provided with a higher voltage nearer to the selection transistor.

In example embodiments, the voltage provided to the dummy memory cell adjacent to the selection transistor may be controlled to be equal to the voltage of the selection line connected to the selection transistor. The select line connected to the select transistor and the dummy word line connected to the dummy memory cell adjacent to the select transistor may be floated.

In an embodiment, during the erase verify operation after the erase operation, a higher dummy verify voltage may be applied to each of the plurality of dummy memory cells as they are closer to the selection transistor.

In an embodiment, a semiconductor memory device may include a memory cell array including a select transistor, a plurality of memory cells connected in series, and a plurality of dummy memory cells disposed between the select transistor and the plurality of memory cells; And a peripheral circuit configured to provide a higher voltage as each of the plurality of dummy memory cells is adjacent to the selection transistor during an erase operation.

In example embodiments, the peripheral circuit may be configured to float a select line connected to the select transistor and a dummy word line connected to a dummy memory cell adjacent to the select transistor.

In example embodiments, the peripheral circuit may be configured to apply a higher dummy verify voltage to each of the plurality of dummy memory cells in the erase verify operation after the erase operation.

Another aspect of the present invention relates to a method of operating a semiconductor memory device. According to at least one example embodiment of the inventive concepts, a method of operating a semiconductor memory device may include: floating a select line connected to a select transistor during an erase operation; When the select line is floated, each of the plurality of dummy memory cells disposed between the select transistor and the memory cells is provided with a higher voltage nearer to the select transistor.

In example embodiments, the operation method may further include applying a higher dummy word line voltage to each of the plurality of dummy memory cells in the erase verify operation after the erase operation.

In example embodiments, the voltage provided to the dummy memory cell adjacent to the selection transistor may be controlled to be the same voltage as the voltage of the selection line.

In example embodiments, a dummy word line connected to a dummy memory cell adjacent to the selection transistor may be floated.

According to the embodiment of the present invention, a semiconductor memory device having improved reliability is provided.

1 is a block diagram showing a semiconductor memory device.
FIG. 2 is a circuit diagram showing one of the plurality of memory blocks of FIG. 1. FIG.
3 is a diagram illustrating a part of any one of the cell strings of FIG. 2.
4 is a table illustrating voltages provided to row lines according to an exemplary embodiment of the present invention.
FIG. 5 is a timing diagram illustrating voltages of row lines according to the table of FIG. 4.
6 is a table illustrating voltages provided to row lines according to another exemplary embodiment of the present invention.
7 is a flowchart illustrating a method of performing erase in the semiconductor memory device of FIG. 1 when erase is performed.
8 is a table showing voltages applied to row lines in an erase verify operation.
9 is a diagram illustrating a threshold voltage distribution of memory cells and dummy memory cells after erase is performed.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

FIG. 1 is a block diagram showing a semiconductor memory device 100. FIG.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 includes a memory cell array 110 and a peripheral circuit 120 for driving the memory cell array 110.

The memory cell array 110 is connected to the address decoder 121 through the row lines RL and to the read and write circuit 123 through the bit lines BL. Row lines RL include source select lines, dummy word lines, word lines, and drain select lines (see FIG. 2). The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an exemplary embodiment, the plurality of memory cells are nonvolatile memory cells. In some example embodiments, each of the plurality of memory cells may be a single level cell or a multi level cell. When each of the plurality of memory cells is a single level cell, memory cells connected to one word line constitute one page. When each of the plurality of memory cells is a multi-level cell, memory cells connected to one word line constitute two or more pages.

The peripheral circuit 120 drives the memory cell array 110. The peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read and write circuit 123, and a control logic 124.

The address decoder 121 is connected to the memory cell array 110 through the row lines RL. The address decoder 121 is configured to operate in response to control of the control logic 124. The address decoder 121 receives an address ADDR from an external input / output buffer (not shown) inside the semiconductor memory device 100.

The address decoder 121 is configured to decode the block address among the received addresses ADDR. The address decoder 121 selects one memory block according to the decoded block address.

The address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 will select one of the word lines according to the decoded row address.

The address decoder 121 may decode a column address among the received addresses ADDR and transmit the decoded column address Yi to the read and write circuit 123.

An erase operation of the semiconductor memory device is performed in units of memory blocks. The read operation and the program operation of the semiconductor memory device are performed in units of pages. In an erase operation, the address ADDR will include a block address. The address decoder 121 will select one memory block according to the address ADDR. In read and program operations, the address ADDR will include a block address, a row address, and a column address. The address decoder 121 may select one memory block and one word line according to the address ADDR and provide the decoded column address Yi to the read and write circuit 123.

In an exemplary embodiment, the address decoder 121 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the semiconductor memory device 100. The voltage generator 122 operates in response to the control of the control logic 124. The voltage generator 122 may generate a plurality of voltages by regulating an external power supply voltage or by amplifying the external power supply voltage using a plurality of pumping capacitors.

In an erase operation, the voltage generator 122 may include a word line voltage Vwl to be applied to word lines, a plurality of dummy word line voltages Vdm to be applied to dummy word lines, and a memory cell array 110. And an erase voltage Vers to be applied to the bulk region.

In the erase operation, the erase voltage Vers generated by the voltage generator 122 is applied to the bulk region of the memory cell array 110. When the erase voltage Vers is applied, the address decoder 121 applies the word line voltage Vwl to word lines connected to the selected memory block and plots the word lines WL connected to the unselected memory block. flaoting). The address decoder 121 applies a plurality of dummy word line voltages Vdm to the plurality of dummy memory cells, respectively. This is explained in more detail with reference to FIGS. 4 and 5.

The read and write circuit 123 is connected to the memory blocks BLK1 to BLKz through the bit lines BL. The read and write circuit 123 operates in response to control of the control logic 124.

In the program operation and the read operation, the read and write circuit 123 exchanges data DATA with an input / output buffer (not shown) of the external or semiconductor memory device 100. In programming, the read and write circuit 123 receives the data DATA and programs the received data DATA into memory cells of the selected word line. In a read operation, the read and write circuit 130 reads data from the memory cells of the selected word line and outputs data DATA corresponding to the decoded column address Yi among the read data.

In an exemplary embodiment, the read and write circuit 130 may include page buffers (or page registers), column selection circuit, and the like.

The control logic 124 is coupled to an address decoder 121, a voltage generator 122 and a read and write circuit 123. The control logic 124 receives the control signal CTRL from the input or output buffer (not shown) of the external or semiconductor memory device 100. The control logic 124 is configured to control all operations of the semiconductor memory device 100 in response to the control signal CTRL.

Although not shown in FIG. 1, the semiconductor memory device 100 may further include an input / output buffer (not shown). The input / output buffer will receive the control signal CTRL and address ADDR from the outside and deliver the received control signal CTRL and address ADDR to the control logic 124 and address decoder 121, respectively. In addition, the input / output buffer may be configured to transfer data DATA from the outside to the read and write circuit 123 and transfer data DATA from the read and write circuit 123 to the outside.

In an exemplary embodiment, the semiconductor memory device 100 may be a flash memory device.

2 is a circuit diagram showing one of the plurality of memory blocks BLK1 to BLKz (BLK1) of FIG.

Referring to FIG. 2, the memory block BLK1 includes a plurality of cell strings CS1 to CSm. Each cell string includes a source select transistor SST, a plurality of source side dummy memory cells SM1 to SM3, a plurality of memory cells M1 to Mn connected in series, a plurality of drain side dummy memory cells DM1 to DM3, and a drain. And a selection transistor DST.

In FIG. 2, for convenience of description, three source side dummy memory cells SM1 to SM3 and three drain side dummy memory cells DM1 to DM3 are provided for each cell string. However, it is to be understood that the present invention is not limited thereto and that the technical idea of the present invention is not limited thereto.

The memory block BLK1 may include a source select line SSL, first to third source side dummy word lines SDL1 to SDL3, first to nth word lines WL1 to WLn, and first to third drains. It is connected to the address decoder 121 through the side dummy word lines DDL1 to DDL3 and the drain select line DSL. The memory block BLK1 is connected to the read and write circuit 123 through the first to m-th bit lines BL1 to BLm. The row lines RL described with reference to FIG. 1 may include a source select line SSL, first to third source side dummy word lines SDL1 to SDL3, and first to nth word lines WL1 to WLn. ), First to third drain side dummy word lines DDL1 to DDL3, and a drain select line DSL.

The source select transistor SST is connected to the source select line SSL. The first to third source side dummy memory cells SM1 to SM3 are connected to the first to third source side dummy word lines SDL1 to SDL3, respectively. The first to nth memory cells M1 to Mn are connected to the first to nth word lines WL1 to WLn, respectively. The first to third drain side dummy memory cells DM1 to DM3 are connected to the first to third drain side dummy word lines DDL1 to DDL3, respectively. The drain select transistor DST is connected to the drain select line.

The common source line SL is commonly connected to the source side of the source select transistor SST of each of the plurality of cell strings CS1 to CSm. A corresponding bit line is connected to the drain side of the drain select transistor DST of each of the cell strings CS1 to CSm.

FIG. 3 is a diagram illustrating a part of any one CS1 of the cell strings CS1 to CSm of FIG. 2. For convenience of description, only the source select transistor SST, the first to third source side dummy memory cells SM1 to SM3, and the first memory cell M1 are shown in FIG. 3.

One memory cell M1 includes a control gate and a floating gate. As is well known, the dummy memory cell has the same configuration as the memory cell M1. That is, each of the source side dummy memory cells SDL1 to SDL3 includes a control gate and a floating gate. The source select transistor SST includes a control gate and a floating gate, and a contact 20 for electrically connecting the control gate and the floating gate.

In the erase operation, a high voltage erase voltage Vers is applied to the bulk region 10. For example, 0V is applied to the word line WL1. The common source line SL and the source select line SSL are floated. Therefore, when the erase voltage Vers rises, the voltages of the common source line SL and the source select line SSL also increase.

As shown in FIG. 3, it is assumed that 0 V is applied to the first to third source side dummy word lines SDL1 to SDL3. The first to third source side dummy word lines SDL1 to SDL3 are maintained at 0V, while the source select line SSL is raised by the erase voltage Vers applied to the bulk region 10. Accordingly, the coupling cap C may be generated between the source select transistor SST and the first to third source side dummy memory cells SM1 to SM3. When the coupling cap C is generated every time the erase operation is performed, an insulating film (eg, between the source select transistor SST and the first to third source side dummy memory cells SM1 to SM3, in particular SM1) may be used. oxide file) will degrade. This deterioration phenomenon becomes worse as the difference between the voltage applied to the first to third source side dummy word lines SDL1 to SDL3 and the voltage applied to the source select line SSL increases. In addition, the degradation phenomenon becomes more severe as the interval between the memory cells of the memory cell array 100 (refer to FIG. 1) becomes smaller.

As described above with reference to FIG. 3, when the erase operations are repeatedly performed, the insulating layer between the drain select transistor DST (see FIG. 2) and the first to third drain side dummy memory cells DM1 to DM3 may be degraded.

4 is a table illustrating voltages provided to row lines RL according to an exemplary embodiment of the present invention.

2 and 4, a word line voltage Vwl, for example, a ground voltage is applied to the word lines WL1 to WLn. As the threshold voltages of the memory cells M1 to Mn decrease according to the difference between the erase voltage Vers and the word line voltage Vwl of the bulk region 10 (refer to FIG. 3), data of the memory cells M1 to Mn is reduced. Will be erased.

The source select line SSL and the drain select line DSL are floated.

According to an embodiment of the present invention, each of the dummy memory cells SM1 to SM3 or DM1 to DM3 is provided with a higher voltage as it is closer to the selection transistor SST or DST.

The first source side dummy word line SDL1 is closest to the source select line SSL. In an exemplary embodiment, the first source side dummy word line SDL1 is controlled to have the same voltage as the source select line SSL. As shown in FIG. 4, the first source side dummy word line SDL1 may be floated like the source select line SSL. Accordingly, the voltage of the first source side dummy word line SDL1 may rise to a specific voltage, similar to the source select line SSL.

The first dummy word line voltage Vdm1 is applied to the second source side dummy word line SDL2. The first dummy word line voltage Vdm1 may be set lower than the voltage of the first source side dummy word line SDL1.

The second dummy word line voltage Vdm2 is applied to the third source side dummy word line SDL3. The second dummy word line voltage Vdm2 may be lower than the first dummy word line voltage Vdm1. In an exemplary embodiment, the second dummy word line voltage Vdm2 may have a level equal to or higher than that of the word line voltage Vwl.

The first to third drain side dummy word lines DDL1 to DDL3 may be controlled similarly to the first to third source side dummy word lines SDL1 to SDL3, respectively. In an exemplary embodiment, the first drain side dummy word line DDL1 may be controlled to have the same voltage as the drain select line DSL. The first drain side dummy word line DDL1 may be floated. The first dummy word line voltage Vdm1 set to be lower than the voltage of the first drain side dummy word line DDL1 may be applied to the second drain side dummy word line DDL2. The second dummy word line voltage Vdm2 lower than the first dummy word line voltage Vdm1 may be applied to the third drain side dummy word line DDL3.

 FIG. 5 is a timing diagram illustrating voltages of row lines RL according to the table of FIG. 4.

2 and 5, the erase voltage Vers is applied to the bulk region 10 (see FIG. 3) at the first time t1. The erase voltage Vers rises to reach the first voltage V1, for example 20V.

Since the source select line SSL and the drain select line DSL are floating, they rise together with the erase voltage Vers to reach the second voltage V2. The second voltage V2 is lower than the first voltage V1.

Since the first source side dummy word line SDL1 is also floated, the first source side dummy word line SDL1 rises together with the erase voltage Vers to reach the second voltage V2.

The first dummy word line voltage Vdm1 is applied to the second source side dummy word line SDL2 at a first time t1. The first dummy word line voltage Vdm1 rises to reach a third voltage V3 lower than the second voltage V2.

The second dummy word line voltage Vdm2 is applied to the third source side dummy word line SDL3 at a second time t2. The second dummy word line voltage Vdm2 is maintained at, for example, a ground voltage. In another embodiment, the second dummy word line voltage Vdm2 may rise to reach a specific voltage lower than the third voltage V3.

As a result, each of the source-side dummy memory cells SM1 to SM3 connected to the source-side dummy word lines SDL1 to SDL3 is provided with a higher voltage as it is closer to the source select transistor SST.

The word line voltage Vwl is maintained at ground voltage, for example. Due to the difference between the erase voltage Vers and the word line voltage Vwl, the threshold voltages of the memory cells M1 to Mn may decrease.

The first to third drain side dummy word lines DDL1 to DDL3 may be controlled to be the same as the first to third source side dummy word lines SDL1 to SDL3, respectively.

As the erase voltage Vers decreases at the second time t2, the floating source select line SSL, the drain select line DSL, and the first dummy word lines SDL1 and DDL1 also decrease.

In addition, the second dummy word lines SDL2 and DDL2 are discharged so that the first dummy word line voltage Vdm1 decreases at the second time t2. The second dummy word line voltage Vdm2 is kept at, for example, a ground voltage.

According to an embodiment of the present invention, each of the dummy memory cells SM1 to SM3 or DM1 to DM3 is provided with a higher voltage as it is closer to the selection transistor SST or DST. Accordingly, the size of the coupling cap generated between the selection transistor SST or DST and the dummy memory cells SM1 to SM3 or DM1 to DM3 is relatively small, and the memory cell array 110 (see FIG. 1) is degraded. The phenomenon will be reduced. Thus, a semiconductor memory device having improved reliability is provided.

FIG. 6 is a table illustrating voltages provided to row lines RL according to another exemplary embodiment.

The row lines RL are controlled in the same manner as in FIG. 5 except that the zero dummy word line voltage Vdm0 is applied to the first dummy word lines SDL1 and DDL1.

The zero dummy word line voltage Vdm0 may be higher than the first dummy word line voltage Vdm1. The first dummy word line voltage Vdm1 may be higher than the second dummy word line voltage Vdm2 as described with reference to FIGS. 4 and 5.

 According to an exemplary embodiment, the zero dummy word line voltage Vdm0 may be the same voltage as those appearing in the source select line SSL and the drain select line DSL by floating.

It will be appreciated that the same effects as the embodiments described with reference to FIGS. 4 and 5 can also be achieved by the present embodiment.

7 is a flowchart illustrating an erase method of the semiconductor memory device 100 of FIG. 1.

1, 2 and 7, in step S110, an erase operation is performed. The peripheral circuit 120 may perform an erase operation by biasing the row lines RL of the selected memory block as described with reference to FIGS. 4 through 6.

In step S120, an erase verify operation is performed. The peripheral circuit 120 reads the threshold voltages of the memory cells of the selected memory block and determines whether the memory cells have reached the desired threshold voltages.

More specifically, first, the bit lines BL1 to BLn are precharged. Thereafter, a predetermined verify voltage is applied to the word lines WL1 to WLn while the source select transistor SST, the drain select transistor DST, and the dummy memory cells SDL1 to SDL3 and DDL1 to DDL3 are turned on. Will be. At this time, the voltages of the bit lines BL1 to BLn may change according to whether the memory cells M1 to Mn are turned on. For example, when any one of the memory cells M1 to Mn is turned off, the voltages of the bit lines BL1 to BLn will not be changed. The voltages of the bit lines BL1 to BLn are sensed to determine whether the memory cells of the selected memory block reach desired threshold voltages.

In step S130, the step S110 is performed again according to whether the memory cells of the selected memory block have reached the desired threshold voltages (passes) or have not reached the desired threshold voltages (fails).

8 is a table illustrating voltages applied to row lines RL during an erase verify operation.

2 and 8, a power supply voltage Vcc is applied to a source select line SSL and a drain select line DSL. The source select transistor SST and the drain select transistor DST will be turned on. The word line verification voltage Vwvfy, for example, 0V to 2V is applied to the word lines WL1 to WLn.

First to third dummy verification voltages Vdvfy1 to Vdvfy3 are applied to the first to third source side dummy word lines SDL1 to SDL3, respectively. The first dummy verify voltage Vdvfy1 is higher than the second dummy verify voltage Vdvfy2. The second dummy verify voltage Vdvfy2 is higher than the third dummy verify voltage Vdvfy3. The third dummy verify voltage Vdvfy3 has the same level as the word line verify voltage Vwvfy, for example.

 Similarly, the first to third dummy verification voltages Vdvfy1 to Vdvfy3 are applied to the first to third drain side dummy word lines DDL1 to DDL3, respectively.

According to an exemplary embodiment of the present invention, in the erase verify operation after the erase operation described with reference to FIGS. 4 to 6, each of the dummy memory cells SM1 to SM3 or DM1 to DM3 is adjacent to the selection transistor SST or DST. The higher the dummy verify voltage is applied. Therefore, the dummy memory cells SM1 to SM3 or DM1 to DM3 may be turned on normally. This is explained in more detail with reference to FIG. 9.

 9 is a diagram illustrating a threshold voltage distribution of memory cells and dummy memory cells after erase is performed.

Referring first to FIGS. 2 and 9, the memory cells have a first threshold voltage distribution 210. Assume that the second dummy word line voltage Vdm2 applied to the third dummy word lines SDL3 and DDL3 has the same level as the voltage Vwl applied to the word lines WL1 to WLn during the erase operation. In other words, the dummy memory cells connected to the third dummy word lines SDL3 and DDL3 may also have a first threshold voltage distribution 210.

In the erase operation, the first dummy word line voltage Vdm1 higher than the second dummy word line voltage Vdm2 is applied to the second dummy word lines SDL2 and DDL2. The dummy memory cells connected to the second dummy word lines SDL2 and DDL2 have a second threshold voltage distribution 220 corresponding to a voltage distribution higher than the first threshold voltage distribution 210.

In the erase operation, the first dummy word lines SDL1 and DDL1 are floated. Alternatively, a zero dummy word line voltage Vdm0 higher than the first dummy word line voltage Vdm1 may be applied to the first dummy word lines SDL1 and DDL1. Therefore, the dummy memory cells connected to the first dummy word lines SDL1 and DDL1 have a third threshold voltage distribution 230 corresponding to a voltage distribution higher than the second threshold voltage distribution 220.

It is assumed that the same dummy verify voltage, for example, the third dummy verify voltage Vdvfy3, is applied to all dummy word lines SDL1 to SDL3 and DDL1 to DDL3. The dummy memory cells connected to the third dummy word lines SDL3 and DDL3 have threshold voltages lower than the third dummy verify voltage Vdvfy3. Dummy memory cells connected to the third dummy word lines SDL3 and DDL3 may be turned on normally.

On the other hand, some of the dummy memory cells connected to the second dummy word lines SDL2 and DDL2 have a threshold voltage higher than that of the third dummy verify voltage Vdvfy3, and thus will not be turned on. Since the dummy memory cells connected to the first dummy word lines SDL1 and DDL1 have a threshold voltage higher than the third dummy verify voltage Vdvfy3, they may not be turned on.

According to an embodiment of the present disclosure, a third dummy verification voltage Vdvfy3 higher than the first threshold voltage distribution 210 is applied to the third dummy word lines SDL3 and DDL3, and the second dummy word lines SDL2 are applied. , The second dummy verification voltage Vdvfy2 higher than the second threshold voltage distribution 220 is applied to the DDL2, and the first dummy word lines SDL1 and DDL1 are higher than the third threshold voltage distribution 230. The dummy verify voltage Vdvfy1 is applied. That is, since the dummy memory cells of different dummy word lines have different threshold voltage distributions, each of the dummy memory cells SM1 to SM3 or DM1 to DM3 has a select transistor SST or DST. The closer it is, the higher the dummy verify voltage is applied. Therefore, dummy memory cells connected to the first dummy word lines SDL1 and DDL1, dummy memory cells connected to the second dummy word lines SDL2 and DDL2, and third dummy word lines SDL3 and DDL3. The memory cells will turn on normally.

According to an exemplary embodiment of the present invention, each of the dummy memory cells is provided with a higher voltage as it is closer to the selection transistor during the erase operation. Thus, deterioration of the insulating film between the selection transistor and the dummy memory cells is prevented.

According to an embodiment of the present invention, during the erase verify operation, a higher dummy verify voltage is applied to each of the dummy memory cells as it is closer to the selection transistor. Therefore, the dummy memory cells may be turned on normally in the erase verify operation.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

110: memory cell array
120: peripheral circuit
SDL1, DDL1: first dummy word lines
SDL2, DDL2: second dummy word lines
SDL3, DDL3: third dummy word lines
SM1, DM1: first dummy memory cells
SM2, DM2: second dummy memory cells
SM3, DM3: third dummy memory cells

Claims (15)

  1. Select transistors;
    A plurality of memory cells connected in series; And
    A plurality of dummy memory cells disposed between the selection transistor and the plurality of memory cells,
    In an erase operation, each of the plurality of dummy memory cells is provided with a higher voltage nearer to the selection transistor.
  2. The method of claim 1,
    And a voltage provided to a dummy memory cell adjacent to the select transistor is controlled to be equal to a voltage of a select line connected to the select transistor.
  3. The method of claim 1,
    And a select line connected to the select transistor and a dummy word line connected to a dummy memory cell adjacent to the select transistor.
  4. The method of claim 1,
    And a voltage equal to or higher than a voltage applied to the plurality of memory cells is applied to the dummy memory cells adjacent to the plurality of memory cells.
  5. The method of claim 1,
    In the erase verify operation after the erase operation, a higher dummy verify voltage is applied to each of the plurality of dummy memory cells closer to the selection transistor.
  6. The method of claim 5, wherein
    And a dummy verify voltage equal to or higher than a verify voltage applied to the plurality of memory cells is applied to the dummy memory cell adjacent to the plurality of memory cells during the erase verify operation.
  7. The method of claim 1,
    And the select transistor is a drain select transistor disposed between a bit line and the plurality of dummy memory cells.
  8. The method of claim 1,
    And the select transistor is a source select transistor disposed between a source line and the plurality of dummy memory cells.
  9. A memory cell array including a selection transistor, a plurality of memory cells connected in series, and a plurality of dummy memory cells disposed between the selection transistor and the plurality of memory cells; And
    And a peripheral circuit configured to provide a higher voltage as each of the plurality of dummy memory cells is adjacent to the selection transistor during an erase operation.
  10. The method of claim 9,
    And the peripheral circuitry is configured to float a select line coupled to the select transistor and a dummy word line coupled to a dummy memory cell adjacent to the select transistor.
  11. The method of claim 9,
    And the peripheral circuit is configured to apply a higher dummy verify voltage to each of the plurality of dummy memory cells in the erase verify operation after the erase operation.
  12. A method of operating a semiconductor memory device comprising:
    During an erase operation, floating a select line coupled to the select transistor;
    And when the select line is floated, providing each of the plurality of dummy memory cells disposed between the select transistor and the memory cells as a voltage is closer to the select transistor.
  13. 13. The method of claim 12,
    And the voltage provided to the dummy memory cell adjacent to the selection transistor is controlled to the same voltage as the voltage of the selection line.
  14. 13. The method of claim 12,
    And a dummy word line connected to a dummy memory cell adjacent to the selection transistor is floated.
  15. 13. The method of claim 12,
    And applying a higher dummy word line voltage to each of the plurality of dummy memory cells in the erase verify operation after the erase operation.
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Publication number Priority date Publication date Assignee Title
KR20140133268A (en) * 2013-05-10 2014-11-19 삼성전자주식회사 3d flash memory device having dummy wordlines and data storage device including the same
KR20160039960A (en) * 2014-10-02 2016-04-12 에스케이하이닉스 주식회사 Semiconductor memory device including dummy memory cell and program method thereof
KR20160062498A (en) * 2014-11-25 2016-06-02 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
CN106971760A (en) * 2017-04-01 2017-07-21 北京兆易创新科技股份有限公司 Threshold voltage method of calibration, device and NAND memory device based on nand flash memory

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4398750B2 (en) * 2004-02-17 2010-01-13 株式会社東芝 NAND flash memory
KR100691384B1 (en) * 2006-03-27 2007-02-28 삼성전자주식회사 Nonvolatile semiconductor memory device having cell string with the structure for preventing the degration of dielectric
KR101297283B1 (en) * 2006-07-10 2013-08-19 삼성전자주식회사 Non-volatile memory device with nand cell strings
JP2008084471A (en) * 2006-09-28 2008-04-10 Toshiba Corp Semiconductor memory device
JP2008135100A (en) * 2006-11-28 2008-06-12 Toshiba Corp Semiconductor memory device and its data erasing method
JP2008146771A (en) * 2006-12-12 2008-06-26 Toshiba Corp Semiconductor memory
KR101392431B1 (en) * 2007-08-14 2014-05-08 삼성전자주식회사 Flash memory device having a dummy cell and erase method thereof
KR101462488B1 (en) * 2008-03-31 2014-11-18 삼성전자주식회사 Flash memory device using dummy cell and driving method thereof
KR101360136B1 (en) * 2008-04-18 2014-02-10 삼성전자주식회사 Flash memory device and operating method thereof, and memory system including the same
JP2009301599A (en) * 2008-06-10 2009-12-24 Toshiba Corp Non-volatile semiconductor memory device
KR101478149B1 (en) * 2008-10-20 2015-01-05 삼성전자주식회사 Flash memory device having dummy transistor
US8199579B2 (en) * 2009-09-16 2012-06-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JP5259667B2 (en) * 2010-09-22 2013-08-07 株式会社東芝 Nonvolatile semiconductor memory device
JP2012069187A (en) * 2010-09-22 2012-04-05 Toshiba Corp Nonvolatile semiconductor memory
KR20120129606A (en) * 2011-05-20 2012-11-28 에스케이하이닉스 주식회사 Operating method of nonvolatile memory device

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