TWI559272B - Gate pulse modulation circuit and angle modulation method thereof - Google Patents

Description

Gate pulse modulation circuit and its chamfer modulation method

The invention relates to a gate pulse modulation circuit and a chamfer modulation method thereof.

A thin film transistor liquid crystal display (TFT-LCD) is driven by a gate pulse signal to drive each pixel transistor to control the on and off states of each pixel; when a gate pulse signal is input to make a pixel transistor When it is turned on, the data signal to be displayed is transmitted to the pixel through the pixel transistor. If the pixel transistor is turned off, the data signal to be displayed is not transmitted to the pixel through the pixel transistor. .

In the pixel array of the display panel, each pixel is composed of an equivalent resistance and an equivalent capacitance. In this case, each gate pulse signal scan causes the input waveform of the front end of the scan line to be different from the waveform of the back end. , the so-called delayed waveform. Therefore, it is necessary to chamfer the gate pulse signal so that the front end input waveform of the scan line is close to the back end waveform, thereby reducing flicker phenomenon caused by different feedthrough voltages of the front and rear ends. .

In view of the above, it is necessary to provide a gate pulse modulation circuit and a chamfer modulation method which can eliminate picture flicker.

A gate pulse modulation circuit is used for outputting a gate pulse modulation signal to a pixel array, including: The logic control gate comprises a gate power supply voltage input terminal for receiving the gate power supply voltage, a discharge output terminal connected to the low voltage level via the discharge resistor, a control signal input end and a power signal output end; The switch is connected to the logic control gate; the lower bridge switch is coupled between the upper bridge switch and the low voltage level, and the node between the upper bridge switch and the lower bridge switch is connected to the gate pulse modulation signal output terminal to output the gate a pulse modulation signal; the upper bridge switch and the lower bridge switch are alternately turned on; when the upper bridge switch is turned on and the lower bridge switch is turned off, the logic selects the gate to perform a logic operation on the control signal, and when the logic operation result is the first value The logic control gate outputs a gate power supply voltage according to the control signal, and the node outputs a gate pulse modulation signal to the pixel array; when the logic operation result is the second value, the logic control gate is controlled according to the control signal The discharge output terminal is gated, and the pixel array is discharged through the upper bridge switch and the discharge resistor to lower the gate pulse modulation signal to form a chamfer signal.

A chamfer modulation method is applied to a gate pulse modulation circuit for outputting a gate pulse modulation signal to a pixel array, the gate pulse modulation circuit comprising: a logic control gate, including a gate power supply voltage input terminal Receiving a gate power supply voltage, the discharge output terminal is connected to a low voltage level via a discharge resistor, and the control signal input terminal is connected; an upper bridge switch is connected to the logic control gate; the lower bridge switch is coupled to the upper bridge switch and the ground terminal Between the upper bridge switch and the lower bridge switch, the node outputs a gate pulse modulation signal to the pixel array; the chamfer modulation method includes: a first time period, controlling the upper bridge switch to be turned on, the lower bridge switch Shutdown, the logic selection The gate device performs a logic operation on the control signal. When the logic operation result is the first value, the logic control gate device electrically connects the gate power input end and the power signal output terminal, and selectively turns off Disconnecting the electrical connection between the gate power input end and the discharge output end, the gate signal output end outputs a gate pulse modulation signal to the pixel array; and in the second time period, controlling the upper bridge switch to be turned on, the lower bridge The switch is turned off, and the logic selects the gate device to perform a logic operation on the control signal. When the logic operation result is the second value, the logic control gate device turns off the gate power input end and electrically connects to the power signal output end. And electrically connecting the gate power input end and the discharge output end, the pixel array is discharged through the upper bridge switch and the discharge resistor to lower the gate pulse modulation signal to form a chamfer signal; and During the three time period, the upper bridge switch is controlled to be turned off, the lower bridge switch is turned off, and the pixel array is completely discharged by the lower bridge switch.

Compared with the prior art, the gate pulse modulation circuit and the chamfer modulation method of the present invention use the pixel array to form a chamfering voltage of the gate voltage by discharging the discharge resistor, thereby reducing the phenomenon of flickering of the picture, and the shaving of the case The angular modulation is formed by the discharge of the pixel array through the discharge resistor to reduce the unevenness of the light transmission caused by the voltage instability.

10‧‧‧ gate pulse modulation circuit

20‧‧‧ pixel array

110‧‧‧Logical Control Gates

120‧‧‧Upper bridge switch

130‧‧‧Bridge switch

140‧‧‧ reverser

150‧‧‧discharge resistor

LX‧‧‧ node

VGH‧‧‧ gate power supply voltage

L‧‧‧ gate power input

H‧‧‧Discharge output

IN1‧‧‧first control signal input

IN2‧‧‧second control signal input

Vo‧‧‧ power signal output

VGL‧‧‧ low voltage level

CLK‧‧‧clock signal

OE‧‧‧Enable signal

CT‧‧‧ conduction control signal

Gout‧‧‧ gate pulse modulation signal

1 is a schematic view showing the circuit structure of an embodiment of a gate pulse modulation circuit of the present invention.

FIG. 2 is a timing diagram of signals when the gate pulse modulation circuit of FIG. 1 operates.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the circuit structure of an embodiment of a gate pulse modulation circuit 10 of the present invention. The gate pulse modulation circuit 10 is configured to output a gate voltage to a pixel matrix Column 20. The gate pulse modulation circuit 10 includes a logic control gate 110, an upper bridge switch 120, a lower bridge switch 130, an inverter 140, and a discharge resistor 150. The logic control gate 110, the upper bridge switch 120 and the lower bridge switch 130 are sequentially connected in series between the gate power supply voltage VGH and the low voltage level VGL. The inverter 140 is configured to receive the conduction control signal CT to control the on and off of the upper and lower bridge switches 120, 130. The node LX outputs a gate pulse modulation signal to the pixel array 20 between the upper bridge switch 120 and the lower bridge switch 130.

The logic control gate 110 includes a gate power input terminal L, a discharge output terminal H, a first control signal input terminal IN1, a second control signal input terminal IN2, and a power signal output terminal Vo. The gate power supply input terminal L is connected to a gate power supply voltage VGH. The discharge output terminal H is connected to the low voltage level VGL via a discharge resistor 150. The first control signal input terminal IN1 is configured to receive a clock signal CLK. The control signal input terminal IN2 is used for receiving the enable signal OE, and the power signal output terminal Vo is used for outputting the gate voltage.

In the present embodiment, the upper bridge switch 120 is a PMOS (P-Metal Oxide Semiconductor) transistor, and the lower bridge switch 130 is an NMOS (N-Metal Oxide Semiconductor) transistor. The source of the upper bridge switch 120 is connected to the power signal output terminal Vo. The drain of the upper bridge switch 120 is electrically connected to the drain of the lower bridge switch 130. The source and the low voltage level of the lower bridge switch 130 are connected. The VGL is electrically connected, and the gates of the upper bridge switch 120 and the lower bridge switch 130 are electrically connected to the inverter 140. The node LX is located between the drain of the upper bridge switch 120 and the drain of the lower bridge switch 130.

Please refer to FIG. 2 together. FIG. 2 is a timing diagram of the signal when the gate pulse modulation circuit 10 shown in FIG. 1 is in operation. In the first time period T1, the inverter 140 receives the conduction control signal CT to control the upper bridge switch 120 to be turned on, and the lower bridge switch 130 to be turned off. In this embodiment, the conduction control signal CT is a high level signal. After the reverser 140 is reversed, The conduction control signal CT controls the upper bridge switch 120 to be turned on and the lower bridge switch 130 to be turned off. At the same time, the logic control strobe 110 performs a logic operation on the clock signal CLK and the enable signal OE. In the embodiment, the clock signal CLK is a high level signal during the first time period, and the enable signal is OE is a low level signal. The logic control gate 110 performs a NOR operation on the clock signal CLK and the enable signal OE. When the operation result is the first value, in the embodiment, when the first value is a logic value “1”, the The logic control gate 110 electrically connects the gate power input terminal L and the power signal output terminal Vo, and selectively turns off the gate power input terminal L and the discharge output terminal H. Electrical connection between. At this time, the gate power supply voltage VGH outputs the gate pulse modulation signal Gout to the pixel array 20 via the power signal output terminal Vo, the upper bridge switch 120, and the node LX.

In the second time period T2, the inverter 140 receives the conduction control signal CT to control the upper bridge switch to be turned on, and the lower bridge switch 130 to be turned off. At the same time, the logic control gate 110 performs a NAND operation on the clock signal CLK and the enable signal. When the operation result is the second value, in the embodiment, when the second value is a logic value “0”, The logic control gate 110 turns off the electrical connection between the gate power input terminal L and the power signal output terminal Vo, and simultaneously enables electrical conduction between the gate power input terminal L and the discharge output terminal H. . In the second embodiment, the clock signal CLK is a low level signal, and the enable signal OE is a low level signal. At this time, the pixel array 20 is discharged through the upper bridge switch 120, the discharge output terminal H, and the discharge resistor 150 to lower the gate pulse modulation signal Gout to form a chamfer of the gate pulse modulation signal Gout.

In the third time period T3, the conduction control signal CT is a low level signal, and the inverter receives the conduction control signal CT to control the upper bridge switch to be turned off, and the lower bridge switch 130 The pixel array 20 is completely discharged through the lower bridge switch 130.

The foregoing gate pulse modulation circuit 10 and its chamfer modulation method use a pixel array to form a chamfering voltage of a gate voltage through resistance discharge, thereby reducing flickering of the picture, and the chamfering modulation of the present case is by drawing The element array is formed by resistance discharge to reduce unevenness of light transmission caused by voltage instability.

While the invention has been described above in terms of a preferred embodiment thereof, it is not intended to limit the invention, and various modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Changes are intended to be included within the scope of the claimed invention.

10‧‧‧ gate pulse modulation circuit

20‧‧‧ pixel array

110‧‧‧Logical Control Gates

120‧‧‧Upper bridge switch

130‧‧‧Bridge switch

140‧‧‧ reverser

150‧‧‧discharge resistor

LX‧‧‧ node

VGH‧‧‧ gate power supply voltage

L‧‧‧ gate power input

H‧‧‧Discharge output

IN1‧‧‧first control signal input

IN2‧‧‧second control signal input

Vo‧‧‧ power signal output

VGL‧‧‧ low voltage level

Claims (15)

A gate pulse modulation circuit for outputting a gate pulse modulation signal to a pixel array, comprising: a logic control gate, comprising a gate power supply voltage input terminal for receiving a gate power supply voltage, and a discharge resistor Connecting a low voltage level discharge output terminal, a control signal input end and a power signal output end; an upper bridge switch is connected to the logic control gate; the lower bridge switch is coupled between the upper bridge switch and the low voltage level, The upper bridge switch and the lower bridge switch are connected to the gate pulse modulation signal output end to output the gate pulse modulation signal; the upper bridge switch and the lower bridge switch are alternately turned on; the upper bridge switch is turned on, and the lower bridge switch is turned off. The logic selection gate performs a logic operation on the control signal. When the logic operation result is the first value, the logic control gate outputs a gate power supply voltage according to the control signal, and the node outputs a gate pulse modulation signal. To the pixel array; when the logic operation result is the second value, the logic control gate strobes the discharge output according to the control signal, and the pixel array is opened by the upper bridge , Resistance for discharge down to the gate signal pulse modulation signal forming chamfered. The gate pulse modulation circuit of claim 1, wherein the gate pulse modulation circuit further comprises an inverter receiving the conduction control signal to control the on and off of the upper and lower bridge switches. The gate pulse modulation circuit of claim 1, wherein the control signal input terminal comprises a first control signal input terminal for receiving a clock signal and a second control signal input terminal for receiving an enable signal, the logic The control gater performs a logic operation on the clock signal and the enable signal. The gate pulse modulation circuit of claim 2, wherein when the inverter receives the conduction control signal to control the upper bridge switch to be turned on and the lower bridge switch to be turned off, the logic control gate is to the clock The signal and the enable signal are ORed. When the operation result is the first value, the logic control gate enables the gate power input terminal to electrically conduct with the power signal output terminal, and selectively turns off the An electrical connection between the gate power input end and the discharge output terminal, wherein the gate power supply voltage is modulated by the power signal output end, the upper bridge switch, and the node output gate pulse. The gate pulse modulation circuit of claim 4, wherein the first value is a logic value "1". The gate pulse modulation circuit of claim 4, wherein when the operation result is the second value, the logic control gate turns off the gate power input terminal and the power signal output end, and simultaneously The electrical connection between the gate power input end and the discharge output end is performed, and the pixel array is discharged through the upper bridge switch, the discharge output end, and the resistor to form a chamfer of the gate pulse modulation signal. The gate pulse modulation circuit of claim 6, wherein the second value is a logic value of "0". The gate pulse modulation circuit of claim 6, wherein the inverter receives the conduction control signal to control the upper bridge switch to be turned off, and the lower bridge switch is turned on, and the pixel array is completely discharged through the lower bridge switch. . A chamfer modulation method is applied to a gate pulse modulation circuit for outputting a gate pulse modulation signal to a pixel array, the gate pulse modulation circuit comprising: a logic control gate, including a gate power voltage input The terminal receives a gate power supply voltage, the discharge output terminal is connected to a low voltage level via a discharge resistor, and the control signal input terminal; and an upper bridge switch is connected to the logic control gate; the lower bridge switch is coupled to the upper bridge switch and low Between the voltage levels, the node between the upper bridge switch and the lower bridge switch outputs a gate pulse modulation signal to the pixel array; the chamfer modulation method includes: a first time period, controlling the upper bridge switch to be turned on, The lower bridge switch is turned off, and the logic selects the gate to perform a logic operation on the control signal. When the logic operation result is the first value, the logic control The gate device electrically connects the gate power input end and the power signal output end, and selectively turns off the electrical connection between the gate power input end and the discharge output end, the gate signal output end Outputting a gate pulse modulation signal to a pixel array; in a second time period, controlling the upper bridge switch to be turned on, the lower bridge switch is turned off, and the logic selecting a gater performs a logic operation on the control signal, the logic operation result is In the case of two values, the logic control gate turns off the gate power input terminal and the power signal output terminal, and simultaneously makes an electrical connection between the gate power input terminal and the discharge output terminal, the pixel The array is discharged by the upper bridge switch and the discharge resistor to lower the gate pulse modulation signal to form a chamfer signal; and the third period of time, the upper bridge switch is controlled to be turned off, and the lower bridge switch is turned off, and the pixel array is turned off. The lower bridge switch is fully discharged. The method of claim 29, wherein the control signal input terminal comprises a first control signal input terminal for receiving a clock signal and a second control signal input terminal for receiving an enable signal, the logic control selection The device performs a logic operation on the clock signal and the enable signal. The chamfering method according to claim 10, wherein, in the first period of time, the logic control gate performs a NAND operation on the clock signal and the enable signal, and when the operation result is the first value, The logic control gate strobes the gate power input end, the power signal output end, and turns off the discharge output end, and the gate power supply voltage is output through the power signal output end, the upper bridge switch, and the gate pulse modulation signal The terminal outputs a gate pulse modulation signal. The chamfer modulation method of claim 11, wherein the first value is a logical value "1". The chamfer modulation method according to claim 11, wherein, in the second period, when the operation result is the second value, the logic control gate strobes the gate power input end and the power signal output end And the discharge output end, the pixel array is discharged through the upper bridge switch, the discharge output end, and the resistor to form a chamfer of the gate pulse modulation signal. The chamfer modulation method of claim 13, wherein the second value is a logical value of "0". The chamfer modulation method according to claim 13, wherein in the third period, the gate pulse is modulated The variable circuit receives the conduction control signal to control the upper bridge switch to be turned off, and the lower bridge switch to be turned on, and the pixel array is completely discharged through the lower bridge switch.