TWI556396B - Semiconductor chip, semiconductor structure using the same and manufacturing method thereof - Google Patents

Description

Semiconductor wafer, semiconductor structure using same and manufacturing method thereof

The present invention relates to a semiconductor wafer, a semiconductor structure using the same, and a method of fabricating the same, and more particularly to a semiconductor wafer having a stepped conductive pillar, a semiconductor structure using the same, and a method of fabricating the same.

A semiconductor wafer typically includes a direct conductive pillar, and the semiconductor wafer is disposed on the substrate as a straight conductive pillar.

However, in the process of placing the semiconductor wafer on the substrate, the stress on the straight conductive column is large, which often leads to the destruction of the straight conductive column. Even if the straight conductive column is not obviously damaged during the setting process, the stress it receives may cause The decline in durability.

The present invention relates to a semiconductor wafer, a semiconductor structure using the same, and a method of fabricating the same, wherein the stepped conductive pillar has a low stress.

In accordance with an embodiment of the present invention, a semiconductor wafer is presented. The semiconductor wafer includes a semiconductor substrate and a stepped conductive pillar. The stepped conductive pillar is formed on the semiconductor substrate and includes a first conductive pillar and a second conductive pillar. The second conductive pillar is formed on the first conductive pillar, and a cross-sectional area of the second conductive pillar is smaller than a sectional area of the first conductive pillar. At least one of the first conductive pillar and the second conductive pillar includes a first portion and a second portion, and the second portion is coupled to the first portion and forms a recess with the first portion.

According to another embodiment of the invention, a semiconductor structure is presented. The semiconductor structure includes a substrate, a semiconductor wafer, and a primer. The semiconductor wafer includes a semiconductor substrate and a stepped conductive pillar. The stepped conductive pillar is formed on the semiconductor substrate and includes a first conductive pillar and a second conductive pillar. The second conductive pillar is formed on the first conductive pillar, and a cross-sectional area of the second conductive pillar is smaller than a sectional area of the first conductive pillar. At least one of the first conductive pillar and the second conductive pillar includes a first portion and a second portion, and the second portion is coupled to the first portion and forms a recess with the first portion. A primer is formed between the substrate and the semiconductor wafer.

According to another embodiment of the present invention, a method of fabricating a semiconductor wafer is presented. The manufacturing method includes the following steps. Providing a semiconductor substrate; and forming a stepped conductive pillar on the semiconductor substrate, wherein the stepped conductive pillar comprises a first conductive pillar and a second conductive pillar, and the second conductive pillar is formed on the first conductive pillar, The cross-sectional area of the second conductive pillar is smaller than the cross-sectional area of the first conductive pillar, and at least one of the first conductive pillar and the second conductive pillar includes a first portion and a second portion, and the second portion is connected to the first portion and A recess is formed between a portion.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Referring to FIG. 1A, a cross-sectional view of a semiconductor structure in accordance with an embodiment of the present invention is shown. The semiconductor structure 10 includes a substrate 12, a semiconductor wafer 100, and an underfill 14, wherein a primer 14 is formed between the substrate 12 and the semiconductor wafer 100.

The semiconductor wafer 100 includes a semiconductor substrate 110 and at least one stepped conductive pillar 120, wherein the stepped conductive pillars 120 are formed on the semiconductor substrate 110. In this embodiment, the pitch W of the adjacent two stepped conductive pillars 120 is less than 100 micrometers, so that the semiconductor wafer 100 belongs to the field of fine pitch semiconductor wafers. In the present embodiment, the semiconductor substrate 110 is, for example, a germanium wafer, but the embodiment is not limited thereto.

The stepped conductive pillars 120 are formed on the semiconductor substrate 110 and include a first conductive pillar 121 and a second conductive pillar 122. The second conductive pillar 122 is formed on the first conductive pillar 121, and the cross-sectional area (such as the cross-sectional area) of the second conductive pillar 122 is smaller than the sectional area of the first conductive pillar 121, so that the stepped conductive pillar 120 provides a larger surface area. The cross-sectional area of the second conductive pillar 122 is equal to the cross-sectional area of the first conductive pillar 121 to be in contact with the primer 14, thereby causing the primer 14 to more closely coat the stepped conductive pillar 120. In this embodiment, the entire second conductive pillars 122 are overlapped with the first conductive pillars 121. However, the second conductive pillars 122 and the first conductive pillars 121 may partially overlap, that is, the second conductive layer. The post 122 is laterally offset from the first conductive post 121 by a distance.

For fine pitch semiconductor wafers, since the spacing between adjacent two conductive pillars is relatively small, the resistance of the primer to flow between the semiconductor substrate and the substrate is increased, which may result in the primer not completely covering the conductive pillar. In this embodiment, since the cross-sectional area of the second conductive pillars 122 is smaller than the cross-sectional area of the first conductive pillars 121, the accommodation space of the primer 14 is increased, so that the primer 14 can be reduced between the semiconductor substrate 110 and the substrate 12. Flow resistance, under this design, even if the stepped conductive pillars 120 are applied to the fine pitch semiconductor wafer, the primer 14 can completely cover the entire stepped conductive pillars 120.

The volume of the first conductive pillar 121 may be less than, equal to, or greater than the volume of the second conductive pillar 122. For example, the volume of the first conductive pillar 121 may be between 0.1 and 5 times the volume of the second conductive pillar 122. The multiples are not intended to limit the embodiments of the invention. In addition, the material of the stepped conductive pillar 120 is, for example, copper, and the material of the stepped conductive pillar 120 is not limited thereto, and may be an alloy or other metal.

As shown in FIG. 1A, the height H1 of the first conductive pillar 121 is between about 2 and 50 micrometers, preferably between about 2 and 20 micrometers, and the height H2 of the second conductive pillar 122 is greater than 15 microns. In one embodiment, the height H2 of the second conductive pillar 122 is between 3 and 6 times the height H1 of the first conductive pillar 121, preferably but not limited to 4 times. Under the above dimensional relationship, the strength of the second conductive pillars 122 can be maintained, and during the process of disposing the semiconductor wafer 100 on the substrate 12, the second conductive pillars 122 are less likely to be cracked or not cracked too seriously. In addition, when the ratio of the height H2 of the second conductive pillar 122 to the height H1 of the first conductive pillar 121 is too high (the slender ratio is too large), the electrical quality of the stepped conductive pillar 120 is likely to be lowered. In this embodiment, Since the height H2 of the second conductive pillar 122 is between 3 and 6 times the height H1 of the first conductive pillar 121, the electrical quality of the stepped conductive pillar 120 can be maintained.

As shown in FIG. 1A, the stepped conductive pillars 120 further include a solder 130 formed on an end surface of the second conductive pillars 122 to help the stepped conductive pillars 120 to be stably formed on the substrate 12. In one embodiment, the outer diameter D1 of the solder 130 is greater than or substantially equal to 10 microns. When the outer diameter D1 of the solder 130 is equal to or smaller than 10 μm, the semiconductor wafer 100 can be made into a fine pitch semiconductor wafer. The position of the stepped conductive pillar 120 corresponds to The pads of the semiconductor wafer 100 can be electrically connected to the pads 13 of the substrate 12 through the stepped conductive pillars 120 on the pads 13 of the substrate 12 .

Referring to Fig. 1B, a cross-sectional view taken along line 1B-1B' in Fig. 1A is shown. In this embodiment, the cross-sectional shape of the first conductive pillar 121 is circular, elliptical or polygonal. In this embodiment, a circular shape is taken as an example, and the cross-sectional shape of the second conductive pillar 122 is a Daisy Chain. In detail, the second conductive pillar 122 includes a first portion 1221, a second portion 1222, and a connecting portion 1223, wherein the cross-sectional shape of the first portion 1221, the second portion 1222, and/or the connecting portion 1223 is circular, elliptical or polygonal. The cross-sectional shapes of the first portion 1221 and the second portion 1222 of the present embodiment are all elliptical, and the cross-sectional shape of the connecting portion 1223 is exemplified by a rectangle.

As shown in FIG. 1B, at least one recess R is formed between the first portion 1221 and the first portion 1212. Due to the formation of the recess R, the second conductive post 122 provides an additional surface area (the sidewall area of the recess R) in contact with the primer 14, thereby allowing the primer 14 to more closely coat the second conductive post 122. The connecting portion 1223 connects the first portion 1221 and the second portion 1222, and the sectional area of the connecting portion 1223 is smaller than the sectional area of the first portion 1221 and the second portion 1222, and more surface area and bottom can be provided (compared to the omitted connecting portion 1223). Glue 14 is in contact.

Referring to FIG. 2, a cross-sectional view of a stepped conductive pillar in accordance with another embodiment of the present invention is shown. In this embodiment, the stepped conductive pillar 220 includes a first conductive pillar 121 and a second conductive pillar 222 , wherein the first conductive pillar 121 is connected to the second conductive pillar 222 . The cross-sectional shape of the first conductive pillar 121 is circular, elliptical or polygonal. The embodiment is illustrated by a circular shape, and the second conductive pillar 222 includes a first portion 1221 and a second portion 1222, wherein The second portion 1222 is directly connected to the first portion 1221, and a recess R is formed between the second portion 1222 and the first portion 1221.

Referring to FIG. 3, a cross-sectional view of a stepped conductive pillar in accordance with another embodiment of the present invention is shown. In this embodiment, the stepped conductive pillar 320 includes a first conductive pillar 321 and a second conductive pillar 122. The first conductive pillar 321 is connected to the second conductive pillar 122. The cross-sectional shape of the first conductive pillar 321 is, for example, a dumbbell shape. It includes a first portion 3211, a second portion 3212, and a connecting portion 3213. The cross-sectional shapes of the first portion 3211, the second portion 3212, and the connecting portion 3213 are similar to those of the first portion 1221, the second portion 1222, and the connecting portion 1223, respectively, and are not described herein.

As shown in FIG. 3, at least one recess R is formed between the first portion 3211 and the second portion 3212. Due to the formation of the recess R, the first conductive pillar 321 provides an additional surface area (the sidewall area of the recess R) in contact with the primer 14 (Fig. 1A), thereby allowing the primer 14 to more closely coat the first conductive pillar 321. The connecting portion 3213 connects the first portion 3211 and the second portion 3212, and the sectional area of the connecting portion 3213 is smaller than the sectional area of the first portion 3211 and the second portion 3212, so that more surface area (compared to the omitted connecting portion 3213) can be provided. The primer 14 is in contact.

In another embodiment, the first conductive pillars 321 of the stepped conductive pillars 320 may be replaced by the first conductive pillars 421 of FIG.

Referring to FIG. 4, a cross-sectional view of a stepped conductive pillar in accordance with another embodiment of the present invention is shown. In this embodiment, the stepped conductive pillar 420 includes a first conductive pillar 421 and a second conductive pillar 422. The first conductive pillar 421 is connected to the second conductive pillar 422, wherein the first conductive pillar 421 includes a first portion 3211 and a second portion. 3212, the first portion 3211 is connected to the second portion 3212, A recess R is formed between the second portion 3212 and the second portion 3212. Due to the formation of the recess R, the first conductive pillar 421 provides an additional surface area (the sidewall area of the recess R) in contact with the primer 14, thereby allowing the primer 14 to more closely coat the second conductive pillar 422. The cross-sectional shape of the second conductive pillar 422 is circular, elliptical or polygonal. This embodiment is described by taking a circular shape as an example.

Referring to FIG. 5, a cross-sectional view of a stepped conductive pillar in accordance with another embodiment of the present invention is shown. In this embodiment, the stepped conductive pillar 520 includes a first conductive pillar 421 and a second conductive pillar 222. The first conductive pillar 421 is connected to the second conductive pillar 222, wherein the first conductive pillar 421 includes a first portion 3211 and a second portion. 3212, the first portion 3211 is coupled to the second portion 3212, and a recess R is formed with the second portion 3212. Due to the formation of the recess R, the first conductive pillar 421 provides an additional surface area (the sidewall area of the recess R) in contact with the primer 14, thereby allowing the primer 14 to more closely coat the second conductive pillar 222.

In summary, the present invention does not limit the geometry of the first conductive pillar and the second conductive pillar. One of the first conductive pillar and the second conductive pillar may be dumbbell-shaped, circular, elliptical, polygonal or other curved shape, and the other of the first conductive pillar and the second conductive pillar may be dumbbell-shaped or circular , oval, polygonal or other curved shape.

Please refer to FIG. 6 , which shows the experimental results of the stress-bearing stress of various stepped conductive columns. The strip A represents the stress of the cylindrical conductive post 620 (non-stepped conductive post). The strips B and C respectively represent the stresses of the stepped conductive pillars 720 and 820, wherein the first conductive pillar 721 and the second conductive pillar 722 of the stepped conductive pillar 720 are all cylindrical, and the stepped conductive pillar 820 is the first. The conductive post 821 and the second conductive post 822 are all cylindrical, in addition, the first The cross-sectional area of the two conductive pillars 722 is larger than the cross-sectional area of the second conductive pillars 822 of the stepped conductive pillars 820. The strip D represents the stress of the stepped conductive post 520 of the above embodiment, and the strip E represents the stress of the stepped conductive post 320 of the above embodiment.

As shown in FIG. 6, the stresses of the stepped conductive pillars 320 and 520 of the present embodiment are relatively small compared to the stresses of the conductive pillars 620, 720, and 820, wherein the stress of the stepped conductive pillar 320 is further increased. The stepped conductive column is smaller than 520. The remaining stepped conductive pillars 120, 220 and 420 have similar effects, and will not be described again. In summary, the stepped conductive pillar of the present embodiment has the characteristic of reducing the stress resistance, and can avoid or improve the damage of the stepped conductive pillar due to excessive stress (in the process of the semiconductor substrate 110 being disposed on the substrate 12), and can be increased. The service life of the stepped conductive column.

The method of manufacturing the semiconductor structure 10 will be described below.

First, a semiconductor substrate 110 (Fig. 1A) is provided.

Then, a stepped conductive pillar 120 (FIG. 1A) may be formed on the semiconductor substrate 110 by, for example, electroplating, wherein the stepped conductive pillar 120 includes a first conductive pillar 121 and a second conductive pillar 122. The second conductive pillar 122 is formed on the first conductive pillar 121 , and the cross-sectional area of the second conductive pillar 122 is smaller than the cross-sectional area of the first conductive pillar 121 , wherein the entire second conductive pillar 122 overlaps with the first conductive pillar 121 . Thus far, the semiconductor wafer 100 as shown in FIG. 1A is formed. The formation method of the other stepped conductive pillars 220, 320, 420 and 520 is similar to the method of forming the stepped conductive pillar 120, and will not be described again.

Then, the semiconductor wafer 100 can be butted to the substrate 12 (FIG. 1A), wherein the position of the stepped conductive pillars 120 of the semiconductor wafer 100 corresponds to the base. The pads 13 of the board 12 electrically connect the semiconductor wafer 100 to the substrate 12 through the stepped conductive pillars 120.

Then, a reflow process is performed to melt the solder 130 to be soldered to the pad 13. After the solder 130 is cured, it is bonded to the pads 13 of the second conductive pillars 122 and the substrate 12.

Then, a primer 14 (FIG. 1A) is formed between the semiconductor wafer 100 and the substrate 12, wherein the primer 14 covers the stepped conductive pillars 120. Thus far, the semiconductor structure 10 as shown in FIG. 1A is formed.

Although the forming of the conductive pillars is exemplified by the first conductive pillars 121 and the second conductive pillars 122, the other first conductive pillars and the second conductive pillars are formed in a similar manner to the first conductive pillars 121 and the second conductive pillars 122, I will not repeat them here.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Semiconductor structure

12‧‧‧Substrate

14‧‧‧Bottom glue

100‧‧‧Semiconductor wafer

13‧‧‧ pads

110‧‧‧Semiconductor substrate

120, 220, 320, 420, 520, 720‧‧‧ stepped conductive columns

121, 321, 421, 721, 821‧‧‧ first conductive column

122, 222, 422, 722, 822‧‧‧ second conductive column

1221, 3211‧‧‧ first part

1222, 3212‧‧‧ Part II

1213, 3213‧‧‧ Connection section

130‧‧‧ solder

620‧‧‧Direct conductive column

D1‧‧‧ OD

H1, H2‧‧‧ height

R‧‧‧ recess

W‧‧‧ spacing

1A is a cross-sectional view of a semiconductor structure in accordance with an embodiment of the present invention.

Fig. 1B is a cross-sectional view taken along line 1B-1B' in Fig. 1A.

2 is a cross-sectional view of a stepped conductive post in accordance with another embodiment of the present invention.

3 is a diagram showing a stepped conductive pillar according to another embodiment of the present invention. Cutaway view.

4 is a cross-sectional view of a stepped conductive post in accordance with another embodiment of the present invention.

Figure 5 is a cross-sectional view showing a stepped conductive post in accordance with another embodiment of the present invention.

Figure 6 is a graph showing experimental results of stress tolerance of various stepped conductive columns.

10‧‧‧Semiconductor structure

12‧‧‧Substrate

13‧‧‧ pads

14‧‧‧Bottom glue

100‧‧‧Semiconductor wafer

110‧‧‧Semiconductor substrate

120‧‧‧stepped conductive column

121‧‧‧First conductive column

122‧‧‧Second conductive column

130‧‧‧ solder

D1‧‧‧ OD

H1, H2‧‧‧ height

W‧‧‧ spacing

Claims (12)

A semiconductor wafer comprising: a semiconductor substrate; and a stepped conductive pillar formed on the semiconductor substrate and comprising: a first conductive pillar; and a second conductive pillar formed on the first conductive pillar The cross-sectional area of the second conductive pillar is smaller than the cross-sectional area of the first conductive pillar; wherein at least one of the first conductive pillar and the second conductive pillar comprises a first portion and a second portion, the second portion A recess is formed between the first portion and the first portion. The semiconductor wafer of claim 1, wherein the first conductive pillar has a volume between 0.1 and 5 times the volume of the second conductive pillar. The semiconductor wafer of claim 1, wherein at least one of the first conductive pillar and the second conductive pillar comprises: a connecting portion connecting the first portion and the second portion, the connecting portion The sectional area is smaller than the sectional area of the first portion and the sectional area of the second portion. The semiconductor wafer of claim 1, wherein the cross-sectional shapes of the first conductive pillar and the second conductive pillar are each circular, elliptical or polygonal. The semiconductor wafer of claim 1, comprising: two adjacent stepped conductive pillars, wherein adjacent ones of the two conductive pillars have a pitch of less than 80 micrometers. The semiconductor wafer of claim 1, wherein the height of the first conductive pillar is between 2 and 50 micrometers, and the height of the second conductive pillar is between the height of the first conductive pillar. Between 6 times. The semiconductor wafer of claim 1, wherein the entire second conductive pillar overlaps the first conductive pillar. The semiconductor wafer of claim 1, wherein the recess is located on a side of the stepped conductive pillar. A semiconductor structure comprising: a substrate; a semiconductor wafer disposed on the substrate and comprising: a semiconductor substrate; and a stepped conductive pillar formed on the semiconductor substrate and comprising: a first conductive pillar; a second conductive pillar is formed on the first conductive pillar, the cross-sectional area of the second conductive pillar is smaller than a cross-sectional area of the first conductive pillar; wherein at least one of the first conductive pillar and the second conductive pillar Each includes a first portion and a second portion, the second portion is coupled to the first portion and defines a recess therebetween; and a primer is formed between the substrate and the semiconductor wafer. A semiconductor wafer manufacturing method comprising: providing a semiconductor substrate; and forming a stepped conductive pillar on the semiconductor substrate, wherein the stepped conductive pillar comprises a first conductive pillar and a second conductive pillar, the first Two conductive pillars are formed on the first conductive pillar, and a cross-sectional area of the second conductive pillar is smaller than the a cross-sectional area of the first conductive pillar, at least one of the first conductive pillar and the second conductive pillar each including a first portion and a second portion, the second portion being connected to the first portion and between the first portion A recess is formed. The manufacturing method of claim 10, wherein at least one of the first conductive pillar and the second conductive pillar comprises: a connecting portion connecting the first portion and the second portion, the connecting portion The sectional area is smaller than the sectional area of the first portion and the sectional area of the second portion. The manufacturing method of claim 10, wherein the recess is formed on a side of the stepped conductive post.