TWI556245B - Resistance random access memory - Google Patents
Resistance random access memory Download PDFInfo
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- TWI556245B TWI556245B TW104105348A TW104105348A TWI556245B TW I556245 B TWI556245 B TW I556245B TW 104105348 A TW104105348 A TW 104105348A TW 104105348 A TW104105348 A TW 104105348A TW I556245 B TWI556245 B TW I556245B
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- 230000004888 barrier function Effects 0.000 claims description 45
- 238000009826 distribution Methods 0.000 claims description 22
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 12
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical group [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 description 19
- 230000015572 biosynthetic process Effects 0.000 description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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Description
本發明係關於一種電阻式記憶體；特別是關於一種含有不同介電係數材質的電阻式記憶體。 The invention relates to a resistive memory; in particular to a resistive memory containing materials of different dielectric constants.
記憶體(Memory)廣泛的使用在各種電子產品上，隨著資料儲存需求與日俱增，對於記憶體容量以及性能的要求也越來越高，在各種記憶體元件中，電阻式記憶體(RRAM)具有極低的操作電壓、極快的讀寫速度以及高度的元件尺寸可微縮性等優點，有機會取代傳統的快閃記憶體(Flash Memory)以及動態隨機存取記憶體(DRAM)，成為下個世代的記憶體元件主流。 Memory is widely used in various electronic products. As data storage requirements increase, the memory capacity and performance requirements are also increasing. Among various memory components, resistive memory (RRAM) has Extremely low operating voltage, extremely fast read/write speed, and high component size and miniaturization, the opportunity to replace the traditional flash memory and dynamic random access memory (DRAM), the next The mainstream of memory components of generations.
請參閱第1圖所示，其係習知電阻式記憶體之結構示意圖，其中，習知電阻式記憶體9具有一下電極91(如：鉑，Pt)、一第一介質體92(如：K值=3.9)、一第二介質層93(如：K值=25)及一上電極94(如：鉑，Pt)，該下電極91設置該第一介質體92，該第一介質體92設有一通孔921，該第二介質層93設於該通孔921內的下電極91及第一介質體92，且該第二介質層93形成一槽部931，該上電極94由該槽部931內延伸至該槽部931外，並形成一溝部941；其中，該第一介質體92的介電係數(K值)通常遠小於該第二介質層93的介電係數，使該第二介質層93可切換為低阻態(LRS)或高阻態(HRS)，其一實施例可參酌「”Characteristics and Mechanisms of Silicon-Oxide-Based Resistance Random Access Memory”IEEE ELECTRON DEVICE LETTERS,VOL.34,NO.3,MARCH 2013」。 Referring to FIG. 1 , it is a schematic structural view of a conventional resistive memory. The conventional resistive memory 9 has a lower electrode 91 (eg, platinum, Pt) and a first dielectric body 92 (eg, K value = 3.9), a second dielectric layer 93 (eg, K value = 25) and an upper electrode 94 (eg, platinum, Pt), the lower electrode 91 is provided with the first dielectric body 92, the first dielectric body The second dielectric layer 93 is disposed on the lower electrode 91 and the first dielectric body 92 in the through hole 921, and the second dielectric layer 93 forms a groove portion 931, and the upper electrode 94 is formed by the through hole 921. The groove portion 931 extends outside the groove portion 931 and forms a groove portion 941. The dielectric constant (K value) of the first dielectric body 92 is generally much smaller than the dielectric constant of the second dielectric layer 93. The second dielectric layer 93 can be switched to a low resistance state (LRS) or a high resistance state (HRS), and an embodiment thereof can be considered as "Characteristics and Mechanisms of Silicon-Oxide-Based Resistance Random Access Memory" IEEE ELECTRON DEVICE LETTERS, VOL .34, NO.3, MARCH 2013".
其中，隨著資料處理裝置的體積日趨縮小，記憶體所佔的體積勢必要隨著微縮(reduction)。惟，在習知電阻式記憶體9微縮的情況下，該通孔921之尺寸(via size)亦將縮小，由於該第一介質體92的介電係數小於該第二介質層93的介電係數，如第2圖所示，若通孔尺寸由4.0縮至0.4微米(μm)，則形成電壓的平均值將由9增至12伏特左右。因此，習知電阻式記憶體9的形成(Forming voltage)電壓將隨著通孔尺寸縮小而不斷上升，導致形成電壓穩定性不佳，如記憶體的形成電壓過大，則會進一步造成記憶體元件在集成電路中操作上的問題，如：耗電量大等。 Among them, as the volume of the data processing device shrinks, the volume occupied by the memory needs to be reduced. However, in the case where the conventional resistive memory 9 is miniaturized, the via size 921 will also be reduced, since the dielectric constant of the first dielectric body 92 is smaller than the dielectric of the second dielectric layer 93. The coefficient, as shown in Fig. 2, if the via size is reduced from 4.0 to 0.4 micrometers (μm), the average value of the formed voltage will increase from 9 to about 12 volts. Therefore, the forming voltage of the conventional resistive memory 9 will increase as the size of the via hole decreases, resulting in poor voltage stability. If the formation voltage of the memory is too large, the memory component is further caused. Problems in operation in integrated circuits, such as: large power consumption.
有鑑於此，上述先前技術在實際使用時確有不便之處，亟需進一步改良，以提升其實用性。 In view of this, the above prior art has inconvenience in actual use, and further improvement is needed to improve its practicability.
本發明係提供一種電阻式記憶體，可提升記憶體的形成電壓穩定性。 The invention provides a resistive memory for improving the formation voltage stability of a memory.
本發明揭示一種電阻式記憶體，包含：一第一電極層，具有一設置面；一阻隔體，具有一第一表面、一第二表面及一通孔，該第一表面設於該第一電極層之設置面，該第二表面與該第一表面相對，該通孔貫穿該第一表面及該第二表面，使該第一電極層之設置面裸露於該通孔中，該阻隔體含有一第一介質；一變阻層，設於該通孔中裸露的設置面、該通孔的內壁面及該阻隔體之該第二表面，該變阻層含有一第二介質，該第二介質的介電常數低於該第一介質的介電常數，或該第二介質的介電常數高於該第一介質的介電常數之值不大於2；及一第二電極層，設於該變阻層表面。 The invention discloses a resistive memory, comprising: a first electrode layer having a setting surface; a blocking body having a first surface, a second surface and a through hole, wherein the first surface is disposed on the first electrode The second surface is opposite to the first surface, the through hole penetrating the first surface and the second surface, so that the setting surface of the first electrode layer is exposed in the through hole, and the barrier body comprises a first medium; a varistor layer disposed on the exposed surface of the through hole, the inner wall surface of the through hole and the second surface of the blocking body, the varistor layer containing a second medium, the second The dielectric constant of the medium is lower than the dielectric constant of the first medium, or the dielectric constant of the second medium is higher than the dielectric constant of the first medium by no more than 2; and a second electrode layer is disposed on The surface of the varistor layer.
所述阻隔體另含有一第三介質，該第三介質的介電常數與該第一介質的介電常數不同，該第一介質分布的區域及該第三介質分布的區域不同，該第一介質分布的區域及該第三介質分布的區域鄰接該變阻層。 The barrier body further includes a third medium having a dielectric constant different from a dielectric constant of the first medium, and the first medium distribution region and the third medium distribution region are different, the first The region in which the medium is distributed and the region in which the third medium is distributed are adjacent to the varistor layer.
所述第一介質分布的區域可鄰近該第一電極層。 The region of the first medium distribution may be adjacent to the first electrode layer.
所述變阻層可形成一槽部，該槽部位於該阻隔體的通孔內。 The varistor layer may form a groove portion located in the through hole of the barrier body.
所述第二電極層可由該槽部內延伸至該槽部外，該第二電極層可形成一溝部，該溝部可位於該變阻層的槽部內。 The second electrode layer may extend from the inside of the groove portion to the outside of the groove portion, and the second electrode layer may form a groove portion, and the groove portion may be located in the groove portion of the varistor layer.
所述第二電極層可充滿該變阻層的槽部，該第二電極層可形成一凸部，該凸部可位於該變阻層的槽部外。 The second electrode layer may fill the groove portion of the varistor layer, and the second electrode layer may form a convex portion, and the convex portion may be located outside the groove portion of the varistor layer.
所述變阻層的第二介質材料可為二氧化鉿與二氧化矽的組成物，該二氧化鉿佔該組成物之莫爾百分比值可為1~10%。 The second dielectric material of the varistor layer may be a composition of cerium oxide and cerium oxide, and the cerium oxide may have a Mohr percentage value of the composition of 1 to 10%.
所述阻隔體的第一介質材料可為二氧化矽。 The first dielectric material of the barrier may be cerium oxide.
上揭電阻式記憶體，藉由該變阻層中第二介質的介電常數低於該阻隔體中第一介質的介電常數，或該第二介質的介電常數高於該第一介質的介電常數之值不大於2，達成「維持形成電壓的穩定性」功效；另，該阻隔體可包含該第一介質及第三介質，達成「易於調整介電常數」功效；又，該第二電極層可向上禿出而形成該凸部，達成「簡化製造過程」及「減少製程成本」等功效。因此，相較習知電阻式記憶體的形成電壓隨通孔尺寸縮小而不斷上升，本發明電阻式記憶體可避免記憶體元件在集成電路中操作上的問題。 The resistive memory is characterized in that the dielectric constant of the second medium in the varistor layer is lower than the dielectric constant of the first medium in the barrier, or the dielectric constant of the second medium is higher than the first medium The value of the dielectric constant is not more than 2, and the effect of "maintaining the stability of the formation voltage" is achieved; in addition, the barrier body may include the first medium and the third medium to achieve the "easy to adjust the dielectric constant" effect; The second electrode layer can be bald up to form the convex portion, thereby achieving the effects of "simplifying the manufacturing process" and "reducing the process cost". Therefore, the resistive memory of the present invention can avoid the problem of the operation of the memory device in the integrated circuit as the forming voltage of the conventional resistive memory increases as the via size decreases.
1‧‧‧第一電極層 1‧‧‧First electrode layer
1a‧‧‧設置面 1a‧‧‧Setting surface
2,2’‧‧‧阻隔體 2,2’‧‧‧Barrier
2a,2a’‧‧‧第一表面 2a, 2a’‧‧‧ first surface
2b,2b’‧‧‧第二表面 2b, 2b’‧‧‧ second surface
21,21’‧‧‧通孔 21,21’‧‧‧through hole
22’‧‧‧第一介質分布的區域 22’‧‧‧The area of the first medium distribution
23’‧‧‧第三介質分布的區域 23’‧‧‧A third medium distribution area
3‧‧‧變阻層 3‧‧‧variable resistance layer
31‧‧‧槽部 31‧‧‧ slot department
4,4’‧‧‧第二電極層 4,4’‧‧‧Second electrode layer
41‧‧‧溝部 41‧‧‧Ditch
4a’‧‧‧凸部 4a’‧‧‧ convex
9‧‧‧習知電阻式記憶體 9‧‧‧Looking Resistive Memory
91‧‧‧下電極 91‧‧‧ lower electrode
92‧‧‧第一介質體 92‧‧‧First medium body
921‧‧‧通孔 921‧‧‧through hole
93‧‧‧第二介質層 93‧‧‧Second dielectric layer
931‧‧‧槽部 931‧‧‧ slot department
94‧‧‧上電極 94‧‧‧Upper electrode
941‧‧‧溝部 941‧‧‧ditch
第1圖：係習知電阻式記憶體之側面剖視圖。 Fig. 1 is a side cross-sectional view showing a conventional resistive memory.
第2圖：係習知電阻式記憶體之形成電壓與通孔尺寸的關係圖。 Fig. 2 is a graph showing the relationship between the formation voltage of a conventional resistive memory and the size of a via.
第3圖：係本發明電阻式記憶體第一實施例之側面剖視圖。 Figure 3 is a side cross-sectional view showing a first embodiment of the resistive memory of the present invention.
第4圖：係本發明電阻式記憶體第一實施例之形成電壓與通孔尺寸的關係圖。 Fig. 4 is a graph showing the relationship between the formation voltage and the via size of the first embodiment of the resistive memory of the present invention.
第5a圖：係習知電阻式記憶體之第二介質的介電係數遠高於第一介 質的介電係數之電場強度的電腦模擬造影影像圖。 Figure 5a: The dielectric constant of the second medium of the conventional resistive memory is much higher than that of the first medium. A computer-simulated image of the electric field strength of the dielectric constant.
第5b圖：係本發明電阻式記憶體第一實施例之第二介質的介電係數高於第一介質的介電係數之值不大於2之電場強度的電腦模擬造影影像圖。 Figure 5b is a computer-simulated image of the second medium of the first embodiment of the resistive memory of the present invention having a dielectric constant higher than a dielectric constant of the first medium of not more than 2.
第5c圖：係本發明電阻式記憶體第一實施例之第二介質的介電係數低於第一介質的介電係數之電場強度的電腦模擬造影影像圖。 Figure 5c is a computer-simulated image of the electric field strength of the second medium of the first embodiment of the resistive memory of the present invention which is lower than the dielectric constant of the dielectric constant of the first medium.
第6圖：係本發明電阻式記憶體第二實施例之側面剖視圖。 Figure 6 is a side cross-sectional view showing a second embodiment of the resistive memory of the present invention.
第7圖：係本發明電阻式記憶體第三實施例之側面剖視圖。 Figure 7 is a side cross-sectional view showing a third embodiment of the resistive memory of the present invention.
第8圖：係本發明電阻式記憶體第四實施例之側面剖視圖。 Figure 8 is a side cross-sectional view showing a fourth embodiment of the resistive memory of the present invention.
為讓本發明之上述及其他目的、特徵及優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下：請參閱第3圖所示，其係本發明之電阻式記憶體第一實施例的側面剖視圖。其中，該電阻式記憶體第一實施例可包含一第一電極層1、一阻隔體2、一變阻層3及一第二電極層4，該阻隔體2設於該第一電極層1，並形成一通孔21用以露出該第一電極層1，該阻隔體2含有一第一介質；該變阻層3由該通孔21內露出的第一電極層1向外延伸至該通孔21外的阻隔體2表面，該變阻層3含有一第二介質，該第二介質的介電常數(K2)低於該第一介質的介電常數(K1)；該第二電極層4設於該變阻層3表面。 The above and other objects, features and advantages of the present invention will become more <RTIgt; It is a side cross-sectional view of a first embodiment of the resistive memory of the present invention. The first embodiment of the resistive memory device includes a first electrode layer 1, a barrier body 2, a varistor layer 3, and a second electrode layer 4. The barrier body 2 is disposed on the first electrode layer 1 And forming a through hole 21 for exposing the first electrode layer 1, the barrier body 2 containing a first medium; the varistor layer 3 extending outward from the first electrode layer 1 exposed in the through hole 21 to the through a surface of the barrier body 2 outside the hole 21, the varistor layer 3 containing a second medium having a dielectric constant (K2) lower than a dielectric constant (K1) of the first medium; the second electrode layer 4 is disposed on the surface of the varistor layer 3.
在此實施例中，該第一電極層1可由導電材料構成，如：氮化鈦(TiN)或鉑(Pt)等，該第一電極層1具有一設置面1a；該阻隔體2可由該第一介質構成，如：二氧化矽(SiO2)，其介電係數為3.9，該阻隔體2另具有一第一表面2a及一第二表面2b，該第一表面2a設於該第一電極層1之設置面1a，該第二表面2b與第一表面2a相對，該通孔21貫穿 該第一表面2a及第二表面2b，使該第一電極層1之設置面1a可裸露於該通孔21中；該變阻層3可由該第二介質構成，如：二氧化鉿(HfO2)與二氧化矽的組成物，二氧化鉿佔該組成物之莫爾百分比值可為1~10%，使該組成物的介電係數可介於3.9至5.9之間，該第二介質的介電常數(K2)與該第一介質的介電常數(K1)之差值介於0至2之間(0<K2-K1≦2)，以利電場集中於該變阻層3，該變阻層3設於該通孔21中裸露的設置面1a、該通孔21的內壁面及該阻隔體2之第二表面2b，該變阻層3可向下凹入而形成一槽部31(如：利用蝕刻技術等)，該槽部31位於該阻隔體2的通孔21內；該第二電極層4可由導電材料構成，如：銦錫氧化物(ITO)或鉑(Pt)等，該第二電極層4可由該變阻層3之槽部31內延伸至該槽部31外，並向下凹入而形成一溝部41，該溝部41位於該變阻層3的槽部3內；又，上述通孔21、槽部31、溝部41的形狀可依實際需求而調整，在此並不設限。 In this embodiment, the first electrode layer 1 may be made of a conductive material, such as titanium nitride (TiN) or platinum (Pt), etc., the first electrode layer 1 has a setting surface 1a; the barrier body 2 may be The first medium is composed of, for example, cerium oxide (SiO 2 ) having a dielectric constant of 3.9. The barrier body 2 further has a first surface 2a and a second surface 2b. The first surface 2a is disposed on the first surface. The first surface 2b of the electrode layer 1 is opposite to the first surface 2a. The through hole 21 extends through the first surface 2a and the second surface 2b, so that the setting surface 1a of the first electrode layer 1 can be exposed. The varistor layer 3 may be composed of the second medium, such as a composition of cerium oxide (HfO 2 ) and cerium oxide, and the cerium oxide may have a Mohr percentage value of the composition of 1 ~10%, the dielectric constant of the composition may be between 3.9 and 5.9, and the difference between the dielectric constant (K2) of the second medium and the dielectric constant (K1) of the first medium is between 0 Between 2 and 2 (0<K2-K1≦2), an electric field is concentrated on the varistor layer 3, and the varistor layer 3 is disposed on the exposed surface 1a of the through hole 21 and the inner wall surface of the through hole 21. And the second table of the barrier 2 2b, the varistor layer 3 may be recessed downward to form a groove portion 31 (eg, by etching technique, etc.), the groove portion 31 is located in the through hole 21 of the barrier body 2; the second electrode layer 4 may be electrically conductive The material composition, such as indium tin oxide (ITO) or platinum (Pt), etc., the second electrode layer 4 may extend from the inside of the groove portion 31 of the varistor layer 3 to the outside of the groove portion 31, and is recessed downward. A groove portion 41 is formed in the groove portion 3 of the varistor layer 3; the shape of the through hole 21, the groove portion 31, and the groove portion 41 can be adjusted according to actual needs, and is not limited herein.
請參閱第4圖所示，其係本發明電阻式記憶體第一實施例之形成電壓與通孔尺寸的關係圖。其中，若通孔尺寸由4.0縮至0.4微米，該電阻式記憶體的形成電壓仍維持一定的數值範圍(平均值約10至11伏特左右)，確實可保持形成電壓的穩定性。以下係以電腦模擬造影影像圖說明本發明電阻式記憶體第一實施例與習知電阻式記憶體相較之電場強度分布情況，其中，電阻式記憶體外加的工作電壓皆為15伏特(V)。 Referring to Fig. 4, it is a graph showing the relationship between the formation voltage and the via size of the first embodiment of the resistive memory of the present invention. Wherein, if the via size is reduced from 4.0 to 0.4 μm, the formation voltage of the resistive memory maintains a certain value range (average value of about 10 to 11 volts), and the stability of the formation voltage can be maintained. The electric field intensity distribution of the first embodiment of the resistive memory of the present invention compared with the conventional resistive memory is illustrated by a computer simulated contrast image. The working voltage of the resistive memory is 15 volts (V). ).
請參閱第5a圖所示，其係習知電阻式記憶體之第二介質的介電係數遠高於第一介質的介電係數之電場強度的電腦模擬造影影像圖。其中，由電場強度(E)的代表色可知，當習知電阻式記憶體之第二介質的介電係數(K2=25)遠高於該第一介質的介電係數(K1=3.9)時，習知電阻式記憶體之電場分散於第一介質體及第二介質層，電場較強的區域(E為5以上的黃紅色部分)未完全集中於介電係數(K2=25)的中間區域， 隨著電阻式記憶體元件的尺寸微縮化，電場強度分布不集中的情況將每況愈下，須外加更大電壓才可使其崩潰而改變電阻值，導致電阻式記憶體之形成電壓穩定性不佳。 Please refer to FIG. 5a, which is a computer-simulated image of the second medium of the conventional resistive memory whose dielectric constant is much higher than the electric field strength of the dielectric constant of the first medium. Wherein, from the representative color of the electric field intensity (E), when the dielectric constant (K2=25) of the second medium of the conventional resistive memory is much higher than the dielectric constant (K1=3.9) of the first medium, The electric field of the conventional resistive memory is dispersed in the first dielectric body and the second dielectric layer, and the region where the electric field is strong (the yellow-red portion where E is 5 or more) is not completely concentrated in the middle of the dielectric constant (K2=25). region, As the size of the resistive memory element is miniaturized, the case where the electric field intensity distribution is not concentrated will be deteriorating, and a larger voltage is required to cause it to collapse and change the resistance value, resulting in poor voltage stability of the resistive memory.
請參閱第5b圖所示，其係本發明電阻式記憶體第一實施例之第二介質的介電係數高於第一介質的介電係數之值不大於2之電場強度的電腦模擬造影影像圖。其中，由電場強度(E)的代表色可知，當該電阻式記憶體第一實施例之第二介質的介電係數(K2=3.9~5.9)高於該第一介質的介電係數(K1=3.9)之值不大於2，該電阻式記憶體第一實施例之電場可集中於介電係數(K2=3.9~5.9)的中間區域，達成提高電阻式記憶體之形成電壓穩定性的效果。 Please refer to FIG. 5b, which is a computer-simulated image of the electric field of the second medium of the first embodiment of the resistive memory of the present invention having a dielectric constant higher than the dielectric constant of the first medium of not more than 2. Figure. It can be seen from the representative color of the electric field intensity (E) that the dielectric constant (K2=3.9~5.9) of the second medium of the first embodiment of the resistive memory is higher than the dielectric constant of the first medium (K1) The value of =3.9) is not more than 2. The electric field of the first embodiment of the resistive memory can be concentrated in the middle region of the dielectric constant (K2=3.9~5.9), thereby achieving the effect of improving the voltage stability of the resistive memory. .
請參閱第5c圖所示，其係本發明電阻式記憶體第一實施例之第二介質的介電係數低於第一介質的介電係數之電場強度的電腦模擬造影影像圖。其中，由電場強度(E)的代表色可知，當該電阻式記憶體第一實施例之第一介質的介電係數(K1=25)遠大於該第二介質的介電係數(K2=3.9~5.9)時，由於該電阻式記憶體第一實施例之電場僅集中分佈於介電係數(K2=3.9~5.9)的中間區域，達成電阻式記憶體之形成電壓穩定性佳的效果。 Please refer to FIG. 5c, which is a computer-simulated image of the electric field strength of the second medium of the first embodiment of the resistive memory of the present invention, which is lower than the dielectric constant of the first medium. Wherein, from the representative color of the electric field intensity (E), the dielectric constant (K1=25) of the first medium of the first embodiment of the resistive memory is much larger than the dielectric constant of the second medium (K2=3.9). In the case of ~5.9), since the electric field of the first embodiment of the resistive memory is concentrated only in the intermediate region of the dielectric constant (K2 = 3.9 to 5.9), the effect of forming voltage stability of the resistive memory is good.
因此，本發明電阻式記憶體第一實施例使用時，可於該第一電極層1及第二電極層4施加一外在電場，以驅動該變阻層3中的氧離子，而主導該變阻層3的電阻值切換成高阻態(HRS)或低阻態(LRS)。值得注意的是，由於該變阻層3中第二介質的介電常數(K2)高於該阻隔體2中第一介質的介電常數(K1)之值不大於2，或該變阻層3中第二介質的介電常數(K2)低於該阻隔體2中第一介質的介電常數(K1)，當該外加電場作用於該變阻層3時，電場將集中於該變阻層3，而不被該阻隔體2分散，因此所需之崩潰電壓並不會改變，可以提高形成電壓的穩定性。 Therefore, when the first embodiment of the resistive memory of the present invention is used, an external electric field can be applied to the first electrode layer 1 and the second electrode layer 4 to drive the oxygen ions in the varistor layer 3, and the dominant The resistance value of the varistor layer 3 is switched to a high resistance state (HRS) or a low resistance state (LRS). It is noted that the dielectric constant (K2) of the second medium in the varistor layer 3 is higher than the dielectric constant (K1) of the first medium in the barrier body 2 by no more than 2, or the varistor layer The dielectric constant (K2) of the second medium in 3 is lower than the dielectric constant (K1) of the first medium in the barrier body 2. When the applied electric field acts on the varistor layer 3, the electric field will concentrate on the varistor The layer 3 is not dispersed by the barrier 2, so the required breakdown voltage does not change, and the stability of the formation voltage can be improved.
且，本發明電阻式記憶體第一實施例的體積縮小時，其形成電壓並不會隨著升高，可以達成「維持形成電壓的穩定性」功效，相較習知電阻式記憶體的形成電壓隨通孔尺寸縮小而不斷上升，本發明電阻式記憶體第一實施例可避免習知記憶體元件在集成電路中操作上的問題。 Further, when the volume of the first embodiment of the resistive memory of the present invention is reduced, the voltage is not increased, and the "stability of maintaining voltage formation" can be achieved, compared with the formation of a conventional resistive memory. The voltage is continuously increased as the size of the via hole is reduced. The first embodiment of the resistive memory of the present invention can avoid the problem of the operation of the conventional memory device in the integrated circuit.
請參閱第6圖所示，其係本發明電阻式記憶體第二實施例之側面剖視圖。其中，該電阻式記憶體第二實施例包含該第一電極層1、阻隔體2、變阻層3及一第二電極層4’，該第二電極層4’與第一實施例的第二電極層4的材質大致相同，第一實施例的第二電極層4與第二實施例的第二電極層4’差異在於，該第二電極層4’充滿該變阻層3的槽部31，該第二電極層4’可向上禿出而形成一凸部4a’，使該凸部41’位於該變阻層3的槽部31外。 Referring to Fig. 6, there is shown a side cross-sectional view of a second embodiment of the resistive memory of the present invention. The second embodiment of the resistive memory includes the first electrode layer 1, the barrier body 2, the varistor layer 3, and a second electrode layer 4'. The second electrode layer 4' is the same as the first embodiment. The material of the second electrode layer 4 is substantially the same, and the second electrode layer 4 of the first embodiment is different from the second electrode layer 4 ′ of the second embodiment in that the second electrode layer 4 ′ fills the groove portion of the varistor layer 3 . 31. The second electrode layer 4' can be baled upward to form a convex portion 4a' such that the convex portion 41' is located outside the groove portion 31 of the varistor layer 3.
如此，本發明電阻式記憶體第二實施例之第二電極層4’無須利用蝕刻製程形成向下凹入的構造，即可提供電性連接外在電場的功能，且該第二電極層4’無須覆蓋該變阻層3的大量表面，可以達成「簡化製造過程」及「減少製程成本」等功效。而且，本發明電阻式記憶體第二實施例的變阻層3中第二介質的介電常數高於該阻隔體2中第一介質的介電常數之值不大於2，或該變阻層3中第二介質的介電常數低於該阻隔體2中第一介質的介電常數，同樣可在體積縮小時，維持形成電壓的穩定性，避免記憶體元件在集成電路中操作上的問題，其理由已說明如前，在此容不贅述。 As such, the second electrode layer 4' of the second embodiment of the resistive memory of the present invention can provide a function of electrically connecting an external electric field without using an etching process to form a downwardly concave structure, and the second electrode layer 4 'The need to cover a large number of surfaces of the varistor layer 3 can achieve the functions of "simplifying the manufacturing process" and "reducing the process cost". Moreover, the dielectric constant of the second medium in the varistor layer 3 of the second embodiment of the resistive memory of the present invention is higher than the dielectric constant of the first medium in the barrier body 2 by no more than 2, or the varistor layer The dielectric constant of the second medium in 3 is lower than the dielectric constant of the first medium in the barrier body 2, and the stability of the formation voltage can be maintained when the volume is reduced, thereby avoiding the problem of the operation of the memory element in the integrated circuit. The reasons have been explained as before, and I will not repeat them here.
請參閱第7圖所示，其係本發明電阻式記憶體第三實施例之側面剖視圖。其中，該電阻式記憶體第三實施例包含該第一電極層1、一阻隔體2’、該變阻層3及第二電極層4，該阻隔體2’可形成一通孔21’用以露出該第一電極層1，該阻隔體2’另具有一第一表面2a’及一第二表面2b’，該第一表面2a’設於該第一電極層1之設置面1a，該第二表面2b’與第一表 面2a’相對，該通孔21’貫穿該第一表面2a’及第二表面2b’，使該第一電極層1之設置面1a裸露於該通孔21’中。 Referring to Fig. 7, there is shown a side cross-sectional view of a third embodiment of the resistive memory of the present invention. The third embodiment of the resistive memory includes the first electrode layer 1, the barrier body 2', the varistor layer 3 and the second electrode layer 4. The barrier body 2' can be formed with a through hole 21'. The first electrode layer 1 is exposed, the barrier body 2' further has a first surface 2a' and a second surface 2b'. The first surface 2a' is disposed on the first surface 2a of the first electrode layer 1. Two surface 2b' and the first table The surface 2a' faces the first surface 2a' and the second surface 2b' so that the installation surface 1a of the first electrode layer 1 is exposed in the through hole 21'.
其中，該第三實施例的阻隔體2’與第一實施例的阻隔體2差異可在於，該阻隔體2’除包含該第一介質外，另含有一第三介質，該第三介質的介電常數(K3)可與該第一介質的介電常數(K1)不同，該第三介質的可為任意絕緣層(如：SiO2或HfO2或任意比例混和)，惟該第三介質亦可和第一介質相同，僅須維持該第一介質的介電常數(K1)與該第二介質的介電常數(K2)間的關係即可；該第一介質分布的區域22’及該第三介質分布的區域23’不同，如：該區域22’、23’可形成二鄰接的材料層，該第一介質分布的區域22’及該第三介質分布的區域23’可鄰接該變阻層3，該第一介質分布的區域22’可鄰近該第一電極層1，該第一電極層1鄰接的第一介質分布的區域22’及該變阻層3局部的厚度可為相同。 The barrier body 2 ′ of the third embodiment may be different from the barrier body 2 of the first embodiment in that the barrier body 2 ′ includes a third medium in addition to the first medium, and the third medium The dielectric constant (K3) may be different from the dielectric constant (K1) of the first medium, and the third medium may be any insulating layer (eg, SiO2 or HfO2 or mixed in any ratio), but the third medium may also be Similar to the first medium, it is only necessary to maintain the relationship between the dielectric constant (K1) of the first medium and the dielectric constant (K2) of the second medium; the region 22' of the first medium distribution and the first The three media distribution regions 23' are different, for example, the regions 22', 23' may form two adjacent material layers, and the first dielectric distribution region 22' and the third dielectric distribution region 23' may be adjacent to the varistor The layer 3, the first medium distribution region 22' may be adjacent to the first electrode layer 1, and the first dielectric layer region 12' adjacent to the first dielectric layer 1 and the portion of the varistor layer 3 may have the same thickness.
如此，本發明電阻式記憶體第三實施例可利用不同介質及其分布區域調整該阻隔體2’的介電常數，以維持該變阻層3中第二介質的介電常數高於該阻隔體2中第一介質的介電常數之值不大於2，或該變阻層3的介電常數低於該阻隔體2’的介電常數之關係，可以達成「易於調整介電常數」功效。而且，本發明電阻式記憶體第三實施例的變阻層3中第二介質的介電常數低於該阻隔體2’中第一介質的介電常數，同樣可在體積縮小時，維持形成電壓的穩定性，避免記憶體元件在集成電路中操作上的問題。 As such, the third embodiment of the resistive memory of the present invention can adjust the dielectric constant of the barrier 2' using different media and its distribution region to maintain the dielectric constant of the second dielectric in the varistor layer 3 higher than the barrier. The value of the dielectric constant of the first medium in the body 2 is not more than 2, or the dielectric constant of the varistor layer 3 is lower than the dielectric constant of the barrier 2', and the "easy adjustment of the dielectric constant" can be achieved. . Moreover, the dielectric constant of the second medium in the varistor layer 3 of the third embodiment of the resistive memory of the present invention is lower than the dielectric constant of the first medium in the barrier body 2', and can also be maintained when the volume is reduced. The stability of the voltage avoids the problem of the operation of the memory component in the integrated circuit.
請參閱第8圖所示，其係本發明電阻式記憶體第四實施例之側面剖視圖。其中，該電阻式記憶體第四實施例可組合上述第一、二、三實施例而成，該第四實施例包含該第一電極層1、阻隔體2’、該變阻層3及第二電極層4’，該阻隔體2’可形成露出該第一電極層1之通孔21’，該通孔21’貫穿該第一表面2a’及第二表面2b’，該阻隔體2’可包含該第一介質及第三介質，該第三介質的介電常數與該第一介質的介電常數不同，該 第一介質分布的區域22’及該第三介質分布的區域23’不同，該第一介質分布的區域22’及該第三介質分布的區域23’鄰接該變阻層3，該第一介質分布的區域22’鄰近該第一電極層1，該第一電極層1鄰接的第一介質分布的區域22’及該變阻層3局部的厚度可為相同；該第二電極層4’可向上禿出而形成凸部41’，該凸部41’位於該變阻層3的槽部31外，惟不以此為限。 Referring to Fig. 8, there is shown a side cross-sectional view of a fourth embodiment of the resistive memory of the present invention. The fourth embodiment of the resistive memory can be combined with the first, second and third embodiments. The fourth embodiment comprises the first electrode layer 1, the barrier body 2', the varistor layer 3 and the first embodiment. a second electrode layer 4', the barrier body 2' may form a through hole 21' exposing the first electrode layer 1, the through hole 21' penetrating the first surface 2a' and the second surface 2b', the barrier body 2' The first medium and the third medium may be included, and the dielectric constant of the third medium is different from the dielectric constant of the first medium, The first medium distribution area 22' and the third medium distribution area 23' are different, the first medium distribution area 22' and the third medium distribution area 23' are adjacent to the varistor layer 3, the first medium The distributed region 22' is adjacent to the first electrode layer 1, and the first dielectric layer region 22' adjacent to the first electrode layer 1 and the portion of the varistor layer 3 may have the same thickness; the second electrode layer 4' may The convex portion 41' is located outside the groove portion 31 of the varistor layer 3, but is not limited thereto.
如此，本發明電阻式記憶體第四實施例可以達成上述「簡化製造過程」、「減少製程成本」及「易於調整介電常數」等功效。而且，本發明電阻式記憶體第四實施例同樣可在體積縮小時，維持形成電壓的穩定性，避免記憶體元件在集成電路中操作上的問題。 As described above, the fourth embodiment of the resistive memory of the present invention can achieve the above-mentioned "simplified manufacturing process", "reduced process cost", and "easy adjustment of dielectric constant". Moreover, the fourth embodiment of the resistive memory of the present invention can also maintain the stability of the formation voltage when the volume is reduced, and avoid the problem of the operation of the memory element in the integrated circuit.
藉由前揭之技術手段，本發明之電阻式記憶體上述實施例的主要特點列舉如下：該電阻式記憶體包含該第一電極層、阻隔體、變阻層及第二電極層，該第一電極層具有該設置面；該阻隔體具有該第一表面、第二表面及通孔，該第一表面設於該第一電極層之設置面，該第二表面與該第一表面相對，該通孔貫穿該第一表面及該第二表面，使該第一電極層之設置面裸露於該通孔中，該阻隔體含有該第一介質；該變阻層設於該通孔中裸露的設置面、該通孔的內壁面及該阻隔體之第二表面，該變阻層含有該第二介質，該第二介質的介電常數高於該第一介質的介電常數之值不大於2(差值僅介於0至2)，或該第二介質的介電常數(K2)低於該第一介質的介電常數(K1)；該第二電極層設於該變阻層表面。 The main features of the above-described embodiment of the resistive memory of the present invention are as follows: the resistive memory includes the first electrode layer, the barrier body, the varistor layer and the second electrode layer, An electrode layer has the setting surface; the barrier body has the first surface, the second surface and the through hole, the first surface is disposed on the setting surface of the first electrode layer, and the second surface is opposite to the first surface The through hole penetrates the first surface and the second surface, so that the setting surface of the first electrode layer is exposed in the through hole, the barrier body contains the first medium; the varistor layer is exposed in the through hole The setting surface, the inner wall surface of the through hole and the second surface of the blocking body, the varistor layer containing the second medium, the dielectric constant of the second medium being higher than the dielectric constant of the first medium Greater than 2 (the difference is only between 0 and 2), or the dielectric constant (K2) of the second medium is lower than the dielectric constant (K1) of the first medium; the second electrode layer is disposed on the varistor layer surface.
藉此，本發明電阻式記憶體上述實施例的體積縮小時，其形成電壓並不會隨著升高，可以達成「維持形成電壓的穩定性」功效，相較習知電阻式記憶體的形成電壓隨通孔尺寸縮小而不斷上升，本發明電阻式記憶體上述實施例可避免記憶體元件在集成電路中操作上的問題。 Therefore, when the volume of the resistive memory of the present invention is reduced, the voltage is not increased, and the "stability of maintaining voltage formation" can be achieved, compared with the formation of a conventional resistive memory. The voltage is continuously increased as the via size is reduced, and the above-described embodiment of the resistive memory of the present invention can avoid the problem of the operation of the memory element in the integrated circuit.
另，本發明電阻式記憶體上述實施例藉由該阻隔體包含該第一介質及第三介質，該第三介質的介電常數與該第一介質的介電常數不 同，該第一介質分布的區域及該第三介質分布的區域不同，該第一介質與該第三介質鄰接該變阻層，該第一介質分布的區域鄰近該第一電極層，該第一電極層鄰接的第一介質分布的區域及該變阻層局部的厚度可為相同，可以達成「易於調整介電常數」功效；又，該第二電極層可向上禿出而形成該凸部，該凸部位於該變阻層的槽部外，可以達成「簡化製造過程」及「減少製程成本」等功效。 In addition, the resistive memory of the present invention includes the first medium and the third medium by the barrier body, and the dielectric constant of the third medium and the dielectric constant of the first medium are not The first medium is adjacent to the third medium and the third medium is adjacent to the varistor layer, and the first medium is distributed adjacent to the first electrode layer. The region of the first medium adjacent to the one electrode layer and the thickness of the portion of the varistor layer may be the same, and the function of “easy to adjust the dielectric constant” may be achieved; and the second electrode layer may be bald upward to form the convex portion. The convex portion is located outside the groove portion of the varistor layer, and the effects of "simplifying the manufacturing process" and "reducing the process cost" can be achieved.
雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described in connection with the preferred embodiments described above, it is not intended to limit the scope of the invention. The technical scope of the invention is protected, and therefore the scope of the invention is defined by the scope of the appended claims.
1‧‧‧第一電極層 1‧‧‧First electrode layer
1a‧‧‧設置面 1a‧‧‧Setting surface
2‧‧‧阻隔體 2‧‧‧Barrier
2a‧‧‧第一表面 2a‧‧‧ first surface
2b‧‧‧第二表面 2b‧‧‧ second surface
21‧‧‧通孔 21‧‧‧through hole
3‧‧‧變阻層 3‧‧‧variable resistance layer
31‧‧‧槽部 31‧‧‧ slot department
4‧‧‧第二電極層 4‧‧‧Second electrode layer
41‧‧‧溝部 41‧‧‧Ditch
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| US15/393,983 US9853214B2 (en) | 2015-02-16 | 2016-12-29 | Resistive random access memory device with reduced power consumption |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687796B2 (en) * | 1995-06-07 | 2010-03-30 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
| US7935564B2 (en) * | 2008-02-25 | 2011-05-03 | International Business Machines Corporation | Self-converging bottom electrode ring |
| US8345463B2 (en) * | 2008-07-24 | 2013-01-01 | Hynix Semiconductor Inc. | Resistive memory device and method for fabricating the same |
| TW201440273A (en) * | 2013-04-12 | 2014-10-16 | Univ Chang Gung | Resistive random-access memory sensor element |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100082604A (en) * | 2009-01-09 | 2010-07-19 | 삼성전자주식회사 | Variable resistive memory device and method of forming thereof |
| US8394669B2 (en) * | 2009-07-13 | 2013-03-12 | Panasonic Corporation | Resistance variable element and resistance variable memory device |
| JP2011146111A (en) * | 2010-01-18 | 2011-07-28 | Toshiba Corp | Nonvolatile storage device and method for manufacturing the same |
| US20120091418A1 (en) * | 2010-10-14 | 2012-04-19 | Yung-Tin Chen | Bipolar storage elements for use in memory cells and methods of forming the same |
| KR101492139B1 (en) * | 2010-12-01 | 2015-02-10 | 캐논 아네르바 가부시키가이샤 | Nonvolatile memory element and method of manufacturing the same |
| JP2012243826A (en) * | 2011-05-16 | 2012-12-10 | Toshiba Corp | Non-volatile storage |
| CN102222763A (en) * | 2011-06-03 | 2011-10-19 | 复旦大学 | RRAM (resistive random access memory) with electric-field enhancement layer and manufacturing method thereof |
| WO2012169195A1 (en) * | 2011-06-10 | 2012-12-13 | 株式会社アルバック | Variable resistance element, and method for producing same |
| US20130286714A1 (en) * | 2011-09-28 | 2013-10-31 | Panasonic Corporation | Data write method for writing data to nonvolatile memory element, and nonvolatile memory device |
| KR101613033B1 (en) * | 2012-03-14 | 2016-04-15 | 고쿠리츠다이가쿠호진 토쿄고교 다이가꾸 | Resistance change memory |
| CN102664235B (en) * | 2012-04-12 | 2013-12-04 | 北京大学 | Small-electrode-structure resistance random access memory and preparation method of small-electrode-structure resistance random access memory |
| US9202846B2 (en) * | 2013-03-22 | 2015-12-01 | Kabushiki Kaisha Toshiba | Resistance random access memory device |
| US9425394B2 (en) * | 2013-09-03 | 2016-08-23 | Intermolecular, Inc. | Doped oxide dielectrics for resistive random access memory cells |
| US9029192B1 (en) * | 2013-12-20 | 2015-05-12 | Intermolecular, Inc. | Metal organic chemical vapor deposition of resistive switching layers for ReRAM cells |
| US20150188039A1 (en) * | 2013-12-26 | 2015-07-02 | Intermolecular Inc. | Embedded Resistors with Oxygen Gettering Layers |
| US20150255513A1 (en) * | 2014-03-04 | 2015-09-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| JP6391009B2 (en) * | 2014-03-17 | 2018-09-19 | パナソニックＩｐマネジメント株式会社 | Method of manufacturing variable resistance nonvolatile memory element |
| US9177916B1 (en) * | 2014-11-25 | 2015-11-03 | Intermolecular, Inc. | Amorphous silicon doped with fluorine for selectors of resistive random access memory cells |
| US9231203B1 (en) * | 2014-12-09 | 2016-01-05 | Intermolecular, Inc. | Doped narrow band gap nitrides for embedded resistors of resistive random access memory cells |
-
2015
- 2015-02-16 TW TW104105348A patent/TWI556245B/en not_active IP Right Cessation
- 2015-06-09 US US14/734,809 patent/US9711720B2/en active Active
-
2016
- 2016-12-29 US US15/393,983 patent/US9853214B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687796B2 (en) * | 1995-06-07 | 2010-03-30 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
| US7935564B2 (en) * | 2008-02-25 | 2011-05-03 | International Business Machines Corporation | Self-converging bottom electrode ring |
| US8345463B2 (en) * | 2008-07-24 | 2013-01-01 | Hynix Semiconductor Inc. | Resistive memory device and method for fabricating the same |
| TW201440273A (en) * | 2013-04-12 | 2014-10-16 | Univ Chang Gung | Resistive random-access memory sensor element |
Non-Patent Citations (1)
| Title |
|---|
| Chang, K. C. et al.," Characteristics and Mechanisms of Silicon-Oxide-Based Resistance Random Access Memory", IEEE Electron Device Letters, March 2013 * |
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