TWI555185B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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本申請案基於且主張西元2014年3月27日申請之美國臨時申請案第61/971445號之優先權,在此併入此申請案之揭露的全部以供參考。 The present application is based on and claims priority to U.S. Provisional Application Serial No. 61/971,445, filed on March 27, 2014, the entire disclosure of which is hereby incorporated by reference.
本發明是有關於一種半導體元件,且特別是有關於一種半導體感測元件。 This invention relates to a semiconductor component, and more particularly to a semiconductor sensing component.
半導體影像感測器用以感測光。一般而言,半導體影像感測器包含互補式金屬氧化物半導體(CMOS)影像感測器(CIS)與電荷耦合元件(CCD)感測器,且已廣泛地使用在各種應用中,例如數位靜態相機(DSC)、行動電話相機、數位攝錄影機(DV)與數位攝影機(DVR)應用。這些半導體影像感測器利用一影像感測元件陣列,每個影像感測元件包含光電二極體與其它元件,以吸收光並將所吸收到的光轉換成數位資料或電子訊號。 A semiconductor image sensor is used to sense light. In general, semiconductor image sensors include complementary metal oxide semiconductor (CMOS) image sensors (CIS) and charge coupled device (CCD) sensors, and have been widely used in various applications, such as digital static Camera (DSC), mobile phone camera, digital video recorder (DV) and digital camera (DVR) applications. These semiconductor image sensors utilize an array of image sensing elements, each of which includes a photodiode and other components to absorb light and convert the absorbed light into digital data or electronic signals.
背照式(BSI)互補式金屬氧化物半導體影像感測器為一種互補式金屬氧化物半導體影像感測器。背照式互補式金屬氧化物半導體影像感測器可操作來檢測從其背面投 射之光。背照式互補式金屬氧化物半導體影像感測器可縮短光學路徑並增加填充係數(fill factor),以改善每單位面積之光敏度與量子效率,且可降低光串擾(cross talk)與光響應不均勻。因此,可大幅改善互補式金屬氧化物半導體影像感測器之影像品質。此外,背照式互補式金屬氧化物半導體影像感測器具有高主光線角(chief ray angle),可允許較短之透鏡高度,而可達成較薄之相機模組。因此,背照式互補式金屬氧化物半導體影像感測器技術逐漸成為主流技術。 The back-illuminated (BSI) complementary metal oxide semiconductor image sensor is a complementary metal oxide semiconductor image sensor. A back-illuminated complementary metal oxide semiconductor image sensor is operable to detect a rear projection Shoot the light. Back-illuminated CMOS image sensors reduce optical paths and increase fill factor to improve photosensitivity and quantum efficiency per unit area, and reduce optical crosstalk and photoresponse Not uniform. Therefore, the image quality of the complementary metal oxide semiconductor image sensor can be greatly improved. In addition, the back-illuminated CMOS image sensor has a high chief ray angle that allows for a shorter lens height to achieve a thinner camera module. Therefore, the back-illuminated complementary metal oxide semiconductor image sensor technology has gradually become the mainstream technology.
然而,當現有背照式互補式金屬氧化物半導體影像感測器已大致滿足其所欲目標時,這些感測器仍無法完全滿足各方面需求。 However, when existing back-illuminated metal-oxide-semiconductor image sensors have substantially met their intended goals, these sensors still cannot fully meet various needs.
因此,本發明之一目的就是在提供一種半導體元件及其製造方法,其介於彩色濾光層與元件層之間的半導體層具有一表面,且此表面上形成有數個微結構,因此大多數的光可被這些微結構折射而進入半導體層,並由元件層所吸收。因此,半導體元件之量子效率因低反射與高吸收而獲得大幅提升。 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device and a method of fabricating the same, wherein a semiconductor layer between a color filter layer and an element layer has a surface on which a plurality of microstructures are formed, and thus most The light can be refracted by these microstructures into the semiconductor layer and absorbed by the element layer. Therefore, the quantum efficiency of the semiconductor element is greatly improved by low reflection and high absorption.
根據本發明之上述目的,提出一種半導體元件,用以感測入射光。半導體元件包含基材、元件層、半導體層以及彩色濾光層。元件層設於基材上,且包含數個感光區。半導體層位於元件層之上方,且具有第一表面以及相對於第一表面之第二表面,其中第一表面鄰近元件層,且半導 體層包含數個微結構位於第二表面上。彩色濾光層設於半導體層之第二表面上。 According to the above object of the present invention, a semiconductor element is proposed for sensing incident light. The semiconductor element includes a substrate, an element layer, a semiconductor layer, and a color filter layer. The component layer is disposed on the substrate and includes a plurality of photosensitive regions. a semiconductor layer above the element layer and having a first surface and a second surface opposite the first surface, wherein the first surface is adjacent to the element layer and the semiconductor The bulk layer comprises a plurality of microstructures on the second surface. The color filter layer is disposed on the second surface of the semiconductor layer.
依據本發明之一實施例,上述每一微結構具有剖面形狀,且剖面形狀為三角形、梯形或弧形。 According to an embodiment of the invention, each of the microstructures has a cross-sectional shape, and the cross-sectional shape is triangular, trapezoidal or curved.
依據本發明之另一實施例,上述微結構中之任相鄰二者彼此鄰接。 According to another embodiment of the invention, any two of the above microstructures are contiguous with each other.
依據本發明之又一實施例,上述微結構中之任相鄰二者彼此分離。 In accordance with yet another embodiment of the present invention, any two of the above microstructures are separated from one another.
依據本發明之再一實施例,上述每一微結構之高度大於λ/2.5,這些微結構之任相鄰二者之間之間距大於λ/2,λ代表入射光之波長。 According to still another embodiment of the present invention, the height of each of the microstructures is greater than λ/2.5, and the distance between any adjacent ones of the microstructures is greater than λ/2, and λ represents the wavelength of the incident light.
根據本發明之上述目的,另提出一種半導體元件之製造方法。在此半導體元件之製造方法中,提供基材,其中元件層與半導體層依序形成在基材之表面上,半導體層具有第一表面以及與第一表面相對之第二表面,第一表面鄰近元件層。形成數個微結構於半導體層之第二表面上。形成彩色濾光層於半導體層之第二表面上。 According to the above object of the present invention, a method of manufacturing a semiconductor device is further proposed. In the method of fabricating a semiconductor device, a substrate is provided, wherein an element layer and a semiconductor layer are sequentially formed on a surface of the substrate, the semiconductor layer having a first surface and a second surface opposite to the first surface, the first surface being adjacent Component layer. A plurality of microstructures are formed on the second surface of the semiconductor layer. A color filter layer is formed on the second surface of the semiconductor layer.
依據本發明之一實施例,上述提供基材之操作包含以矽或鍺形成半導體層。 According to an embodiment of the invention, the operation of providing the substrate comprises forming a semiconductor layer with germanium or germanium.
依據本發明之另一實施例,上述進行形成微結構之操作係利用微影製程與蝕刻製程。 In accordance with another embodiment of the present invention, the above-described operation for forming a microstructure utilizes a lithography process and an etching process.
依據本發明之又一實施例,上述進行形成微結構之操作係使每一微結構具有一剖面形狀,且此剖面形狀為三角形、梯形或弧形。 According to still another embodiment of the present invention, the operation of forming the microstructure is such that each microstructure has a cross-sectional shape, and the cross-sectional shape is triangular, trapezoidal or curved.
依據本發明之再一實施例,上述進行形成微結構之操作係使這些微結構之任相鄰二者彼此鄰接。 In accordance with still another embodiment of the present invention, the operation of forming the microstructures is such that any two adjacent of the microstructures are adjacent to each other.
依據本發明之再一實施例,上述進行形成微結構之操作係使這些微結構之任相鄰二者彼此分離。 In accordance with still another embodiment of the present invention, the operation of forming the microstructures described above separates any adjacent ones of the microstructures from each other.
依據本發明之再一實施例,在形成微結構之操作與形成彩色濾光層之操作之間,上述半導體元件之製造方法更包含形成介電層覆蓋在半導體層之第二表面上,其中介電層具有平坦表面,且進行形成彩色濾光層之操作係將彩色濾光層形成在平坦表面上。 According to still another embodiment of the present invention, between the operation of forming a microstructure and the operation of forming a color filter layer, the method of fabricating the semiconductor device further includes forming a dielectric layer overlying the second surface of the semiconductor layer, wherein The electrical layer has a flat surface, and the operation of forming the color filter layer forms a color filter layer on the flat surface.
依據本發明之再一實施例,上述半導體元件之製造方法更包含形成數個微透鏡於彩色濾光層上。 According to still another embodiment of the present invention, the method of fabricating the semiconductor device further includes forming a plurality of microlenses on the color filter layer.
根據本發明之上述目的,更提出一種半導體元件之製造方法。在此半導體元件之製造方法中,提供第一基材,此第一基材具有第一表面以及與第一表面相對之第二表面。形成數個微結構於第一基材之第二表面上。形成介電層覆蓋在第一基材之第二表面上。將第二基材接合至介電層。形成元件層於第一基材之第一表面上。將第三基材接合至元件層。移除第二基材與介電層以暴露出第一基材之第二表面。形成彩色濾光層於第一基材之第二表面上。 According to the above object of the present invention, a method of manufacturing a semiconductor device is further proposed. In the method of fabricating a semiconductor device, a first substrate is provided, the first substrate having a first surface and a second surface opposite the first surface. A plurality of microstructures are formed on the second surface of the first substrate. A dielectric layer is formed overlying the second surface of the first substrate. A second substrate is bonded to the dielectric layer. Forming a component layer on the first surface of the first substrate. A third substrate is bonded to the element layer. The second substrate and the dielectric layer are removed to expose the second surface of the first substrate. A color filter layer is formed on the second surface of the first substrate.
依據本發明之一實施例,上述提供第一基材之操作包含提供第一層與第二層堆疊在第一層上,且進行形成結構之操作係將這些微結構形成在第二層上。 In accordance with an embodiment of the present invention, the operation of providing the first substrate includes providing the first layer and the second layer stacked on the first layer, and performing the operation of forming the structure to form the microstructure on the second layer.
依據本發明之另一實施例,在接合第二基材之操作與形成元件層之操作之間,上述半導體元件之製造方法更 包含移除第一層。 According to another embodiment of the present invention, the method of manufacturing the above semiconductor element is further between the operation of bonding the second substrate and the operation of forming the element layer. Includes removing the first layer.
依據本發明之又一實施例,上述提供第一基材之操作包含以不同材料製作第一層與第二層。 In accordance with yet another embodiment of the present invention, the above described operation of providing the first substrate comprises making the first layer and the second layer from different materials.
依據本發明之再一實施例,在形成元件層之操作與接合第三基材之操作之間,上述半導體元件之製造方法更包含形成鈍化層覆蓋在元件層上、以及平坦化此鈍化層。 According to still another embodiment of the present invention, between the operation of forming the element layer and the operation of bonding the third substrate, the method of fabricating the semiconductor device further includes forming a passivation layer over the element layer and planarizing the passivation layer.
依據本發明之再一實施例,上述進行形成微結構之操作係使這些微結構之任相鄰二者彼此鄰接。 In accordance with still another embodiment of the present invention, the operation of forming the microstructures is such that any two adjacent of the microstructures are adjacent to each other.
依據本發明之再一實施例,上述進行形成微結構之操作係使這些微結構之任相鄰二者彼此分離。 In accordance with still another embodiment of the present invention, the operation of forming the microstructures described above separates any adjacent ones of the microstructures from each other.
100‧‧‧半導體元件 100‧‧‧Semiconductor components
102‧‧‧基材 102‧‧‧Substrate
104‧‧‧表面 104‧‧‧ Surface
106‧‧‧元件層 106‧‧‧Component layer
108‧‧‧感光區 108‧‧‧Photosensitive area
110a‧‧‧半導體層 110a‧‧‧Semiconductor layer
110b‧‧‧半導體層 110b‧‧‧Semiconductor layer
112‧‧‧第一表面 112‧‧‧ first surface
114a‧‧‧第二表面 114a‧‧‧second surface
114b‧‧‧第二表面 114b‧‧‧second surface
116a‧‧‧微結構 116a‧‧‧Microstructure
116b‧‧‧微結構 116b‧‧‧Microstructure
118‧‧‧介電層 118‧‧‧ dielectric layer
120‧‧‧表面 120‧‧‧ surface
122‧‧‧彩色濾光層 122‧‧‧Color filter layer
124‧‧‧微透鏡層 124‧‧‧Microlens layer
126‧‧‧微透鏡 126‧‧‧Microlens
128‧‧‧入射光 128‧‧‧ incident light
130‧‧‧正面 130‧‧‧ positive
132‧‧‧背面 132‧‧‧Back
200‧‧‧光罩 200‧‧‧ mask
202‧‧‧光 202‧‧‧Light
300‧‧‧操作 300‧‧‧ operations
302‧‧‧操作 302‧‧‧ operation
304‧‧‧操作 304‧‧‧ operation
400‧‧‧第一基材 400‧‧‧First substrate
402‧‧‧第一層 402‧‧‧ first floor
404‧‧‧第二層 404‧‧‧ second floor
406‧‧‧第一表面 406‧‧‧ first surface
408‧‧‧第二表面 408‧‧‧ second surface
410‧‧‧微結構 410‧‧‧Microstructure
412‧‧‧表面 412‧‧‧ surface
414‧‧‧介電層 414‧‧‧ dielectric layer
416‧‧‧表面 416‧‧‧ surface
418‧‧‧第二基材 418‧‧‧Second substrate
420‧‧‧元件層 420‧‧‧Component layer
422‧‧‧感光區 422‧‧‧Photosensitive area
424‧‧‧鈍化層 424‧‧‧passivation layer
426‧‧‧表面 426‧‧‧ surface
428‧‧‧第三基材 428‧‧‧ Third substrate
430‧‧‧介電層 430‧‧‧ dielectric layer
432‧‧‧表面 432‧‧‧ surface
434‧‧‧彩色濾光層 434‧‧‧Color filter layer
436‧‧‧微透鏡層 436‧‧‧Microlens layer
438‧‧‧微透鏡 438‧‧‧Microlens
440‧‧‧半導體元件 440‧‧‧Semiconductor components
500‧‧‧光罩 500‧‧‧ mask
502‧‧‧光 502‧‧‧Light
600‧‧‧操作 600‧‧‧ operation
602‧‧‧操作 602‧‧‧ operation
604‧‧‧操作 604‧‧‧ operation
606‧‧‧操作 606‧‧‧ operation
608‧‧‧操作 608‧‧‧ operation
610‧‧‧操作 610‧‧‧ operation
612‧‧‧操作 612‧‧‧ operation
614‧‧‧操作 614‧‧‧ operation
h1‧‧‧高度 H1‧‧‧ Height
h2‧‧‧高度 H2‧‧‧ height
w1‧‧‧間距 W1‧‧‧ spacing
w2‧‧‧間距 W2‧‧‧ spacing
從以下結合所附圖式所做的詳細描述,可對本揭露之態樣有更佳的了解。需注意的是,根據業界的標準實務,各特徵並未依比例繪示。事實上,為了使討論更為清楚,各特徵的尺寸都可任意地增加或減少。 A better understanding of the aspects of the present disclosure can be obtained from the following detailed description taken in conjunction with the drawings. It should be noted that, according to industry standard practices, the features are not drawn to scale. In fact, in order to make the discussion clearer, the dimensions of each feature can be arbitrarily increased or decreased.
第1圖係繪示依照本發明之各實施方式的一種半導體元件的剖面示意圖。 1 is a cross-sectional view showing a semiconductor device in accordance with various embodiments of the present invention.
第2A圖係繪示依照本發明之各實施方式的一種半導體元件之半導體層的剖面放大示意圖。 2A is a schematic enlarged cross-sectional view showing a semiconductor layer of a semiconductor device in accordance with various embodiments of the present invention.
第2B圖係繪示依照本發明之各實施方式的一種半導體元件之半導體層的剖面放大示意圖。 2B is a schematic enlarged cross-sectional view showing a semiconductor layer of a semiconductor device in accordance with various embodiments of the present invention.
第3A圖至第3D圖係繪示依照各實施方式之一種半導體元件之製造方法之各個中間階段的剖面示意圖。 3A to 3D are schematic cross-sectional views showing respective intermediate stages of a method of fabricating a semiconductor device in accordance with various embodiments.
第4圖係繪示依照各實施方式之一種半導體元件之製造方法的流程圖。 4 is a flow chart showing a method of manufacturing a semiconductor device in accordance with various embodiments.
第5A圖至第5F圖係繪示依照各實施方式之一種半導體元件之製造方法之各個中間階段的剖面示意圖。 5A to 5F are schematic cross-sectional views showing respective intermediate stages of a method of fabricating a semiconductor device in accordance with various embodiments.
第6圖係繪示依照各實施方式之一種半導體元件之製造方法的流程圖。 Fig. 6 is a flow chart showing a method of manufacturing a semiconductor device in accordance with various embodiments.
以下的揭露提供了許多不同實施方式或實施例,以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定例子係用以簡化本揭露。當然這些僅為實施例,並非用以做為限制。舉例而言,於描述中,第一特徵形成於第二特徵之上方或之上,可能包含第一特徵與第二特徵以直接接觸的方式形成的實施方式,亦可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施方式,如此第一特徵與第二特徵可能不會直接接觸。此外,本揭露可能會在各實施例中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的,以其本身而言並非用以指定所討論之各實施方式及/或配置之間的關係。如在此所使用的,用詞「及/或(and/or)」包含一或多個相關列示項目的任意或所有組合。 The following disclosure provides many different embodiments or embodiments to implement different features of the subject matter provided. Specific examples of components and arrangements described below are used to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description, the first feature is formed above or above the second feature, and may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed in the first An embodiment between a feature and a second feature such that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or text in the various embodiments. Such repetitions are based on the simplification and clarity of the invention and are not intended to specify the relationship between the various embodiments and/or configurations discussed. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
在一般之背照式互補式金屬氧化物半導體影像感測器中,在光由其背面投射且穿過彩色濾光層而進入彩色濾光層與下方元件層之間的半導體層之前,光會碰撞到半導體層之平坦表面,而半導體層之平坦表面會將大多數的 光反射。因此,背照式互補式金屬氧化物半導體影像感測器之量子效率會因半導體層之高光反射與元件層之低光接收而減少。 In a general back-illuminated complementary metal oxide semiconductor image sensor, before the light is projected from the back side and passes through the color filter layer and enters the semiconductor layer between the color filter layer and the lower device layer, the light will Colliding to the flat surface of the semiconductor layer, while the flat surface of the semiconductor layer will Light reflection. Therefore, the quantum efficiency of the back-illuminated metal-oxide-semiconductor image sensor is reduced by the high-light reflection of the semiconductor layer and the low-light reception of the element layer.
本揭露之實施方式係針對一種半導體元件及製造此半導體元件之方法,其中介於彩色濾光層與元件層之間的半導體層具有一表面,且此表面上形成有數個微結構,因此大多數的光可被這些微結構折射而進入半導體層,並由元件層所吸收。因此,半導體元件之量子效率因低反射與高吸收而獲得大幅提升。 Embodiments of the present disclosure are directed to a semiconductor device and a method of fabricating the same, wherein a semiconductor layer interposed between a color filter layer and an element layer has a surface on which a plurality of microstructures are formed, and thus most The light can be refracted by these microstructures into the semiconductor layer and absorbed by the element layer. Therefore, the quantum efficiency of the semiconductor element is greatly improved by low reflection and high absorption.
第1圖係繪示依照本發明之各實施方式的一種半導體元件的剖面示意圖。在一些實施例中,半導體元件100為互補式金屬氧化物半導體影像感測元件,其可操作來感測入射光128。半導體元件100具有正面130與背面132。在特定實施例中,半導體元件100為背照式互補式金屬氧化物半導體影像感測元件,其可操作來感測從其背面132投射之入射光128。如第1圖所示,半導體元件100包含基材102、元件層106、半導體層110a與彩色濾光層122。基材102為半導體基材。基材102由單晶半導體材料或化合物半導體材料所組成。在一些例子中,基材102為矽基材。在一些實施例中,亦可使用鍺或玻璃來作為基材102之材料。 1 is a cross-sectional view showing a semiconductor device in accordance with various embodiments of the present invention. In some embodiments, semiconductor component 100 is a complementary metal oxide semiconductor image sensing component that is operable to sense incident light 128. The semiconductor device 100 has a front side 130 and a back side 132. In a particular embodiment, semiconductor component 100 is a back-illuminated complementary metal oxide semiconductor image sensing component that is operable to sense incident light 128 projected from its back side 132. As shown in FIG. 1, the semiconductor device 100 includes a substrate 102, an element layer 106, a semiconductor layer 110a, and a color filter layer 122. The substrate 102 is a semiconductor substrate. The substrate 102 is composed of a single crystal semiconductor material or a compound semiconductor material. In some examples, substrate 102 is a tantalum substrate. In some embodiments, tantalum or glass may also be used as the material for the substrate 102.
在一些實施例中,元件層106設於基材102之表面104上。在一替代實施例中,可在元件層106與基材102之間額外形成鈍化層(未繪示)。元件層106包含數個感光區 108。在一些例子中,每個感光區108包含一像素,此像素包含一影像感測元件,其中影像感測元件包含光電二極體與其它元件。感光區108操作來感測入射光128。 In some embodiments, component layer 106 is disposed on surface 104 of substrate 102. In an alternate embodiment, a passivation layer (not shown) may be additionally formed between the element layer 106 and the substrate 102. Component layer 106 includes a plurality of photosensitive regions 108. In some examples, each photosensitive region 108 includes a pixel that includes an image sensing element, wherein the image sensing element includes a photodiode and other components. Photosensitive region 108 operates to sense incident light 128.
半導體層110a位於元件層106之上方。在一些實施例中,半導體層110a由矽、鍺、磊晶矽及/或磊晶鍺所組成。半導體層110a具有第一表面112以及相對於第一表面112之第二表面114a,第一表面112鄰近於元件層106。半導體層110a包含數個微結構116a形成在第二表面114a上。請參照第2A圖與第2B圖,第2A圖係繪示依照本發明之各實施方式的一種半導體元件之半導體層的剖面放大示意圖,第2B圖係繪示依照本發明之各實施方式的一種半導體元件之半導體層的剖面放大示意圖。在一些實施例中,每個微結構116a具有剖面形狀,此剖面形狀為三角形、梯形或弧形,例如半圓形或半橢圓形。舉例而言,每個微結構116a具有如第2A圖所示之三角形剖面形狀,而形成在半導體層110b之第二表面114b上的每個微結構116b具有如第2B圖所示之梯形剖面形狀。在這些例子中,半導體層110b類似於半導體層110a,係位於元件層106上方,且半導體層110b之第一表面112與第二表面114b相對並鄰近於元件層106。類似的,半導體層110b可由矽、鍺、磊晶矽及/或磊晶鍺所組成。 The semiconductor layer 110a is located above the element layer 106. In some embodiments, the semiconductor layer 110a is composed of tantalum, niobium, epitaxial germanium, and/or epitaxial germanium. The semiconductor layer 110a has a first surface 112 and a second surface 114a opposite the first surface 112, the first surface 112 being adjacent to the element layer 106. The semiconductor layer 110a includes a plurality of microstructures 116a formed on the second surface 114a. 2A and 2B, FIG. 2A is a schematic enlarged cross-sectional view showing a semiconductor layer of a semiconductor device in accordance with various embodiments of the present invention, and FIG. 2B is a cross-sectional view showing an embodiment of the present invention. A schematic cross-sectional view of a semiconductor layer of a semiconductor device. In some embodiments, each microstructure 116a has a cross-sectional shape that is triangular, trapezoidal, or curved, such as semi-circular or semi-elliptical. For example, each microstructure 116a has a triangular cross-sectional shape as shown in FIG. 2A, and each microstructure 116b formed on the second surface 114b of the semiconductor layer 110b has a trapezoidal cross-sectional shape as shown in FIG. 2B. . In these examples, the semiconductor layer 110b is similar to the semiconductor layer 110a above the element layer 106, and the first surface 112 of the semiconductor layer 110b is opposite the second surface 114b and adjacent to the element layer 106. Similarly, the semiconductor layer 110b may be composed of germanium, germanium, epitaxial germanium, and/or epitaxial germanium.
在一些例子中,微結構116a或116b規則排列。在一些例子中,微結構116a或116b不規則排列。此外,如第2A圖所示,微結構116a之任相鄰二者可彼此鄰接。在 一些例子中,如第2B圖所示,微結構116b之任相鄰二者彼此分離。在第2A圖所示之半導體層110a中,每個微結構116a具有高度h1,且微結構116a之任相鄰二者之間形成有一間距w1。在一些例子中,高度h1介於100λ與λ/100之間,且間距w1介於100λ與λ/100之間,其中λ代表入射光128之波長。在特定例子中,高度h1大於λ/2.5,且間距w1大於λ/2。在第2B圖所示之半導體層110b中,每個微結構116b具有高度h2,且微結構116b之任相鄰二者之間形成有一間距w2。在一些例子中,高度h2介於100λ與λ/100之間,且間距w2介於100λ與λ/100之間。在特定例子中,高度h2大於λ/2.5,且間距w2大於λ/2。 In some examples, microstructures 116a or 116b are regularly arranged. In some examples, the microstructures 116a or 116b are arranged irregularly. Furthermore, as shown in FIG. 2A, any adjacent ones of the microstructures 116a may abut each other. in In some examples, as shown in Figure 2B, any two adjacent microstructures 116b are separated from one another. In the semiconductor layer 110a shown in Fig. 2A, each of the microstructures 116a has a height h1, and a space w1 is formed between any adjacent ones of the microstructures 116a. In some examples, height h1 is between 100λ and λ/100, and pitch w1 is between 100λ and λ/100, where λ represents the wavelength of incident light 128. In a particular example, height h1 is greater than λ/2.5 and pitch w1 is greater than λ/2. In the semiconductor layer 110b shown in Fig. 2B, each of the microstructures 116b has a height h2, and a gap w2 is formed between any adjacent ones of the microstructures 116b. In some examples, height h2 is between 100λ and λ/100, and pitch w2 is between 100λ and λ/100. In a particular example, height h2 is greater than λ/2.5 and spacing w2 is greater than λ/2.
藉由微結構116a或116b,可增加第二表面114a或114b之面積,且入射光128投射於第二表面114a或114b之入射角小於入射光128投射於一平坦表面之入射角,因此入光射128之大多數可在微結構116a或116b中多次折射,接著穿過半導體層110a或110b而抵達元件層106,並由元件層106所吸收。因此,可大幅提升入射光128之吸收率。 By the microstructures 116a or 116b, the area of the second surface 114a or 114b can be increased, and the incident angle of the incident light 128 projected onto the second surface 114a or 114b is smaller than the incident angle at which the incident light 128 is projected onto a flat surface, thus entering the light. Most of the radiation 128 can be refracted multiple times in the microstructures 116a or 116b, then passed through the semiconductor layer 110a or 110b to the element layer 106 and absorbed by the element layer 106. Therefore, the absorption rate of the incident light 128 can be greatly improved.
在一些實施例中,彩色濾光層122形成在半導體層110a之第二表面114a上。彩色濾光層122包含許多排成一陣列之彩色濾光器,例如多個紅色濾光器、多個綠色濾光器與多個藍色濾光器。在一些實施例中,如第1圖所示,半導體元件100選擇性地包含介電層118,此介電層118形成來覆蓋半導體層110a之第二表面114a。在一些例子中, 介電層118由氧化矽、氮化矽或氮氧化矽所組成。介電層118之表面120係平坦的,且彩色濾光層122形成在介電層118之平坦的表面120上。 In some embodiments, color filter layer 122 is formed on second surface 114a of semiconductor layer 110a. The color filter layer 122 includes a plurality of color filters arranged in an array, such as a plurality of red filters, a plurality of green filters, and a plurality of blue filters. In some embodiments, as shown in FIG. 1, the semiconductor device 100 selectively includes a dielectric layer 118 formed to cover the second surface 114a of the semiconductor layer 110a. In some examples, Dielectric layer 118 is composed of hafnium oxide, tantalum nitride or hafnium oxynitride. The surface 120 of the dielectric layer 118 is flat and the color filter layer 122 is formed on the planar surface 120 of the dielectric layer 118.
請再次參照第1圖,在一些實施例中,半導體元件100選擇性地包含微透鏡層124。此微透鏡層124形成在彩色濾光層122上。微透鏡層124包含數個微透鏡126。這些微透鏡126可將入射光128朝元件層106之感光區108導引並聚焦。這些微透鏡126可根據微透鏡126之折射率、以及感光區108與微透鏡126之間的距離而排列成具各種形狀的各種形式。 Referring again to FIG. 1, in some embodiments, semiconductor component 100 selectively includes microlens layer 124. This microlens layer 124 is formed on the color filter layer 122. The microlens layer 124 includes a plurality of microlenses 126. These microlenses 126 can direct incident light 128 toward the photosensitive region 108 of the component layer 106 and focus. These microlenses 126 can be arranged in various forms having various shapes depending on the refractive index of the microlenses 126 and the distance between the photosensitive regions 108 and the microlenses 126.
請參照第3A圖至第3D圖,第3A圖至第3D圖係繪示依照各實施方式之一種半導體元件之製造方法之各個中間階段的剖面示意圖。如第3A圖所示,提供基材102。基材102由單晶半導體材料或化合物半導體材料所構成。在一些實施例中,使用矽、鍺或玻璃來作為形成基材102之材料。依序形成元件層106與半導體層110a於基材102之表面104上。半導體層110a具有第一表面112以及與第一表面112相對之第二表面114a。在一些實施例中,先形成元件層106於半導體層110a之第一表面112上,接著利用例如接合(bonding)技術,將元件層106附著至基材102之表面104。在一些例子中,可選擇性地對半導體層110a之第二表面114a進行薄化製程,以縮減半導體層110a之厚度。在特定例子中,形成半導體層110a在暫時基材(未繪示)上,形成元件層106在半導體層110a之第一表面112 上,並將元件層106接合至基材102之表面104,接著進行薄化製程以移除暫時基材,半導體層110a可在薄化製程中被薄化。可利用化學機械研磨(CMP)技術來進行薄化製程。 Referring to FIGS. 3A to 3D, FIGS. 3A to 3D are schematic cross-sectional views showing respective intermediate stages of a method of fabricating a semiconductor device in accordance with various embodiments. As shown in Figure 3A, a substrate 102 is provided. The substrate 102 is composed of a single crystal semiconductor material or a compound semiconductor material. In some embodiments, tantalum, niobium or glass is used as the material for forming the substrate 102. The element layer 106 and the semiconductor layer 110a are sequentially formed on the surface 104 of the substrate 102. The semiconductor layer 110a has a first surface 112 and a second surface 114a opposite the first surface 112. In some embodiments, element layer 106 is first formed on first surface 112 of semiconductor layer 110a, and then element layer 106 is attached to surface 104 of substrate 102 using, for example, bonding techniques. In some examples, the second surface 114a of the semiconductor layer 110a may be selectively thinned to reduce the thickness of the semiconductor layer 110a. In a specific example, the semiconductor layer 110a is formed on a temporary substrate (not shown), and the element layer 106 is formed on the first surface 112 of the semiconductor layer 110a. The element layer 106 is bonded to the surface 104 of the substrate 102, followed by a thinning process to remove the temporary substrate, and the semiconductor layer 110a can be thinned in the thinning process. Chemical mechanical polishing (CMP) techniques can be utilized to perform the thinning process.
在一些實施例中,元件層106包含數個感光區108。每個感光區108可包含一像素,此像素包含一影像感測元件,且影像感測元件包含光電二極體與其它元件。在一些例子中,半導體層110a由矽、鍺、磊晶矽及/或磊晶鍺所構成。 In some embodiments, component layer 106 includes a plurality of photosensitive regions 108. Each photosensitive region 108 can include a pixel that includes an image sensing element, and the image sensing element includes a photodiode and other components. In some examples, the semiconductor layer 110a is composed of tantalum, niobium, epitaxial germanium, and/or epitaxial germanium.
如第3C圖所示,數個微結構116a形成在半導體層110a之第二表面114a上。在一些實施例中,如第3B圖與第3C圖所示,利用微影製程與蝕刻製程進行形成微結構116a之操作,其中藉由透過光罩200而朝第二表面114a投射光202的方式來進行微影製程,以定義出欲形成微結構116a之區域,再根據微影製程的定義,於第二表面114a上進行蝕刻製程,以移除半導體層110a之一部分,而在第二表面114a上形成微結構116a。在一些例子中,利用乾式蝕刻技術或化學蝕刻技術進行蝕刻製程。在特定例子中,利用雷射移除技術形成這些微結構116a。 As shown in Fig. 3C, a plurality of microstructures 116a are formed on the second surface 114a of the semiconductor layer 110a. In some embodiments, as shown in FIGS. 3B and 3C, the operation of forming the microstructures 116a is performed by a lithography process and an etching process in which the light 202 is projected toward the second surface 114a by the reticle 200. The lithography process is performed to define a region where the microstructure 116a is to be formed, and then an etching process is performed on the second surface 114a to remove a portion of the semiconductor layer 110a, and at the second surface 114a, according to the definition of the lithography process. A microstructure 116a is formed thereon. In some examples, the etching process is performed using a dry etch technique or a chemical etch technique. In a particular example, these microstructures 116a are formed using a laser removal technique.
每個微結構116a可形成有三角形、梯形或弧形之剖面形狀,弧形可例如為半圓形或半橢圓形。微結構116a規則地形成。在一些例子中,微結構116a不規則地形成。在一些實施例中,請同時參照的2A圖與第3C圖,進行形成微結構116a之操作,以使微結構116a之任相鄰二者彼此鄰接。請參照第2B圖,在形成微結構116b之操作中, 微結構116b之任相鄰二者可彼此分離。每個微結構116a具有高度h1,且微結構116a之任相鄰二者之間形成有一間距w1。在一些例子中,高度h1介於100λ與λ/100之間,且間距w1介於100λ與λ/100之間,其中λ代表入射光128之波長。在特定例子中,高度h1大於λ/2.5,且間距w1大於λ/2。 Each of the microstructures 116a may be formed with a triangular, trapezoidal or curved cross-sectional shape, which may be, for example, semi-circular or semi-elliptical. The microstructures 116a are formed regularly. In some examples, microstructures 116a are formed irregularly. In some embodiments, the operations of forming the microstructures 116a are performed in conjunction with the 2A and 3C drawings, so that any adjacent ones of the microstructures 116a are adjacent to each other. Referring to FIG. 2B, in the operation of forming the microstructure 116b, Adjacent two of the microstructures 116b can be separated from each other. Each microstructure 116a has a height h1 and a spacing w1 is formed between any adjacent ones of the microstructures 116a. In some examples, height h1 is between 100λ and λ/100, and pitch w1 is between 100λ and λ/100, where λ represents the wavelength of incident light 128. In a particular example, height h1 is greater than λ/2.5 and pitch w1 is greater than λ/2.
在一些實施例中,於微結構116a形成後,形成彩色濾光層122於半導體層110a之第二表面114a上。彩色濾光層122包含許多排成一陣列之彩色濾光器,例如多個紅色濾光器、多個綠色濾光器與多個藍色濾光器。在一些實施例中,如第3D圖所示,於微結構116a形成後,形成介電層118,以覆蓋半導體層110a之第二表面114a,並填充微結構116a之任相鄰二者之間的間隙,而彩色濾光層122形成於介電層118上。介電層118可由氧化矽、氮化矽或氮氧化矽所構成。介電層118具有平坦之表面120,且彩色濾光層122形成在介電層118之平坦的表面120上。在一些例子中,利用熱氧化技術或沉積技術,例如化學氣相沉積(CVD)技術,進行形成介電層118之操作。在特定例子中,於介電層118形成後,對介電層118進行平坦化製程,以形成具有平坦之表面120的介電層118。可利用化學機械研磨技術進行平坦化製程。 In some embodiments, after the microstructures 116a are formed, a color filter layer 122 is formed on the second surface 114a of the semiconductor layer 110a. The color filter layer 122 includes a plurality of color filters arranged in an array, such as a plurality of red filters, a plurality of green filters, and a plurality of blue filters. In some embodiments, as shown in FIG. 3D, after the microstructures 116a are formed, a dielectric layer 118 is formed to cover the second surface 114a of the semiconductor layer 110a and fill the gap between any adjacent ones of the microstructures 116a. The color filter layer 122 is formed on the dielectric layer 118. The dielectric layer 118 may be composed of tantalum oxide, tantalum nitride or hafnium oxynitride. Dielectric layer 118 has a flat surface 120 and color filter layer 122 is formed on planar surface 120 of dielectric layer 118. In some examples, the operation of forming dielectric layer 118 is performed using thermal oxidation techniques or deposition techniques, such as chemical vapor deposition (CVD) techniques. In a particular example, after the dielectric layer 118 is formed, the dielectric layer 118 is planarized to form a dielectric layer 118 having a planar surface 120. The chemical mechanical polishing technique can be used for the planarization process.
在一些實施例中,於彩色濾光層122形成後,選擇性地形成包含數個微透鏡126之微透鏡層124於彩色濾光層122上,以完成半導體元件100。進行形成微透鏡126 之操作係可根據微透鏡126之折射率、以及感光區108與微透鏡126之間的距離,而以各種排列與各種形狀形成微透鏡126。 In some embodiments, after the color filter layer 122 is formed, the microlens layer 124 including the plurality of microlenses 126 is selectively formed on the color filter layer 122 to complete the semiconductor device 100. Forming a microlens 126 The operation is based on the refractive index of the microlens 126 and the distance between the photosensitive region 108 and the microlens 126, and the microlenses 126 are formed in various arrangements and in various shapes.
請一併參照第4圖與第3A圖至第3D圖,第4圖係繪示依照各實施方式之一種半導體元件之製造方法的流程圖。此方法始於操作300,以提供基材102,再依序形成元件層106與半導體層110a於基材102之表面104上,如第3A圖所示。半導體層110a具有第一表面112以及相對於第一表面112之第二表面114a。在一些實施例中,形成元件層106於半導體層110a之第一表面112上,並利用例如接合方式,將元件層106附著至基材102之表面104。選擇性地,對半導體層110a之第二表面114a進行薄化製程,以縮減半導體層110a之厚度。 Referring to FIG. 4 and FIGS. 3A to 3D together, FIG. 4 is a flow chart showing a method of manufacturing a semiconductor device in accordance with various embodiments. The method begins at operation 300 to provide a substrate 102, which in turn forms element layer 106 and semiconductor layer 110a on surface 104 of substrate 102, as shown in FIG. 3A. The semiconductor layer 110a has a first surface 112 and a second surface 114a relative to the first surface 112. In some embodiments, the element layer 106 is formed on the first surface 112 of the semiconductor layer 110a and the element layer 106 is attached to the surface 104 of the substrate 102 using, for example, bonding. Optionally, the second surface 114a of the semiconductor layer 110a is thinned to reduce the thickness of the semiconductor layer 110a.
在操作302中,如第3B圖與第3C圖所示,利用例如微影製程與蝕刻製程,形成微結構116a於半導體層110a之第二表面114a上。在一些例子中,利用乾式蝕刻技術或化學蝕刻技術進行蝕刻製程。在特定例子中,利用雷射移除技術形成這些微結構116a。可進行形成微結構116a之操作來使每個微結構116a具有三角形、梯形或弧形之剖面形狀,弧形可例如為半圓形或半橢圓形。微結構116a可規則地形成。在一些例子中,微結構116a不規則地形成。 In operation 302, as shown in FIGS. 3B and 3C, the microstructures 116a are formed on the second surface 114a of the semiconductor layer 110a using, for example, a lithography process and an etching process. In some examples, the etching process is performed using a dry etch technique or a chemical etch technique. In a particular example, these microstructures 116a are formed using a laser removal technique. The operation of forming the microstructures 116a may be performed such that each of the microstructures 116a has a triangular, trapezoidal or curved cross-sectional shape, which may be, for example, semi-circular or semi-elliptical. The microstructures 116a can be formed regularly. In some examples, microstructures 116a are formed irregularly.
在一些實施例中,進行形成微結構116a之操作,以使微結構116a之任相鄰二者彼此鄰接,如第2A圖所示。替代地,如第2B圖所示,可使微結構116b之任相鄰二者 彼此分離。在一些例子中,每個微結構116a之高度h1介於100λ與λ/100之間,且微結構116a之任相鄰二者之間的間距w1介於100λ與λ/100之間,其中λ代表入射光之波長。在特定例子中,每個微結構116a之高度h1大於λ/2.5,且微結構116a之任相鄰二者之間的間距w1大於λ/2。 In some embodiments, the operation of forming microstructures 116a is performed such that any adjacent ones of microstructures 116a are contiguous with each other, as shown in FIG. 2A. Alternatively, as shown in FIG. 2B, any two adjacent microstructures 116b may be Separated from each other. In some examples, the height h1 of each microstructure 116a is between 100λ and λ/100, and the spacing w1 between any adjacent ones of the microstructures 116a is between 100λ and λ/100, where λ represents incidence The wavelength of light. In a particular example, the height h1 of each microstructure 116a is greater than λ/2.5, and the spacing w1 between any adjacent ones of the microstructures 116a is greater than λ/2.
在操作304中,形成彩色濾光層122於半導體層110a之第二表面114a上。彩色濾光層122包含包含許多排成一陣列之彩色濾光器,例如多個紅色濾光器、多個綠色濾光器與多個藍色濾光器。在一些實施例中,如第3D圖所示,先利用熱氧化技術或沉積技術形成介電層118,以覆蓋半導體層110a之第二表面114a,並填充微結構116a之任相鄰二者之間的間隙,再形成彩色濾光層122於介電層118上。介電層118具有利用平坦化製程所形成之平坦的表面120,而彩色濾光層122形成在此平坦之表面120上。在一些實施例中,選擇性地形成包含數個微透鏡126之微透鏡層124於彩色濾光層122上,以完成半導體元件100。 In operation 304, a color filter layer 122 is formed on the second surface 114a of the semiconductor layer 110a. The color filter layer 122 includes a plurality of color filters arranged in an array, such as a plurality of red filters, a plurality of green filters, and a plurality of blue filters. In some embodiments, as shown in FIG. 3D, a dielectric layer 118 is first formed using a thermal oxidation technique or a deposition technique to cover the second surface 114a of the semiconductor layer 110a and fill between any adjacent ones of the microstructures 116a. The gap is formed to form a color filter layer 122 on the dielectric layer 118. The dielectric layer 118 has a flat surface 120 formed by a planarization process, and a color filter layer 122 is formed on the flat surface 120. In some embodiments, a microlens layer 124 comprising a plurality of microlenses 126 is selectively formed on the color filter layer 122 to complete the semiconductor device 100.
第5A圖至第5F圖係繪示依照各實施方式之一種半導體元件之製造方法之各個中間階段的剖面示意圖。如第5A圖所示,提供第一基材400。第一基材400具有第一表面406與第二表面408,其中第一表面406與第二表面408為第一基材400之相對二側。第一基材400可由單層結構所構成。在一些實施例中,如第5A圖所示,第一基材400包含第一層402與第二層404堆疊在第一層402上。第一層402與第二層404由單晶半導體材料或化合物半導體 材料所構成。在一些例子中,使用矽、鍺、磊晶矽、磊晶鍺或玻璃來作為形成第一層402與第二層404之材料。第一層402與第二層404可由不同材料所形成,例如,第一層402可由矽所形成,第二層404可由磊晶矽所形成。在特定例子中,第一層402與第二層404可由相同材料所形成。 5A to 5F are schematic cross-sectional views showing respective intermediate stages of a method of fabricating a semiconductor device in accordance with various embodiments. As shown in FIG. 5A, a first substrate 400 is provided. The first substrate 400 has a first surface 406 and a second surface 408, wherein the first surface 406 and the second surface 408 are opposite sides of the first substrate 400. The first substrate 400 may be composed of a single layer structure. In some embodiments, as shown in FIG. 5A, the first substrate 400 includes a first layer 402 and a second layer 404 stacked on the first layer 402. The first layer 402 and the second layer 404 are made of a single crystal semiconductor material or a compound semiconductor Made up of materials. In some examples, germanium, germanium, epitaxial germanium, epitaxial germanium, or glass is used as the material for forming the first layer 402 and the second layer 404. The first layer 402 and the second layer 404 may be formed of different materials, for example, the first layer 402 may be formed of tantalum and the second layer 404 may be formed of an epitaxial germanium. In a particular example, first layer 402 and second layer 404 can be formed from the same material.
如第5C圖所示,形成微結構410於第一基材400之第二表面408上,其中這些微結構410形成於第二層404上。在一些實施例中,如第5B圖與第5C圖所示,利用微影製程與蝕刻製程進行形成微結構410之操作,其中藉由透過光罩500而朝第二表面408投射光502的方式來進行微影製程,再根據微影製程的定義於第二表面408上進行蝕刻製程,以移除第一基材400之第二層404的一部分,而在第二表面408上形成微結構410。在一些例子中,利用乾式蝕刻技術或化學蝕刻技術進行蝕刻製程。在特定例子中,利用雷射移除技術形成這些微結構410。 As shown in FIG. 5C, microstructures 410 are formed on second surface 408 of first substrate 400, wherein the microstructures 410 are formed on second layer 404. In some embodiments, as shown in FIGS. 5B and 5C, the operation of forming the microstructures 410 is performed by a lithography process and an etch process in which the light 502 is projected toward the second surface 408 by the reticle 500. The lithography process is performed, and an etching process is performed on the second surface 408 according to the definition of the lithography process to remove a portion of the second layer 404 of the first substrate 400, and a microstructure 410 is formed on the second surface 408. . In some examples, the etching process is performed using a dry etch technique or a chemical etch technique. In a particular example, these microstructures 410 are formed using a laser removal technique.
在一些例子中,每個微結構410可形成有三角形、梯形或弧形之剖面形狀,弧形可例如為半圓形或半橢圓形。微結構410可規則排列。在一些例子中,微結構410不規則排列。在一些實施例中,請再次參照第5C圖,進行形成微結構410之操作,以使微結構410之任相鄰二者彼此鄰接。請同時參照第2B圖與第5C圖,微結構410之排列可類似於微結構116b,其中可使微結構410之任相鄰二者彼此分離。類似於第2A圖所示之微結構116a或第2B圖 所示之微結構116b,每個微結構410之高度可介於100λ與λ/100之間,且微結構410之任相鄰二者之間的間距可介於100λ與λ/100之間,其中λ代表入射光之波長。在特定例子中,每個微結構410之高度大於λ/2.5,且微結構410之任相鄰二者之間的間距大於λ/2。微結構410之安排與形狀可類似於第2A圖之微結構116a或第2B圖之微結構116b。 In some examples, each microstructure 410 can be formed with a triangular, trapezoidal or curved cross-sectional shape, which can be, for example, semi-circular or semi-elliptical. The microstructures 410 can be arranged regularly. In some examples, the microstructures 410 are arranged irregularly. In some embodiments, referring again to FIG. 5C, the operation of forming microstructures 410 is performed such that any adjacent ones of microstructures 410 are adjacent to each other. Referring also to FIGS. 2B and 5C, the arrangement of microstructures 410 can be similar to microstructures 116b, wherein any adjacent ones of microstructures 410 can be separated from one another. Similar to the microstructure 116a or 2B shown in Figure 2A In the illustrated microstructures 116b, the height of each of the microstructures 410 may be between 100λ and λ/100, and the spacing between any adjacent ones of the microstructures 410 may be between 100λ and λ/100, where λ Represents the wavelength of incident light. In a particular example, the height of each microstructure 410 is greater than λ/2.5, and the spacing between any adjacent ones of the microstructures 410 is greater than λ/2. The arrangement and shape of the microstructures 410 can be similar to the microstructures 116a of FIG. 2A or the microstructures 116b of FIG. 2B.
在微結構410形成於第一基材400之第二表面408上之後,形成介電層414,以覆蓋第一基材400之第二表面408,並填充微結構410之任相鄰二者之間的間隙,如第5C圖所示。在一些例子中,利用熱氧化技術或化學氣相沉積技術,進行形成介電層414之操作。舉例而言,介電層414由氧化物,例如氧化矽所構成。選擇性地,對介電層414進行平坦化操作,如此介電層414之表面416係平坦的。可利用化學機械研磨技術進行平坦化操作。 After the microstructures 410 are formed on the second surface 408 of the first substrate 400, a dielectric layer 414 is formed to cover the second surface 408 of the first substrate 400 and fill between any adjacent ones of the microstructures 410. The gap is shown in Figure 5C. In some examples, the operation of forming dielectric layer 414 is performed using thermal oxidation techniques or chemical vapor deposition techniques. For example, dielectric layer 414 is comprised of an oxide, such as hafnium oxide. Optionally, the dielectric layer 414 is planarized such that the surface 416 of the dielectric layer 414 is flat. The planarization operation can be performed using chemical mechanical polishing techniques.
於形成介電層414之操作之後,提供第二基材418,並將第二基材418接合至介電層414之表面416。將介電層414之表面416平坦化成平坦,因此第二基材418可順利且穩固地與介電層414之表面416接合。在一些例子中,第二基材418由玻璃或半導體材料,例如矽與鍺所形成。選擇性地,於接合操作後,利用例如化學機械研磨技術或蝕刻技術,對第一基材400之第一表面406進行薄化操作,以移除部分之第一基材400。在特定例子中,如第5C圖所示,移除第一基材400之第一層402,以暴露出第 二層404之表面412。 After the operation of forming the dielectric layer 414, a second substrate 418 is provided and the second substrate 418 is bonded to the surface 416 of the dielectric layer 414. The surface 416 of the dielectric layer 414 is planarized to be flat so that the second substrate 418 can smoothly and firmly engage the surface 416 of the dielectric layer 414. In some examples, the second substrate 418 is formed from a glass or semiconductor material, such as tantalum and niobium. Optionally, after the bonding operation, the first surface 406 of the first substrate 400 is thinned using, for example, a chemical mechanical polishing technique or an etching technique to remove portions of the first substrate 400. In a specific example, as shown in FIG. 5C, the first layer 402 of the first substrate 400 is removed to expose the first The surface 412 of the second layer 404.
接著,如第5D圖所示,形成元件層420於第一基材400之第二層404的表面412上。元件層420包含數個感光區422。在一些例子中,每個感光區422包含一像素,此像素包含一影像感測元件,其中影像感測元件包含光電二極體與其它元件。 Next, as shown in FIG. 5D, the element layer 420 is formed on the surface 412 of the second layer 404 of the first substrate 400. The element layer 420 includes a plurality of photosensitive regions 422. In some examples, each photosensitive region 422 includes a pixel that includes an image sensing component, wherein the image sensing component includes a photodiode and other components.
在一些實施例中,於形成元件層420後,提供第三基材428,接著將第三基材428接合至元件層420。舉例而言,第三基材428由玻璃或半導體材料,例如矽與鍺所形成。在一些實施例中,如第5E圖所示,於第三基材428之接合操作之前,形成鈍化層424,以覆蓋元件層420。鈍化層424可例如由氧化矽、氮化矽或氮氧化矽所構成。在一些例子中,對鈍化層424進行平坦化操作,因此鈍化層424之表面426可為平坦。可利用化學機械研磨技術進行平坦化操作。由於鈍化層424之表面426被平坦化而呈平坦,因此可將第三基材428順利且穩固地接合至鈍化層424之表面426。 In some embodiments, after forming the component layer 420, a third substrate 428 is provided, followed by bonding the third substrate 428 to the component layer 420. For example, the third substrate 428 is formed from a glass or semiconductor material, such as tantalum and niobium. In some embodiments, as shown in FIG. 5E, a passivation layer 424 is formed to cover the element layer 420 prior to the bonding operation of the third substrate 428. The passivation layer 424 can be composed, for example, of hafnium oxide, tantalum nitride, or hafnium oxynitride. In some examples, the passivation layer 424 is planarized so that the surface 426 of the passivation layer 424 can be flat. The planarization operation can be performed using chemical mechanical polishing techniques. Since the surface 426 of the passivation layer 424 is flattened to be flat, the third substrate 428 can be smoothly and firmly bonded to the surface 426 of the passivation layer 424.
於第三基材428之接合操作後,利用例如化學機械研磨技術及/或蝕刻技術,在第二基材418上進行薄化操作,以依序移除第二基材418與介電層414。於薄化操作後,暴露出第一基材400之第二表面408上的微結構410,如第5E圖所示。 After the bonding operation of the third substrate 428, a thinning operation is performed on the second substrate 418 by, for example, chemical mechanical polishing techniques and/or etching techniques to sequentially remove the second substrate 418 and the dielectric layer 414. . After the thinning operation, the microstructures 410 on the second surface 408 of the first substrate 400 are exposed, as shown in Figure 5E.
在一些實施例中,暴露出微結構410之後,形成彩色濾光層434於第一基材400之第二表面408上。彩色濾 光層434包含許多排成一陣列之彩色濾光器,例如多個紅色濾光器、多個綠色濾光器與多個藍色濾光器。在一些實施例中,如第5F圖所示,暴露出微結構410之後,先形成介電層430,以覆蓋第一基材400之第二表面408,並填充微結構410之任相鄰二者之間的間隙,接著形成彩色濾光層434於介電層430上。介電層430可由氧化矽、氮化矽或氮氧化矽所構成。介電層430具有平坦之表面432,且彩色濾光層434形成在平坦之表面432上。可利用熱氧化技術或沉積技術,例如化學氣相沉積技術,來形成介電層430。選擇性地,在介電層430形成後,對介電層430進行平坦化製程,因此介電層430之表面432係平坦的。可利用化學機械研磨技術進行平坦化製程。 In some embodiments, after the microstructures 410 are exposed, a color filter layer 434 is formed on the second surface 408 of the first substrate 400. Color filter Light layer 434 includes a plurality of color filters arranged in an array, such as a plurality of red filters, a plurality of green filters, and a plurality of blue filters. In some embodiments, as shown in FIG. 5F, after exposing the microstructures 410, a dielectric layer 430 is formed to cover the second surface 408 of the first substrate 400 and fill any adjacent ones of the microstructures 410. The gap between them is followed by formation of a color filter layer 434 on the dielectric layer 430. The dielectric layer 430 may be composed of tantalum oxide, tantalum nitride or hafnium oxynitride. Dielectric layer 430 has a flat surface 432 and color filter layer 434 is formed on planar surface 432. Dielectric layer 430 can be formed using thermal oxidation techniques or deposition techniques, such as chemical vapor deposition techniques. Optionally, after the dielectric layer 430 is formed, the dielectric layer 430 is planarized, and thus the surface 432 of the dielectric layer 430 is flat. The chemical mechanical polishing technique can be used for the planarization process.
在一些實施例中,再次如第5F圖所示,於彩色濾光層434形成後,形成包含數個微透鏡438之微透鏡層436於彩色濾光層434上,以完成半導體元件440。形成微透鏡438之操作係可根據微透鏡438之折射率、以及感光區422與微透鏡438之間的距離,而以各種排列與各種形狀形成微透鏡438。 In some embodiments, as shown in FIG. 5F, after the color filter layer 434 is formed, a microlens layer 436 including a plurality of microlenses 438 is formed on the color filter layer 434 to complete the semiconductor device 440. The operation of forming the microlens 438 may form the microlens 438 in various arrangements and various shapes depending on the refractive index of the microlens 438 and the distance between the photosensitive region 422 and the microlens 438.
請一併參照第6圖與第5A圖至第5F圖,第6圖係繪示依照各實施方式之一種半導體元件之製造方法的流程圖。此方法始於操作600,操作600提供第一基材400,第一基材400具有第一表面406以及與第一表面406相對之第二表面408。第一基材400可由單層結構所構成。在一些實施例中,如第5A圖所示,第一基材400包含第一層 402與第二層404堆疊在第一層402上。第一層402與第二層404可由不同材料所形成。在特定例子中,第一層402與第二層404可由相同材料所形成。 Referring to FIG. 6 and FIGS. 5A to 5F together, FIG. 6 is a flow chart showing a method of manufacturing a semiconductor device in accordance with various embodiments. The method begins at operation 600, which provides a first substrate 400 having a first surface 406 and a second surface 408 opposite the first surface 406. The first substrate 400 may be composed of a single layer structure. In some embodiments, as shown in FIG. 5A, the first substrate 400 includes a first layer 402 and second layer 404 are stacked on first layer 402. The first layer 402 and the second layer 404 can be formed from different materials. In a particular example, first layer 402 and second layer 404 can be formed from the same material.
在操作602中,如第5B圖與第5C圖所示,利用例如微影製程與蝕刻製程,形成微結構410於第一基材400之第二表面408上。在一些例子中,利用乾式蝕刻技術或化學蝕刻技術進行蝕刻製程。可利用雷射移除技術形成這些微結構410。可進行形成微結構410之操作來使每個微結構410具有三角形、梯形或弧形之剖面形狀,弧形可例如為半圓形或半橢圓形。微結構410可規則地形成。在一些例子中,微結構410不規則地形成。 In operation 602, as shown in FIGS. 5B and 5C, the microstructures 410 are formed on the second surface 408 of the first substrate 400 using, for example, a lithography process and an etch process. In some examples, the etching process is performed using a dry etch technique or a chemical etch technique. These microstructures 410 can be formed using laser removal techniques. The operation of forming the microstructures 410 can be performed such that each of the microstructures 410 has a triangular, trapezoidal or arcuate cross-sectional shape, which can be, for example, semi-circular or semi-elliptical. The microstructures 410 can be formed regularly. In some examples, microstructures 410 are formed irregularly.
在一些實施例中,進行形成微結構410之操作,以使微結構410之任相鄰二者彼此鄰接,如第2A圖所示之微結構116a般。如同第2B圖所示之微結構116b,可使微結構410之任相鄰二者彼此分離。在一些例子中,每個微結構410之高度介於100λ與λ/100之間,且微結構410之任相鄰二者之間的間距介於100λ與λ/100之間,其中λ代表入射光之波長。在特定例子中,每個微結構410之高度大於λ/2.5,且微結構410之任相鄰二者之間的間距大於λ/2。 In some embodiments, the operation of forming the microstructures 410 is performed such that any adjacent ones of the microstructures 410 are contiguous with each other, such as the microstructures 116a shown in FIG. 2A. As with the microstructure 116b shown in FIG. 2B, any adjacent ones of the microstructures 410 can be separated from each other. In some examples, the height of each microstructure 410 is between 100λ and λ/100, and the spacing between any adjacent ones of the microstructures 410 is between 100λ and λ/100, where λ represents incident light. wavelength. In a particular example, the height of each microstructure 410 is greater than λ/2.5, and the spacing between any adjacent ones of the microstructures 410 is greater than λ/2.
在操作604中,如第5C圖所示,形成介電層414,以覆蓋第一基材400之第二表面408。在一些例子中,利用熱氧化技術或化學氣相沉積技術,進行形成介電層414之操作。選擇性地,可利用例如化學機械研磨技術,對介電 層414進行平坦化操作,以形成具有平坦之表面416的介電層414。 In operation 604, as shown in FIG. 5C, a dielectric layer 414 is formed to cover the second surface 408 of the first substrate 400. In some examples, the operation of forming dielectric layer 414 is performed using thermal oxidation techniques or chemical vapor deposition techniques. Alternatively, for example, chemical mechanical polishing techniques can be used for dielectric Layer 414 is planarized to form a dielectric layer 414 having a flat surface 416.
在操作606中,再次如第5C圖所示,提供第二基材418,並將第二基材418接合至介電層414之表面416。在一些例子中,第二基材418由玻璃或半導體材料所形成。選擇性地,利用例如化學機械研磨技術或蝕刻技術,對第一基材400之第一表面406進行薄化操作,以移除部分之第一基材400。在特定例子中,移除第一基材400之第一層402,以暴露出第二層404之表面412。在操作608中,如第5D圖所示,形成元件層420於第一基材400之第二層404的表面412上。元件層420包含數個感光區422。每個感光區422可包含一像素。 In operation 606, again as shown in FIG. 5C, a second substrate 418 is provided and a second substrate 418 is bonded to the surface 416 of the dielectric layer 414. In some examples, the second substrate 418 is formed from a glass or semiconductor material. Optionally, the first surface 406 of the first substrate 400 is thinned using, for example, a chemical mechanical polishing technique or an etching technique to remove portions of the first substrate 400. In a particular example, the first layer 402 of the first substrate 400 is removed to expose the surface 412 of the second layer 404. In operation 608, element layer 420 is formed on surface 412 of second layer 404 of first substrate 400 as shown in FIG. 5D. The element layer 420 includes a plurality of photosensitive regions 422. Each photosensitive region 422 can include one pixel.
在操作610中,提供第三基材428,並將第三基材428接合至元件層420。第三基材428可由玻璃或半導體材料,例如矽與鍺所形成。在一些實施例中,如第5E圖所示,形成鈍化層424,以覆蓋元件層420。在一些例子中,利用例如化學機械研磨技術平坦化鈍化層424,因此鈍化層424之表面426係平坦的。在操作612中,利用例如化學機械研磨技術及/或蝕刻技術,在第二基材418上進行薄化操作,以依序移除第二基材418與介電層414,而暴露出第一基材400之第二表面408與微結構410。 In operation 610, a third substrate 428 is provided and a third substrate 428 is bonded to the component layer 420. The third substrate 428 can be formed from a glass or semiconductor material such as tantalum and niobium. In some embodiments, as shown in FIG. 5E, a passivation layer 424 is formed to cover the element layer 420. In some examples, passivation layer 424 is planarized using, for example, a chemical mechanical polishing technique such that surface 426 of passivation layer 424 is flat. In operation 612, a thinning operation is performed on the second substrate 418 by, for example, chemical mechanical polishing techniques and/or etching techniques to sequentially remove the second substrate 418 and the dielectric layer 414 to expose the first The second surface 408 of the substrate 400 is associated with the microstructures 410.
在操作614中,形成彩色濾光層434於第一基材400之第二表面408上。彩色濾光層434包含許多排成一陣列之彩色濾光器,例如多個紅色濾光器、多個綠色濾光器 與多個藍色濾光器。在一些實施例中,如第5F圖所示,先形成介電層430,以覆蓋第一基材400之第二表面408,接著形成彩色濾光層434於介電層430上。在特定例子中,介電層430具有平坦之表面432,且彩色濾光層434形成在平坦之表面432上。選擇性地,利用例如化學機械研磨技術,對介電層430進行平坦化製程。在一些實施例中,形成包含數個微透鏡438之微透鏡層436於彩色濾光層434上,以完成半導體元件440。 In operation 614, a color filter layer 434 is formed on the second surface 408 of the first substrate 400. The color filter layer 434 includes a plurality of color filters arranged in an array, such as a plurality of red filters and a plurality of green filters. With multiple blue filters. In some embodiments, as shown in FIG. 5F, a dielectric layer 430 is formed to cover the second surface 408 of the first substrate 400, and then a color filter layer 434 is formed on the dielectric layer 430. In a particular example, dielectric layer 430 has a flat surface 432 and color filter layer 434 is formed on planar surface 432. Optionally, the dielectric layer 430 is planarized using, for example, a chemical mechanical polishing technique. In some embodiments, a microlens layer 436 comprising a plurality of microlenses 438 is formed on color filter layer 434 to complete semiconductor component 440.
依照一實施例,本揭露揭示一種半導體元件,其操作來感測入射光。此半導體元件包含基材、元件層、半導體層以及彩色濾光層。元件層設於基材上,且包含數個感光區。半導體層位於元件層之上方,且具有第一表面以及相對於第一表面之第二表面。第一表面鄰近元件層。半導體層包含數個微結構位於第二表面上。彩色濾光層設於半導體層之第二表面上。 In accordance with an embodiment, the present disclosure discloses a semiconductor component that operates to sense incident light. The semiconductor device includes a substrate, an element layer, a semiconductor layer, and a color filter layer. The component layer is disposed on the substrate and includes a plurality of photosensitive regions. The semiconductor layer is above the component layer and has a first surface and a second surface opposite the first surface. The first surface is adjacent to the component layer. The semiconductor layer includes a plurality of microstructures on the second surface. The color filter layer is disposed on the second surface of the semiconductor layer.
依照另一實施例,本揭露揭示一種半導體元件之製造方法。在此方法中,提供基材,且依序形成元件層與半導體層在基材之表面上。半導體層具有第一表面以及與第一表面相對之第二表面,第一表面鄰近元件層。形成數個微結構於半導體層之第二表面上。形成彩色濾光層於半導體層之第二表面上。 According to another embodiment, the present disclosure discloses a method of fabricating a semiconductor device. In this method, a substrate is provided, and the element layer and the semiconductor layer are sequentially formed on the surface of the substrate. The semiconductor layer has a first surface and a second surface opposite the first surface, the first surface being adjacent to the element layer. A plurality of microstructures are formed on the second surface of the semiconductor layer. A color filter layer is formed on the second surface of the semiconductor layer.
依照又一實施例,本揭露揭示一種半導體元件之製造方法。在此方法中,提供具有第一表面以及與第一表面相對之第二表面的第一基材。形成數個微結構於第一基材 之第二表面上。形成介電層覆蓋在第一基材之第二表面上。將第二基材接合至介電層。形成元件層於第一基材之第一表面上。將第三基材接合至元件層。移除第二基材與介電層以暴露出第一基材之第二表面。形成彩色濾光層於第一基材之第二表面上。 According to still another embodiment, the present disclosure discloses a method of fabricating a semiconductor device. In this method, a first substrate having a first surface and a second surface opposite the first surface is provided. Forming a plurality of microstructures on the first substrate On the second surface. A dielectric layer is formed overlying the second surface of the first substrate. A second substrate is bonded to the dielectric layer. Forming a component layer on the first surface of the first substrate. A third substrate is bonded to the element layer. The second substrate and the dielectric layer are removed to expose the second surface of the first substrate. A color filter layer is formed on the second surface of the first substrate.
上述已概述數個實施例的特徵,因此熟習此技藝者可更了解本揭露之態樣。熟習此技藝者應了解到,其可輕易地利用本揭露做為基礎,來設計或潤飾其他製程與結構,以實現與在此所介紹之實施例相同之目的及/或達到相同的優點。熟習此技藝者也應了解到,這類對等架構並未脫離本揭露之精神和範圍,且熟習此技藝者可在不脫離本揭露之精神和範圍下,在此進行各種之更動、取代與替代。 The features of several embodiments have been summarized above, and those skilled in the art will appreciate the aspects of the disclosure. It will be appreciated by those skilled in the art that the present disclosure can be readily utilized to design or refine other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. It is also to be understood by those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the disclosure. Alternative.
100‧‧‧半導體元件 100‧‧‧Semiconductor components
102‧‧‧基材 102‧‧‧Substrate
104‧‧‧表面 104‧‧‧ Surface
106‧‧‧元件層 106‧‧‧Component layer
108‧‧‧感光區 108‧‧‧Photosensitive area
110a‧‧‧半導體層 110a‧‧‧Semiconductor layer
112‧‧‧第一表面 112‧‧‧ first surface
114a‧‧‧第二表面 114a‧‧‧second surface
116a‧‧‧微結構 116a‧‧‧Microstructure
118‧‧‧介電層 118‧‧‧ dielectric layer
120‧‧‧表面 120‧‧‧ surface
122‧‧‧彩色濾光層 122‧‧‧Color filter layer
124‧‧‧微透鏡層 124‧‧‧Microlens layer
126‧‧‧微透鏡 126‧‧‧Microlens
128‧‧‧入射光 128‧‧‧ incident light
130‧‧‧正面 130‧‧‧ positive
132‧‧‧背面 132‧‧‧Back
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