TWI555025B - Forced-bias method in sub-block erase - Google Patents

Description

Forced bias method for erasing sub-blocks

This invention relates to a high density memory device, and more particularly to the operation of a stacked memory structure.

As the critical dimensions of the components of the integrated circuit shrink toward the limits of manufacturing technology, designers are looking for techniques that can achieve larger storage capacities and achieve smaller cost per bit. Various technologies pursue a single chip containing a plurality of memory cells. The operation of three-dimensional NAND memory with multi-layer memory cells includes read, write, and erase.

The erase action is usually performed on a number of blocks of the memory cell. High-density NAND (especially high-density 3D NAND) memory cells are usually quite large. When users only need to change the three-dimensional anti-gate memory When a small part of the code is formed, it is inconvenient. As the density of the three-dimensional anti-gate memory increases, the number of layers stacked is not The increase in the number of blocks causes the size of the block to become larger and larger, which affects the convenience of the erasing action.

Therefore, there is an urgent need in the industry for an efficient and convenient three-dimensional anti-gate memory erasing technique.

The present invention relates to a method of sub-block erasing of a NAND array. A sub-block may include one half of a block of memory cells, or other portions of a block. The term "block" refers to a set of inverse gate trains that operate simultaneously during the erase operation. In the erase operation, all of these reverse gate trains are typically connected to a reference voltage through a common source line. This erase operation is responsive to a shared control signal, which is commonly referred to as a ground select line (GSL). In addition, all of the reverse gate series of a block are connected to a common set of word lines. The bit lines of a block can be independently connected to the anti-gate string to receive a control signal (commonly referred to as a serial selection signal) of the serial selection line. In a block erase operation, all of the serial select signals of the selected block operate simultaneously, and all blocks are erased. The blocks are usually placed in the integrated circuit, so adjacent blocks can be insulated from each other.

The method for operating a reverse gate array is described below. The anti-gate array includes a plurality of blocks composed of memory cells. This method includes several sub-block erase operations. This method is applicable to single-layer reverse gate arrays and multilayer, or three-dimensional inverse gate arrays.

In the method described here, a sub-block can be erased. A subblock includes more than one unit. This erase method can erase less than one block of the memory sub-array and increase the flexibility of the operation.

A block may be logically or physically divided into two or more sub-blocks to perform sub-block erase procedures using the bias arrangement of the word lines. The ground selection signal and all serial selection signals are used to select the block. The word line can be biased to the selected block to erase the sub-block and suppress the remainder of the block from being erased. One or more word lines can operate in a boundary mode. The boundary mode is different from the inhibit mode, which is used to assist the erasure of sub-blocks.

In the method of operation described herein, the channel side erase voltage is applied to the channel line of the selected block and the gate sequence through the first series select switch. The word line side erase voltage is applied to the selected subset of the selected blocks to induce the pinning action of the memory cells coupled to the selected subset. The selected subset may include a word line side suppression voltage applied to the unselected subset of the word lines to suppress the pinning action coupled to the unselected subset. The unselected subset can include more than one word line.

A first bias voltage can be applied to the first boundary word line of the word line to induce a first boundary condition between the selected subset of the word line and the unselected subset of the word line. A second bias voltage can be applied to the second boundary word line of the word line to induce a second boundary condition between the unselected subsets of the first boundary character county level word line. In an embodiment, the first bias voltage may be between the word line side erase voltage and the second bias voltage. The word line side suppression voltage is higher than the second bias voltage.

The first boundary condition can include a number of electric fields. The electric fields are coupled to a suppression of a hot carrier injection of such memory cells of the selected subset. The hot carrier injection is induced by a difference between a first channel potential and a second channel potential. The first channel potential is located at the channel lines of the memory cells coupled to the selected subset. The second channel potential is located at the channel lines of the memory cells coupled to the unselected subset.

A wipe operation can be performed correctly. The memory cell coupled to the selected subset has a first threshold voltage distribution, and the uncoupled memory cell has a second threshold voltage distribution. The first threshold voltage distribution does not overlap with the second threshold voltage distribution. The erase operation includes one or more erase and verify cycles including applying a first bias voltage and a second bias voltage during a word line side erase voltage application period and a word line side suppression voltage application period.

Before the voltage is erased on the side of the word line, the data stored in the memory cell coupled between the first boundary word line and the second boundary word line is moved from the selected block to another block of the memory cell. After the voltage is erased on the application word line side, the data stored in the memory cells coupled to the first boundary word line and the second boundary word line are respectively moved back to the selected block.

A first bias voltage may be applied to one of the third boundary word lines of the word line to induce a first boundary condition. The third boundary word line is adjacent to one side of the selected subset of the first boundary word line. The second bias voltage may have been applied to one of the fourth boundary word lines of the word line (fourth boundary word) Line) to induce a second boundary condition. The fourth boundary word line is adjacent to one side of the selected subset of the third boundary word line relative to the word line.

A number of word lines can be selected as selected subsets of word lines.

In the selected block, in response to erasing a command of a memory cell coupled to the selected subset of the word line, applying a channel side erase voltage, applying a word line side erase voltage, and applying The word line side suppresses the action of the voltage. In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100‧‧‧ integrated circuit

110‧‧‧Anti-gate flash memory array

111‧‧‧ column decoder

112, 325-1 WL, 325-N WL, WL0, WL1, WL29, WL32, WL33, WL60, WL61, WL(i+1), WL(i-2)‧‧‧ character line

113‧‧‧Page Buffer

114, BL-0, BL-1, BL-2, BL-3, GBL _n+1 , GBL _n , GBL _n-1 ‧‧‧ global bit line

115‧‧‧ busbar

116‧‧‧ row decoder

117‧‧‧ data bus

118‧‧‧Pressure Arrangement Unit

119‧‧‧ state machine

123‧‧‧ data input line

124‧‧‧Other circuits

200, 202, 204‧‧‧ vertical wiring

210, 212, 214, 309, 319, 530, 531, 532, 533, 540, 541‧‧‧ tandem selection switch

220, 222, 224, 226‧ ‧ memory cells

230, 232, 234‧‧‧ pads

240, 242, 244‧‧ ‧ branch lines

258‧‧‧Group Decoder

260‧‧‧Ground selection switch

261‧‧‧ column decoder

263‧‧‧Page Buffer

269‧‧‧ state machine

302, 303, 304, 305, 312, 313, 314, 315‧‧‧ channel lines

302B, 303B, 304B, 305B, 312A, 313A, 314A, 315A‧‧‧ ladder pads

326, 327, GSL, GSL (even), GSL (odd) ‧ ‧ grounding selection line

328‧‧‧ source line

411, 412, BL ₁₁ , BL ₂₁ , BL ₃₁ ‧‧‧ channel lines

511‧‧‧First Global Character Line Driver

511g‧‧‧first global word line

512‧‧‧Second universal word line driver

512g‧‧‧first global word line

513‧‧‧third word line driver

513g‧‧‧third word global character line

514‧‧‧ fourth character line driver

514g‧‧‧fourth global character line

520, 521‧‧‧ common source line

551‧‧‧First subset

559‧‧‧ second subset

560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571‧‧‧ area word line drivers

580‧‧‧ area word line decoder

585‧‧‧Regional word line

590‧‧‧Global character line decoder

595‧‧‧Connecting parts

710, 720, 730, 740, 750‧‧‧ process steps

CSL‧‧‧Common source line

ML1‧‧‧ first metal layer

ML2‧‧‧ second metal layer

ML3‧‧‧ third metal layer

SSL _n-1 , SSL _n , SSL _n+1 ‧‧‧ tandem selection line

Vbl, V _BL ‧‧‧ channel side erase voltage

V _{bnd1 ‧‧‧first} bias

V _{bnd2 ‧‧‧second} bias

V _CSL ‧‧‧Source side voltage

V _ers ‧‧‧ character line side erase voltage

V _GSL ‧‧‧ Grounding selection switch voltage

V _inhibit ‧‧‧ character line side suppression voltage

V _SSL ‧‧‧voltage of serial selector switch

WL (bnd1)‧‧‧ first boundary character line

WL (bnd2)‧‧‧second boundary character line

WL (bnd3) ‧‧‧ third boundary character line

WL (bnd4)‧‧‧ fourth boundary character line

Figure 1 is a simplified block diagram of an integrated circuit.

Figure 2 is a schematic illustration of one portion of a three-dimensional anti-gate flash memory that can be used in a device similar to that of Figure 1.

FIG. 3 illustrates a three-dimensional vertical gate (VG) and gate flash memory array structure including an even block and an odd block.

Figure 4 is a wiring diagram of the three-dimensional anti-gate flash memory array structure of Figure 3.

Figure 5 is a diagram showing the X-Y plan view of the inverse of the memory cell block connected to the area of the three-dimensional memory and the global word line driver.

Figure 6 is a timing diagram showing the execution of sub-block erase using the circuit of Figure 5.

Figure 7 is a flow chart showing the sub-block erase operation.

Figure 8 is a diagram showing the threshold voltage distribution of the memory cells of the selected block after the sub-block erase operation.

FIG. 9 is a diagram showing a threshold voltage distribution diagram of a memory cell coupled to the selected subset and adjacent to the first boundary word line and the third boundary word line after the sub-block erase operation.

The embodiments of the present invention are described in detail below with reference to the drawings. The present invention is not limited to the specific structures and methods disclosed in the embodiments. The invention can be implemented by other features, component methods, or other embodiments. The preferred embodiments are merely illustrative of the invention and are not intended to limit the scope of the invention. The scope of protection of the present invention is still subject to the scope of the patent application. Those of ordinary skill in the art to which the present invention pertains will appreciate that the recited content includes equivalent variations thereof. Also, in the different embodiments, like elements are recited in the like.

FIG. 1 is a simplified block diagram of an integrated circuit 100. The integrated circuit 100 includes a NAND flash memory array 110. In some embodiments, the inverse gate flash memory array 110 is a three-dimensional memory (3D memory) of a multi-layer memory cell. The array can include a plurality of blocks composed of a plurality of memory cells. A block of memory cells can include a number of NAND strings. The reverse gate train includes a channel line between the first string select switch and the second string select switch. The inverse gate trains share a set of word lines between the first string select switch and the second string select switch.

A row decoder 111 is coupled to a plurality of word lines 112. The word lines are arranged along the sequence of the anti-gate flash memory array 110. The column decoder can include a set of local word line drivers. The area word line driver drives one of the memory cells to select some of the word lines corresponding to the selected block. The area word line driver may include a first subset, a second subset, a first boundary word line driver, and a second boundary word line. Second boundary word line driver. The first subset of regional word line drivers drives a first subset of one of the word lines. A second subset of the regional word line drivers drives a second subset of word lines. The first boundary word line driver drives a first boundary word line of the word line. The first boundary word line is located between the first subset and the second subset of the word line. The second boundary word line driver drives a second boundary word line. The second boundary word line is between the first boundary word line and the second subset of the word lines.

The memory includes a set of global word lines. The global character line includes a plurality of first global word lines, a plurality of second global word lines, a third global word line, and a first global word line Fourth global word line. The first global word line is coupled to the first subset of the regional word line drivers. The second global word line is coupled to the second subset of the regional word line drivers. The third global word line is coupled to the first boundary word line driver. The fourth global word line is coupled to the second boundary word line driver.

A column decoder 116 is coupled to a set of page buffers 113 by a data bus 117. The global bit line 114 is coupled to the page buffer 113 and channel lines (not shown) arranged along the rows of the anti-gate flash memory array 110. The address is provided by a bus 115 to a row decoder 116 and a row decoder 111. The data is input from other circuitry 124 by means of a data-in line 123. The other circuit 124 includes, for example, an input/output port on the integrated circuit. The integrated circuit is, for example, a combination of a general purpose processor, a special purpose application circuit, or a system-on-a-chip module that the gate flash memory array 110 can support. The data is supplied to the input/output port or to the internal or external destination of the integrated circuit 100 via the data input line 123.

The controller of this embodiment is, for example, a state machine 119. The state machine 119 is coupled to a plurality of blocks of the memory cell and provides various signals to control the bias arrangement supply voltage. The bias voltage is generated or provided by a voltage supply or bias arrangement supply voltage 118 to effect various operations of the data described herein for the array. These operations include programming, block erase, sub-block erase, and read. The controller can use conventional special-purpose logic (special-purpose logic) Circuitry) to achieve. In another embodiment, the controller includes a general-purpose processor that can be employed in the same integrated circuit and that executes a computer program to control the operation of the device. In another embodiment, the controller can be implemented using a combination of special purpose logic circuitry and a general purpose processor.

The controller can include logic to perform sub-block erase operations. For example, the controller may include a logic circuit that biases a sub-block of the memory cell to provide a negative FN (Negative Fowler-Nordheim tunneling (-FNtunneling)) to inject the hole into the selected sub-block. The charge storage structure of the memory cell. Thereby, the threshold voltages can be lowered, at least for the memory cells that do not have a low threshold voltage in the sub-blocks to lower their threshold voltage.

In an embodiment, the controller may include logic circuits for applying a channel-side erase voltage to the channel line through the first series selection switch in the selected block; The selection block applies a word line-side erase voltage to a first subset of the word lines for coupling to the first subset of memory cells to induce a tunneling effect (tunneling) And applying a word line-side inhibit voltage to the second subset of the word line for the selected block to enable the memory cell suppression coupled to the second subset Wear a sputum effect. The first subset of word lines can include at least one word line, and the second subset of word lines can include at least one word line.

The controller can include a logic circuit for the first of the word lines A first bias voltage is applied to the boundary word line to induce a first boundary condition between the first subset of the word line and the second boundary word line. The first boundary condition can include a number of electric fields. The electric fields are used to effect a suppression of hot carrier injection of memory cells coupled to the first subset of word lines. The hot carrier injection can be induced by the difference between the first channel potential and the second channel potential. The first channel potential is located in a channel line of a memory cell coupled to the first subset of word lines. The second channel potential is located in a channel line of the memory cell coupled to the second subset of word lines.

The controller may include a logic circuit for applying a second bias voltage to the second boundary word line of the word line for the first boundary word line and the second subset of the word line A second boundary condition is induced between them. The second boundary condition can include a number of electric fields. The electric fields are used to effect suppression of hot carrier injection of memory cells coupled to the second subset of word lines. The hot carrier injection can be induced by the difference between the first channel potential and the second channel potential. The first channel potential is located in a channel line of a memory cell coupled to the first subset of word lines. The second channel potential is located in a channel line of the memory cell coupled to the second subset of word lines.

The controller can include a logic circuit for selecting a plurality of word lines as selected subsets of the word lines. The controller may include a logic circuit for storing data of the memory cells coupled to the first boundary word line and the second boundary word line from the selected block before applying the word line side erase voltage Move to another block. The controller may include a logic circuit for respectively applying the data stored in the memory cells coupled to the first boundary word line and the second boundary word line to another area after applying the word line side erase voltage The block moves back to the selected block.

The controller can execute the following logic in response to a sub-block erase command: erasing the memory cells coupled to the first subset of the word lines in the selected block; The block applies a channel test erase voltage; applying a word line side erase voltage to the first subset of the word line in the selected block; and applying a word line side suppression voltage to the word line in the selected block The second subset. The sub-block erase command can be issued to the memory by an external source or an internal source. A number of word lines can be logically selected as the first subset of the word lines. For example, the sub-block erase command can include a parameter that indicates the size of the sub-block to be erased. This size may be the number of character lines (eg, 11) of the first subset of word lines, or the range of word lines (eg, the 10th character line to the 20th character line).

For the sake of clarity, "programming" herein refers to the operation of increasing the threshold voltage of a memory cell. The data stored in a programmed memory cell can be represented by a logical symbol "0" or a logical symbol "1". By "erasing" herein is meant the operation of reducing the threshold voltage of a memory cell. The data stored in an erased memory cell can be represented by the opposite of the programmed state, such as the logical symbol "1" or the logical symbol "0". A multi-bit cell can be programmed into multiple threshold levels and erased to a single lower threshold level. Furthermore, the term "write" in this paper is used to describe the change of the threshold voltage of a memory cell. Operation, which implicitly performs stylization and erasing, or performs a combination of stylization and erasure.

Figure 2 is a schematic illustration of one portion of a three-dimensional anti-gate flash memory that can be used in a device similar to that of Figure 1. In this example, the figure depicts a p-channel memory cell of a block, which may include a number of layers, representative of which are three layers of memory cells.

In one embodiment, a set of word lines in a block of memory cells can include 64 bit lines. In another embodiment, a set of word lines of a block of memory cells may include more or fewer word lines, such as 128 or 32 word lines. In the example illustrated in FIG. 2, a set of word lines includes a word line WL(i-2) and a second boundary word of the number 0 of the number 0 along the first direction. The bit line WL (bnd2), the first boundary word line WL (bnd1), the word line WL(i+1) of the number i+1, and the bit line of the number 63. The word line WL(i-2), the second boundary word line WL(bnd2), the first boundary word line WL(bnd1), and the word line WL(i+1) are shown in FIG. The first boundary word line WL(bnd1) may correspond to the word line of number i, and the second boundary word line WL(bnd2) may correspond to the word line of number i-1. A set of word lines can include a first subset and a second subset. The first subset includes the word line WL(i+1)~63 of the number i+1, and the second subset includes the word line of the number 0~ the word line WL of the number i-2 (i) -2). The indicator i is used to indicate that the first subset of word lines includes more than one word line, and the second subset of word lines includes more than one word line.

The word line includes a first boundary word line WL (bnd1) and a second side The boundary word line WL (bnd2). The first boundary word line WL(bnd1) is located between the first subset of the word line and the second subset of the word line, and the second boundary word line WL(bnd2) is located at the first boundary word line WL (bnd1) ) and between the second subset of the word line. The Sub-block erase operation using the first and second boundary word lines is described in FIGS. 5 and 6.

The word line is electrically connected to the column decoder 261. Column decoder 261 includes a global word line decoder 590 (shown in Figure 5) and an area word line decoder 580 (shown in Figure 5). The word line is coupled to the gates of the plurality of memory cells. The memory cells are arranged in series in a plurality of inverse gate trains. As shown in Fig. 2, each word line is vertically connected to the gates of the underlying memory cells.

The gate sequence has a channel line located in the multi-layer memory array. As shown in FIG. 2, the memory array is included in one of the channel lines BL ₃₁ in the third horizontal plane, one of the channel lines BL ₂₁ in the second horizontal plane, and one of the channel lines BL ₁₁ in the first horizontal plane. The memory cell has a dielectric charge trapping structure. The dielectric charge trapping structure is located between the corresponding word line and the channel line. In the description herein, it is simplified to have one memory cell with four memory cells. For example, the reverse gate sequence formed by the channel line BL ₃₁ includes a memory cell 220, a memory cell 222, a memory cell 224, and a memory cell 226. In a typical embodiment, an inverted gate train can include 16, 32, 64 or more memory cells connected to 16, 32, 64 or more word lines, respectively.

Comprising a serial select lines SSL _n-1, serial select lines SSL _n, serial select lines SSL _{n +} serial number of select lines are electrically connected to _a decoder group (group decoder) 258 (which may be part Column decoder 261). Group decoder 258 selects a set of strings. The serial select line is coupled to the gate of the first string select switch arranged at the first end of the memory cell and the gate train. As shown in Fig. 2, each of the series selection lines is vertically connected to the gates of the series selection switches of the respective different levels. For example, the tandem select line SSL _{n+1 is} connected to the tandem select switches 210, 212, 214 of the three levels.

The channel lines of a particular layer are selectively coupled to the extension of the particular layer by the corresponding serial selection switch. For example, the channel line of the third layer is selectively coupled to the branch line 240 by the corresponding serial selection switch. Likewise, the channel lines of the second layer are selectively coupled to the branch lines 242, and the channel lines of the first layer are selectively coupled to the branch lines 244.

The spurs of each layer include corresponding contact pads for connection to one of the vertical connectors of the global bit line. For example, the branch line 240 of the third layer is coupled to a global bit line GBL _n-1 through the pad 230 and the vertical line 200. The branch line 242 located on the second layer is coupled to a global bit line GBL _n through the pad 232 and the vertical line 202. The sub-line 244 on the third layer is coupled to a global bit line GBL _n+1 through pads 234 and vertical lines 204. The pads can be, for example, a stair step pad (such as the step pad 302B depicted in FIG. 3).

The global bit line GBL _n-1 , the global bit line GBL _n and the global bit line GBL _{n+1 are} coupled to an additional block (not shown) of the memory array and extend to the page buffer 263.

A ground select switch (sometimes referred to as a second tandem select switch) is located at the second end of the reverse gate train. For example, the ground selection switch 260 is arranged at the second end of the reverse gate sequence formed by the memory cell 220, the memory cell 222, the memory cell 224, and the memory cell 226. The ground selection line GSL is connected to the gate of the ground selection switch. The ground select line GSL is electrically coupled to the column decoder 261 to receive a bias during operation.

The ground selection switch is configured to selectively couple all of the blocks and the second end of the gate string to a common source line CSL. The common source line CSL receives a bias voltage from a bias circuit (such as the bias arrangement unit 118 in FIG. 1) during operation.

A plurality of blocks may be arranged in an array of blocks comprising a plurality of blocks and a plurality of blocks. Blocks in the same column can share the same set of word lines and ground selection lines GSL. Blocks in the same row can share the same set of global bit lines GBL _n-1 , global bit lines GBL _n and global bit lines GBL _n+1 . In this way, a three-dimensional decoding network is established. The selected memory cell of a portion of the page can be accessed using a word line. A set of global bit lines GBL _n-1 , GBL _n , GBL _n+1 and a string of select lines transmit data in parallel with the global bit lines GBL _n-1 , GBL _n , GBL _{n+1 of} each layer.

The memory array of Figure 2 includes a horizontally structured P-channel NAND string. In another three-dimensional arrangement, the inverse gate train can be a vertical architecture. In some embodiments, the anti-gate sequences are not connected, and there are no P-type endpoints between the memory cells. P-type endpoints are only used to connect bit line legs One side of the series selection switch 210 of 244 and one side of the ground selection switch 260 connected to the common source line CSL. The illustrated state machine 269 is used to control the memory array and the execution program, block erase, sub-block erase and read operations.

FIG. 3 illustrates a three-dimensional vertical gate (VG) and gate flash memory array structure including an even block and an odd block. The three-dimensional anti-gate flash memory array structure has been described in U.S. Patent No. 8,503,213, issued on Aug. 6, 2013, the disclosure of which is incorporated herein. The insulating material is removed in the figure to expose the remaining structure. For example, the insulating layer between the stacks of the gate trains is removed.

Another three-dimensional anti-gate structure can also be a vertical channel NAND array, which has been described in co-pending applications for US patent applications and applications filed May 21, 2014. U.S. Patent Application, December 24, 2014, the disclosure of which is incorporated herein by reference. The vertical channel reversal gate array also includes the blocks described herein, and the sub-block erase operation using biasing techniques described herein is also applicable.

The three-dimensional inverse gate flash memory array structure of the vertical channel and the vertical gate structure includes a stacked memory structure to form an array of dense memory cell blocks.

As illustrated in FIG. 3, the multilayer array of blocks is formed on an insulating layer and includes a plurality of word lines 325-1 WL~325-N WL. The stacked structure includes channel lines (eg, channel lines 312, 313, 314, 315 located in the first even page stack). One end of the stack structure of the channel lines 312, 313, 314, 315 terminates in stairstep pads 312A, 313A, Next to 314A, 315A, and through serial selector switch 319, ground select line 326, word line 325-1 WL to word line 325-N WL and ground select line 327, and the other end terminates at Next to the source line 328. The stacked structure of the channel lines 312, 313, 314, 315 is not connected to the step pads 302B, 303B, 304B, 305B. Therefore, the even blocks share the even ground selection line and all the bit lines, and the odd blocks share the odd ground selection lines and all the bit lines. In this example, the odd blocks and the even blocks are staggered to allow one of the N-type string widths to perform N/2 bit lines. Odd and even page blocks can perform an erase operation together due to the similarity of the alternate memory cell strings of the odd and even blocks. Other embodiments do not use alternating odd and even stack structures.

The stack structure of channel lines 302, 303, 304, 305 is located in a first odd page stack. One end of the stack structure of the channel lines 302, 303, 304, 305 terminates next to the step pads 302B, 303B, 304B, 305B and passes through the serial selection switch 309, the ground selection line 327, and the word line 325-N WL to Word line 325-1 WL and ground select line 326, while the other end terminates next to a source line (covered by other objects in the figure). The stack structure of the channel lines 302, 303, 304, 305 is not connected to the step pads 312A, 313A, 314A, 315A.

The serial selection line of the even memory page is connected to the ground selection line, and the number of the word line is incremented from 1 to N from the back to the front. In the sequence application of the string selection line to the ground selection line of the odd memory page, the label of the word line is decremented from N to 1 after going to.

Step pads 312A, 313A, 314A, 315A terminate the channel line Even pages (eg, channel lines 312, 313, 314, 315). For example, the landing pads 312A, 313A, 314A, 315A are electrically connected to different bit lines to connect the decoding circuit to select the level of the memory cells in the array. The landing pads 312A, 313A, 314A, 315A can be patterned simultaneously.

The landing pads 302B, 303B, 304B, 305B terminate the channel lines to odd pages, such as channel lines 302, 303, 304, 305. For example, the landing pads 302B, 303B, 304B, 305B are electrically connected to different bit lines to connect the decoding circuit to select the level of the memory cells in the array. The landing pads 302B, 303B, 304B, 305B can be patterned simultaneously.

The stacking structure of the channel lines is coupled to the step pads 312A, 313A, 314A, 315A at one end of the block or the step pads 302B, 303B, 304B, 305B at the other end of the block, but not both ends. The other blocks of the array block can be electrically insulated from other blocks by a separate stack of channel lines and ladder pads. In this method, if the control signals are separately decoded, the independent blocks can perform the erase operation separately.

Ground select line 326 and ground select line 327 are similar to word lines and form conformal with a plurality of stacked structures.

One end of each stack structure of the channel line terminates in a set of step pads, and the other end terminates in a source line. For example, one of the stacked structures of the channel lines 312, 313, 314, 315 terminates next to the landing pads 312A, 313A, 314A, 315A and ends at the source line 328. In the proximal side of the illustration, one end of each of the stacking layers terminates next to the step pads 302B, 303B, 304B, 305B. And the stack structure of each channel line terminates in a separate source line. In the distal side of the illustration, one end of each of the channel layers terminates next to the step pads 312A, 313A, 314A, 315A, and the stack structure of each channel line terminates in a separate source line, respectively.

The bit line and the tandem selection line are formed on the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3.

The memory cell is formed by a memory material between the channel line and the bit line 325-1 WL to the bit line 325-N WL. In the memory cell, a channel line (for example, channel line 313) serves as the channel area of the device. The serial select switches (e.g., tandem select switch 319, tandem select switch 309) may be patterned during the same step of forming word lines 325-1 WL~325-N WL. The memory material can be used as a gate dielectric for the serial selection switch. The serial select switch can be coupled to a decode circuit to select a particular stack structure in the array.

The most controversial part of the three-dimensional inverse gate memory is that the block size of the memory cell is usually large. As the density of the three-dimensional inverse gate memory increases, the number of pages and the number of layers also increases, resulting in a larger and slower speed specification for the block size used to perform the block erase. When the user only needs to change a small unit code stored in the sub-block of the memory cell in the three-dimensional anti-gate memory, the low-speed specification for performing the block erase reduces the performance of the three-dimensional anti-gate memory. .

In the present technology, a group of character lines sharing a plurality of inverse gate series can be divided into a first subset and a second subset. The memory cells coupled to one of the first subset and the second subset may be erased and coupled to the first subset and The memory cells of the other of the second subset are inhibited from tunneling. Therefore, only a portion of the memory cells (not all) are erased in a block erase process, so that there is a faster speed specification and an increase in the performance of the three-dimensional gate memory.

A sub-block erase command can be sent internally or externally to the memory. The number of word lines of the first subset of word lines can be selected logically. For example, the secondary block erase command may include a parameter that erases the size of the secondary block, which may be the number of word lines (eg, 11), or the range of word lines (eg, 10-20 words). Yuan line).

Figure 4 is a wiring diagram of the three-dimensional anti-gate flash memory array structure of Figure 3. The three-dimensional inverse gate flash memory array structure includes a plurality of memory cell blocks. One of the memory cells includes a plurality of inverse gate trains. The reverse gate train has channel lines located in the first series select switch (eg, the tandem select switch) and the second tandem select switch (eg, the ground select switch). The reverse gate sequence between the first string select switch and the second string select switch shares a set of word lines (eg, a 0th word line to a 63rd word line).

In the wiring diagram of FIG. 4, the stacked structure of the channel lines is a vertical strip of broken lines. The adjacent stack structures of the channel lines are alternately arranged in the number of coupled and odd columns. Each odd channel line (e.g., channel line 411) extends from the top bit line pad structure to the bottom odd bit source line. A stack structure of each even channel line (e.g., channel line 412) extends from the bit line pads at the bottom end to the even source lines at the top end.

The horizontal word line, the horizontal ground selection line GSL(even), and the horizontal ground selection line GSL(odd) are overlapped on the stack structure of the channel line. The serial selection switch also overlaps the stack structure of the channel lines. Odd serial selector switch overlaps each At the top of the one channel line stack structure, the even series select switch overlaps the bottom of every other channel line stack structure. In the two connection types, the serial selection switch controls the electrical connection between the stack structure of the channel lines and the ladder pads corresponding to the stacked structure.

As shown in FIG. 4, a set of word lines includes a word line WL0 to a word line WL29 extending along a first direction, a second boundary word line WL (bnd2), and a first boundary character. Line WL (bnd1), word line WL (32) to word line WL61, word line WL (bnd3), and word line WL (bnd4). Word line WL0, word line WL29, second boundary word line WL (bnd2), first boundary word line WL (bnd1), word line WL (32), word line WL61, third boundary character Line WL (bnd3) and fourth boundary word line WL (bnd4) are shown in FIG. A set of word lines includes a first subset (packet or word line WL32 to word line WL61) and a second subset (word line WL0 to word line WL29). The word line is located in column decoder 161 (shown in Figure 2) in electronic communication. The word line is connected to a gate of the memory cell arranged in series to oppose the gate string.

The set of character lines includes a first boundary word line (eg, a first boundary word line WL(bnd1)) between the first subset and the second subset, and is located at the first boundary A second boundary word line between the word line and the second subset (eg, a second boundary word line WL(bnd2)). The sub-block erase operation includes using the first boundary word line and the second boundary word line as described in FIGS. 5-6.

The vertically oriented tandem selection line (first metal layer ML1) is overlaid on Word line, ground selection line and serial selector switch. The horizontally oriented tandem selection line (second metal layer ML2) is overlaid on the tandem selection line (first metal layer ML1). Although the illustrated tandem selection line (second metal layer ML2) terminates in the tandem selection line (first metal layer ML1), the tandem selection line (second metal layer ML2) also extends further horizontally. The serial selection line (second metal layer ML2) carries a carry signal from the decoder, and the serial selection line (first metal layer ML1) receives the signal of the decoder to a specific serial selection switch to select a specific channel. Line stacking structure.

The odd and even source lines overlap the tandem selection line (first metal layer ML1). Furthermore, a bit line (a third metal layer not shown) is overlaid on the tandem selection line (second metal layer ML2) and connected to the top and bottom stair step contact structures. Through the stepped pad structure, the bit line selects a particular level of the channel layer.

A specific number of bit lines can be electrically connected to channel lines of different layers. The tandem select lines of a particular bit line can be biased to connect a particular bit line to a different layer of channel lines.

Under a block bias arrangement, a channel-side erase voltage (eg, channel side erase voltage Vbl) can be applied to the channel line through a first series select switch of a selected block. . A plurality of bit lines are connected to a plurality of channel lines of the memory cell block (eg, channel lines 411, 412). In the selected block, a first subset of word line-side erase voltages to word lines (eg, word lines WL32 through WL61) may be applied to induce coupling to the first The tunneling effect of the memory cells of the subset. In the selected block, a second subset of the word line-side inhibit voltage to the word line (eg, word lines WL0 to WL29) may be applied to inhibit coupling to the second sub- The tunneling effect of the memory cells of the collection.

In the word line, a first bias voltage may be applied to the first boundary word line (eg, the first boundary word line WL (bnd1)) to the first subset of the word line and the word line A first boundary condition is induced between the two subsets. In the word line, a second bias voltage may be applied to the second boundary word line (eg, the second boundary word line WL (bnd2)), which is already at the first boundary word line and the second sub-word line The set induces a second boundary condition.

In the three-dimensional structure of the vertical gate of FIG. 3, the block of the memory cell includes several pages of memory cells. For clarity of description, one page of this structure is defined as a stack of a plurality of channel lines selected by a single serial select line switch. Each channel layer is coupled to a corresponding bit line through a step pad. An array page can be defined as pages of different blocks of parallel operation. The definition of a page and the way in which a page is decoded can be changed with the architecture of a particular memory. The memory structure can include a page program buffer of N parallel coupled bit lines for use in the stylized and stylized verification steps described herein. In this embodiment, the memory cells are four layers, and four bit lines are provided per page. In other embodiments, there may be different numbers of layers. Another embodiment of the present invention may be eight levels of eight odd stacked structures and eight even stacked structures as a memory block, so a memory block includes 16 pages of eight bits.

The memory unit can be repeatedly added to the left and right to create a wider array. Column page. In a representative architecture in which N*8 megabytes are stored in a column of blocks, the integrated circuit may include 8000 global bit lines that overlap 1000 columns of side-by-side memory cells. Each block has 16 pages consisting of 512 N clouds memory cells coupled to 8 odd/even array global bit lines. Each column block can have 64 word lines and have a depth of 8 layers to form 256 memory cells for each odd/even block. Therefore, the 8-layer string selected by the tandem selection signal of a single block will induce 512 memory cells (64*8), which store the data of the bits. The 16 serial blocks have 8K memory cells.

Figure 5 is a diagram showing the X-Y plan view of the inverse of the memory cell block connected to the area of the three-dimensional memory and the global word line driver. The reverse gate sequence corresponds to the four pages of the memory cell: page 0, page 1, page 2, and page 3. The anti-gate sequence can be set in the same layer of the three-dimensional array as in FIG. 2, and share the even and odd ground selection lines of the even and odd pages. The reverse gate series have a separation from global bit lines (eg, global bit lines BL-0, BL-1, BL-2, BL-3) and even/odd common source lines 520, 521 The string selection line. The series is connected to the corresponding global bit lines BL-0~BL-3 by a first string select switch (e.g., tandem select switches 530, 531, 532, and 533). The string is connected to the odd or even common source line by a second string select switch (eg, tandem select switches 540, 541, also referred to as ground select switches). a plurality of reverse gate series of a memory block having a plurality of channel lines between the first serial selection switch and the second serial selection switch, and sharing between the first serial selection switch and the second serial Select one of the group of character lines (for example, word line WL0~word line WL28, ..., word line WL(i-2), second boundary word line WL(bnd2), first boundary word line WL(bnd1), word line) WL(i+1), ..., word line WL33~word line WL61, third boundary word line WL(bnd3), fourth boundary word line WL(bnd4)). The set of character lines includes a second subset of word lines WL0, WL1 WL WL28, . . . , WL(i-2) (eg, second subset 551) and a word line WL(i+1), ..., the first subset of WL33~WL60, WL61.

The memory includes a set of local word line drivers (LWLDs) (e.g., area word line drivers 560-571) that drive corresponding word lines of the memory cells. The set of regional word line drivers includes a first subset (eg, area word line drivers 566-569), a second subset (eg, area word line drivers 560-563), and a first boundary word line driver. (for example, the area word line driver 565) and the second boundary word line driver (for example, the area word line driver 564). A first subset of the regional word line drivers is used to drive a first subset of word lines (eg, the first subset 559). A second subset of the regional word line drivers is used to drive a second subset of the word lines (eg, the second subset 551). The first boundary word line driver is configured to drive a first boundary word line (eg, a first boundary word line WL(bnd1)) between the first subset and the second subset of the word line. The second boundary word line is used to drive a second boundary word line (eg, a second boundary word line WL (bnd2)) between the first boundary word line and the second subset.

The memory includes a set of global character lines. This set of global character lines includes a first global word line (eg, first global word line 511g), a second global word line (eg, a second global word line 512g), and a third global word line (third global word line) 513g) and a fourth global word line (eg, fourth global word line 514g). The first global word line is coupled to the first subset of the regional word line drivers. The second global word line is coupled to the second subset of the regional word line drivers. The third global word line is coupled to the first boundary word line driver. A fourth global word line driver is coupled to the second boundary word line driver.

The memory includes a first global word line driver (eg, a first global word line driver 511). The first global word line driver drives a first global word line 511g that provides N parallel global word line signals to the selected block by the regional word line decoder and the regional word line. The memory includes a second global word line driver (e.g., a second global word line driver 512). The second global word line driver drives a first global word line 512g that provides M parallel global word line signals to the selected block by the regional word line decoder and the regional word line.

Moreover, the memory includes a third global word line driver 513 and a fourth global word line driver 514. The third word line driver 513 provides a signal to the third word global word line 513g to drive the first boundary word line. The fourth word line driver 514 provides a signal to the fourth global word line 514g to drive the second boundary word line. The third global word line driver 513 can include circuitry to provide a first boundary word line bias to the first boundary word line during sub-block erase. The fourth global word line driver 514 can include circuitry to provide a second boundary word line bias to the second boundary word line during sub-block erase.

The set of regional word line drivers includes a third boundary word line driver (e.g., third boundary word line driver 570) and a fourth boundary word line driver (e.g., fourth boundary word line driver 571). The third boundary word line driver drives a third boundary word line (eg, a third boundary word line WL (bnd3)). The third boundary word line is adjacent to the first subset of the word line (eg, the first subset) and is located relative to the first boundary word line (eg, the first boundary word line WL (bnd1)) The other side. The fourth boundary word line driver drives a fourth boundary word line (eg, a fourth boundary word line WL (bnd4)). The fourth boundary word line is adjacent to the third boundary word line and is located on the other side of the first subset of the word line (eg, the first subset 559). A third global word line (e.g., a third global word line 513g) is coupled to the third boundary word line driver. A fourth global word line (e.g., a fourth global word line 514g) is coupled to the fourth boundary word line driver.

In this embodiment, only a set of even and odd blocks is illustrated. However, the global word line can be connected to several blocks of the regional word line driver.

A global word line decoder (GWL decoder) (eg, global word line driver 590) is connected to the entire domain by a connector of a patterned patterned layer (eg, connector 595) Word line driver. The connector can carry one or more output signals to the global word line driver. A local word line decoder (LWL decoder) (for example, an area word line decoder 580) is connected to an area word line driver (eg, an area character by a connector of the patterned conductive layer) Line drivers 560~571) for connecting power signals, bias signals, address signals and/or He controls the signal to the area word line driver. The connection of the regional word line decoder 580 may include control signals for carrying the control signal to the respective area word line drivers of the block.

The area word line driver (for example, the area word line driver 566) may include an N-type metal oxide semiconductor transistor (NMOS transistor) having an input terminal, an output terminal, and a control. Gate. The input is coupled to a global word line (e.g., global word line 511g). The output is connected to a word line (for example, word line WL(i+1)). The control gate connection area word line decoder (e.g., area word line decoder 585) transmits control signals transmitted over the area word line (e.g., area word line 585). The global word line driver (e.g., global word line driver 511) can include a level shifter. The level shifter offsets the output voltage level based on one or more output signals from a global word line decoder (e.g., global word line decoder 590). For example, the level shifter can change the output voltage level according to the requirements of the sub-block erase operation and the requirements of the read, write, and block erase operations.

The sub-block erase bias using the regional and global word line drivers can be understood by the following table.

In FIG. 5, when the first serial selection switch is biased (for example, -2V), the global bit lines are connected (for example, global bit lines BL-0, BL-1, BL-2, BL). -3) to the channel line of the different layers of the gate sequence, through the first serial selection switch (for example, the first series selection switch 530, 531, 532, 533), the channel can be applied to remove the voltage (for example, +6V) in the channel. line. A word line-side erase voltage may be applied to a first subset of word lines of the selected block to induce wear of memory cells coupled to the first subset of word lines. Tunneling action. A word line-side inhibit voltage may be applied to a second subset of word lines of the selected block to inhibit tunneling of memory cells coupled to the second subset of word lines effect.

In an embodiment, the first global word line voltage (-10V) may be applied to the first global character coupled to the first subset of the regional word line drivers. Line (for example, the first global character line 511g). A second global word line voltage (+4V) may be applied to the second global word line of the second subset of the coupled area word line drivers (eg, the second global word line 512g). A control voltage (eg, +15V) can be applied from the control signal line 585 through the control signal to the regional word line driver to initiate a first subset of the regional word line drivers to provide word line side erase voltage to characters. A first subset of the lines and a second subset of the regional word line drivers are enabled to provide a second subset of word line side inhibit voltages to word lines.

A third global word line voltage (eg, -4V) may be applied to the third global word line (eg, the third global word line 513g). A fourth global word line voltage (e.g., +2V) may be provided to the fourth global word line (e.g., fourth global word line 514g). When a control voltage (eg, +15V) is applied to the regional word line driver (eg, region word line driver 585) by a control signal, the first boundary word line driver (eg, first boundary word line driver 565) a first boundary condition is induced between the first subset of the word line and the second boundary word line; and the second boundary word line driver (eg, the second boundary word line driver 564) is activated A second boundary condition is induced between the first boundary word line and the second subset of the word lines.

The first boundary condition may include a plurality of electric fields for suppressing injection of hot carriers into the memory cells of the first subset of coupled word lines. The second boundary condition may include a plurality of electric fields for suppressing injection of the hot carrier into the memory cells of the second subset of the coupled word lines. The hot carrier injection can be induced by the difference between the first channel potential and the second channel potential. The first channel potential is coupled to the first subset The channel line of the memory cell. The second channel potential is located in a channel line of the memory cell to which the second subset is coupled.

In several embodiments of sub-block erase techniques, more than one or all of the global word line drivers and regional word line drivers can provide boundary bias. In these embodiments, the sub-block size in the erase program can be designed based on instructions from the source or internal source of the memory, or the configuration of the memory.

Figure 6 is a timing diagram showing the execution of sub-block erase using the circuit of Figure 5. As shown in Fig. 5, the block of the memory cell includes a plurality of inverse gate series. The reverse gate and the series include channel lines located in the first series selection switch and the second series selection switch. The reverse gate and the string share the word line that is not in the first and second series of select switches.

At the beginning of the self-block erase cycle (before time T0), the bit line, the source line, the string select line, the ground select line, the selected word line to be erased, and the unselected word to be suppressed The meta line, the first boundary word line, and the second second boundary word line may be initial values (eg, 0V). At time point T0, the channel side erase voltage _VBL (e.g., +6V) is applied to the channel line through the first string select switch of the selected block. A source-side voltage V _CSL (eg, +6 V) is applied to the channel line through a second string select switch (eg, a ground select switch). At the time point T0, the voltage V _{SSL of the} serial selection switch becomes about -2 V, and the voltage V _{GSL of the} ground selection switch becomes -2 V.

At time point T0, a first bias voltage V _bnd1 (eg, -4V) is applied to the first boundary word line of the word line for the selected subset of the boundary word line side and the boundary word line inducing non-selected subset of the boundary condition between the other side, a second bias voltage _V bnd2 (for example, + 2V) is applied to the selected word line first boundary of the block, to the word line to one side of the boundary of the A boundary condition is induced between the selected subset and the unselected subset of the other side of the boundary character line.

At time point T0, a word line-side inhibit voltage (eg, +4V) is applied to the unselected subset of the word lines of the unselected block to suppress coupling to the unselected subset. The wearing effect of the memory pack.

At time point T1, the word line side erase voltage V _ers (eg, -10 V) is applied to the selected sub-block of the word line to couple the memory cells of the selected subset to induce a puncturing effect (eg, The hole is worn through). At time point T2, the voltage of the selected subset of the word line can be returned to 0V. At time point T3, the sub-block erase cycle ends and the remaining voltages can be returned to 0V.

In the sub-block erase operation described herein, the bias voltage (e.g., -4V) may be between the bit line side erase voltage (e.g., -10V) and the second bias (e.g., +2V). The word line side suppression voltage V _inhibit (for example, +4 V) is higher than the second bias voltage.

Figure 7 is a flow chart showing the sub-block erase operation. A controller (e.g., state machine 119 of integrated circuit 100 of Fig. 1) can implement various operations of the present process.

The controller may receive a sub-block erase command from an external source or an internal source to erase the word line coupled to the anti-gate array (eg, the inverse flash memory array 110 of FIG. 1) The memory cells of the subset have been selected. A number of character lines can be selected as the selected subset. The sub-block erase command may include a parameter, this The parameter indicates the size of the sub-block to be erased. The size here may refer to the number of word lines (for example, 11), or the range of word lines (for example, the 10th word line to the 20th word line). After receiving the sub-block erase command, the steps of FIG. 7 can be performed.

In step 710, the channel side erase voltage (eg, +6V) can be applied to the selected block through the first serial select switch (eg, the first tandem select switches 530531, 532, and 533 of FIG. 5). The channel line of the memory. The source line voltage (e.g., +6 VP) can be applied to the channel line of the selected block through the second series select switch (e.g., the second string select switch 540, 541 of FIG. 5). The source line voltage can be matched to the channel side erase voltage. In step 720, the word line side erase voltage (eg, -10 V) can be applied to the selected subset of word lines to couple the memory cells of the selected subset to induce pinching (eg, hole penetration).遂). In step 730, a word line side suppression voltage (eg, +4V) may be applied to the unselected subset of the selected blocks to couple the memory cells of the selected subset to suppress the transmission (eg, electricity) The hole penetrates the role).

In step 740, a first bias voltage may be applied to the first boundary word line of the word line (eg, the first boundary word line WL (bnd1) of FIG. 5) to select the selected word line. The set and word lines induce a first boundary condition between the selected subsets. The first bias voltage can be applied to a third boundary word line of the word line (e.g., the third boundary word line of Figure 5) to induce a first boundary condition. The third boundary word line is adjacent to the other side of the selected subset of the first boundary word line.

In step 750, a second bias voltage may be applied to the second boundary word line of the word line (eg, the second boundary word line WL (bnd2) of FIG. 5) for the first boundary word line and A second boundary condition is induced between the unselected subsets of the word lines. A second bias voltage may be applied to the fourth boundary word line of the word line (e.g., the fourth boundary word line WL (bnd4) of Figure 5) to induce a second boundary condition. The fourth boundary word line is adjacent to the third boundary word line relative to the other side of the selected subset.

The sequence of steps may be different from the sequence of steps of Figure 7. For example, step 720 can be performed after steps 710 and 730-750.

In one embodiment, the memory is coupled between the first boundary word line and the second boundary word line before the voltage is erased to the selected subset of the selected block. The cell data is moved from the selected block to another block of the memory cell. Then, after the voltage is erased on the application word line side, the data stored in the memory cells coupled to the first boundary word line and the second boundary word line are respectively moved back to the selected block.

For example, in the selected block of the memory cell, a plurality of inverted gate columns share 64 word lines (0th through 63rd), and the parameter of the sub-block erase command indicates that the coupling has been selected. The 10th to 20th character lines of the sub-set need to be erased. Meanwhile, the 9th word line, the 8th word line, the 21st word line, and the 22nd word line of the word line can be respectively used as the first boundary word line and the second boundary word line, The third boundary word line and the fourth boundary word line.

The erased voltage applied to the selected block of the selected block on the word line side Before the collection, the data stored in the memory cells coupled to the 9th word line, the 8th word line, the 21st word line, and the 22nd word line may be moved to another block. The word line side erase voltage can then be applied to the selected subset of word lines to erase the memory cells coupled to the 10th to 20th word lines.

The verification program can be executed on the word line adjacent to the first boundary word line and the third boundary word line (for example, the 10th word line and the 20th word line). This is due to the fact that these memory cells are susceptible to interference from hot hole injection in past experience. The thermowell injection system induces a difference in the first channel potential of the selected subset and the second channel potential of the selected subset.

After the voltage is erased to the selected subset, the data is moved back to the 9th word line, the 8th word line, the 21st word line, and the 22nd word line. Memory cell. At the same time, only the data stored in the memory cell coupled to the fourth boundary word line needs to be moved back.

In contrast, in the conventional block erase operation, in order to erase a portion of the memory cells (coupled to the 10th to 20th word lines) having 64 word lines, the remaining memory cells (coupled to the block) All the remaining word lines, for example, items 53 to 9 and 21 to 63, need to be moved to another block before the erasing process, and after the erasing process, the data is moved back to the original position. Therefore, the sub-block erase operation described herein can improve the time requirements of the erase operation and the performance of the integrated circuit of the three-dimensional anti-gate array.

Figure 8 is a diagram showing the threshold voltage distribution of the memory cells of the selected block after the sub-block erase operation. Threshold voltage distributions 810, 820, 830, 840, and 850 Respectively indicating that the selected subset of selected blocks uses different voltage values (eg, -4V, -2V, 0V, 2V, and 4V) as the first bias voltage applied to the first boundary word line (eg, Figure 5) The case of the first boundary word line WL(bnd1)). The other voltage application of the sub-block erase operation is described in FIG. The threshold voltage distribution 860 corresponds to the memory cells after the block erase operation. The threshold voltage distribution 810 corresponds to a memory cell of the programmed state in which the selected block is selected as a subset.

The first boundary word line, the second boundary word line, the third boundary word line, and the fourth boundary word line may interfere with each other during the sub-block erase operation. In an embodiment, one or more of the first boundary word line, the second boundary word line, the third boundary word line, and the fourth boundary word line may be used as virtual word lines, and No data is stored in the memory cells coupled to the boundary word line. In another embodiment, the data stored in the memory cell coupled to the boundary word line may be interfered, but will not disappear, for example, by detecting and correcting an error correcting code (ECC). The error of the memory cell of the boundary word line.

Figure 8 illustrates that the erase operation can be performed correctly. The erase operation may cause the first threshold voltage distribution of the selected subset (eg, the threshold voltage distribution 810) to not overlap with the second threshold voltage distribution of the unselected subset (eg, the threshold voltage distribution 870). The erase operation includes one or more erase and verify cycles including applying a first bias (eg, -4V). The first bias voltage is between the word line side erase voltage (eg, -10V) and the second bias voltage (eg, +2V). The remaining voltages are described in Figure 6. In contrast, another erase operation causes the threshold voltage distribution (eg, threshold voltage distribution 850) of the selected subset to be unselected. The second threshold voltage distribution of the subset (eg, the threshold voltage distribution 870) overlaps. This erase operation includes one or more erase and verify cycles that include applying a first bias (eg, 4V). The first bias voltage is higher than the second bias voltage (eg, +2V).

Figure 9 illustrates the sub-block erase operation coupled to the selected subset (e.g., selected subset 559) and adjacent to the first boundary word line WL (bnd1) and the third boundary word line WL ( Bnd3) (for example, the threshold voltage distribution map of the memory cell of the word line WL(i+1) and WL61 of Fig. 5). In the past experience, these memory cells are susceptible to interference from hot hole injection. The thermowell injection system induces a difference in the first channel potential of the selected subset and the second channel potential of the selected subset.

The threshold voltage distributions 910, 920, 930, 940, and 950 respectively indicate that the selected subset of the selected blocks are applied with different voltage values (eg, -4V, -2V, 0V, 2V, and 4V) as the first bias voltage. a boundary word line (for example, the first boundary word line WL (bnd1) of FIG. 5) and a third boundary word line (for example, the third boundary word line WL (bnd3) of FIG. 5) . The other voltage application of the sub-block erase operation is described in FIG.

Figure 9 illustrates that the erase operation can be performed correctly. The erase operation may cause the first threshold voltage distribution of the selected subset (eg, the threshold voltage distribution 910) to not overlap with the second threshold voltage distribution of the unselected subset (eg, the threshold voltage distribution 870). The erase operation includes one or more erase and verify cycles including applying a first bias (eg, -4V). The first bias voltage is between the word line side erase voltage (eg, -10V) and the second bias voltage (eg, +2V). The remaining voltages are described in Figure 6. In contrast, another erase operation causes the threshold voltage distribution of the selected subset (eg, threshold voltage distribution 950) to overlap with the second threshold voltage distribution of the unselected subset (eg, threshold voltage distribution 870). This erase operation includes one or more erase and verify cycles that include applying a first bias (eg, 4V). The first bias voltage is higher than the second bias voltage (eg, +2V).

The sub-block erase operation has been described above with respect to the vertical gate structure of FIG. These operations can be applied to a variety of different 3D memory architectures. Moreover, the sub-block erase operation of the above embodiment takes the flash memory as an example. But these operations can also be applied to other types of memory.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ integrated circuit

110‧‧‧Anti-gate flash memory array

111‧‧‧ column decoder

112‧‧‧ character line

113‧‧‧Page Buffer

114‧‧‧Global bit line

115‧‧‧ busbar

116‧‧‧ row decoder

117‧‧‧ data bus

118‧‧‧Pressure Arrangement Unit

119‧‧‧ state machine

123‧‧‧ data input line

124‧‧‧Other circuits

Claims (20)

A method for operating a NAND array, the NAND array comprising a plurality of blocks composed of a plurality of memory cells, wherein one of the blocks includes a plurality of blocks And a NAND string having a plurality of first string select switches and a plurality of second string select switches a plurality of channel lines, and the reverse gate series share a set of word lines between the first series selection switches and the second series selection switches The method includes: applying a channel-side erase voltage to the channel lines through the first series selection switches in a selected block; a block, applying a plurality of word line-side erase voltages to a selected subset of the set of word lines for coupling to the selected subset Some memory cells induce tunneling, the selected one Included in the selected block, a plurality of word line-side inhibit voltages are applied to one of the unselected subsets of the set of word lines. And the memory cell is coupled to the unselected subset to inhibit tunneling, the unselected subset includes a number of word lines greater than one; applying a first bias voltage to One of the character lines first a first boundary word line for inducing a plurality of first boundary conditions between the selected subset of the word lines and the unselected subset of the word lines And applying a second bias voltage to the second boundary word line of the one of the word lines for the first boundary word line and the word lines A plurality of second boundary conditions are induced between the unselected subsets, wherein the first bias is between the word line side erase voltage and the second bias, and the The word line side suppression voltage is higher than the second bias. The method of claim 1, wherein the first boundary conditions comprise a plurality of electric fields, the electric fields being coupled to a hot carrier of the memory cells of the selected subset Suppression of hot carrier injection, wherein the hot carrier injection is induced by a difference between a first channel potential and a second channel potential, The first channel potential is located in the channel lines of the memory cells coupled to the selected subset, and the second channel potential is located in the channel lines of the memory cells coupled to the unselected subset. The method of claim 1, wherein the second boundary states comprise a plurality of electric fields, the electric fields being coupled to a suppression of a hot carrier injection of the memory cells of the unselected subset Wherein the hot carrier injection is performed by a first channel potential and a second channel potential (second) Inducing a difference in a channel potential, the first channel potential being located in the channel lines of the memory cells coupled to the selected subset, the second channel potential being located in the unselected subset These channel lines of memory cells. The method of claim 1, further comprising: performing an erase operation such that the memory cells coupled to the selected subset have a first threshold voltage distribution (first threshold voltage distribution) The first threshold voltage distribution does not overlap with a second threshold voltage distribution of the memory cells coupled to the unselected subset in the stylized state, wherein the erase action includes a Or an erase and verify cycle, the erase and verify cycle includes applying the word line side erase voltage and applying the word line side suppression voltage a bias voltage and the second bias voltage. The method of claim 1, further comprising: before applying the word line side erase voltage, storing the signal coupled to the first boundary word line and the second boundary word line The data of the memory cells are moved from the selected block to another block of the blocks; and after the voltage is erased by applying the word line side, the data is coupled to the first boundary character. The data of the lines and the memory cells of the second boundary word line are respectively moved back to the selected block by the block. The method of claim 1, further comprising: applying the first bias voltage to one of the third boundary word lines of the word lines (third Boundary word line) to induce the first boundary condition, wherein the third boundary word line is adjacent to one side of the selected subset of the first boundary word line; and applying the second bias to a fourth boundary word line of the word lines to induce the second boundary conditions, wherein the fourth boundary word line is adjacent to the third boundary word line One of the selected subsets of the word line. The method of claim 1, wherein the first boundary character line boundary is between the selected subset of the word lines and the unselected subset of the word lines, the second boundary The word line is located between the first boundary word line and the unselected subset of the word lines, and the method includes: before being applied to the word line side, the voltage is stored and coupled to the The data of the memory cells of the first boundary word line and the second boundary word line are moved by the selected block to another block of the blocks of the memory cells; and the words are applied After the voltage is erased on the side of the line, the data stored in the memory cells coupled between the first boundary word line and the second boundary word line are respectively moved back to the selected block by the other block. . The method of claim 1, wherein the first boundary word line is located between the selected subset of the word lines and the unselected subset of the word lines, the second The boundary word line is located between the first boundary word line and the unselected subset of the word lines, and the method further includes: selecting a plurality of word lines as the selected one of the word lines set; Before the voltage is erased by applying the word line side, the data stored in the memory cells coupled between the first boundary word line and the second boundary word line is moved from the selected block to And another block of the blocks of the memory cells; and after applying the word line side erase voltage, storing the first boundary word line and the second boundary word line The data of the memory cells are moved back to the selected block by another block. The method of claim 1, further comprising: in response to the selected block, echoing one of the memory cells of the selected subset of the selected word lines. The operation of applying the channel side erasing voltage, applying the word line side erasing voltages, and applying the word line side suppression voltages is performed. A memory, comprising: a NAND array, comprising a plurality of blocks composed of a plurality of memory cells, wherein one of the blocks comprises a plurality of NAND strings. The reverse gate sequence has a plurality of channel lines between a plurality of first string select switches and a plurality of second string select switches, and The reverse gate series share a set of word lines between the first series select switches and the second series select switches; and a controller coupled In the blocks of the memory cells, the controller includes a plurality of logic circuits for selecting a selected block through the first series of columns. Off, applying a channel-side erase voltage to the channel lines; applying a plurality of word line-side erase voltages to the selected blocks a first subset of word lines for inducing tunneling of the memory cells coupled to the first subset, the first subset comprising more than one a word line; applying a plurality of word line-side inhibit voltages to a second subset of the set of word lines in the selected block to be coupled to the second subset of the set of word lines The memory cells of the second subset suppress the tunneling, the second subset includes a number of word lines greater than one; applying a first bias voltage to the word lines a first boundary word line for inducing a plurality of first boundary conditions between the first subset of the word lines and the second subset of the word lines (first Boundary condition); and applying a second bias voltage to the word lines a second boundary word line, wherein a plurality of second boundary conditions are induced between the first boundary word line and the second subset of the word lines, wherein The first bias voltage is between the word line side erase voltage and the second bias voltage, and the word line side suppression voltages are higher than the second bias voltage. The memory of claim 10, further comprising: a plurality of regional word line drivers for respectively driving the selected block Dividing the word lines, the regional word line drivers include a first subset, a second subset, a first boundary word line driver, and a second boundary word line driver, the regional words The first subset of the line driver drives the first subset of the word lines, and the second subset of the regional word line drivers are used to drive the second set of the word lines The first boundary word line driver is configured to drive the first boundary word line of the word line, the first boundary word line is located in the first subset of the word lines and the characters Between the second subset of lines, the second boundary word line driver is configured to drive the second boundary word line of the word lines, and the second boundary word line is located at the first boundary word line And the second subset of the word lines; and the plurality of global word lines, including a first global word line, a second global word line, a third global word line, and a first a fourth global word line, the first global word line being coupled to the first subset of the regional word line drivers The second global word line is connected to the second subset of the regional word line drivers, the third global word line is connected to the first boundary word line driver, and the fourth global word line is Connected to the second boundary word line driver. The memory of claim 11, wherein the logic circuit is further configured to apply a first global word line voltage to the first global word line; applying a second global word line voltage to the a second global word line; initiating the first subset of the regional word line drivers to provide the word line side erase voltage to the first subset of the word lines; and initiating the regions The second subset of word line drivers to provide the character The line side suppression voltage produces the second subset of the word lines. The memory of claim 12, wherein the logic circuit is further configured to apply a third global word line voltage to the third global word line; applying a fourth global word line voltage to the a fourth global word line line; initiating the first boundary word line driver to induce the first boundary condition between the first subset of the word lines and the second boundary word line; and initiating the a second boundary word line driver, wherein the second boundary condition is induced by the first boundary word line and the second subset of the word lines, wherein the third global word line voltage is first Between the global word line voltage and the fourth global word line voltage, and the second global word line voltage is higher than the fourth global word line voltage. The memory of claim 13, wherein the first boundary condition comprises a plurality of electric fields, wherein the electric fields are used to suppress a portion of the memory cells coupled to the first subset of the word lines a thermal hole injection, wherein the hot carrier injection is induced by a difference between a first channel potential and a second channel potential, the first channel potential being coupled to The channel lines of the memory cells of the first subset of the word lines, the second channel potentials being located at the portions of the second subset of the word lines These channel lines of the cell. The memory of claim 13, wherein the second boundary The condition includes a plurality of electric fields for suppressing a thermoelectric hole injection of the memory cells coupled to a portion of the second subset of the word lines, wherein the hot carrier injection system is coupled to a first channel Inducing a difference between a first channel potential and a second channel potential, the first channel potential being located in the memory cells coupled to the portion of the first subset of the word lines The channel lines, the second channel potentials are located in the channel lines of the memory cells coupled to portions of the second subset of the word lines. The memory of claim 11, wherein the logic circuit is further configured to be coupled to the first boundary word line and the first before applying the word line side erase voltage The data of the memory cells of the two boundary word lines are moved by the selected block to another block of the memory cells; and after the voltage is applied to the word line side, the voltage is The data stored in the memory cells coupled between the first boundary word line and the second boundary word line are separately moved back to the selected block by the other block. The memory of claim 11, wherein the set of regional word line drivers comprises a third boundary word line driver and a fourth boundary word line driver, the third boundary word line driver is used Driving a third boundary word line adjacent to the first subset of the word lines with respect to one side of the first boundary word line, the fourth boundary word line driver Used to drive a fourth boundary word line adjacent to the third boundary word line relative to the other side of the first subset of the word lines; The third global word line line is coupled to the third global word line driver; and the fourth global word line driver is coupled to the fourth global word line driver. The memory of claim 10, wherein the first boundary word line is located between the first subset of the word lines and the second subset of the word lines, the first The two boundary word lines are located between the first boundary bit line and the second subset of the word lines, and the logic circuits of the controller are further configured to apply the word line side erase voltages And, the data stored in the memory cells coupled to the first boundary word line and the second boundary word line is moved from the selected block to another block of the blocks; After applying the word line side erase voltage, the data stored in the memory cells coupled to the first boundary word line and the second boundary word line are respectively returned from the other block to the Select the block. The memory of claim 10, wherein the first boundary word line is located between the first subset of the word lines and the second subset of the word lines, the first The two boundary word lines are located between the first boundary word line and the second subset of the word lines, and the logic circuits of the controller are further used to select a plurality of word lines as the words The selected subset of the meta-line is stored in the memory cells coupled between the first boundary word line and the second boundary word line before applying the word line side erase voltage Data is moved from the selected block to another block of the blocks of the memory cells; and after the voltage is erased by applying the word line side, the data is stored and coupled to the first side The data of the memory cells of the boundary word line and the second boundary word line are respectively moved back to the selected block by the block. The memory of claim 10, wherein the control unit performs the application of the channel in response to erasing a command of the memory cells coupled to the selected subset of the word lines. The side erase voltage, the application of the word line side erase voltage, and the operation of applying the word line side suppression voltages.