TWI554170B - Interposer substrate and method of fabricating the same - Google Patents

Description

Intermediary substrate and its preparation method

The present invention relates to a semiconductor substrate and a method of fabricating the same, and more particularly to an interposer substrate and a method of fabricating the same.

As electronic products are gradually becoming more and more miniaturized, the area of the printed circuit board (PCB) surface for semiconductor packages is getting smaller and smaller. Therefore, the industry has developed a three-dimensional stacking technology for semiconductor packages, which is tied to a semiconductor. Another semiconductor package is stacked on the package to form a package on package (POP) to meet the requirements of high density component placement.

The conventional stacked package structure connects a semiconductor package through a plurality of solder balls and is electrically connected to another semiconductor package. However, due to process constraints, the size and spacing of the solder balls need to be certain. Under the limited area of the package, the external electrical contact of the package is reduced, and the thickness of the overall package structure is high.

Referring to FIG. 1 , in order to further improve the number and thinness of the electrical contacts of the stacked package structure, the industry is immersed in the first semiconductor package 1A and An interposer 10 is disposed between the second semiconductor package 1B. The first surface and the second surface of the interposer substrate 10 are provided with a first circuit layer 11 and a second circuit layer 12, and the interposer substrate 10 is disposed. The conductive vias 13 are electrically connected to the first circuit layer 11 and the second circuit layer 12 for the first semiconductor package 1A to be connected through the first conductive material 14 and electrically connected to the first circuit layer 11 of the interposer substrate 10, The second circuit layer 12 and the second conductive material 15 of the interposer substrate 10 are connected and electrically connected to the second semiconductor package 1B to form a stacked package structure.

Please refer to Figures 2A to 2E for the process of an interposer substrate.

As shown in FIG. 2A, a core board 20 is provided. The core board 20 has a first surface 20a and a second surface 20b opposite to each other, and a plurality of cores 20 are drilled through the first and second surfaces. The through hole 20c is then plated with a metal layer 21 on the first surface, the second surface and the through hole of the core plate.

As shown in FIG. 2B, the metal layers of the first surface 20a and the second surface 20b of the core board 20 are patterned to form a first wiring layer 21a and a second wiring layer 21b, and the first wiring layer 21a and the second layer are formed. The circuit layer 21b is electrically connected to each other through a metal layer (that is, a conductive via 21c) formed in the through hole. Further, an insulating layer (solderproof layer) 22 is formed on the first wiring layer 21a and the second wiring layer 21b, and the insulating layer 22 is formed with a plurality of exposed portions, the first wiring layer 21a and the second wiring layer 21b. .

As shown in FIG. 2C, a conductive layer 23 and a resist layer 24 are covered on the insulating layer 22 of the first surface 20a and the second surface 20b of the core board 20.

As shown in FIG. 2D, the resist layer 24 is patterned to form a plurality of openings to expose a portion of the second wiring layer 21b; and then an electroplating process is performed. The conductive material 25 is formed in the opening of the resist layer, and the conductive material 25 is electrically coupled to the second circuit layer 21b.

As shown in FIG. 2E, the resist layer 24 and the conductive layer 23 covered thereby are removed to form an interposer substrate.

However, the foregoing process is complicated and costly, and in the foregoing process, an additional conductive layer is required, and the setting of the conductive layer easily affects the electrical quality of the interposer; in addition, the thickness of the interposer is limited during the process, and the thickness thereof is more When thin (for example, below 130μm), the production is not easy and it is easy to cause damage; in addition, the line width/line spacing (L/S) design of the line in such a process is easily limited. When L/S is 25/25μm or less, The yield is also affected.

Therefore, how to overcome the problems of the above-mentioned conventional techniques has become a problem to be solved.

In view of the above-mentioned prior art, the present invention provides a method for fabricating an interposer, comprising: providing a carrier plate, forming a plurality of grooves on the surface of the carrier plate, and forming a first dielectric material layer in the groove; Forming a first circuit layer on the carrier board and the first dielectric material layer; forming a plurality of first conductive blocks on the first circuit layer; and forming the first dielectric material layer, the first circuit layer, and the plurality of first conductive layers Covering a second layer of dielectric material on the block, and exposing the second layer of dielectric material to the end of the first conductive block; forming a second circuit layer on the second layer of dielectric material, and making the second line The layer is electrically connected to the first conductive block; a plurality of second conductive blocks are formed on the second circuit layer; and the carrier plate is removed.

The invention further provides an interposer substrate comprising: a first dielectric material a layer, a second dielectric material layer, a first wiring layer, a second wiring layer, a first conductive block, and a second conductive block. The second dielectric material layer has opposite first and second surfaces; the first circuit layer has opposite first and second surfaces, and the first circuit layer is embedded in the second dielectric material layer The first surface of the first circuit layer is flush with the first surface of the second dielectric material layer; the first dielectric material layer is formed on the first surface of the second dielectric material layer, and the The first dielectric material layer has a plurality of openings to expose the first circuit layer; the first conductive block has a first end surface and a second end surface, and the first end surface of the first conductive block is connected to the first circuit layer a second surface, and the second end surface of the first conductive block is flush with the second surface of the second dielectric material layer; the second circuit layer has opposite first and second surfaces, the second a circuit layer is formed on the second surface of the second dielectric material layer, and a portion of the first surface of the second circuit layer is connected to the second end surface of the first conductive block; the second conductive block is formed on the second conductive layer On the second surface of the second circuit layer.

The present invention further provides a second embodiment of the method for fabricating an interposer, comprising: providing a carrier plate, and forming a first dielectric material layer on the carrier plate, wherein the first dielectric material layer is formed with a plurality of openings Exposing a portion of the carrier board; forming a first circuit layer on the carrier board and the first dielectric material layer, a portion of the first circuit layer is formed in the opening of the dielectric material layer, and a portion of the first circuit layer is formed on the first circuit layer Forming a plurality of first conductive blocks on the first circuit layer; covering the first dielectric material layer, the first circuit layer, and the first conductive block with a second dielectric material layer, And exposing the second conductive material layer to the outer surface of the first conductive block; and the second dielectric material Forming a second circuit layer on the material layer, and electrically connecting the second circuit layer to the first conductive block; forming a plurality of second conductive blocks on the second circuit layer; and removing the carrier plate.

The present invention further provides a second embodiment of an interposer substrate, which includes a first dielectric material layer, a second dielectric material layer, a first circuit layer, a second circuit layer, a first conductive block, and The second conductive block. The first dielectric material layer has an opposite first surface, a second surface, and a plurality of openings extending through the first surface and the second surface; the first circuit layer has opposite first and second surfaces, wherein the portion The first circuit layer is formed on the second surface of the first dielectric material layer, and the remaining portion of the first circuit layer is formed in the opening of the first dielectric material layer to make the first portion The first surface of the circuit layer exposes the first dielectric material layer and is flush with the first surface of the first dielectric material layer; the first conductive block is formed on the second surface of the first circuit layer; The second dielectric material layer covers the second surface of the first dielectric material layer and the second surface of the first circuit layer, and covers the first conductive block and makes the first conductive block end Exposing the second dielectric material layer; the second circuit layer is formed on the second dielectric material layer and electrically connected to the first conductive block; the second conductive block is formed on the second circuit On the floor.

As can be seen from the foregoing description, the interposer substrate of the present invention and the method for manufacturing the same are first formed by etching a recess on a carrier plate to fill a dielectric material in the recess to form a first dielectric material layer, or first on the carrier board. Forming a patterned first dielectric material layer, and sequentially forming a first circuit layer, a first conductive block, and a second dielectric material layer on the carrier plate and the first dielectric material layer, and The first circuit layer and the first conductive block are embedded in the second dielectric material layer, and the second circuit layer and the second conductive block are formed on the second dielectric material layer to form a coreless and The intermediate substrate of the fine line is used for the purpose of lightening and thinning the product, and the invention can also solve the problem that the line width/line spacing (L/S) design of the line in the conventional process is limited. Moreover, the process only exposes a portion of the first circuit layer for external electronic components, and an additional insulating layer (solderproof layer) is required, and an additional conductive layer is not required to reduce the process and cost.

1A‧‧‧First semiconductor package

1B‧‧‧Second semiconductor package

10‧‧‧Intermediate substrate

11‧‧‧First line layer

12‧‧‧Second circuit layer

13‧‧‧Electrical perforation

14‧‧‧First conductive material

15‧‧‧Second conductive material

20‧‧‧ core board

20a‧‧‧ first surface

20b‧‧‧second surface

20c‧‧‧Perforation

21‧‧‧metal layer

21a‧‧‧First circuit layer

21b‧‧‧Second circuit layer

21c‧‧‧Electrical perforation

22‧‧‧Insulation

23‧‧‧ Conductive layer

24‧‧‧resist

25‧‧‧Electrical materials

30, 50‧‧‧ carrying board

31a, 51a‧‧‧ first barrier

300‧‧‧ Groove

32a, 52a‧‧‧ first dielectric material layer

31b, 51b‧‧‧ second resistive layer

33a, 53a‧‧‧ first line layer

31c, 51c‧‧‧ third resistive layer

34a, 54a‧‧‧ first conductive block

32b, 52b‧‧‧Second dielectric material layer

31d, 51d‧‧‧ fourth resistive layer

33b, 53b‧‧‧ second circuit layer

31e‧‧‧ fifth barrier

34b, 54b‧‧‧second conductive block

321b, 521a‧‧‧ first surface

322b, 522a‧‧‧ second surface

331a, 531a‧‧‧ first surface

332a, 532a‧‧‧ second surface

331b‧‧‧ first surface

332b‧‧‧ second surface

341a‧‧‧ first end

342a‧‧‧second end face

35, 55‧‧‧Insulating protective layer

1 is a schematic cross-sectional view of a conventional stacked package structure; 2A to 2E are schematic cross-sectional views of a conventional interposer substrate; and FIGS. 3A to 3K are first embodiment of a method for fabricating an interposer of the present invention; 4A to 4B are cross-sectional views showing a second embodiment of the method for fabricating the interposer of the present invention; and FIGS. 5A to 5I are cross-sectional views showing a third embodiment of the method for fabricating the interposer of the present invention; and 6A FIG. 6B is a schematic cross-sectional view showing a fourth embodiment of the method for fabricating the interposer of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It should be noted that the structure, proportion and size depicted in the drawings of this specification And the like, which are used for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the invention, and thus do not have technical significance, any structural modification, The change of the proportional relationship or the adjustment of the size should be within the scope of the technical content disclosed by the present invention without affecting the effects and the achievable effects of the present invention. In the meantime, the terms "upper", "first", "second", "top" and "bottom" are used in this description for convenience of description and are not intended to limit the invention. Changes in the scope of implementation, changes or adjustments in their relative relationship, are considered to be within the scope of the present invention.

Please refer to FIGS. 3A to 3K, which are schematic diagrams of the manufacturing method of the interposer substrate of the present invention.

As shown in FIG. 3A, a carrier 30 is provided, and the first barrier layer 31a is covered on the surface of the carrier 30, and then the first barrier layer 31a is patterned to form a plurality of external exposure layers in the first barrier layer 31a. The opening of the carrier plate 30. The carrier plate 30 is a substrate, for example, a copper foil substrate, but is not particularly limited.

As shown in FIG. 3B, the portion of the carrier sheet 30 that is not covered by the first barrier layer 31a is removed by, for example, etching to form a plurality of recesses 300 on the surface of the carrier sheet 30.

As shown in FIG. 3C, the first resist layer 31a is removed and a dielectric material is filled in the recess 300 to form a first dielectric material layer 32a. The first dielectric material layer may be formed in the groove by a molding method, a coating method or a pressing method, and the dielectric material is, for example, an epoxy resin.

As shown in FIG. 3D, the carrier board 30 and the first dielectric material layer 32a A patterned second resist layer 31b is formed thereon, and the second resist layer 31b is formed with a plurality of exposed portions of the first dielectric material layer 32a and a portion of the carrier plate 30. Next, a first wiring layer 33a is formed in the opening of the second resist layer 31b.

As shown in FIG. 3E, a third resist layer 31c is overlaid on the first circuit layer 33a and the second resist layer 31b, and the third resist layer 31c is patterned to form the third resist layer 31c. A portion of the opening of the first circuit layer is exposed. Then, a plurality of first conductive blocks 34a are formed in the openings of the third resist layer 31c.

As shown in FIG. 3F, the second resist layer 31b and the third resist layer 31c are removed, and the first wiring layer 33a and the plurality of first conductive bumps 34a are exposed.

As shown in FIG. 3G, the second dielectric material layer 32b is covered on the first dielectric material layer 32a, the first circuit layer 33a and the plurality of first conductive blocks 34a, and the first conductive block 34a is outside the end. The second dielectric material layer 32b is exposed.

As shown in FIG. 3H, a fourth resist layer 31d is overlaid on the second dielectric material layer 32b, and the fourth resist layer 31d is patterned to form a plurality of exposed first conductive bumps 34a and a second portion. The opening of the dielectric material layer 32b. Next, a second wiring layer 33b is formed in the opening of the fourth resist layer 31d. The second circuit layer 33b is electrically connected to the first circuit layer 33a through the first conductive block 34a.

As shown in FIG. 3I, a fourth resist layer 31e is covered on the fourth resist layer 31d and the second wiring layer 33b, and the fifth resist layer 31e is patterned to form a plurality of exposed portions of the second circuit layer. The opening of 33b. Then, a second conductive block 34b is formed in the opening of the fifth resistive layer 31e, wherein the second conductive block 34b is electrically connected to the second wiring layer 33b.

As shown in FIG. 3J, the fifth resistive layer 31e and the fourth resistive layer 31d are removed, and the second wiring layer 33b and the second conductive bump 34b are exposed.

As shown in Fig. 3K, the carrier board 30 is removed, and a portion of the first wiring layer 33a is exposed to form an interposer substrate of the present invention. In addition, the central portion of the carrier plate may be removed by etching, and a frame-type carrier plate is formed around the portion of the carrier plate, and the frame-type carrier plate remaining on the first dielectric material layer is used as an intermediate substrate. supporting structure.

Referring to FIG. 3K, the interposer substrate of the present invention comprises: a first dielectric material layer 32a, a second dielectric material layer 32b, a first wiring layer 33a, a second wiring layer 33b, a first conductive block 34a, and a first Two conductive blocks 34b.

The second dielectric material layer 32b has a first surface 321b and a second surface 322b opposite to each other.

The first circuit layer 33a has a first surface 331a and a second surface 332a opposite to each other.

The first circuit layer 33a is embedded in the second dielectric material layer 32b, and the first surface 331a of the first circuit layer 33a is flush with the first surface 321b of the second dielectric material layer 32b.

The first dielectric material layer 32a is formed on the first surface 321b of the second dielectric material layer 32b, and the first dielectric material layer 32a has a plurality of openings to expose a portion of the first wiring layer 33a. The partially exposed first circuit layer 33a is, for example, a plurality of pads for external electronic components (such as semiconductor packages) to be connected and electrically connected to the pads through conductive members such as solder balls.

The first conductive block 34a has a first end surface 341a and a second end surface 342a. The first end surface 341a of the first conductive block 34a is connected to the first line. The second surface 332a of the first layer of the first conductive layer 34a is flush with the second surface 322b of the second layer of dielectric material 32b.

The second circuit layer 33b has a first surface 331b and a second surface 332b opposite to each other. The second circuit layer 33b is formed on the second surface 322b of the second dielectric material layer 32b, and a portion of the second circuit layer The first surface 331b of the 33b is connected to the second end surface 342a of the first conductive block 34a.

A plurality of second conductive blocks 34b are formed on the second surface 332b of the second circuit layer 33b, and the second conductive block 34b is exposed to the outside.

4A-4B is a cross-sectional view showing a second embodiment of the method for fabricating the interposer substrate of the present invention.

As shown in FIG. 4A, after the fifth resistive layer and the fourth resistive layer are removed in FIG. 3J, and the second wiring layer 33b and the second conductive bump 34b are exposed, the second dielectric material is exposed. The layer 32b, the second circuit layer 33b and the second conductive block 34b are covered with an insulating protective layer 35.

As shown in FIG. 4B, a portion of the insulating protective layer 35 is removed to expose the second conductive block 34b, that is, at least the end portion of the second conductive block 34b away from the second circuit layer 33b is exposed to the outside, and The carrier plate 30 is removed, and the first dielectric material layer 32a and a portion of the first circuit layer 33a are exposed.

Please also refer to FIGS. 5A to 5I, which are schematic views of a third embodiment of the intermediate substrate manufacturing method of the present invention.

As shown in FIG. 5A, a carrier 50 is provided, and a patterned first dielectric material layer 52a is formed on the surface of the carrier 50, and the first dielectric material layer 52a is formed with a plurality of exposed portions. The carrier plate 50.

As shown in FIG. 5B, a patterned first resist layer 51a is formed on the carrier 50 and the first dielectric material layer 52a, and the patterned first resistor is formed. The layer 51a is formed with a plurality of openings to expose the carrier plate 50 and a portion of the first dielectric material layer 52a. A first wiring layer 53a is then formed in the opening of the first resist layer 51a. The first resistive opening exposing the carrier plate corresponds to the opening of the previous first dielectric material layer.

As shown in FIG. 5C, a patterned second resist layer 51b is formed on the first resist layer 51a and the first wiring layer 53a, and the second resist layer 51b is formed with a plurality of exposed portions. The opening of layer 53a. Then, a first conductive block 54a is formed in the opening of the second resist layer 51b, and the first conductive block 54a is electrically connected to the first circuit layer 53a. Wherein the second resist opening corresponds to the previous first resist opening.

As shown in FIG. 5D, the second resist layer 51b and the first resist layer 51a are removed, and the first dielectric material layer 52a, the first wiring layer 53a, and the first conductive bump 54a are exposed.

As shown in FIG. 5E, the first dielectric material layer 52a, the first circuit layer 53a, and the first conductive block 54a are covered with a second dielectric material layer 52b, and the first conductive block 54a is out of the end surface. The second dielectric material layer 52b is exposed.

As shown in FIG. 5F, a patterned third resist layer 51c is formed on the second dielectric material layer 52b, and the third resist layer 51c is formed with an opening to expose the first conductive block 54a and a portion thereof. A second dielectric material layer 52b. Then, a second wiring layer 53b is formed in the opening of the third resistive layer 51c, and the second wiring layer 53b is electrically connected to the first conductive bump 54a.

As shown in FIG. 5G, a patterned fourth resist layer 51d is formed on the third resist layer 51c and the second wiring layer 53b, and the fourth resist layer 51d is formed with a plurality of openings to expose the second line. Layer 53b. Followed by the fourth A second conductive block 54b is formed in the opening of the resist layer 51d, and the second conductive block 54b is electrically connected to the second circuit layer 53b.

As shown in FIG. 5H, the fourth resistive layer 51d and the third resistive layer 51c are removed, and the second wiring layer 53b and the second conductive bump 54b are exposed.

As shown in FIG. 5I, the carrier 50 is removed, and the first dielectric material layer 52a and a portion of the first wiring layer 53a are exposed to form an interposer substrate of the present invention. In addition, the central portion of the carrier plate may be removed by etching, and the surrounding portion of the carrier plate may be retained to form a frame type carrier plate as an intermediate substrate supporting structure.

Referring to FIG. 5I, the interposer substrate of the present invention comprises: a first dielectric material layer 52a, a second dielectric material layer 52b, a first wiring layer 53a, a second wiring layer 53b, a first conductive block 54a, and a first Two conductive blocks 54b.

The first dielectric material layer 52a has an opposite first surface 521a, a second surface 522a, and a plurality of openings extending through the first surface 521a and the second surface 522a.

The first circuit layer 53a has an opposite first surface 531a and a second surface 532a, wherein a portion of the first circuit layer 53a is formed on the second surface 522a of the first dielectric material layer 52a, and a portion of the first circuit layer 53a Formed in the opening of the first dielectric material layer 52a such that the first surface 531a of the portion of the first wiring layer 53a exposes the first dielectric material layer 52a and the first dielectric material layer 52a The first surface 521a is flush. The partially exposed first circuit layer 53a is, for example, a plurality of pads for external electronic components (such as semiconductor packages) to be connected and electrically connected to the pads through conductive elements such as solder balls.

The first conductive block 54a is formed on the second surface 532a of the first circuit layer 53a to electrically connect the first circuit layer 53a.

The second dielectric material layer 52b covers the second surface 522a of the first dielectric material layer 52a and the second surface 532a of the first circuit layer 53a, and covers the first conductive block 54a, and The second conductive material layer 52b is exposed outside the end of the first conductive block 54a.

The second circuit layer 53b is formed on the second dielectric material layer 52b and electrically connected to the first conductive block 54a.

The second conductive block 54b is formed on the second circuit layer 53b, and the second conductive block 54b is exposed to the outside.

6A to 6B are cross-sectional views showing a fourth embodiment of the method for fabricating the interposer substrate of the present invention.

As shown in FIG. 6A, after the fourth resistive layer and the third resistive layer are removed in FIG. 5H, and the second wiring layer 53b and the second conductive bump 54b are exposed, the second dielectric material is exposed. The layer 52b, the second wiring layer 53b and the second conductive block 54b are covered with an insulating protective layer 55.

As shown in FIG. 6B, a portion of the insulating protective layer 55 is removed, and the second conductive block 54b is exposed, that is, at least the end of the second conductive block 54b away from the second wiring layer 53b is exposed to the outside, and The carrier plate 50 is removed, and the first dielectric material layer 52a and a portion of the first circuit layer 53a are exposed.

Therefore, the interposer substrate of the present invention and the method for manufacturing the same are first formed by etching a recess on a carrier plate to fill a dielectric material in the recess to form a first dielectric material layer, or to form a pattern on the carrier board. a first dielectric material layer, and a first circuit layer, a first conductive block, and a second dielectric material layer are sequentially formed on the carrier plate and the first dielectric material layer, and the first circuit layer is formed And the first conductive block is embedded in the second dielectric material layer, and then the second dielectric A second circuit layer and a second conductive block are formed on the material layer to form a coreless and fine circuit interposer substrate, thereby achieving the purpose of lightening and thinning the product, and the invention can also solve the line width of the line in the conventional process. The /line spacing (L/S) design is limited. Moreover, the process only exposes a portion of the first circuit layer for external electronic components, and an additional insulating layer (solderproof layer) is required, and an additional conductive layer is not required to reduce the process and cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

32a‧‧‧First dielectric material layer

33a‧‧‧First line layer

34a‧‧‧First conductive block

32b‧‧‧Second dielectric material layer

33b‧‧‧second circuit layer

34b‧‧‧Second conductive block

321b‧‧‧ first surface

322b‧‧‧ second surface

331a‧‧‧ first surface

332a‧‧‧ second surface

331b‧‧‧ first surface

332b‧‧‧ second surface

341a‧‧‧ first end

342a‧‧‧second end face

Claims (19)

The method for manufacturing an intermediate substrate comprises: forming a plurality of grooves on a surface of a carrier plate and forming a first dielectric material layer in the groove; forming a first circuit layer on the carrier plate and the first dielectric material layer; Forming a plurality of first conductive blocks on the first circuit layer; covering the first circuit layer and the first conductive block with a second dielectric material layer, exposing the second conductive body to the end of the first conductive block Forming a second circuit layer on the second dielectric material layer to electrically connect the second circuit layer to the first conductive block; forming a second conductive block on the second circuit layer, and the The ends of the two conductive blocks away from the second circuit layer are exposed to the outside; and the carrier plate is removed. The method of manufacturing the interposer according to claim 1, wherein the groove is formed by forming a first resist layer on the carrier plate, and the first resist layer is formed with a plurality of external exposed regions. Opening, the portion of the carrier plate not covered by the first resist layer is removed by etching to form a plurality of grooves on the surface of the carrier plate. The method of fabricating the interposer according to claim 1, wherein the first circuit layer is formed by forming a second resist layer on the carrier and the first dielectric material layer, the second resist layer The first dielectric material layer and a portion of the carrier plate are formed with a plurality of exposed portions, and a first circuit layer is formed in the second barrier layer opening. The method of manufacturing the interposer according to claim 3, wherein the first conductive block is formed by forming a third resist layer on the first circuit layer and the second resist layer, the third resist layer Forming a plurality of openings exposing a portion of the first circuit layer, and forming a first conductive block in the third barrier layer opening. The method for fabricating an interposer according to claim 1, wherein the second circuit layer is formed by forming a fourth resist layer on the second dielectric material layer, the fourth resist layer being formed with a plurality of layers Exposing the opening of the first conductive block and a portion of the second dielectric material layer, and forming a second circuit layer in the fourth resistive layer opening, so that the second circuit layer is electrically connected to the first conductive block to The first circuit layer. The method of manufacturing the interposer according to claim 5, wherein the second conductive block is formed on the fourth resist layer and the second circuit layer to form a fifth resist layer, the fifth resist layer Forming a plurality of openings for exposing a portion of the second circuit layer, and forming a second conductive block in the opening of the fifth resist layer to electrically connect the second conductive block to the second circuit layer. The method of manufacturing the interposer according to claim 1, wherein before the removing the carrier, the second dielectric material layer, the second circuit layer and the second conductive block are formed to form an external exposed surface. An insulating protective layer of the second conductive block. The method for fabricating an interposer includes: forming a first dielectric material layer on a carrier plate, wherein the first dielectric material layer is formed with a plurality of openings to expose the carrier plate; and the carrier plate and the first dielectric material layer Forming the first line a layer, a portion of the first circuit layer is formed in the opening of the dielectric material layer, a portion of the first circuit layer is formed on the dielectric material layer; a plurality of first conductive blocks are formed on the first circuit layer; The first dielectric material layer, the first circuit layer, and the first conductive block are covered with a second dielectric material layer, such that the first conductive block end surface exposes the second dielectric material layer; Forming a second circuit layer on the layer of the electrical material, the second circuit layer is electrically connected to the first conductive block; forming a plurality of second conductive blocks on the second circuit layer, and the second conductive block is away from the second The end of the circuit layer is exposed to the outside; and the carrier is removed. The method for fabricating an interposer according to claim 8 , wherein the first circuit layer is formed by forming a first resist layer on the carrier and the first dielectric material layer, the first resist layer The carrier plate and the first dielectric material layer are exposed except for the plurality of openings, and the first circuit layer is formed in the first barrier layer opening. The method of fabricating the interposer according to claim 9 , wherein the first conductive block is formed by forming a second resist layer on the first resist layer and the first circuit layer, the second resist layer Forming a plurality of openings exposing the first circuit layer, forming a first conductive block in the second resist layer opening, and electrically connecting the first conductive block to the first circuit layer. The method for fabricating an interposer according to claim 8, wherein the second circuit layer is formed by forming a third resist layer on the second dielectric material layer, the third resist layer being formed with a plurality of layers Exposing the first guide An opening of the electrical block and the second dielectric material layer, a second circuit layer is formed in the third resistive layer opening, and the second circuit layer is electrically connected to the first conductive block. The method of manufacturing the interposer according to claim 11, wherein the second conductive block is formed on the third resist layer and the second circuit layer to form a fourth resistive layer, the fourth resistive layer Forming a plurality of openings exposing the second circuit layer, forming a second conductive block in the fourth resistive opening, and electrically connecting the second conductive block to the second circuit layer. The method of manufacturing the interposer according to claim 8 , wherein before the removing the carrier, the second dielectric material layer, the second circuit layer and the second conductive block are formed to form an external exposed surface. An insulating protective layer of the second conductive block. An interposer substrate comprising: a second dielectric material layer having opposite first and second surfaces; a first circuit layer having opposite first and second surfaces, the first circuit layer being embedded Buried in the second dielectric material layer, the first surface of the first circuit layer is flush with the first surface of the second dielectric material layer; a first dielectric material layer is formed on the second dielectric layer The first dielectric material layer has a plurality of openings exposing the first circuit layer on the first surface of the electrical material layer; the plurality of first conductive blocks having opposite first and second end faces, the first conductive block Embedded in the second dielectric material layer, and the first end surface thereof is connected to the second surface of the first circuit layer, the second end surface is The second surface of the second dielectric material layer is flush; the second circuit layer has opposite first and second surfaces, and the second circuit layer is formed on the second surface of the second dielectric material layer And the first surface of the second circuit layer is connected to the second end surface of the first conductive block; and the plurality of second conductive blocks are formed on the second surface of the second circuit layer, and the second conductive The end of the block away from the second circuit layer is exposed to the outside. The interposer substrate of claim 14, further comprising a frame type carrier plate formed on the first surface of the first dielectric material layer. The interposer substrate of claim 14, wherein the first circuit layer portion exposing the first dielectric material layer is a solder pad for external electronic components to be connected through the conductive component and electrically connected to The pad. An interposer includes: a first dielectric material layer having a first surface, a second surface, and a plurality of openings extending through the first surface and the second surface; a first circuit layer, a portion of the first a circuit layer is formed on the second surface of the first dielectric material layer, and the remaining portion of the first circuit layer is formed in the opening of the first dielectric material layer and exposed to the first dielectric material layer a first surface; a plurality of first conductive blocks formed on the first circuit layer; a second dielectric material layer covering the second surface of the first dielectric material layer and the first circuit layer And covering the first conductive block, and exposing the second dielectric material layer to the end of the first electrical block; a second circuit layer is formed on the second dielectric material layer and electrically connected to the first conductive block; and a plurality of second conductive blocks are formed on the second circuit layer, and the second The end of the conductive block away from the second circuit layer is exposed to the outside. The interposer substrate of claim 17 further comprising a frame-type carrier plate formed on the first surface of the first dielectric material layer. The interposer substrate of claim 17, wherein the first circuit layer portion exposing the first dielectric material layer is a solder pad for external electronic components to be connected and electrically connected to the conductive component The pad.