TWI553696B - Plasma processing device and its substrate DC bias voltage measurement method - Google Patents

Plasma processing device and its substrate DC bias voltage measurement method Download PDF

Info

Publication number
TWI553696B
TWI553696B TW103142793A TW103142793A TWI553696B TW I553696 B TWI553696 B TW I553696B TW 103142793 A TW103142793 A TW 103142793A TW 103142793 A TW103142793 A TW 103142793A TW I553696 B TWI553696 B TW I553696B
Authority
TW
Taiwan
Prior art keywords
power
radio frequency
clock
bias voltage
substrate
Prior art date
Application number
TW103142793A
Other languages
Chinese (zh)
Other versions
TW201532111A (en
Inventor
Jie Liang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of TW201532111A publication Critical patent/TW201532111A/en
Application granted granted Critical
Publication of TWI553696B publication Critical patent/TWI553696B/en

Links

Landscapes

  • Plasma Technology (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Description

等離子體處理裝置及其基片直流偏置電壓測量方法 Plasma processing device and substrate DC bias voltage measuring method thereof

本發明涉及等離子體處理技術領域,尤其涉及一種監控基片表面直流偏置電壓的技術領域。 The present invention relates to the field of plasma processing technologies, and in particular, to a technical field of monitoring a DC bias voltage on a surface of a substrate.

在等離子體處理工藝過程中,常採用靜電卡盤(Electro Static Chuck,簡稱ESC)來固定、支撐及傳送基片(Wafer)等待加工件。靜電卡盤設置於反應腔室中,其採用靜電引力的方式,而非機械方式來固定基片,可減少對基片可能的機械損失,並且使靜電卡盤與基片完全接觸,有利於熱傳導。反應過程中,向反應腔室通入反應氣體,並對反應腔施加射頻功率,通常射頻功率施加到靜電卡盤下方的導體基座上,射頻功率主要包括射頻源功率和射頻偏置功率,射頻源功率和射頻偏置功率共同作用,將反應氣體電離生成等離子體,等離子體與基片進行等離子體反應,完成對基片的工藝處理。在這一過程中,由於等離子體的特性及反應腔內的一些參數條件,基片表面會產生直流偏置電壓,該直流偏壓的大小代表等離子體的一些狀態,直流偏壓的大小發生變化意味著反應腔內的等離子體狀態發生變化,因此需要對其進行監控。 In the plasma processing process, Electro Static Chuck (ESC) is often used to fix, support and transfer the substrate (Wafer) to the workpiece. The electrostatic chuck is disposed in the reaction chamber, and the electrostatic chucking method is used instead of mechanically fixing the substrate, which can reduce the possible mechanical loss to the substrate and completely contact the electrostatic chuck with the substrate, thereby facilitating heat conduction. . During the reaction, a reaction gas is introduced into the reaction chamber, and RF power is applied to the reaction chamber. Usually, the RF power is applied to the conductor base under the electrostatic chuck. The RF power mainly includes the RF source power and the RF bias power, and the RF The source power and the RF bias power work together to ionize the reaction gas to generate a plasma, and the plasma and the substrate undergo a plasma reaction to complete the processing of the substrate. In this process, due to the characteristics of the plasma and some parameter conditions in the reaction chamber, a DC bias voltage is generated on the surface of the substrate. The magnitude of the DC bias represents some states of the plasma, and the magnitude of the DC bias changes. This means that the state of the plasma in the reaction chamber changes and therefore needs to be monitored.

正常狀態下,射頻功率源和射頻偏置功率源的輸出恒定,基片表面的直流偏置電壓相對較穩定,可以直接對其進行信號採集,實現對基片表面直流偏置電壓的監控。然而在某些應用中,需要設置射頻功率源 或者射頻偏置功率源的輸出為脈衝輸出,所述基片表面的直流偏置電壓會隨著射頻源功率或射頻偏置功率的輸出大小改變而發生變化,為了實現對直流偏置電壓的監控,等離子體反應裝置需要增大對直流偏置電壓的採樣頻率,對於需要以年為單位記錄資料的設備來說勢必會浪費很大的資料空間,同時增加了監控難度。給現有的等離子體處理裝置增加負擔。 Under normal conditions, the output of the RF power source and the RF bias power source is constant, and the DC bias voltage on the surface of the substrate is relatively stable. The signal can be directly collected to monitor the DC bias voltage on the surface of the substrate. However, in some applications, RF power sources need to be set up. Or the output of the RF bias power source is a pulse output, and the DC bias voltage of the surface of the substrate changes according to the output of the RF source power or the RF bias power, in order to monitor the DC bias voltage. The plasma reaction device needs to increase the sampling frequency of the DC bias voltage, which is a waste of a large data space for the device that needs to record data in units of years, and increases the difficulty of monitoring. Adding a burden to existing plasma processing equipment.

為了解決上述技術問題,本發明提供一種等離子體處理裝置,包括一真空反應腔,所述真空反應腔下方設置一支撐基片的靜電卡盤,所述靜電卡盤下方設置一基座,所述基座同時作為所述真空反應腔的下電極,所述下電極連接射頻功率源,所述射頻功率源輸出脈衝功率,所述基片下方設置一直流偏置電壓探測針,所述探測針連接一時鐘觸發開關,所述時鐘觸發開關的後端分別連接高電位積分電路和低電位積分電路。 In order to solve the above problems, the present invention provides a plasma processing apparatus including a vacuum reaction chamber, an electrostatic chuck supporting a substrate is disposed under the vacuum reaction chamber, and a susceptor is disposed under the electrostatic chuck. The pedestal serves as a lower electrode of the vacuum reaction chamber, the lower electrode is connected to a radio frequency power source, the radio frequency power source outputs pulse power, and a DC bias voltage detecting pin is disposed under the substrate, and the probe pin is connected. A clock trigger switch, the back end of the clock trigger switch is respectively connected to a high potential integration circuit and a low potential integration circuit.

優選的,所述射頻功率包括射頻源功率與射頻偏置功率,所述射頻源功率或射頻偏置功率至少一個輸出脈衝功率。 Preferably, the radio frequency power comprises radio frequency source power and radio frequency bias power, and the radio frequency source power or radio frequency offset power is at least one output pulse power.

優選的,所述射頻功率的脈衝頻率和所述時鐘觸發開關的時鐘頻率相同。 Preferably, the pulse frequency of the radio frequency power is the same as the clock frequency of the clock trigger switch.

優選的,所述射頻源功率的輸出為脈衝信號,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的低電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的高電位積分電路相連。 Preferably, the output of the radio frequency source power is a pulse signal, and the pulse signal is used as a clock signal of the clock trigger switch. When the output pulse signal of the radio frequency power is a rising edge, the clock triggers the switch and the back end. The low potential integration circuit is connected, and when the output signal is a falling edge, the clock trigger switch is connected to the high potential integration circuit at the back end.

優選的,所述射頻偏置功率的輸出為脈衝信號時,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號為 上升沿時,所述時鐘觸發開關與後端的高電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的低電位積分電路相連。 Preferably, when the output of the radio frequency offset power is a pulse signal, the pulse signal is used as a clock signal of the clock trigger switch, and the output pulse signal of the radio frequency power is At the rising edge, the clock trigger switch is connected to the high potential integration circuit of the back end, and when the output signal is a falling edge, the clock trigger switch is connected to the low potential integration circuit of the back end.

優選的,所述射頻源功率和所述射頻偏置功率的輸出均為脈衝信號時,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的高電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的低電位積分電路相連。 Preferably, when the output of the radio frequency source power and the radio frequency offset power are both pulse signals, the pulse signal is used as a clock signal of the clock trigger switch, and the output pulse signal of the radio frequency power is a rising edge. The clock trigger switch is connected to a high potential integration circuit at the back end. When the output signal is a falling edge, the clock trigger switch is connected to a low potential integration circuit at the back end.

優選的,所述射頻偏置功率的頻率範圍為400KHz至13.56MHz,所述射頻源功率的頻率範圍為27MHz至120MHz。 Preferably, the frequency of the radio frequency bias power ranges from 400 kHz to 13.56 MHz, and the frequency of the radio frequency source power ranges from 27 MHz to 120 MHz.

優選的,所述射頻偏置功率和所述射頻源功率的脈衝頻率範圍為50Hz至10KHz,工作比範圍為10%至90%。 Preferably, the radio frequency offset power and the radio frequency source power have a pulse frequency ranging from 50 Hz to 10 KHz, and the working ratio ranges from 10% to 90%.

進一步的,本發明還公開了一種測量等離子體處理裝置內基片表面直流偏置電壓的方法,包括下列步驟:將一探測直流偏置電壓的探測針放置在所述基片表面,所述探測針後端連接一時鐘觸發開關,所述時鐘觸發開關後端分別連接一高電位積分電路和一低電位積分電路;調節所述射頻功率的輸出脈衝信號頻率;將所述脈衝輸出信號頻率作為所述時鐘觸發開關的調節頻率,當所述射頻功率的輸出脈衝信號為上升沿或者下降沿時,所述時鐘觸發開關分別連接到所述高電位積分電路或者低電位積分電路,所述高電位積分電路或者低電位積分電路分別對所述探測針探測到的直流偏置電壓的高電位脈衝和低電位脈衝進行積分,得到直流偏置電壓在高電位時的平均值和低電位時的平均值,再分別對其進行信號採集,實現對基片表面直流偏置電壓的監測。 Further, the present invention also discloses a method for measuring a DC bias voltage of a surface of a substrate in a plasma processing apparatus, comprising the steps of: placing a probe for detecting a DC bias voltage on a surface of the substrate, the detecting a clock trigger switch is connected to the rear end of the pin, and a high potential integration circuit and a low potential integration circuit are respectively connected to the rear end of the clock trigger switch; the output pulse signal frequency of the RF power is adjusted; and the pulse output signal frequency is used as a The clock trigger switch adjusts the frequency. When the output pulse signal of the RF power is a rising edge or a falling edge, the clock trigger switch is respectively connected to the high potential integration circuit or the low potential integration circuit, and the high potential integration The circuit or the low potential integration circuit respectively integrates the high potential pulse and the low potential pulse of the DC bias voltage detected by the probe, and obtains an average value of the DC bias voltage at a high potential and an average value at a low potential. Then separately collect signals to realize the monitoring of the DC bias voltage on the surface of the substrate.

優選的,對所述直流偏置電壓在高電位時的平均值和低電位時的平均值的採樣時間間隔大於等於0.1s。 Preferably, the sampling time interval between the average value of the DC bias voltage at a high potential and the average value at a low potential is greater than or equal to 0.1 s.

本發明的優點在於:通過一脈衝觸發開關分離脈衝開-關狀態下的直流偏置電壓,所述時鐘觸發開關後端連接一高電位積分電路和一低電位積分電路,所述時鐘觸發開關以時脈信號的上升沿和下降沿為信號進行切換,分別與後端的高電位積分電路或者低電位積分電路進行連接,實現將直流偏置電壓分別在較高值和較低值時積分求平均值得到連續類比信號,從而實現對基片表面直流偏置電壓的監測。通過採用本發明所述的技術方案,可以大大降低採樣頻率,簡化採樣電路。 The invention has the advantages that the DC bias voltage in the pulse on-off state is separated by a pulse trigger switch, and the clock trigger switch is connected to a high potential integration circuit and a low potential integration circuit, and the clock trigger switch is The rising edge and the falling edge of the clock signal switch the signal, and are respectively connected with the high-potential integration circuit or the low-potential integration circuit at the back end to realize the integration of the DC bias voltage at a higher value and a lower value respectively. Continuous analog signal to monitor the DC bias voltage on the substrate surface. By adopting the technical solution described in the present invention, the sampling frequency can be greatly reduced, and the sampling circuit can be simplified.

10‧‧‧探測針 10‧‧‧ probe needle

20‧‧‧時鐘觸發開關 20‧‧‧clock trigger switch

30‧‧‧高電位積分電路 30‧‧‧High potential integration circuit

40‧‧‧低電位積分電路 40‧‧‧Low potential integration circuit

60‧‧‧支撐基片 60‧‧‧Support substrate

100‧‧‧真空反應腔 100‧‧‧vacuum reaction chamber

110‧‧‧靜電卡盤 110‧‧‧Electrostatic chuck

130‧‧‧射頻源功率 130‧‧‧RF source power

140‧‧‧射頻偏置功率 140‧‧‧RF bias power

第1圖,為本發明所述等離子體處理裝置的結構示意圖。 Fig. 1 is a schematic view showing the structure of a plasma processing apparatus according to the present invention.

第2圖,為本發明射頻源功率為脈衝輸出時直流偏置電壓的脈衝示意圖。 Fig. 2 is a schematic diagram showing the pulse of the DC bias voltage when the power of the RF source is pulse output according to the present invention.

第3圖,為本發明射頻偏置功率為脈衝輸出時直流偏置電壓的脈衝示意圖。 Fig. 3 is a schematic diagram showing the pulse of the DC bias voltage when the RF bias power is a pulse output according to the present invention.

第4圖,為本發明射頻源功率和射頻偏置功率均為脈衝輸出時直流偏置電壓的脈衝示意圖。 Fig. 4 is a schematic diagram showing the pulse of the DC bias voltage when the RF source power and the RF bias power are pulse output according to the present invention.

第5圖,為本發明直流偏置電壓的探測裝置示意圖。 Fig. 5 is a schematic view showing the detecting device of the DC bias voltage of the present invention.

本發明公開了一種等離子體處理裝置及其測量基片直流偏置電壓的方法,為使本發明的上述目的、特徵和優點能夠更為明顯易懂,下面結合附圖和實施例對本發明的具體實施方式做詳細的說明。 The present invention discloses a plasma processing apparatus and a method for measuring a DC bias voltage of a substrate. The above objects, features and advantages of the present invention can be more clearly understood. The specific embodiments of the present invention are described below with reference to the accompanying drawings and embodiments. The embodiment will be described in detail.

第1圖示出本發明所述等離子體處理裝置的結構示意圖,所 述等離子體處理裝置包括一真空反應腔100,真空反應腔100下方設置一支撐基片60的靜電卡盤110,靜電卡盤110下方設置一基座120,基座120同時作為所述真空反應腔100的下電極,下電極120連接射頻功率源,所述射頻功率包括射頻源功率130和射頻偏置功率140,射頻源功率130和射頻偏置功率140至少有一個輸出脈衝功率。反應氣體源中的反應氣體經過同時作為氣體噴淋頭的上電極進入真空反應腔100內,在射頻功率的作用下解離生成等離子體,對基片進行等離子體處理,完成刻蝕工藝。等離子體在對基片進行處理時由於等離子體的特性,會在基片表面產生直流偏置電壓,所述直流偏置電壓的大小反應了等離子體的一些參數狀態,如果直流偏置電壓大小發生變化,說明反應腔內的等離子體狀態發生了變化,需要予以調節,以免影響等離子體工藝進程。另外,基片60表面的直流偏壓還決定了所述靜電卡盤110上施加的直流電壓大小,所述直流電壓的大小決定了靜電卡盤對基片60的靜電吸力,靜電卡盤上的直流電壓會被基片表面的直流偏置電壓抵消,如果不對直流偏置電壓進行監控,進而回饋調整靜電卡盤110上的直流電壓,會導致靜電卡盤110對基片的靜電吸力不足導致基片脫離靜電吸盤的固定。造成工藝處理事故。 1 is a schematic view showing the structure of a plasma processing apparatus according to the present invention. The plasma processing apparatus includes a vacuum reaction chamber 100. An electrostatic chuck 110 supporting a substrate 60 is disposed under the vacuum reaction chamber 100. A susceptor 120 is disposed under the electrostatic chuck 110. The susceptor 120 serves as the vacuum reaction chamber at the same time. The lower electrode of the 100 is connected to a radio frequency power source. The radio frequency power includes a radio frequency source power 130 and a radio frequency bias power 140. The radio frequency source power 130 and the radio frequency bias power 140 have at least one output pulse power. The reaction gas in the reaction gas source enters the vacuum reaction chamber 100 through the upper electrode as a gas shower head, dissociates the generated plasma under the action of the radio frequency power, and performs plasma treatment on the substrate to complete the etching process. When the plasma is processed on the substrate, due to the characteristics of the plasma, a DC bias voltage is generated on the surface of the substrate, and the magnitude of the DC bias voltage reflects some parameter states of the plasma, if the DC bias voltage occurs. The change indicates that the plasma state in the reaction chamber has changed and needs to be adjusted to avoid affecting the plasma process. In addition, the DC bias voltage on the surface of the substrate 60 also determines the magnitude of the DC voltage applied to the electrostatic chuck 110. The magnitude of the DC voltage determines the electrostatic attraction of the electrostatic chuck to the substrate 60, and the electrostatic chuck. The DC voltage is offset by the DC bias voltage on the surface of the substrate. If the DC bias voltage is not monitored and the DC voltage on the electrostatic chuck 110 is fed back, the electrostatic chuck of the electrostatic chuck 110 will be insufficient. The piece is detached from the electrostatic chuck. Cause process accidents.

正常狀態下,射頻功率源和射頻偏置功率源的輸出恒定,基片表面的直流偏置電壓相對較穩定,可以直接對其進行信號採集,實現對基片表面直流偏置電壓的監控。然而在本發明所述應用中,需要設置射頻功率源或者射頻偏置功率源的輸出為脈衝輸出,而對應時刻的基片表面直流偏置電壓會隨著射頻輸出的脈衝變化發生變化,當脈衝頻率為50Hz至10kHz,如果直接對該頻率範圍下的射頻輸出對應的基片表面的直流偏置電 壓進行採樣,需要非常高的採樣頻率,由於等離子體處理裝置一直處於工作狀態,所以採樣結果需要一直記錄,對於需要以年為單位記錄資料的刻蝕設備來說勢必浪費很大的資料空間,同時增加了監控難度。給現有的等離子體處理裝置增加負擔。 Under normal conditions, the output of the RF power source and the RF bias power source is constant, and the DC bias voltage on the surface of the substrate is relatively stable. The signal can be directly collected to monitor the DC bias voltage on the surface of the substrate. However, in the application of the present invention, the output of the RF power source or the RF bias power source needs to be set as a pulse output, and the DC bias voltage of the substrate surface at the corresponding time changes with the pulse change of the RF output, when the pulse The frequency is 50Hz to 10kHz, if the direct current bias of the substrate surface corresponding to the RF output in the frequency range is directly Sampling requires very high sampling frequency. Since the plasma processing device is always in working state, the sampling result needs to be recorded all the time. It is a waste of a large data space for the etching equipment that needs to record data in units of years. At the same time, it increases the difficulty of monitoring. Adding a burden to existing plasma processing equipment.

本申請發明人通過大量的資料獲取和研究發現,直流偏置電壓隨著射頻功率脈衝輸出的變化進行週期性變化,第2圖到第4圖示出直流偏置電壓隨射頻功率的源功率和偏置功率變化的示意圖,由第2圖中可以看出,當射頻源功率為脈衝輸出,射頻偏置功率為恒定輸出時,基片表面直流偏置電壓大小也為脈衝狀,並且當射頻源功率的輸出脈衝信號為上升沿時,直流偏置電壓的大小為下降沿,當射頻源功率的輸出脈衝信號為下降沿時,直流偏置電壓的大小為上升沿。由第3圖中可以看出,當射頻源功率為恒定輸出,射頻偏置功率為脈衝輸出時,基片表面直流偏置電壓大小也為脈衝狀,並且當射頻偏置功率的輸出脈衝信號為上升沿時,直流偏置電壓的大小為上升沿,當射頻偏置功率的輸出脈衝信號為下降沿時,直流偏置電壓的大小為下降沿。由第4圖中可以看出,當射頻源功率和射頻偏置功率同為脈衝輸出時,基片表面直流偏置電壓大小也為脈衝狀,並且當射頻偏置功率的輸出脈衝信號為上升沿時,直流偏置電壓的大小為上升沿,當射頻偏置功率的輸出脈衝信號為下降沿時,直流偏置電壓的大小為下降沿。由上述附圖可以看出,基片表面的直流偏置電壓的脈衝變化頻率與射頻功率的脈衝輸出頻率相同,利用該特點,第5圖示出本發明探測直流偏置電壓的技術方案。 The inventors of the present application have found through a large amount of data acquisition that the DC bias voltage periodically changes with the change of the RF power pulse output, and FIG. 2 to FIG. 4 show the DC bias voltage with the source power of the RF power. Schematic diagram of the bias power variation, as can be seen from Figure 2, when the RF source power is pulse output and the RF bias power is constant output, the DC bias voltage on the substrate surface is also pulsed, and when the RF source When the output pulse signal of the power is a rising edge, the magnitude of the DC bias voltage is a falling edge. When the output pulse signal of the RF source power is a falling edge, the magnitude of the DC bias voltage is a rising edge. It can be seen from Fig. 3 that when the RF source power is constant output and the RF bias power is pulse output, the DC bias voltage of the substrate surface is also pulsed, and when the RF bias power output pulse signal is On the rising edge, the magnitude of the DC bias voltage is the rising edge. When the output pulse signal of the RF bias power is the falling edge, the magnitude of the DC bias voltage is the falling edge. It can be seen from Fig. 4 that when the RF source power and the RF bias power are both pulse outputs, the DC bias voltage on the surface of the substrate is also pulsed, and the output pulse signal of the RF bias power is a rising edge. When the magnitude of the DC bias voltage is a rising edge, when the output pulse signal of the RF bias power is a falling edge, the magnitude of the DC bias voltage is a falling edge. As can be seen from the above figures, the pulse change frequency of the DC bias voltage on the surface of the substrate is the same as the pulse output frequency of the RF power. With this feature, FIG. 5 shows a technical solution for detecting the DC bias voltage of the present invention.

第5圖示出本發明所述直流偏置電壓的探測裝置示意圖,在 基片60上方設置一直流偏置電壓探測針10,探測針10連接一時鐘觸發開關20,時鐘觸發開關20的後端分別連接高電位積分電路30和低電位積分電路40,所述時鐘觸發開關20受一時脈信號50控制,所述時脈信號50的頻率和所述射頻功率的脈衝信號頻率相同。在時脈信號50的控制下,當時脈信號處於上升沿或下降沿時,時鐘觸發開關20進行切換,分別與高電位積分電路30或低電位積分電路40相連。對應的高電位積分電路30和低電位積分電路40開始對該週期內的直流偏置電壓位於高電位時和低電位時分別進行積分求平均值,由於高電位積分電路30和低電位積分電路40為類比電路,可以對探測針10測得的直流偏置電壓值進行即時積分求值,再利用採樣裝置對高電位積分電路30和低電位積分電路40算出的平均值的基礎上進行高低電位採樣,可以大大降低採樣頻率,節約了等離子體處理裝置的存儲空間,提高等離子體處理裝置的工藝處理效率。 Figure 5 is a schematic view showing the detecting device of the DC bias voltage of the present invention, A DC bias voltage detecting pin 10 is disposed above the substrate 60. The detecting pin 10 is connected to a clock triggering switch 20. The rear end of the clock triggering switch 20 is connected to a high potential integrating circuit 30 and a low potential integrating circuit 40, respectively. 20 is controlled by a clock signal 50, the frequency of which is the same as the frequency of the pulse signal of the radio frequency power. Under the control of the clock signal 50, when the pulse signal is at the rising edge or the falling edge, the clock trigger switch 20 switches, and is connected to the high potential integrating circuit 30 or the low potential integrating circuit 40, respectively. The corresponding high-potential integration circuit 30 and low-potential integration circuit 40 start to integrate and average the DC bias voltage in the period at the high potential and the low potential, respectively, because the high-potential integration circuit 30 and the low-potential integration circuit 40 For the analog circuit, the DC bias voltage value measured by the probe pin 10 can be instantaneously integrated, and the sampling device can be used to perform high and low potential sampling on the basis of the average value calculated by the high potential integration circuit 30 and the low potential integration circuit 40. The sampling frequency can be greatly reduced, the storage space of the plasma processing device is saved, and the processing efficiency of the plasma processing device is improved.

具體的,考慮到射頻源功率脈衝輸出信號同一週期內高低電位與直流偏置電壓的高低電位正好相反,故當射頻源功率輸出為脈衝信號時,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻源功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的低電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的高電位積分電路相連。 Specifically, considering that the high and low potentials of the RF source power pulse output signal in the same period are opposite to the high and low potentials of the DC bias voltage, when the RF source power output is a pulse signal, when the pulse signal is used as the clock trigger switch a pulse signal, when the output pulse signal of the RF source power is a rising edge, the clock trigger switch is connected to a low potential integration circuit at the back end, and when the output signal is a falling edge, the clock triggers a high potential of the switch and the back end The integration circuit is connected.

由於射頻偏置功率脈衝輸出信號同一週期內高低電位與直流偏置電壓的高低電位相同,故所述射頻偏置功率的輸出為脈衝信號時,無論射頻源功率的輸出是否為脈衝輸出,當所述射頻偏置功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的高電位積分電路相連,所述 輸出信號為下降沿時,所述時鐘觸發開關與後端的低電位積分電路相連。 Since the high-low potential of the RF bias power pulse output signal is the same as the high-low potential of the DC bias voltage in the same period, when the output of the RF bias power is a pulse signal, regardless of whether the output of the RF source power is a pulse output, When the output pulse signal of the RF bias power is a rising edge, the clock trigger switch is connected to a high potential integration circuit at the back end, When the output signal is a falling edge, the clock trigger switch is connected to the low potential integration circuit at the back end.

本發明雖然以較佳實施例公開如上,但其並不是用來限定本發明,任何本領域技術人員在不脫離本發明的精神和範圍內,都可以做出可能的變動和修改,因此本發明的保護範圍應當以本發明權利要求所界定的範圍為准。 The present invention is disclosed in the above preferred embodiments, but it is not intended to limit the present invention, and any one skilled in the art can make possible variations and modifications without departing from the spirit and scope of the invention. The scope of protection should be determined by the scope defined by the claims of the present invention.

10‧‧‧探測針 10‧‧‧ probe needle

60‧‧‧支撐基片 60‧‧‧Support substrate

100‧‧‧真空反應腔 100‧‧‧vacuum reaction chamber

110‧‧‧靜電卡盤 110‧‧‧Electrostatic chuck

130‧‧‧射頻源功率 130‧‧‧RF source power

140‧‧‧射頻偏置功率 140‧‧‧RF bias power

Claims (6)

一種等離子體處理裝置,包括一真空反應腔,所述真空反應腔下方設置一支撐基片的靜電卡盤,所述靜電卡盤下方設置一基座,所述基座同時作為所述真空反應腔的下電極,所述下電極連接射頻功率源,所述射頻功率源輸出脈衝功率,其特徵在於:所述基片上方設置一直流偏置電壓探測針,所述探測針連接一時鐘觸發開關,所述時鐘觸發開關的後端分別連接高電位積分電路和低電位積分電路,所述射頻功率包括射頻源功率與射頻偏置功率,所述射頻源功率或射頻偏置功率至少一個輸出脈衝功率,所述射頻功率的脈衝頻率和所述時鐘觸發開關的時鐘頻率相同。 A plasma processing apparatus includes a vacuum reaction chamber, an electrostatic chuck supporting a substrate is disposed under the vacuum reaction chamber, a pedestal is disposed under the electrostatic chuck, and the pedestal serves as the vacuum reaction chamber simultaneously a lower electrode, the lower electrode is connected to a radio frequency power source, and the radio frequency power source outputs a pulse power, wherein: a constant current bias voltage detecting pin is disposed above the substrate, and the detecting pin is connected to a clock trigger switch. The rear end of the clock-triggered switch is respectively connected to a high-potential integration circuit and a low-potential integration circuit, and the radio frequency power includes a radio frequency source power and a radio frequency offset power, and the radio frequency source power or the radio frequency bias power is at least one output pulse power. The pulse frequency of the radio frequency power is the same as the clock frequency of the clock trigger switch. 一種等離子體處理裝置,包括一真空反應腔,所述真空反應腔下方設置一支撐基片的靜電卡盤,所述靜電卡盤下方設置一基座,所述基座同時作為所述真空反應腔的下電極,所述下電極連接射頻功率源,所述射頻功率源輸出脈衝功率,其特徵在於:所述基片上方設置一直流偏置電壓探測針,所述探測針連接一時鐘觸發開關,所述時鐘觸發開關的後端分別連接高電位積分電路和低電位積分電路,所述射頻功率包括射頻源功率與射頻偏置功率,所述射頻源功率或射頻偏置功率至少一個輸出脈衝功率,所述射頻源功率的輸出為脈衝信號,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的低電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的高電位積分電路相連。 A plasma processing apparatus includes a vacuum reaction chamber, an electrostatic chuck supporting a substrate is disposed under the vacuum reaction chamber, a pedestal is disposed under the electrostatic chuck, and the pedestal serves as the vacuum reaction chamber simultaneously a lower electrode, the lower electrode is connected to a radio frequency power source, and the radio frequency power source outputs a pulse power, wherein: a constant current bias voltage detecting pin is disposed above the substrate, and the detecting pin is connected to a clock trigger switch. The rear end of the clock-triggered switch is respectively connected to a high-potential integration circuit and a low-potential integration circuit, and the radio frequency power includes a radio frequency source power and a radio frequency offset power, and the radio frequency source power or the radio frequency bias power is at least one output pulse power. The output of the RF source power is a pulse signal, and the pulse signal is used as a clock signal of the clock trigger switch. When the output pulse signal of the RF power is a rising edge, the clock triggers a low potential integration of the switch and the back end. The circuit is connected, and when the output signal is a falling edge, the clock trigger switch is connected to the high potential integration circuit at the back end. 一種等離子體處理裝置,包括一真空反應腔,所述真空反應腔下方設置一支撐基片的靜電卡盤,所述靜電卡盤下方設置一基座,所述基座同時作為所述真空反應腔的下電極,所述下電極連接射頻功率源,所述射頻功率源輸出脈衝功率,其特徵在於:所述基片上方設置一直流偏置電壓探測針,所述探測針連接一時鐘觸發開關,所述時鐘觸發開關的後端分別連接高電位積分電路和低電位積分電路,所述射頻功率包括射頻源功率與射頻偏置功率,所述射頻源功率或射頻偏置功率至少一個輸出脈衝功率,所述射頻偏置功率的輸出為脈衝信號時,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號為上升沿時,所述時鐘觸發開關與後端的高電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的低電位積分電路相連。 A plasma processing apparatus includes a vacuum reaction chamber, an electrostatic chuck supporting a substrate is disposed under the vacuum reaction chamber, a pedestal is disposed under the electrostatic chuck, and the pedestal serves as the vacuum reaction chamber simultaneously a lower electrode, the lower electrode is connected to a radio frequency power source, and the radio frequency power source outputs a pulse power, wherein: a constant current bias voltage detecting pin is disposed above the substrate, and the detecting pin is connected to a clock trigger switch. The rear end of the clock-triggered switch is respectively connected to a high-potential integration circuit and a low-potential integration circuit, and the radio frequency power includes a radio frequency source power and a radio frequency offset power, and the radio frequency source power or the radio frequency bias power is at least one output pulse power. When the output of the RF bias power is a pulse signal, the pulse signal is used as a clock signal of the clock trigger switch, and when the output pulse signal of the RF power is a rising edge, the clock trigger switch and the back end are high. The potential integration circuit is connected, and when the output signal is a falling edge, the clock trigger switch and the low potential integration circuit at the back end . 一種等離子體處理裝置,包括一真空反應腔,所述真空反應腔下方設置一支撐基片的靜電卡盤,所述靜電卡盤下方設置一基座,所述基座同時作為所述真空反應腔的下電極,所述下電極連接射頻功率源,所述射頻功率源輸出脈衝功率,其特徵在於:所述基片上方設置一直流偏置電壓探測針,所述探測針連接一時鐘觸發開關,所述時鐘觸發開關的後端分別連接高電位積分電路和低電位積分電路,所述射頻功率包括射頻源功率與射頻偏置功率,所述射頻源功率或射頻偏置功率至少一個輸出脈衝功率,所述射頻源功率和所述射頻偏置功率的輸出均為脈衝信號時,所述脈衝信號作為所述時鐘觸發開關的時脈信號,所述射頻功率的輸出脈衝信號 為上升沿時,所述時鐘觸發開關與後端的高電位積分電路相連,所述輸出信號為下降沿時,所述時鐘觸發開關與後端的低電位積分電路相連。 A plasma processing apparatus includes a vacuum reaction chamber, an electrostatic chuck supporting a substrate is disposed under the vacuum reaction chamber, a pedestal is disposed under the electrostatic chuck, and the pedestal serves as the vacuum reaction chamber simultaneously a lower electrode, the lower electrode is connected to a radio frequency power source, and the radio frequency power source outputs a pulse power, wherein: a constant current bias voltage detecting pin is disposed above the substrate, and the detecting pin is connected to a clock trigger switch. The rear end of the clock-triggered switch is respectively connected to a high-potential integration circuit and a low-potential integration circuit, and the radio frequency power includes a radio frequency source power and a radio frequency offset power, and the radio frequency source power or the radio frequency bias power is at least one output pulse power. When the output of the RF source power and the RF bias power are both pulse signals, the pulse signal serves as a clock signal of the clock trigger switch, and an output pulse signal of the RF power When the rising edge is the rising edge, the clock triggering switch is connected to the high potential integrating circuit of the back end, and when the output signal is the falling edge, the clock triggering switch is connected to the low potential integrating circuit of the back end. 一種基片直流偏置電壓測量方法,其特徵在於:包括下列步驟,將一探測直流偏置電壓的探測針放置在所述基片表面,所述探測針後端連接一時鐘觸發開關,所述時鐘觸發開關後端分別連接一高電位積分電路和一低電位積分電路;調節一射頻功率的輸出脈衝信號頻率;將所述脈衝輸出信號頻率作為所述時鐘觸發開關的調節頻率,當所述射頻功率的輸出脈衝信號為上升沿或者下降沿時,所述時鐘觸發開關分別連接到所述高電位積分電路或者低電位積分電路,所述高電位積分電路或者低電位積分電路分別對所述探測針探測到的直流偏置電壓的高電位脈衝和低電位脈衝進行積分,得到直流偏置電壓在高電位時的平均值和低電位時的平均值,再分別對其進行信號採集,實現對基片表面直流偏置電壓的監測。 A method for measuring a DC bias voltage of a substrate, comprising: placing a probe for detecting a DC bias voltage on a surface of the substrate, and connecting a rear end of the probe to a clock trigger switch, a rear end of the clock trigger switch is respectively connected to a high potential integration circuit and a low potential integration circuit; adjusting an output pulse signal frequency of a radio frequency power; using the pulse output signal frequency as an adjustment frequency of the clock trigger switch, when the radio frequency When the output pulse signal of the power is a rising edge or a falling edge, the clock triggering switch is respectively connected to the high potential integrating circuit or the low potential integrating circuit, and the high potential integrating circuit or the low potential integrating circuit respectively respectively pairs the detecting pin The high-potential pulse and the low-potential pulse of the detected DC bias voltage are integrated, and the average value of the DC bias voltage at the high potential and the average value at the low potential are obtained, and then the signal is separately collected to realize the substrate. Monitoring of surface DC bias voltage. 如申請專利範圍第5項所述之基片直流偏置電壓測量方法,其特徵在於:對所述直流偏置電壓在高電位時的平均值和低電位時的平均值的採樣時間間隔大於等於0.1s。 The method for measuring a DC bias voltage of a substrate according to claim 5, wherein the sampling time interval of the average value of the DC bias voltage at a high potential and the average value at a low potential is greater than or equal to 0.1s.
TW103142793A 2013-12-17 2014-12-09 Plasma processing device and its substrate DC bias voltage measurement method TWI553696B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310695325.1A CN104715988B (en) 2013-12-17 2013-12-17 Plasma processing device and DC bias voltage measuring method for substrate of plasma processing device

Publications (2)

Publication Number Publication Date
TW201532111A TW201532111A (en) 2015-08-16
TWI553696B true TWI553696B (en) 2016-10-11

Family

ID=53415207

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103142793A TWI553696B (en) 2013-12-17 2014-12-09 Plasma processing device and its substrate DC bias voltage measurement method

Country Status (2)

Country Link
CN (1) CN104715988B (en)
TW (1) TWI553696B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107295739A (en) * 2016-04-12 2017-10-24 北京北方华创微电子装备有限公司 Produce the method and its plasma apparatus of pulsed plasma
CN114582692A (en) * 2020-11-18 2022-06-03 中微半导体设备(上海)股份有限公司 DC bias control method and plasma processing device
WO2024032432A1 (en) * 2022-08-08 2024-02-15 深圳市恒运昌真空技术有限公司 Radio frequency power supply signal acquisition method and apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432464B (en) * 1997-03-26 2001-05-01 Lam Res Corp Unbalanced bipolar electrostatic chuck power supplies and methods therefor
US20020173059A1 (en) * 2001-05-18 2002-11-21 Shawming Ma Method of real-time plasma charging voltage measurement on powered electrode with electrostatic chuck in plasma process chambers
TW520621B (en) * 2001-01-22 2003-02-11 Tokyo Electron Ltd Vertically translatable chuck assembly and method for a plasma reactor system
CN101110347A (en) * 2006-07-17 2008-01-23 应用材料公司 Double offset frequency plasma body reactor with electrostatic chuck voltage feedback control
JP2010004009A (en) * 2008-05-21 2010-01-07 Tokyo Electron Ltd Mounting table mechanism, plasma processing apparatus using the same and method of applying voltage to electrostatic chuck

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4904947A (en) * 1988-11-09 1990-02-27 Tideland Signal Corporation Method and circuit for measuring pulse width
CN102680910B (en) * 2012-05-15 2015-07-22 华为技术有限公司 Supply current detection method and circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432464B (en) * 1997-03-26 2001-05-01 Lam Res Corp Unbalanced bipolar electrostatic chuck power supplies and methods therefor
TW520621B (en) * 2001-01-22 2003-02-11 Tokyo Electron Ltd Vertically translatable chuck assembly and method for a plasma reactor system
US20020173059A1 (en) * 2001-05-18 2002-11-21 Shawming Ma Method of real-time plasma charging voltage measurement on powered electrode with electrostatic chuck in plasma process chambers
CN101110347A (en) * 2006-07-17 2008-01-23 应用材料公司 Double offset frequency plasma body reactor with electrostatic chuck voltage feedback control
JP2010004009A (en) * 2008-05-21 2010-01-07 Tokyo Electron Ltd Mounting table mechanism, plasma processing apparatus using the same and method of applying voltage to electrostatic chuck

Also Published As

Publication number Publication date
TW201532111A (en) 2015-08-16
CN104715988B (en) 2017-05-24
CN104715988A (en) 2015-06-17

Similar Documents

Publication Publication Date Title
CN109417013B (en) System and method for controlling voltage waveform at substrate during plasma processing
US10431437B2 (en) Detecting an arc occuring during supplying power to a plasma process
TWI342898B (en) Sensor array for measuring plasma characteristics in plasma processing environments
JP2019216164A5 (en)
US8502689B2 (en) System and method for voltage-based plasma excursion detection
US9745660B2 (en) Method for controlling a plasma chamber
TWI553696B (en) Plasma processing device and its substrate DC bias voltage measurement method
SG10201406957PA (en) Methods and apparatus for detecting the confinement state of plasma in a plasma processing system
JP2019004027A5 (en)
JP2007073309A (en) Plasma processing device and abnormal discharge preventing method
KR20130099976A (en) System and method for current-based plasma excursion detection
JP2013511815A5 (en)
WO2011021160A2 (en) Method and apparatus for measuring wafer bias potential
WO2008036210A3 (en) Methods of and apparatus for measuring and controlling wafer potential in pulsed rf bias processing
JP2009532916A (en) Control of plasma processing using PIF probing configuration
TWI604496B (en) Plasma processing apparatus and plasma processing method
JP2018107265A5 (en)
JP2013033726A5 (en)
KR20180081145A (en) Arcing detection device for plasma processing
US20240234111A9 (en) Method for OES Data Collection and Endpoint Detection
Yasaka et al. Micro arc monitoring by detecting charge build-up on glass surface of viewing port due to plasma dispersion in plasma processing equipment
KR101685087B1 (en) The noncontact plasma electric field detection device and the method for detection
KR101236208B1 (en) Arc detecting power control apparatus and method thereof
TW452884B (en) Frequency modulated endpoint detecting method and manufacturing apparatus for applying the method
JP3950177B2 (en) Charge monitor for high voltage pulse flow dose measurement apparatus and method