TWI553640B - Nonvolatile memory device, memory system including the same, and electronic device - Google Patents

Description

Non-volatile memory device, memory system including the device, and electronic device [Cross-Reference to Related Patent Applications]

The present application claims the Korean Patent Application No. 10-2011-0036943, filed on Apr. 20, 2011, and the U.S. Provisional Patent Application No. 61/447,133, filed on Feb. 28, 2011, in the s. The entire disclosure of both patent applications is hereby incorporated by reference.

This invention relates to non-volatile memory devices and systems, and more particularly to the generation of various voltages used in non-volatile memory devices and systems.

Semiconductor memory devices are generally classified as volatile semiconductor memory devices or non-volatile memory devices. If the power supply is interrupted, the volatile semiconductor memory device will lose the stored data, whereas if the power supply is interrupted, the non-volatile memory device will retain the stored data.

Examples of non-volatile semiconductor memory devices include mask read-only memories (MROMs), programmable read-only memories (PROMs), and erasable programmable read-only Erasable programmable read only memories (EPROM), electrically erasable programmable read only memories (EEPROM), and the like.

The development of self-power erasable programmable read-only memory (EEPROM) technology, NAND flash memory device has been widely used in non-volatile large-scale data storage applications. For example, anti-gate flash memory devices are commonly used to store audio, video and/or video data in a myriad of different types of host devices, such as computers, mobile phones, personal digital assistants (PDAs), Digital cameras, camcorders, tape recorders, MP3 players, handheld personal computers (PCs), game consoles, fax machines, scanners, printers, and more.

According to the number of bits stored in each memory cell, for example, the non-volatile memory device of the anti-gate flash memory device is usually classified into a single level cell (SLC) device or more. A multi-level cell (MLC) device. A single-stage memory cell (SLC) device stores a single bit of data in each non-volatile memory cell, whereas a multi-level memory cell (MLC) device stores two or more bits of data in each non-volatile memory. Cell.

There is a continuing need in the industry to increase the integrated density of semiconductor devices, particularly high capacity storage devices such as anti-gate flash memory devices. In this regard, for example, multi-level memory cell (MLC) devices have become more common on the market. However, efforts to increase device integration have encountered some major design challenges, including minimizing power consumption and maintaining operational stability.

According to an aspect of the inventive concept, a non-volatile memory cell array includes: a non-volatile memory cell array including a plurality of word lines; a voltage generator for Production Generating a first high voltage of the power supply voltage and a second high voltage using an external voltage higher than the power supply voltage; and a word-line selection circuit for applying the first time during the program operation of the memory cell array A high voltage to a selected one of the plurality of word lines, and applying a second high voltage to the unselected word lines of the plurality of word lines.

According to another aspect of the inventive concept, a memory system is provided, including: a memory controller; and a non-volatile memory device for being controlled by a memory controller. The non-volatile memory device includes: a voltage generator for generating a first high voltage using a power supply voltage and a second high voltage using an external voltage higher than a power supply voltage; and a word line selection circuit for The first high voltage is applied to the selected word line among the plurality of word lines during the program operation of the memory cell array, and the second high voltage is applied to the unselected word lines among the plurality of word lines.

According to still another aspect of the inventive concept, a method of operating a non-volatile memory device includes: generating a first high voltage from a power supply voltage; generating a second high voltage from an external voltage higher than a power supply voltage; and non-volatile The first high voltage is applied to the selected word line of the non-volatile memory device during the stylized operation of the memory device and the second high voltage is applied to the unselected word line of the non-volatile memory device.

The above and other aspects and features of the present invention will become more apparent from the following description.

The invention will now be described more fully hereinafter with reference to the accompanying drawings in which FIG. However, the invention may be embodied in many different forms. Therefore, it should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be more complete, and the concept of the invention will be more fully conveyed to those of ordinary skill in the art. In the figures, the size and relative sizes of layers and regions in the drawings may be exaggerated for clarity. The same reference symbols in the drawings denote the same elements.

It is to be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not Limited by these terms. The terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, a first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section, without departing from the principles of the invention.

In order to facilitate the description of the relationship between one element or feature and another element or feature in the figures, it is possible to use, for example, "below", "below", "lower", "below", " Spatial terminology higher than "higher" and so on. It should be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is turned over, the elements that are described as "below" other elements or features will be converted "above" other elements or features. Thus, the term "below" can encompass both the above and below. The above described devices may also point to different orientations (rotated 90 degrees or other directions), and the spatial relationship descriptors used herein will be interpreted accordingly. In addition, it should be noted that when a layer is called "between" two layers, it may be this A unique layering between two layers, or there may be one or more layers of mediation.

The terminology used herein is for the purpose of illustration and description of the embodiments. As used herein, the singular """ And the use of the terms "including" and / or "comprising", when used in this specification, is intended to indicate the presence of the described features, integers, steps, operations, components and/or components, but does not exclude the presence or addition of one or more other Features, integers, steps, operations, components, components, and/or combinations thereof. The term "and/or" when used herein includes any and all combinations of one or more of the associated listed items.

It should be understood that when a component or layer is referred to as "located," "connected," "coupled," or "adjoining" another element or layer, it may be directly located, connected, coupled, or contiguous. Or there may be an intermediary component or layering. In contrast, when a component or layer is referred to as "directly," "directly connected," "directly coupled," or "directly adjoining" another element or layer, there are no intervening elements or layers.

Unless otherwise defined, all terms (including technical and scientific terms, <RTI ID=0.0>&quot; </ RTI> used herein have the ordinary meaning as understood by one of ordinary skill in the art to which the invention pertains. It should also be understood that the meaning of the terms (such as the terms defined in the general dictionary) should be interpreted in accordance with the relevant technical field and/or the meaning of the specification, and should not be interpreted in an idealized or overly formalized meaning, unless otherwise definition.

In accordance with the conventions of the present invention, the elements of the embodiments can be utilized in block diagrams. The functional unit is shown to illustrate. Anyone having ordinary skill in the art to which the invention pertains will appreciate that these functional units are actually implemented by electronic circuitry with or without control software.

The following examples employ a reverse gate flash memory as the memory technology of the non-volatile memory device of the present invention. However, the invention is not limited thereto. Other examples of non-volatile memory devices to which the present invention is applicable include vertical NAND flash memories, NOR flash memories, and resistive random access memories. Resistive random access memories (RRAM), phase-change random access memories (PRAM), magnetoresistive random access memories (MRAM), ferroelectric random access Ferroelectric random access memories (FRAM), spin transfer torque random access memories (STT-RAM), and the like.

1 is a block diagram of an electronic device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the electronic device 1000 includes a host 1100 and a memory system (or storage device) 1200. The host 1100 of this example includes an external power managing unit 1110. The memory system 1200 of this example includes a memory controller 1210, a non-volatile memory 1220, and an external power switching unit 1230.

Examples of host 1100 include handheld electronic devices such as personal/handheld computers, personal digital assistants (PDAs), portable media players (portable media player, PMP), MP3 player, etc. An example of a memory system 1200 is a solid state disk/drive (SSD). Other examples of the memory system 1200 include a Personal Computer Memory Card International Association (PCMCIA) card, a compact flash (CF) card, and a smart media card (SM, SMC). , memory stick, multimedia card (MMC, RS-MMC, MMC-micro), security card (SD, miniSD, microSD, SDHC), universal flash storage (universal flash storage, UFS) devices and so on. An example of a memory system 1200 is disclosed in U.S. Patent Application Publication No. 2010-0082, the entire disclosure of which is incorporated herein by reference.

The host 1100 and the memory system 1200 can be effectively connected using any of a variety of standardized interfaces, examples of which include a peer-to-peer network (PPN), a universal serial bus (USB), a small computer system interface (SCSI), and an enhanced type. Small Device Interface (ESDI), Serial Advanced Technology Connectivity (SATA), Serial Attached Small Computer System Interface (SAS), PCI-express, and Integrated Electronics (IDE) interface. The present invention is not limited to the interface structure between the host 1100 and the memory system 1200.

In operation, memory system 1200 produces various operating voltages applied to word lines of non-volatile memory 1220. For example, in a stylized operation, the resulting word line voltage includes a program voltage applied to the selected word line of non-volatile memory 1220 and an unselected word line applied to non-volatile memory 1220. Pass voltage. Reading The verify word operation (which forms part of the stylization operation and used to verify the stylized result), the generated word line voltage includes the read verify voltage supplied to the selected word line of the non-volatile memory 1220 and applied to The verification of the unselected word lines of the non-volatile memory 1220 passes the voltage. In a read operation, the resulting word line voltage includes a read voltage of the selected word line provided to the non-volatile memory 1220, and an unselected voltage applied to the non-volatile memory 1220. The word line is read through the voltage. It should be noted that the voltage level of the verification pass voltage may be the same as the voltage level of the read pass voltage.

Some of these various word line voltages are described as "high voltage" because they are generated at a voltage level exceeding the power supply voltage (Vdd). For example, the program voltage, the pass voltage, the verify pass voltage, and the read pass voltage may exceed the power supply voltage Vdd. A technique for generating a word line voltage using an externally supplied high voltage is disclosed in U.S. Patent No. 7,672,170, the entire disclosure of which is incorporated herein by reference.

Still referring to the example of FIG. 1, the external power management unit 1110 of the host 1100 generates an external high voltage Ext_Vpp and an external power enable signal EPM_en, which will be described later to be used in the memory system 1200. In an embodiment, the external high voltage Ext_Vpp is in a range from 11 volts (V) to 16 volts (V). However, the invention is not limited to this particular voltage range.

The memory controller 1210 of the memory system 1200 controls the read operation, the program operation, and the erase operation of the non-volatile memory 1220 in response to The request/command as a control signal CTRL is transferred from the host 1100.

The external power source switching unit 1230 receives the external high voltage Ext_Vpp from the host 1100, and transfers the external high voltage Ext_Vpp to the non-volatile memory 1220 under the control of the memory controller 1210. The external power switching unit 1230 may constitute a separate circuit within the memory system 1200 or may form part of and/or be included in the memory controller 1210.

The non-volatile memory 1220 of the example of FIG. 1 includes a plurality of non-volatile memory devices 1221, 1222, 1223, and 1224 that may be comprised of the same type of non-volatile memory or different types of non-volatile memory. In the particular example of this embodiment, each of the non-volatile memory devices 1221-1224 is a reverse gate flash memory chip. The memory controller 1210 communicates with the non-volatile memory devices 1221-1224 on respective data input/output (I/O) channels. Moreover, the invention is not limited to the specification that the non-volatile memory 1220 includes a plurality of memory devices. That is, the non-volatile memory 1220 can also include a single non-volatile memory device.

According to the embodiment associated with FIG. 1, the memory system 1200 operates in at least two power modes in accordance with the state of the external power enable signal EPM_en. The first mode is referred to as the general mode (also referred to herein as the first power mode) and the second mode is referred to as the external voltage mode OVM (also referred to herein as the second power mode). When the external power enable signal EPM_en of the host 1100 is in an inactive state (or OFF), the memory system 1200 will operate in the normal mode. When the external power supply enable signal EPM_en of the host 1100 is in effect At the state (or ON), the memory system 1200 will operate in an external voltage mode OVM.

In the normal mode of operation, non-volatile memory 1220 generates an operating word line voltage from supply voltage Vdd. For example, a charge pump can be used to generate the necessary high voltage word line voltage from the supply voltage Vdd. It should be noted that the power supply voltage Vdd can be supplied to the non-volatile memory 1220 from the host 1100, the memory controller 1210, or a voltage regulator (not shown).

In the external voltage mode OVM, the memory controller 1210 controls the external power switching unit 1230 to transfer the external high voltage Ext_Vpp to the non-volatile memory 1220, and the non-volatile memory 1220 generates at least some operational words from the external high voltage Ext_Vpp. Yuan line voltage. In this case, in the example of FIG. 1, at least one of the non-volatile memory devices 1221 through 1224 is used to support the external voltage mode OVM. If any of the non-volatile memory devices 1221 through 1224 are not used to support the external voltage mode OVM, such devices will operate in the normal mode, while devices that support the external voltage mode OVM will operate in the external voltage mode OVM. In at least a portion of the following explanation, it is assumed that the first non-volatile memory device 1221 of FIG. 1 supports the external voltage mode OVM.

Therefore, it should be noted that in the modified example of FIG. 1, the external power supply switching unit 1230 will be omitted, and the external high voltage Ext_Vpp is directly supplied to the non-volatile memory 1220. Such modifications and other modifications will be described later with reference to other embodiments of the invention.

In the example of FIG. 1, the memory controller 1210 is based on the host 1100. The external power enable signal EPM_en sets the power mode of each of the non-volatile memory devices 1221 to 1224. However, the invention is not limited thereto. For example, the non-volatile memory devices 1221 through 1224 can directly receive the external power enable signal EPM_en and accordingly set their respective power modes. In another example, the external power enable signal EPM_en may be omitted, and thus the non-volatile memory devices 1221 through 1224 may detect whether an external high voltage Ext_Vpp is present and accordingly set their respective power modes. Also, as described above, the power modes set by the non-volatile memory devices 1221 to 1224 may be the same or different from each other.

2 is a block diagram of an example of the memory controller 1210 and the non-volatile memory device 1221 shown in FIG. 1. As described above, it is assumed that the non-volatile memory device 1221 supports the external voltage mode OVM.

Referring to FIG. 2, the memory controller 1210 of this example includes at least one central processing unit (CPU) 1211, a host interface 1212, a volatile memory device 1213, and a non-volatile memory interface 1214.

The central processing unit 1211 is configured to analyze and process signals input from the host 1100 shown in FIG. 1. The central processor 1211 controls the non-volatile memory device 1221 via the non-volatile memory interface 1214. The central processing unit 1211 controls the overall operation of the non-volatile memory device 1221 in accordance with firmware installed for this purpose.

The host interface 1212 includes a data exchange protocol for the host 1100 coupled to the memory system 1200 of FIG. The host interface 1212 provides an operational interface for the host 1100 in accordance with the data exchange protocol of the host 1100.

The volatile memory device 1213 temporarily stores data written from the host 1100 or data read from the non-volatile memory device 1221. The volatile memory device 1213 is configured to store meta data or cache data to be stored in the non-volatile memory device 1221. The volatile memory device 1213 may include dynamic random access memory (DRAM), static random access memory (SRAM), and the like.

The non-volatile memory interface 1214 provides an interface to the non-volatile memory device 1221. The non-volatile memory interface 1214 transfers the input/output (I/O) data provided by the volatile memory device 1213 to the non-volatile memory device 1221 and transfers the input read from the non-volatile memory device 1221. The data is output to the volatile memory device 1213. In addition, the non-volatile memory interface 1214 provides a control signal CTRL for controlling the overall operation of the non-volatile memory device 1221 to the non-volatile memory device 1221 in response to control by the central processing unit 1211.

In an embodiment of the invention, the host interface 1212 receives the external power enable signal EPM_en from the external power management unit 1110 of the host 1100. In this case, the central processing unit 1211 provides control signals and input/output data to the non-volatile memory device 1221 via the non-volatile memory interface 1214 in response to the external power enable signal EPM_en. Also, the central processing unit 1211 controls the external power supply switching unit 1230 shown in FIG. 1 to supply an external high voltage Ext_Vpp to the non-volatile memory device 1221.

The non-volatile memory device 1221 is selectively set to the above-described general mode or external voltage mode OVM. This can be done, for example, by setting a non-volatile The value of the set register 1225 of the memory device 1221 is achieved in response to the control signal CTRL provided by the memory controller 1210. The control signal CTRL (for example, the external power enable signal EPM_en) related to the setting of the normal mode or the external voltage mode OVM is referred to herein as "power control information". For example, in the case where the external power enable signal EPM_en is in the active state (or ON), the memory controller 1210 can control the non-volatile memory device 1221 to set the corresponding external voltage mode OVM in the setting register 1225. Value. This can be set by appropriately transmitting the power control information to the control logic 160 of the non-volatile memory device 1221, which will be described later with reference to FIG. 3, and the control logic 160 responds to the power control information. The value of 1225 is reached.

In one example of the external voltage mode OVM of the present invention, the non-volatile memory device 1221 generates some word line voltages from the external high voltage Ext_Vpp and uses the power supply voltage Vdd to generate other word line voltages. For example, in the stylization operation, the pass voltage Vpass to be applied to the unselected word line and the read verify pass voltage Vread may be generated from the external high voltage Ext_Vpp, and may be generated from the power supply voltage Vdd to be applied to the selected character. The line program voltage Vpgm. This and other examples of the external voltage mode OVM will be described with reference to the following embodiments.

3 is a block diagram of the non-volatile memory device 1221 of FIG. 2 in accordance with one or more embodiments of the present invention.

Referring to FIG. 3, the non-volatile memory device 1221 includes a voltage generation circuit 110 and a column selection circuit (row A selection circuit 120, a memory cell array 130, a read and write circuit 140, a data input/output circuit 150, and a control logic 160.

Control logic 160 controls the overall operation of non-volatile memory device 1221. For example, control logic 160 is responsive to the program requirements or read requirements of memory controller 1210 shown in FIG. 1, and controls the overall operation of non-volatile memory device 1221 to perform program operations or read operations.

It is assumed here that the external high voltage Ext_Vpp is supplied from the host 1100 shown in FIG. 1 to the memory system 1200 shown in FIG. 1, that is, the value corresponding to the external voltage mode OVM is stored in the setting register described above with reference to FIG. 1225. In response to setting the external voltage mode OVM value stored by the register 1225, the control logic 160 will provide an external voltage mode signal OVMS to the voltage generating circuit 110. As such, an external voltage mode OVM will be established.

The voltage generating circuit 110 generates a voltage (i.e., a word line voltage) to be supplied to the word line WL of the memory cell array 130. This voltage will be generated in response to external voltage mode signal OVMS of control logic 160 in accordance with external voltage mode OVM.

As shown in FIG. 3, the voltage generating circuit 110 of this example includes a high voltage (HV) generator 111 and a low voltage (LV) generator 112.

The high voltage generator 111 includes a general high voltage generator 111_a and a selective high voltage generator 111_b. The general high voltage generator 111_a generates a program voltage Vpgm to be supplied to the selected word line during program operation in response to control by the control logic 160. In this particular embodiment, the general high voltage generator 111_a generates a program voltage Vpgm from the supply voltage Vdd, such as a charge pump by the supply voltage Vdd.

The selective high voltage generator 111_b is responsive to control of the control logic 160 and generates a pass voltage Vpass to be supplied to the unselected word line during program operation or a supply to the unselected word line during the read operation. The read voltage Vread is read.

In the case where the external high voltage Ext_Vpp is in the active state (ON), the selective high voltage generator 111_b operates in accordance with the external voltage mode signal OVMS received from the control logic 160. That is, in the external voltage mode OVM, the selective high voltage generator 111_b generates the pass voltage Vpass and the read pass voltage Vread from the external high voltage Ext_Vpp, for example, by lowering the voltage level of the external high voltage Ext_Vpp.

In the case where the external high voltage Ext_Vpp is in an inactive state (OFF), the selective high voltage generator 111_b will operate according to the general mode. That is, in the normal mode, the selective high voltage generator 111_b generates a pass voltage Vpass and a read pass voltage Vread from the power supply voltage Vdd, for example, a charge pump by the power supply voltage Vdd.

Under the control of control logic 160, a low voltage generator 112 generates a verification read voltage Vvfy to be supplied to the selected word line during a verify read operation included in the program operation. Alternatively, a read voltage Vrd to be supplied to the selected word line is generated during the read operation. In this example of this embodiment, the low voltage generator 112 generates a verify read voltage Vvfy using the high voltage Vpp. And reading voltage Vrd. Here, the high voltage Vpp may be a high voltage generated by the general high voltage generator 111_a or the selective high voltage generator 111_b. In another example of this embodiment, the verify read voltage Vvfy and/or the read voltage Vrd are lower than the power supply voltage Vdd, and the low voltage generator 112 utilizes the power supply voltage Vdd to generate the verify read voltage Vvfy and/or the read voltage. Vrd.

The column selection circuit 120 obtains the word line voltages Vpgm, Vpass, Vread, Vvfy, and Vrd from the voltage generation circuit 110, and supplies a corresponding voltage to the specified word line WL in response to the row address RA. The column selection circuit 120 of this example includes a voltage selection switch 121, a first column decoder 122, and a second column decoder 123.

The voltage selection switch 121 generates selection signals S<1> to S<n> to be supplied to the word line WL in response to the address portion RAi of the column address RA.

For example, during a stylized cycle of program operation, voltage select switch 121 activates one of select signals S<1> through S<n> in response to column address RAi and turns off the remaining select signals. The voltage selection switch 121 shifts the program voltage Vpgm to the activated selection signal and shifts the pass voltage Vpass to the closed selection signal.

In another example, during the verify read cycle of the program operation, the voltage select switch 121 transfers the verify read voltage Vvfy to the select signal initiated during the program execution cycle and transfers the verify pass voltage Vread to the select signal that is turned off during the program execution cycle.

In still another example, during the read operation, the voltage selection switch 121 activates one of the selection signals S<1> to S<n> in response to the column address RAi. At this time, the remaining selection signals will be turned off. The voltage selection switch 121 shifts the read voltage Vrd to the activated select signal and shifts the read pass voltage Vread to the turned-off select signal.

Each of the first column decoder 122 and the second column decoder 123 drives the word line WL with a corresponding word line voltage in response to the selection signals S<1> to S<n> and the rest of the column address RA Part of RAj. In this example of this embodiment, the column address portion RAj is an address for selecting a memory block 131 or 132 (i.e., memory block BLK1 or BLK2). Also according to this example, the first column decoder 122 selects the first memory block 131 in response to the column address RAj, and the second column decoder 123 selects the second memory block 132 in response to the column address RAj.

Each of the first column decoder 122 and the second column decoder 123 transfers the word line voltage supplied via the selection signals S<1> to S<n> to the word line WL of the selected memory block. During the program execution cycle of the program operation, the program voltage Vpgm is applied to the selected word line and the pass voltage Vpass is applied to the unselected word line. Also, during the read operation, the read voltage Vrd is applied to the selected word line, respectively, and the read pass voltage Vread is applied to the unselected word line.

As described above, the memory cell array 130 is connected to the column selection circuit 120 via the word line WL. Further, the memory cell array 130 is connected to the read/write circuit 140 via bit lines BL. As described above, the memory cell array 130 includes a first memory block 131 and a second memory block 132. First memory Each of the block 131 and the second memory block 132 includes a plurality of memory cells that store data. For convenience of explanation, two memory blocks 131 and 132 are shown in FIG. However, the present invention is not limited to the number of memory blocks of the memory cell array 130. In other words, the memory cell array 130 can have a single memory block or have two or more memory blocks.

The invention is also not limited to the number of bits stored in each memory cell. For example, each memory cell of memory cell array 130 can store a single bit of data, which is commonly referred to as a single-order memory cell (SLC) or a single bit cell (SBC). On the other hand, each memory cell of the memory cell array 130 can store data of two or more bits, which is commonly referred to as a multi-order memory cell (MLC) or a multi-bit cell (MBC). . Also, the memory cell array 130 may include both a single-order memory cell (SLC)/unit cell memory cell (SBC) and a multi-order memory cell (MLC)/unit cell memory cell (MBC).

Read and write circuit 140 is coupled to memory cell array 130 via bit line BL and to data input/output circuit 150 via data lines DL and is operatively responsive to control logic 160. In the stylized operation, the read and write circuit 140 receives data from the data input/output circuit 150 to store the received data in the memory cell array 130. In the read operation, the read/write circuit 140 reads data from the memory cell array 130 to transfer the read data to the data input/output circuit 150. For example, the read/write circuit 140 may include: constituent elements for performing reading and writing of data, such as a page buffer (or page register); for selecting a bit line BL a column selector circuit; and other components.

The data input/output circuit 150 is connected to the read/write circuit 140 via the data line DL. The data input/output circuit 150 is operatively responsive to the control logic 160 and is used to exchange input/output data with an external device. In the program operation, the data input/output circuit 150 transfers the input/output data supplied from the external device to the read/write circuit 140 via the data line DL. In the read operation, the data input/output circuit 150 transfers the input/output data supplied from the read/write circuit 140 to the external device via the data line DL.

As described above with reference to FIG. 3, the non-volatile memory device 1221 supports the external voltage mode OVM and utilizes the external high voltage Ext_Vpp to generate a high word line voltage to be supplied to the unselected word line (ie, through the voltage Vpass). Or read through voltage Vread). In contrast, in the case where a high word line voltage is generated by a charge pump of the power supply voltage Vdd, an excessive transient peak current may occur. This may result in the generation of unstable word line voltages, which in turn may cause operational failure of the non-volatile memory device. The above embodiment can avoid this disadvantage because the voltage generating circuit 110 generates a high word line voltage of an unselected word line by lowering the external high voltage Ext_Vpp, thereby avoiding an instantaneous peak current. In addition, since the high-character line voltage source is applied from the external voltage Ext_Vpp to many unselected word lines at the same time, the power consumption in the non-volatile memory device can be reduced.

4 is a block diagram of an example of a general high voltage generator 111_a that can be used in the embodiment of FIG. In particular, as described above, the general high voltage generator 111_a generates the program voltage Vpgm in response to the control of the control logic 160 of FIG.

Referring to FIG. 4, the general high voltage generator 111_a includes an oscillator 111_a1, a voltage regulator 111_a2, and a charge pump 111_a3.

The oscillator 111_a1 generates an oscillation signal OSC. The regulator 111_a2 outputs the oscillation signal OSC as the clock CLK according to whether the level of the output voltage of the charge pump 111_a3 is higher than the level of the target voltage TV. The charge pump 111_a3 performs a boosting operation in response to the clock CLK. The charge pump 111_a3 boosts the voltage level of the output voltage to the voltage level of the program voltage Vpgm by charging a plurality of serially connected capacitors (not shown) with the power supply voltage Vdd.

5 is a block diagram of an example of a selective high voltage generator 111-b that can be used in the embodiment of FIG. 3, and FIG. 6 is a timing diagram for explaining the relative voltage of the transfer path shown in FIG.

As described above, during stylization, the selective high voltage generator 111_b generates a pass voltage Vpass in response to the control of the control logic 160 shown in FIG. During reading, the selective high voltage generator 111_b generates a read pass voltage Vread in response to the control of the control logic 160 shown in FIG. These high voltages Vpass and Vread will be applied to the unselected word line WL. FIG. 3 illustrates an example of generating a pass voltage Vpass.

Referring to FIG. 5, the selective high voltage generator 111_b includes an oscillator 111_b1, a voltage regulator 111_b2, a charge pump 111_b3, a switching circuit 111_b5, and a voltage division circuit 111_b6. The oscillator 111_b1, the regulator 111_b2, and the charge pump 111_b3 are substantially identical to those described with reference to FIG. 4, and are collectively referred to herein as a pumping circuit 111_b4.

The selective high voltage generator 111_b generates the pass voltage Vpass in one of two ways depending on whether the device operates in the above-described general mode or the above-described external voltage mode OVM. In particular, in the external voltage mode OVM, the selective high voltage generator 111_b generates the pass voltage Vpass using the external high voltage Ext_Vpp. On the other hand, in the normal mode, the selective high voltage generator 111_b generates the pass voltage Vpass using the power supply voltage Vdd.

Referring to FIGS. 5 and 6, it is assumed that the external high voltage Ext_Vpp is transferred to the selective high voltage generator 111_b at least for a time period in which the external voltage mode signal OVMS is in an active state (eg, a logic high level).

At time t1, the external voltage mode signal OVMS becomes active (eg, a logic high level), such as according to a set value of the set register 1225 (FIG. 2). As a result, the switching circuit 111_b5 is switched to be turned on (i.e., closed) to couple the external high voltage Ext_Vpp and the voltage dividing circuit 111_b6 along the first path. At the same time, the oscillator 111_b1 of the boosting circuit 111_b4 is turned off (or turned off), thereby stopping the function of the boosting circuit 111_b4. Therefore, in the first time period T1, the external high voltage Ext_Vpp having the Vpp voltage level is supplied to the voltage dividing circuit 111_b6 along the first path, and the pass voltage Vpass is generated by the divided voltage of the external high voltage Ext_Vpp.

At time t2, the external voltage mode signal OVMS becomes inactive (eg, a logic low level), such as according to a set value of the set register 1225 (FIG. 2). As a result, the switching circuit 111_b5 is switched to be turned off (i.e., open) to release the coupling of the external high voltage Ext_Vpp and the voltage dividing circuit 111_b6 along the first path. At the same time, the oscillator 111_b1 of the boosting circuit 111_b4 is activated (or turned on), thereby starting the boosting circuit 111_b4. So in the second time In the period T2, the internal high voltage Int_Vpp having the Vpp voltage level is supplied to the voltage dividing circuit 111_b6 along the second path, and the pass voltage Vpass is generated by the divided voltage of the internal high voltage Int_Vpp.

At time t3, at time t1, the external voltage mode signal OVMS again becomes active (for example, a logic high level), and the switching circuit 111_b5 is switched to be turned on (ie, closed) to couple the external high voltage Ext_Vpp and the voltage divider along the first path. The circuit 111_b6, and turns off (or turns off) the oscillator 111_b1 of the boosting circuit 111_b4. Therefore, the pass voltage Vpass is generated by the partial voltage of the external high voltage Ext_Vpp.

Fig. 7 is a circuit diagram showing an example of the voltage dividing circuit 111_b6 shown in Fig. 5. Referring to FIG. 7, the voltage dividing circuit 111_b6 includes a power supply unit 1, a voltage dividing unit 2, a bias current unit 3, and a comparison unit 4.

The power supply unit 1 receives the voltage of the Vpp level (that is, the external high voltage Ext_Vpp or the internal high voltage Int_Vpp) supplied via the first path or the second path (refer to FIG. 5). The power supply unit 1 of this example includes a P-channel MOS transistor PM_L.

The voltage dividing unit 2 is connected between the output node NO_L and the comparison node NC_L, and outputs the pass voltage Vpass by dividing the Vpp voltage according to the trim code TRMi_L.

The voltage dividing unit 2 of this example includes: a plurality of resistors R2_L to R4_L connected in series between the output node NO_L and the comparison node NC_L; The transistors M0_L to M2_L connected in parallel with the corresponding resistors R4_L to R2_L; and the switches SW0_L to SW2_L connected to the gates of the corresponding transistors M0_L to M2_L, respectively. Each of the resistors R4_L to R2_L may be short-circuited or open circuited according to the trimming codes TRM0_L to TRM2_L. In FIG. 7, three resistors R4_L to R2_L capable of being short-circuited according to the trimming codes TRM0_L to TRM2_L are illustrated. However, the invention is not limited thereto. That is, the voltage dividing unit 2 may include one or more resistors that can be short-circuited according to at least one trimming code.

Each of the switches SW0_L~SW2_L receives the corresponding one of the high voltage Vpp and the trimming codes TRM0_L to TRM2_L, and supplies the high voltage Vpp to the gate of the corresponding transistor according to the corresponding trimming code.

The bias current unit 3 is connected between the comparison node NC_L and the ground terminal, and flows out a fixed current according to the startup of the voltage dividing circuit 111_b6. The bias current unit 3 of this example includes a resistor R1_L.

The comparison unit 4 controls the startup of the power supply unit 1 by comparing the voltage of the comparison node NC_L with the reference voltage Vref_LV of the low voltage. For example, the comparison unit 4 will continue to activate the power supply unit 1 when the voltage of the comparison node NC_L is not equal to the reference voltage Vref_LV of the low voltage. The comparison unit 4 of this example includes a positive input terminal that receives the voltage of the comparison node NC_L and a negative input terminal that receives the reference voltage Vref_LV of the low voltage.

FIG. 8 is a block diagram showing an example of a trim code generator 5. The trimming code generator 5 generates a trimming code to be applied to the voltage dividing circuit 111_b6 of Fig. 7. The trimming code generator 5 of this example includes the first data latch A data latch 5_a and a second data latch 5_b.

For ease of explanation, it is assumed that the first data latch 5_a latches the data on the voltage Vpass and the second data latch 5_b latches the data on the read voltage Vread. In order to obtain the target pass voltage Vpass from the voltage dividing circuit 111_b6 of FIG. 7, the first data latch 5_a outputs the latched data as the i-th trimming code TRMi_L (i is an integer of 1 or more) in response to the A trim code enable signal TEN1. On the other hand, in order to obtain the target read pass voltage Vread from the voltage dividing circuit 111_b6 of FIG. 7, the second data latch 5_b outputs the latched data as the i-th trimming code TRMi_L in response to the second trimming code. Can signal TEN2.

FIG. 9 is a block diagram showing another example of the trimming code generator 6. The trimming code generator 6 generates a trimming code to be applied to the voltage dividing circuit 111_b6 of Fig. 7. Referring to Fig. 9, the trimming code generator 6 of this example includes a first electric fuse (E-fuse) 6_a, a second electric fuse 6_b, and a switch 6_c.

For convenience of explanation, it is assumed that the first electric fuse 6_a includes an electric fuse value corresponding to the pass voltage Vpass and the second electric fuse 6_b includes an electric fuse value corresponding to the read pass voltage Vread. In order to obtain the target pass voltage Vpass from the voltage dividing circuit 111_b6 of FIG. 7, the switch 6_c outputs the data of the electric fuse value corresponding to the first electric fuse 6_a as the i-th trimming code TRMi_L (i is an integer of 1 or more ). On the other hand, in order to obtain the target read pass voltage Vread from the voltage dividing circuit 111_b6 of FIG. 7, the switch 6_c outputs the material of the electric fuse value corresponding to the second electric fuse 6_b as the i-th trimming code TRMi_L.

Fig. 10 is a circuit diagram showing an example of one of the switches SW0_L shown in Fig. 7. Referring to FIG. 10, the switch SW0_L of this example includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second P-channel metal oxide semiconductor (PMOS) transistor PM2, and a first N-channel metal oxide semiconductor transistor. (NMOS transistor) NM1, a second N-channel metal oxide semiconductor (NMOS) transistor NM2, a first inverter INV1, and a second inverter INV2. The switch SW0_L is a level shifter that converts the level of the trimming code TRM0_L into a level of the high voltage Vpp. Here, the trimming code TRM0_L has a level of the power supply voltage Vdd which is lower than the level of the high voltage Vpp. The remaining switches SW1_L and SW2_L shown in FIG. 7 can be substantially identical to the switches shown in FIG.

The selective high voltage generator 111_b (Fig. 3) described above with reference to Figures 5 through 10 is for illustration only and may be modified or redesigned without departing from the principles of the invention. For example, another embodiment of the selective high voltage generator 111_b will now be described with reference to FIG.

Fig. 11 is a circuit diagram showing another example of the selective high voltage generator 111_b'. It is apparent that the selective high voltage generator 111_b' shown in FIG. 11 is similar to the selective high voltage generator shown in FIG. 5 except that the first path voltage is Ext_Vpass obtained by dividing the external high voltage Ext_VPP, and the switching circuit. 111_b5 selects between a first path with Ext_Vpass and a second path with Int_Vpass. In the description of Fig. 11, constituent elements equivalent to those of Fig. 5 will be denoted by the same reference numerals and their operation will be omitted.

Referring to FIG. 11, the selective high voltage generator 111_b' includes an oscillator. 111_b1, a voltage regulator 111_b2, a charge pump 111_b3, a switching circuit 111_b5, and a voltage dividing circuit 111_b6. The oscillator 111_b1, the regulator 111_b2, and the charge pump 111_b3 constitute a booster circuit 111_b4. In this example, the boosting circuit 111_b4 may further include a voltage dividing circuit (not shown) for generating an internal pass voltage Int_Vpass at the output stage of the charge pump 111_b3.

In the external voltage mode OVM, the external voltage mode signal OVMS is in an active state, so the switching circuit 111_b5 will couple the output to the first path, thereby outputting Ext_Vpass as the pass voltage Vpass. During this time, the oscillator 111_b1 can be turned off to turn off the charge pump 111_b3. In the normal mode, the external voltage mode signal OVMS is in an inactive state, so the switching circuit 111_b5 will couple the output to the second path, thereby outputting Int_Vpass as the pass voltage Vpass. During this time, the oscillator 111_b1 will be activated to activate the charge pump 111_b3.

FIG. 12 is a block diagram showing an example of the voltage selection switch 121 shown in FIG. Referring to Fig. 12, the voltage selection switch 121 of this example includes a decoding unit 121_a and a plurality of driving units 121_b1 to 121_bn.

The decoding unit 121_a decodes the column address RAi to generate decoded column addresses DRA_1 to DRA_n. The decoding unit 121_a transfers the decoded column address addresses DRA_1 to DRA_n to the corresponding ones of the plurality of driving units 121_b1 to 121_bn, respectively.

During the program execution cycle of the program operation, the plurality of driving units 121_b1 to 121_bn receive the program voltage Vpgm and the pass voltage Vpass from the voltage generating circuit 110 of FIG. A plurality of driving units 121_b1 to 121_bn are activated One of the signals S<1> to S<n> is selected in response to the decoded column address. One of the plurality of driving units 121_b1 to 121_bn corresponding to the driving signal of the activated selection signal drives the selected selection signal with the program voltage Vpgm. The remaining drive units drive the unactivated (or remaining) selection signals with the pass voltage Vpass, respectively.

The plurality of driving units 121_b1 to 121_bn receive the verification read voltage Vvfy, the read pass voltage Vread, and the read voltage Vrd from the voltage generating circuit 110 during the verify read operation of the program operation or during the read operation. The plurality of driving units 121_b1 to 121_bn activate one of the selection signals S<1> to S<n> in response to the decoded column address. One of the plurality of driving units 121_b1 to 121_bn corresponds to the driving signal of the activated selection signal to drive the selected selection signal with the read voltage Vrd or the verify read voltage Vvfy. The remaining drive units drive the unactivated (or remaining) selection signals with the read pass voltage Vread, respectively.

At the same time, the selection signals S<1> to S<n> generated by the voltage selection switch 121 are supplied to the column decoders 122 and 123. This will be explained more fully with reference to FIG.

FIG. 13 is a block diagram showing an example of the column decoder 122 and the memory cell array 130 shown in FIG. The memory cell array 130 includes a plurality of memory blocks. For ease of explanation, FIG. 13 illustrates a memory block and a column decoder 122 corresponding to the memory block.

Referring to Figure 13, column decoder 122 selects a memory block in response to column address RAj. That is, the column decoder 122 activates a block control signal BS corresponding to the column address RAj and is controlled by the block. The signal BS turns on or off voltage transfer transistors BS0 to BSn+1. When the voltage transfer transistors BS0 to BSn+1 are turned on, the selection signal lines SL1 to SLn are electrically connected to the word lines WL1 to WLn, respectively. Therefore, the voltages of the selection signals S<1> to S<n> are supplied to the word lines WL1 to WLn, respectively.

For example, during the program execution cycle of the program operation, the program voltage Vpgm of the selected selection signal is supplied to the selected word line, and the pass voltage Vpass of the selected selection signal is respectively supplied to the unselected word line. In another example, during the read operation or during the verify read cycle of the program operation, the read voltage Vrd of the selected select signal or the verify read voltage Vvfy will be supplied to the selected word line, and the selected select signal is turned off. The read pass voltage Vread will be provided to the unselected word lines, respectively.

The memory block of the memory cell array 130 of this example includes a plurality of strings, each of which corresponds to a plurality of bit lines BL1 to BLm. Each of the strings includes a string selection transistor SST, a ground selection transistor GST, and memory cells M1 to Mn connected in series between the selection transistors GST and SST. The memory cells M1 to Mn of each string are connected to the corresponding word lines WL1 to WLn, respectively. That is, the memory cells of the same column (eg, M1) are connected in common to the corresponding word line (eg, WL1).

During the program execution cycle of the program operation, the program voltage Vpgm is supplied to the memory cells of the selected word line via the selected word line, and the unselected character characters are supplied via the unselected word line through the voltage Vpass. The memory of the line. Verification during a read operation or during program operation The read cycle will supply the read voltage Vrd or the verify read voltage Vvfy to the memory cells of the selected word line via the selected word line, and will supply the read pass voltage Vread to the connection via the unselected word line supply. Memory cells of unselected word lines.

Other embodiments of the present invention will now be described with reference to Figs.

Figure 14 is a block diagram of a non-volatile memory device in accordance with another embodiment of the present invention. The non-volatile memory device 1221' shown in FIG. 14 supports the external voltage mode OVM, and generates a low voltage (for example, the read voltage Vrd or the verify read voltage Vvfy) to be supplied to the selected word line by using the external high voltage Ext_Vpp. .

The non-volatile memory device 1221' shown in Fig. 14 includes the same-named elements as those shown in Fig. 3 except for the voltage generating circuit 210, and thus detailed description of those elements will be omitted below to avoid redundant description.

Referring to Fig. 14, the non-volatile memory device 1221' includes a voltage generating circuit 210, a column selecting circuit 220, a memory cell array 230, a read/write circuit 240, a data input/output circuit 250, and control logic 260.

The voltage generating circuit 210 generates a voltage (i.e., a word line voltage) to be supplied to the word line WL of the memory cell array 230. At least a portion of the characteristics of the embodiment of FIG. 14 is that the voltage generating circuit 210 generates the read voltage Vrd to be supplied to the selected word line and/or the verify read voltage Vvfy using the external high voltage Ext_Vpp in response to the external voltage mode signal OVMS. The voltage generating circuit 210 includes a high voltage generator 211 and a low voltage generator 212.

The high voltage generator 211 generates the program voltage Vpgm, the pass voltage Vpass, and the read pass voltage Vread in response to the control logic 260. system. In this example of this embodiment, the high voltage generator 211 generates the program voltage Vpgm, the pass voltage Vpass, and the read pass voltage Vread using the power supply voltage Vdd regardless of whether or not the external high voltage Ext_Vpp is supplied. This can be achieved by a charge pump such as supply voltage Vdd.

The low voltage generator 212 includes a first low voltage generator 212_a and a second low voltage generator 212_b. Each of the first low voltage generator 212_a and the second low voltage generator 212_b generates a read voltage Vrd or a verify read voltage Vvfy in response to control of the control logic 260.

The first low voltage generator 212_a generates the read voltage Vrd or the verify read voltage Vvfy using the power supply voltage Vdd. For convenience of explanation, it is assumed that the first low voltage generator 212_a generates the first read voltage Vrd1 or the first verify read voltage Vvfy1. The level of the first read voltage Vrd1 and the first verify read voltage Vvfy1 is equal to or lower than the level of, for example, the power supply voltage Vdd.

The second low voltage generator 212_b generates the read voltages Vrd2 to Vrdn whose levels are higher than a predetermined voltage (for example, the power supply voltage Vdd) or verifies the read voltages Vvfy2 to Vvfyn in response to the control of the control logic 260. The second low voltage generator 212_b generates the read voltages Vrd2 to Vrdn or verify the read voltages Vvfy2 to Vvfyn by lowering the external high voltage Ext_Vpp in the external voltage mode or lowering the internal high voltage Int_Vpp in the normal mode.

In particular, if the external high voltage Ext_Vpp is supplied, the second low voltage generator 212_b will lower the external high voltage Ext_Vpp to generate the read voltages Vrd2 to Vrdn to be supplied to the selected word line or verify the read voltages Vvfy2 to Vvfyn in response. For external voltage mode signal OVMS. In this case, the read voltages Vrd2 to Vrdn and the verify read voltage Vvfy2 The level to Vvfyn is higher than the level of the power supply voltage Vdd.

If the external high voltage Ext_Vpp is not supplied, the second low voltage generator 212_b will divide the internal high voltage Int_Vpp (refer to FIG. 5) to generate the read voltages Vrd2 to Vrdn or verify the read voltages Vvfy2 to Vvfyn. In this case, the internal high voltage Int_Vpp is transferred from the high voltage generator 211 and has the same Vpp voltage level as the external high voltage Ext_Vpp. The high voltage generator 211 for generating the internal high voltage Int_Vpp may be the same as the general high voltage generator 111_a shown in FIG. 4 described above and the booster circuit 111_b4 shown in FIG. 5 described above.

15 and 16 are schematic views for explaining the operation of the voltage generating circuit shown in Fig. 14. 15 illustrates the voltage levels of the verify read voltages Vvfy1 to Vvfy3 of the verify read cycle performed during the program operation, and FIG. 16 shows the read voltages Vrd1 to the threshold voltage distribution according to the memory cells. The voltage level of Vrd3.

Referring to Figure 15, the non-volatile memory device 1221' shown in Figure 14 performs program operations in accordance with incremental step pulse programming (ISPP) techniques. In the example, the verify read cycle is performed using three verify read voltages Vvfy1 through Vvfy3. However, the number of verified read voltages is not limited thereto, and can be variously set, particularly according to the number of bits stored in each memory cell.

If the verify read cycle is performed using the three verify read voltages Vvfy1 to Vvfy3, as illustrated in the example of FIG. 15, the level of the first verify read voltage Vvfy1 is lower than the level of the reference voltage Vref, and the second verification The reading voltage Vvfy2 and the third verification reading voltage Vvfy3 are higher than the reference power Press the level of Vref. In this example, the reference voltage Vref is equal to or similar to the power supply voltage Vdd.

In this case, the low voltage generator 212 of FIG. 14 generates the verify read voltage Vvfy1 lower than the reference voltage Vref using the power supply voltage Vdd, and generates the verify read voltage Vvfy2 higher than the reference voltage Vref by using the external high voltage Ext_Vpp and Vvfy3.

For example, the first low voltage generator 212_a of the low voltage generator 212 generates the first verification read voltage Vvfy1 by the output power supply voltage Vdd as the first verification read voltage Vvfy1. The second low voltage generator 212_b of the low voltage generator 212 generates the second verification read voltage Vvfy2 and the third verification read voltage Vvfy3 by lowering the external high voltage Ext_Vpp. If the external high voltage Ext_Vpp is not supplied, the second low voltage generator 212_b of the low voltage generator 212 will generate the second verify read voltage Vvfy2 and the third verify read voltage Vvfy3 by lowering the internal high voltage Int_Vpp.

Referring to Figure 16, the memory cell of memory cell array 230 of Figure 4 has one of four threshold voltage distributions. That is, the threshold voltage distribution of the memory cell corresponds to one of an erase state ST0, a first program state ST1, a second program state ST2, and a third program state ST3. The number of logic states ST0 to ST3 and logic states ST0 to ST3 of the memory cell is not limited to this example.

If there are four possible threshold voltage distributions for each memory cell, the read operation requires three read voltages Vrd1, Vrd2, and Vrd3. In this case, as shown in the example of FIG. 16, the level of the first read voltage Vrd1 is lower than the level of the reference voltage Vref, and the second read voltage Vrd2 and the The level of the three read voltages Vrd3 is higher than the level of the reference voltage Vref. In this example, the reference voltage Vref is equal to or similar to the power supply voltage Vdd.

In this case, the manner in which the low voltage generator 212 generates the read voltage is similar to the operation described above for generating the verify read voltage. That is, the first low voltage generator 212_a of the low voltage generator 212 generates the read voltage Vrd1 whose level is lower than the level of the reference voltage Vref using the power supply voltage Vdd. The second low voltage generator 212_b of the low voltage generator 212 generates the read voltages Vrd2 and Vrd3 which are higher than the level of the reference voltage Vref using the external high voltage Ext_Vpp. If the external high voltage Ext_Vpp is not supplied, the second low voltage generator 212_b of the low voltage generator 212 will generate the second read voltage Vrd2 and the third read voltage Vrd3 by lowering the internal high voltage Int_Vpp.

Figure 17 is a block diagram showing an example of the second low voltage generator 212_b shown in Figure 14. As described above with reference to FIGS. 14 to 16, if the external high voltage Ext_Vpp is supplied, the second low voltage generator 212_b will generate the verify read voltage or the read voltage using the external high voltage Ext_Vpp (the level thereof is higher than the reference voltage Vref). Level). Otherwise, the second low voltage generator 212_b will generate a verify read voltage or a read voltage (the level of which is higher than the reference voltage Vref) using the internal high voltage Int_Vpp.

As shown in FIG. 17, the second low voltage generator 212_b of this example includes a switching circuit 212_b1 and a voltage dividing circuit 212_b2.

The switching circuit 212_b1 receives the external high voltage Ext_Vpp via the first path and receives the internal high voltage Int_Vpp via the second path. The switching circuit 212_b1 sets the external high voltage Ext_Vpp and the internal high voltage Int_Vpp One of them is transferred to the voltage dividing circuit 212_b2 in response to the external voltage mode signal OVMS.

For example, when the external voltage mode signal OVMS is in the active state, the switching circuit 212_b1 will receive the external high voltage Ext_Vpp via the first path and transfer it to the voltage dividing circuit 212_b2. On the other hand, when the external voltage mode signal OVMS is in an inactive state, the switching circuit 212_b1 will receive the internal high voltage Int_Vpp via the second path and transfer it to the voltage dividing circuit 212_b2. The voltage dividing circuit 212_b2 shown in Fig. 17 can be similar to the voltage dividing circuit previously explained with reference to Figs. 7 to 10, and thus the description thereof will be omitted.

As described above, the internal high voltage Int_Vpp can be supplied from the high voltage generator 211 shown in FIG. The high voltage generator 211 can be similar to the general high voltage generator 111_a shown in FIG. 4 and the booster circuit 111_b4 shown in FIG. 5, and thus the description thereof will be omitted.

In the example explained above with reference to FIGS. 14 to 17, the first low voltage generator 212_a generates a verification voltage Vvfy1 and/or a read voltage Vrd1. It should be noted that this is for illustrative purposes only. For example, the number of verify read voltages or read voltages generated by the first low voltage generator 212_a may be modified according to the level of the reference voltage Vref.

Figure 18 is a block diagram of a non-volatile memory device in accordance with yet another embodiment of the present invention. The non-volatile memory device 1221" shown in Fig. 18 supports the external voltage mode OVM.

Referring to Fig. 18, the non-volatile memory device 1221" of this example includes a voltage generating circuit 310, a column selecting circuit 320, a memory cell array 330, a read/write circuit 340, a data input/output circuit 350, and control logic 360. The non-volatile memory device 1221" shown in FIG. 18 includes the same elements of the same name as those shown in FIG. 3 except for the voltage generating circuit 310, and thus detailed description of these elements will be omitted below to avoid redundant description.

The voltage generating circuit 310 of this example includes a high voltage generator 311 and a low voltage generator 312. The high voltage generator 311 includes a general high voltage generator 311_a and a selective high voltage generator 311_b, and the low voltage generator 312 includes a first low voltage generator 312_a and a second low voltage generator 312_b.

If the external high voltage Ext_Vpp is supplied, the selective high voltage generator 311_b will generate the pass voltage Vpass or the read pass voltage Vread using the external high voltage Ext_Vpp. The selective high voltage generator 311_b is similar to the selective high voltage generator shown in FIG. 3, and thus the description thereof will be omitted. At the same time, the general high voltage generator 311_a generates the program voltage Vpgm from the power supply voltage Vdd. Also, in the case where the external high voltage Ext_Vpp is supplied, the second low voltage generator 312_b will use the external high voltage Ext_Vpp to generate the read voltages Vrd2 to Vrdn or verify the read voltages Vvfy2 to Vvfyn. The second low voltage generator 312_b is similar to the low voltage generator shown in FIG. 14, and thus the description thereof will be omitted. At the same time, the first low voltage generator 312_a generates the read voltage Vrd1 or the read verify voltage Vvfy1 from the power supply voltage Vdd.

In the case where the external high voltage Ext_Vpp is not supplied, all of the generators 311_a, 311_b, 312_a, and 312_b generate their respective voltages from the power supply voltage Vdd.

Figure 19 is a diagram for explaining the operation of the memory system 1200 shown in Figure 1. Flow chart.

In step S110, the memory system 1200 receives the external power enable signal EPM_en from the host 1100.

In step S120, the memory controller 1210 of the memory system 1200 provides power control information to the non-volatile memory (NVM) device, that is, sets the control signal and data of the external voltage mode OVM in response to the external power enable signal. EPM_en.

In step S130, the non-volatile memory device set to the external voltage mode OVM generates a voltage Vx from the external high voltage Ext_Vpp. The voltage Vx may be, for example, a pass voltage to be supplied to an unselected word line in a program operation; a read verify pass voltage to be supplied to an unselected word line in a read verify operation; or a read operation The read pass voltage to be supplied to the unselected word line. Also, the voltage Vx may be a read voltage higher than the power supply voltage Vdd or a read verify voltage.

In the above example, the memory system 1200 obtains information on the voltage division of the external high voltage Ext_Vpp from the host 1100 via the external power enable signal EPM_en. However, the invention is not limited thereto. For example, the host may not support the function of providing an external power enable signal EPM_en to the memory system. The next embodiment to be described is suitable for this case.

Figure 20 is a block diagram of an electronic device in accordance with another embodiment of the present invention. Referring to FIG. 20, the electronic device 2000 includes a host 2100 and a memory system 2200. The electronic device 2000 shown in FIG. 20 is similar to the electronic device of FIG. 1, so only the difference between the two will be discussed below.

Memory system 2200 includes memory controller 2210 and non-volatile Memory component 2220. Unlike the host 1100 shown in FIG. 1, the host 2100 shown in FIG. 20 does not provide an external power enable signal EPM_en to the memory system 2200. In this regard, the memory system 2200 is equipped with an external power detecting circuit 2211 for detecting whether or not to receive the external high voltage Ext_Vpp.

A pad 2230 of the memory system 2200 receives an external high voltage Ext_Vpp from the host 2100. The external high voltage Ext_Vpp received via pin 2230 will be transferred to non-volatile memory devices 2221 through 2224.

The external power detecting circuit 2211 detects whether or not the external high voltage Ext_Vpp is received via the pin 2230. For example, if the external high voltage Ext_Vpp is received via the pin 2230, the external power detecting circuit 2211 will detect the input of the external high voltage Ext_Vpp to transmit the control signal and data for setting the external voltage mode OVM to the non-volatile memory device. . These non-volatile memory devices are similar to the non-volatile memory devices explained with reference to FIGS. 3 to 19, and thus the description thereof will be omitted.

In FIG. 20, the external power detection circuit 2211 is illustrated as being included in the memory controller 2210. However, the invention is not limited thereto. For example, the external power detecting circuit 2211 can be disposed outside the memory controller 2210 or in a non-volatile memory device (for example, the first non-volatile memory device 2221) that supports the external voltage mode OVM. This replacement will be more fully described with reference to Figures 21 and 22.

21 is a block diagram of an electronic device 3000 in accordance with still another embodiment of the present invention. Figure 22 is a block diagram of the non-volatile memory device 3221 of Figure 21 in accordance with an embodiment of the present invention. In Figures 21 and 22, The external power detecting circuit 3240 is included in the first non-volatile memory device 3221 that supports the external voltage mode OVM. The electronic device 3000 shown in FIG. 21 is similar to the electronic device of FIGS. 1 and 20, so only the differences between the two will be discussed below. In addition, the non-volatile memory device 3221 shown in FIG. 22 includes the same elements of the same name as those shown in FIG. 3 except for the external power detecting circuit 3240, and thus detailed description of those elements will be omitted below to avoid redundant description. .

Referring to FIG. 21, the pin 3230 receives the external high voltage Ext_Vpp from the host 3100, and supplies an external high voltage Ext_Vpp to the first non-volatile memory device 3221. In this case, the first non-volatile memory device 3221 will support the external voltage mode OVM and include an external power detection circuit 3240 for detecting an input of the external high voltage Ext_Vpp.

Referring to FIG. 22, the external power detecting circuit 3240 of the first non-volatile memory device 3221 detects whether or not the external high voltage Ext_Vpp is received. If an input to the external high voltage Ext_Vpp is detected, the external power detection circuit 3240 will provide a signal to the control logic 460 to activate the external voltage mode OVM. The control logic 460 transfers the external voltage mode signal OVMS to the voltage generating circuit 410 in response to the control signal, and the voltage generating circuit 410 generates the pass voltage Vpass or the read pass voltage Vread using the external high voltage Ext_Vpp.

In FIG. 22, the voltage generating circuit 410 is illustrated to generate the pass voltage Vpass or the read pass voltage Vread using the external high voltage Ext_Vpp. However, the invention is not limited thereto. For example, as shown in FIG. 14, the voltage generating circuit 410 can utilize the external high voltage Ext_Vpp to generate a verification read. Voltage Vvfy or read voltage Vrd. In another example, as shown in FIG. 18, the voltage generating circuit 410 can generate the pass voltage Vpass, the read pass voltage Vread, the verify read voltage Vvfy, or the read voltage Vrd using the external high voltage Ext_Vpp.

23 is a flow chart for explaining the operation of the memory system shown in FIG. 20 in accordance with an embodiment of the present invention.

In step S310, the external power detecting circuit 2211 of the memory system 2200 detects whether the external high voltage Ext_Vpp is received via the pin 2230.

In step S320, if an input of the external high voltage Ext_Vpp is detected, the external power detecting circuit 2211 will activate the external voltage mode OVM of the non-volatile memory device. At the same time, the external high voltage Ext_Vpp received via pin 2230 will be provided to the non-volatile memory device set to the external voltage mode OVM.

In step S330, the non-volatile memory device set to the external voltage mode OVM generates the word line voltage Vx using the external high voltage Ext_Vpp. The word line voltage Vx has been discussed above with reference to step S130 of FIG.

FIG. 24 is a flow chart for explaining the operation of the non-volatile memory device capable of supporting the external voltage mode OVM shown in FIGS. 21 and 22.

In step S401, the control logic 460 of the non-volatile memory device 3221 receives a request from the memory controller 3210 to generate the word line voltage Vx.

In step S420, the external power detecting circuit 3240 detects the input of the external high voltage Ext_Vpp (S420).

In step S430, if the external high voltage Ext_Vpp is detected, the voltage generating circuit 410 generates the word line voltage Vx using the external high voltage Ext_Vpp as required to generate the word line voltage Vx. Here, the requirement to generate the word line voltage Vx may include a program command or a read command.

In step S440, if the external high voltage Ext_Vpp is not detected, the voltage generating circuit 410 generates the word line voltage Vx using the power supply voltage Vdd as required to generate the word line voltage Vx.

In step S450, a word line voltage is supplied to the corresponding word line. The word line voltage Vx has been discussed above with reference to step S130 of FIG.

As described above, embodiments of the present invention are applicable to both stylization and reading of non-volatile memory devices. An example of a stylized method of a non-volatile memory device is disclosed in detail in U.S. Patent Nos. 6,335,881 and 7,064,986, the entireties of each of each of An example of a method of reading a non-volatile memory device is disclosed in detail in U.S. Patent Application Serial No. 2010/003986, the entire disclosure of which is incorporated herein by reference.

In the above embodiment, the word line voltage is generated from the external high voltage Ext_Vpp. However, the present invention also encompasses generating other voltages from the external high voltage Ext_Vpp, such as the voltage supplied to the string selection line and/or the ground selection line of the memory cell array.

The non-volatile memory device according to an embodiment of the present invention may utilize, for example, a 2-dimensional (2D) anti-gate flash memory array and a 3-dimensional (3D) flash memory array (also referred to as vertical anti-gate fast Flash memory VNAND device) The device is implemented. An example of a vertical anti-gate flash memory device is disclosed in U.S. Patent Application Publication No. 2009/0306583, No. 2010/0078701, No. 2010/0117141, No. 2010/0140685, No. 2010/02135527, The entire disclosures of these patent application publications are hereby incorporated by reference.

25 is a block diagram of a solid state hard disk (SSD) including a memory system in accordance with an embodiment of the present invention. Referring to FIG. 25, the solid state hard disk system 4000 includes a host 4100 and a solid state hard disk 4200. The solid state drive 4200 exchanges signals with the host 4100 via a signal connector 4211 and receives power via the power connector 421. The solid state hard disk 4200 includes a plurality of non-volatile memory devices 4201 to 420n, a solid state hard disk controller 4210, and a power supply 4220.

A plurality of non-volatile memory devices 4201 to 420n will serve as storage media. The solid state hard disk 4200 can first be implemented using flash memory. On the other hand, the solid state hard disk 4200 can be implemented by other non-volatile memory, such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory. Body (FRAM) and so on. In addition, the solid state drive 4200 can be implemented using different types of non-volatile memory.

The power supply 4220 provides power to the plurality of non-volatile memory devices 4201 to 420n. And, when the external high voltage Ex_Vpp is supplied from the host 4100, the power supply 4220 will supply an external high voltage Ext_Vpp One or more of the non-volatile memory devices 4201 to 420n are given. In this case, as described in the previous embodiment of the present invention, the solid state hard disk controller 4210 can set one or more non-volatile memory devices 4201 to 420n to the above-described external voltage mode OVM.

The solid state hard disk controller 4210 transmits the signal SGL to the host 4100 via the signal connector 4211 and receives the signal SGL from the host 4100. Here, the signal SGL may include commands, addresses, materials, and the like. The solid state hard disk controller 4210 writes data to or reads data from the corresponding memory device according to the command of the host 4100. The solid state hard disk controller 4210 can be constructed as the memory controller 1210 previously described with reference to FIG.

Figure 26 is a schematic illustration of a memory card in accordance with an embodiment of the present invention. In particular, Figure 26 is a perspective view of a secure digital card. Referring to Figure 26, the secure digital card includes nine feet. For example, a secure digital card includes four data pins (eg 1, 7, 8, 9), one command pin (eg 2), one clock pin (eg 5), and three power pins (eg 3 , 4, 6).

Here, the command and response signals will be transferred via command pin 2. Usually, the command is transferred from the host to the memory card, and the response signal is transferred from the memory card to the host. According to an embodiment of the invention, at least one of the three power pins is for receiving the external high voltage Ext_Vpp, and the command pin 2 is for receiving the external power enable signal EPM_en.

Figure 27 is a block diagram of the memory card shown in Figure 26. The memory card system 4000 includes a host 4100 and a memory card 4200. Host 4100 includes host control A host controller 4110 and a host connection unit 4120. The memory card 4200 includes a memory card connection unit 4210, a memory card controller 4220, and a memory 4230.

The host connection unit 4120 and the memory card connection unit 4210 form a plurality of pins, which may include a command pin, a data pin, a clock pin, a power pin, and the like. The number of pins can vary depending on the type of memory card 4200.

The host 4100 writes data to or reads data from the memory card 4200. The host controller 4110 provides commands (such as a write command), a clock CLK generated by a clock generator (not shown) in the host 4100, and data to the memory card 4200 via the host connection unit 4120.

The memory card controller 4220 stores data in the memory 4230 in synchronization with a clock generated by a clock generator (not shown) in the memory card controller 4220 in response to a write command received via the memory card connection unit 4210. The memory 4230 stores the material transferred from the host 4100. For example, if the host 4100 is a digital camera, the memory 4230 will store the image data.

The memory 4230 includes at least one non-volatile memory device (e.g., the non-volatile memory device 1221 of FIG. 3) that supports the external voltage mode OVM. The memory 4230 receives the external high voltage Ext_Vpp to generate a word line voltage using the external high voltage Ext_Vpp as described with reference to the previous embodiment of the present invention.

28 is a block diagram of an electronic device 5000 including a flash memory device in accordance with an embodiment of the present invention. Embodiments of the electronic device 5000 may be, for example, a personal computer or a handheld electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), a camera, and the like.

Referring to FIG. 28, the electronic device 5000 includes a semiconductor memory device 5100, a power supply 5200, an auxiliary power supply 5250, at least one central processing unit 5300, a random access memory (RAM) 5400, and a user interface. 5500. The semiconductor memory device 5100 includes at least one non-volatile memory 5110 and a memory controller 5120.

In FIG. 28, the auxiliary power supply 5250 or the power supply 5200 supplies a high voltage (ie, an external high voltage Ext_Vpp) to the non-volatile memory device 5110. The non-volatile memory device 5110 generates a word line voltage using the external high voltage Ext_Vpp as described with reference to the previous embodiment of the present invention.

The above disclosure is intended to be illustrative of the invention, and is not intended to limit the scope of the invention. Therefore, the scope of the invention should be construed as being limited by the scope of the invention,

1‧‧‧Power supply unit

2‧‧‧Voltage unit

3‧‧‧Bias current unit

4‧‧‧Comparative unit

5, 6‧‧‧ trimming code generator

5_a, 5_b, DL_VF, DL_VR‧‧‧ data latch

6_a, 6_b, E_FUSE_VF, E_FUSE_VR‧‧‧ electric fuse

6_c, SW0_L, SW1_L, SW2_L, S/W‧‧‧ switch

110, 210, 310, 410‧‧‧ voltage generation circuit

111, 211, 311, 411‧‧‧ high voltage generator

111_a, 311_a, 411_a‧‧‧General high voltage generator

111_a1, 111_b1‧‧‧ oscillator

111_a2, 111_b2‧‧‧ voltage regulator

111_a3, 111_b3‧‧‧ charge pump

111_b, 111_b', 311_b, 411_b‧‧‧ selective high voltage generator

111_b4‧‧‧Boost circuit

111_b5, 212_b1‧‧‧ switching circuit

111_b6, 212_b2‧‧‧ voltage divider circuit

112, 212, 212_a, 212_b, 312, 312_a, 312_b, 412‧‧‧ low voltage generator

120, 220, 320, 420‧‧‧ column selection circuit

121, 221, 321, 421‧‧‧ voltage selection switch

121_a‧‧‧Decoding unit

121_b1, 121_bn-1, 121_bn‧‧‧ drive unit

122, 123, 222, 223, 322, 323, 422, 423 ‧ ‧ column decoding Device

130, 230, 330, 430‧‧‧ memory cell array

131, 132, 231, 232, 331, 332, 431, 432‧‧‧ memory blocks

140, 240, 340, 440‧‧‧ read and write circuits

150, 250, 350, 450‧‧‧ data input/output circuits

160, 260, 360, 460‧‧‧ control logic

1000, 2000, 3000, 5000‧‧‧ electronic devices

1100, 2100, 3100, 4100‧‧‧ host

1110‧‧‧External Power Management Unit

1200, 2200, 3200‧‧‧ memory system

1210, 2210, 3210, 5120‧‧‧ memory controller

1211, 5300‧‧‧ central processor

1212‧‧‧Host interface

1213‧‧‧Volatile memory device

1214‧‧‧ Non-volatile memory interface

1220, 2220, 3220, 5110‧‧‧ non-volatile memory

1221, 1221', 1221", 1222, 1223, 1224, 2221, 2222, 2223, 2224, 3221, 3222, 3223, 3224, 4201, 4202, 420n‧‧‧ non-volatile memory devices

1225‧‧‧Setting the register

1230‧‧‧External power switching unit

2211, 3240‧‧‧ External power detection circuit

2230, 3230‧‧‧ feet

4000‧‧‧Solid State Drive System / Memory Card System

4110‧‧‧Host Controller

4120‧‧‧Host connection unit

4200‧‧‧ Solid State Drive/Memory Card

4210‧‧‧Solid State Drive Controller/Memory Card Connection Unit

4211‧‧‧Signal Connector

4220‧‧‧Power supply/memory card controller

4221‧‧‧Power connector

4230‧‧‧ memory

5100‧‧‧Semiconductor memory device

5200‧‧‧Power supply

5250‧‧‧Auxiliary power supply

5400‧‧‧ Random access memory

5500‧‧‧User interface

BL, BL1, BL2, BLm‧‧‧ bit line

BS‧‧‧ block control signal

BS0, BS1, BSn-1, BSn, BSn+1‧‧‧ voltage transfer transistor

CH1, CH2, CHn‧‧‧ channels

CLK‧‧‧ clock

CMD‧‧‧ Order

CTRL‧‧‧ control signal

DAT‧‧‧Information

DL‧‧‧ data line

DRA_1, DRA_n-1, DRA_n‧‧‧ Decoded column address

EPM_en‧‧‧External power enable signal

Ext_Vpass‧‧‧ external pass voltage

Ext_Vpp‧‧‧External high voltage

GS‧‧‧Ground selection signal

GSL‧‧‧ Grounding selection line

GST‧‧‧Ground selection transistor

Int_Vpass‧‧‧ internal pass voltage

Int_Vpp‧‧‧Internal high voltage

INV1, INV2‧‧‧ inverter

I/O‧‧‧ Input/Output

M0_L, M1_L, M2_L‧‧‧ transistor

M1, Mn-1, Mn‧‧‧ memory cells

NC_L‧‧‧ comparison node

NM1, NM2‧‧‧N-channel metal oxide semiconductor transistor

NO_L‧‧‧Output node

OSC‧‧‧ oscillation signal

OUT‧‧‧ output

OVMS‧‧‧ external voltage mode signal

PM1, PM2, PM_L‧‧‧P channel metal oxide semiconductor transistor

PWR‧‧‧ power supply

R1_L, R2_L, R3_L, R4_L‧‧‧ resistors

RA, RAi, RAj‧‧‧ address

S110, S120, S130, S310, S320, S330, S420, S430, S440, S450‧‧ steps

SGL‧‧‧ signal

SL1, SLn-1, SLn‧‧‧Select signal line

SS‧‧‧ string selection signal

SSD‧‧‧ Solid State Drive

SSL‧‧‧ string selection line

SST‧‧‧ string selection transistor

ST0‧‧‧Erasing status

ST1‧‧‧ first program status

ST2‧‧‧Second program status

ST3‧‧‧ third program status

S<1>, S<n-1>, S<n>, S<n:1>‧‧‧Selection signal

T1, T2‧‧ ‧ time period

T1, t2, t3‧‧‧ time

TEN1, TEN2‧‧‧ trimming code enable signal

TRM0_L, TRM1_L, TRM2_L, TRMi_L‧‧‧ trimming code

TV‧‧‧target voltage

Vdd‧‧‧Power supply voltage

Vpass‧‧‧ pass voltage

Vpgm, Vpgm1, Vpgm2, VpgmN‧‧‧ program voltage

Vpp‧‧‧High voltage

Vread‧‧‧ read through voltage

Vrd, Vrd1, Vrd2, Vrd3, Vrdn‧‧‧ read voltage

Vref, Vref_LV‧‧‧ reference voltage

Vvfy, Vvfy1, Vvfy2, Vvfy3, Vvfyn‧‧‧ verify the read voltage

WL, WL1, WLn-1, WLn‧‧‧ character lines

1 is a block diagram of an electronic device in accordance with one or more embodiments of the present invention.

2 is a block diagram of the memory controller of FIG. 1 in accordance with one or more embodiments of the present invention.

3 is a block diagram of the non-volatile memory device of FIG. 2 in accordance with one or more embodiments of the present invention.

4 is a block diagram showing an example of the high voltage generator shown in FIG.

5 is a block diagram of the selective high voltage generator of FIG. 3 in accordance with one or more embodiments of the present invention.

Fig. 6 is a timing chart for explaining an example of a transfer path of voltages supplied to a voltage dividing circuit of the selective high voltage generator shown in Fig. 5.

7 is a circuit diagram of the voltage divider circuit of FIG. 5 in accordance with one or more embodiments of the present invention.

8 is a block diagram of a trim code generator in accordance with one or more embodiments of the present invention.

9 is a block diagram of another trimming code generator in accordance with one or more embodiments of the present invention.

Figure 10 is a circuit diagram of one of the switches of Figure 7 in accordance with one or more embodiments of the present invention.

11 is a circuit diagram of the selective high voltage generator of FIG. 3 in accordance with one or more embodiments of the present invention.

Figure 12 is a block diagram of the voltage selection switch of Figure 3 in accordance with one or more embodiments of the present invention.

13 is a block diagram of the column decoder and memory cell array of FIG. 3 in accordance with one or more embodiments of the present invention.

14 is a block diagram of a non-volatile memory device in accordance with one or more embodiments of the present invention.

15 and 16 are schematic views for explaining an operation example of the voltage generating circuit shown in Fig. 14.

17 is a block diagram of the second low voltage generator of FIG. 14 in accordance with one or more embodiments of the present invention.

18 is a block diagram of a non-volatile memory device in accordance with one or more embodiments of the present invention.

Figure 19 is a flow chart for explaining an operation example of the memory system shown in Figure 1.

20 is a block diagram of an electronic device in accordance with one or more embodiments of the present invention.

21 is a block diagram of an electronic device in accordance with one or more embodiments of the present invention.

22 is a block diagram of the non-volatile memory device of FIG. 21 in accordance with one or more embodiments of the present invention.

23 is a flow chart for explaining an example of the operation of the memory system shown in FIG. 20 in accordance with one or more embodiments of the present invention.

FIG. 24 is a flow chart for explaining an operation example of a non-volatile memory device capable of supporting the external voltage mode OVM shown in FIGS. 21 and 22.

25 is a block diagram of a solid state hard disk including a memory system in accordance with one or more embodiments of the present invention.

26 is a schematic diagram of a memory card including a memory system in accordance with one or more embodiments of the present invention.

Figure 27 is a block diagram showing an example of the memory card shown in Figure 26.

28 is a block diagram of an electronic device including a flash memory device in accordance with one or more embodiments of the present invention.

110‧‧‧Voltage generation circuit

111‧‧‧High voltage generator

111_a‧‧‧General high voltage generator

111_b‧‧‧Selective high voltage generator

112‧‧‧Low voltage generator

120‧‧‧ column selection circuit

121‧‧‧Voltage selection switch

122, 123‧‧‧ column decoder

130‧‧‧ memory cell array

131, 132‧‧‧ memory blocks

140‧‧‧Reading and writing circuit

150‧‧‧Data input/output circuit

160‧‧‧Control logic

1221‧‧‧ Non-volatile memory device

BL‧‧‧ bit line

CTRL‧‧‧ control signal

DL‧‧‧ data line

Ext_Vpp‧‧‧External high voltage

I/O‧‧‧ Input/Output

OVMS‧‧‧ external voltage mode signal

RA, RAi, RAj‧‧‧ address

S<n:1>‧‧‧Selection signal

Vdd‧‧‧Power supply voltage

Vpass‧‧‧ pass voltage

Vpgm‧‧‧ program voltage

Vread‧‧‧ read through voltage

Vrd‧‧‧ reading voltage

Vvfy‧‧‧Verified read voltage

WL‧‧‧ character line

Claims (9)

A non-volatile memory device includes: a non-volatile memory cell array including a plurality of word lines; a voltage generator for respectively receiving an external voltage from an external device and receiving a power supply voltage, and utilizing The power supply voltage generates a first high voltage and generates a second high voltage using the external voltage higher than the power supply voltage; and a word line selection circuit for applying the program during operation of the memory cell array And a first high voltage is applied to the selected word line among the plurality of word lines, and the second high voltage is applied to an unselected word line among the plurality of word lines. The non-volatile memory device of claim 1, wherein the voltage generator comprises a charge pump, the charge pump receiving the power supply voltage and being driven by the power supply voltage to generate the first high voltage. The non-volatile memory device of claim 2, wherein the voltage generator comprises a voltage divider, the voltage divider receives and divides the external voltage and outputs the second high voltage . The non-volatile memory device of claim 1, wherein the first high voltage is a program voltage Vpgm, and the second high voltage is a pass voltage Vpass. The non-volatile memory device of claim 1, further comprising a low voltage generator, the low voltage generator generating a lower than the first high voltage and the second high voltage Voltage. The non-volatile memory device of claim 5, wherein the memory cell array comprises a first memory block and a second memory block, and wherein the word line selection circuit comprises: a voltage selection switch that selectively shifts the first high voltage, the second high voltage, and the low voltage to a plurality of signal lines according to a first portion of a column of address signals; and a block decoder according to the The second portion of the address signal selectively shifts the voltage of the signal line to the word line of the first memory block and the second memory block. The non-volatile memory device of claim 1, wherein the non-volatile memory cell array comprises a 2-dimensional inverse gate flash memory array or a 3-dimensional inverse gate flash memory array. A memory system comprising: at least one non-volatile memory device; a memory controller for controlling the at least one non-volatile memory device; and a power supply for supplying a power voltage and a High voltage to the at least one non-volatile memory device, the high voltage being higher than the power supply voltage; wherein operation of the at least one non-volatile memory device is controlled by the memory controller, The power supply voltage generates a first high voltage and generates a second high voltage by using the high voltage, wherein the first high voltage is a program voltage, and the second high voltage is a pass voltage, and the pass voltage is low The program voltage. An electronic device comprising: a host; and a storage device for storing the written data from the host and outputting the read data to the host; wherein the storage device comprises: a plurality of non-volatile memory a memory controller for controlling the plurality of non-volatile memory devices; and a power supply for supplying a power voltage and a high voltage to the plurality of non-volatile memory devices, The high voltage is higher than the power supply voltage; wherein operation of at least one of the plurality of non-volatile memory devices is controlled by the memory controller to generate a first high voltage and utilization by using the power supply voltage The high voltage produces a second high voltage, wherein the first high voltage is a program voltage, and the second high voltage is a pass voltage, the pass voltage being lower than the program voltage.